CONSIDERING CAPACITANCES By Prasad Pande

MOS DEVICE CAPACITANCE MODEL

• CGS : Gate to Source Capacitance
CGS = CGCS + CGSO
• CGD : Gate to Drain Capacitance
CGD = CGCD + CGDO
• CGB : Gate to Body(Bulk) Capacitance
CGB = CGCB
• CSB : Source to Body(Bulk) Capacitance
CSB = CSdiff
• CDB : Drain to Body(Bulk) Capacitance
CDB = CDdiff
CASCADED INVERTER PAIR CAPACITANCES
OUTPUT CAPACITANCE CL
• To make the analysis tractable, assume that all capacitances are lumped together
into one single capacitor CL, located between Vout and GND
• Components of CL
1. Gate-Drain Capacitance Cgd12
Only contributions to Cgd12 are the overlap capacitances Cgdo of both M1 and M2.
The channel capacitance of the MOS transistors does not play a role here, as it is located either completely between
gate and bulk (cut-off) or gate and source (saturation)
OUTPUT CAPACITANCE CL
Components of CL
2. Diffusion Capacitances Cdb1 and Cdb2
These capacitances between drain and bulk are due to the reverse-biased
pn-junction.
3. Wiring Capacitance CW
The capacitance due to the wiring depends upon the length and width of the
connecting wires, and is a function of the distance of the fanout from the
driving gate and the number of fanout gates.
4. Gate Capacitance of Fanout Cg3 and Cg3
We assume that the fanout capacitance equals the total gate capacitance of
the loading gates M3 and M4
OUTPUT CAPACITANCE CL
• Total CL Summary – Mathematical

+ Cgd1 + Cgd2
OUTPUT CAPACITANCE CL
• Total CL Summary – Practical
• Capacitances of a 0.25µm CMOS Inverter set at 2.5V VDD
EFFECT OF CL ON PERFORMANCE
• Propagation delay of the CMOS inverter is determined by the time it takes to
charge and discharge the load capacitor CL through the PMOS and NMOS
transistors, respectively

• This observation suggests that

getting CL as small as possible is crucial to the realization of high-performance
CMOS circuits.
SIZING INVERTERS FOR PERFORMANCE
• Assumption: symmetrical inverter such that the rise and fall delays are identical.
• The load capacitance of the inverter can be divided into an intrinsic and an extrinsic
component, or
CL = Cint + Cext
• Cint represents the self-loading or intrinsic output capacitance of the inverter, and is
associated with the diffusion capacitances of the NMOS and PMOS transistors (Cdb1,
Cdb2) as well as the gate-drain overlap (Miller) capacitances (Cgd1, Cgd2).
• Cext is the extrinsic load capacitance, attributable to fanout (Cg3, Cg4)and wiring
capacitance (CW).
• Assuming that Req stands for the equivalent resistance of the gate
SIZING INVERTERS FOR PERFORMANCE
Propagation Delay is given by
SIZING INVERTERS FOR PERFORMANCE
• How transistor sizing impacts the performance of the gate ???
• Relation between sizing factor S of desired inverter and reference inverter of minimum
size
• The intrinsic capacitance Cint consists of the diffusion and Miller capacitances, both of
which are proportional to the width of the transistors. Hence, Cint = S.Ciref
• The resistance of the gate relates to the reference gate as Req = Rref/S
SIZING INVERTERS FOR PERFORMANCE
This leads to two important conclusions:

• The intrinsic delay of the inverter tp0 is independent of the sizing of the gate, and is
purely determined by technology and inverter layout. When no load is present, an
increase in the drive of the gate is totally offset by the increased capacitance.

• Making S infinitely large yields the maximum obtainable performance gain,

eliminating the impact of any external load, and reducing the delay to the intrinsic
one. Yet, any sizing factor S that is sufficiently larger than (Cext/Cint) produces similar
results at a substantial gain in silicon area.
• Drawback : Sizing up an inverter reduces its delay BUT it also increases its input
capacitance
HOW TO DRIVE LARGE CL ??
SIZING A CHAIN OF INVERTERS (SUPER BUFFER DESIGN)

• Larger the CL, larger the amount of pull-up/pull-down current required for charging/
discharging

• One way - Single inverter with infinite S – got drawback of large Cint

• Another way – have a chain of inverters with progressively increasing sizes

• Objective : Given a load capacitance faced by a logic gate, design an scaled chain
of N inverters such that the delay time between input logic gate and the load
capacitance CL is minimized
HOW TO DRIVE LARGE CL ??
SIZING A CHAIN OF INVERTERS (SUPER BUFFER DESIGN)

• To determine the input loading effect, the relationship between the input gate
capacitance Cg and the intrinsic output capacitance Cint of the inverter has to be
established.
• Both are proportional to the gate sizing. Hence, the following relationship holds,
independent of gate sizing
HOW TO DRIVE LARGE CL ??
SIZING A CHAIN OF INVERTERS (SUPER BUFFER DESIGN)

• Now The goal is to minimize the delay through the inverter chain, with the input
capacitance of the first inverter Cg1—typically a minimally-sized device— and the
load capacitance CL fixed.
HOW TO DRIVE LARGE CL ??
SIZING A CHAIN OF INVERTERS (SUPER BUFFER DESIGN)
HOW TO DRIVE LARGE CL ??
SIZING A CHAIN OF INVERTERS (SUPER BUFFER DESIGN)
HOW TO DRIVE LARGE CL ??
SIZING A CHAIN OF INVERTERS (SUPER BUFFER DESIGN)
NUMBER OF STAGES IN CHAIN OF INVERTERS

First component (N.tpo)is intrinsic delay of the stages while second is effective fan-
out of each stage.
TRADEOFF : If no. of stages are more, intrinsic delay dominates.
If no. of stages are too few, effective fan-out dominates.
The optimum value can be found by the minimum delay expression by the number
of stages, and setting the result to 0. i.e.
NUMBER OF STAGES IN CHAIN OF INVERTERS
i) When g = 0 (neglecting self-loading effect), optimal number of stages equals
N = ln(F) and
the effective fanout of each stage is set to f = e = 2.71828

ii) When g ≠ 0 (considering self-loading effect) equation has to be solved

iii) When g = 1 (Practical value), the optimum scaler factor turns out to be close
to 3.6
A common practice is to select an optimum fanout of 4. The use of too many
stages (f < fopt), on the other hand, has a substantial negative impact on the
delay, and should be avoided.
NUMBER OF STAGES IN CHAIN OF INVERTERS
NUMBER OF STAGES IN CHAIN OF INVERTERS
The Impact of Introducing Buffer Stages :
Below table enumerates the values of tp,opt/tp0 for the unbuffered design, the dual stage, and optimized inverter chain for
a variety of values of F (for g = 1).
Observe the impressive speed-up obtained with cascaded inverters when driving very large capacitive loads .
Prasad Pande