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LOGIC FAMILIES (D.E.)

Overview:
1. Basic gates of Logic Family
2. Characteristics of Logic Family
3. Types of Logic Family
• Transistor based Logic Family
• MOSFET based Logic Family.
4. BJT Family
• RTL
• DCTL
• DTL
• HTL
• TTL
• Schottky TTL
• ECL
• I2L
5. MOSFET based Logic Familiy
6. Advantages of NMOS – PMOS over BJT
7. MOS Family
• Single NMOS Transistor
• Series connection
• Parallel connection
• Single PMOS transistor
• Series connection
• Parallel connection
• CMOS
1. BASIC GATES OF A LOGIC FAMILY
The standard gate construction of any logic family performs either the NAND
operation or NOR operation. Hence, it is said that the basic gate of any logic
family is either NAND (or) NOR gate.

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2. LOGIC FAMILY CHARACTERISTICS

(i) Propagation Delay (TPD):
• It is the average transition delay time for the signal to propagate from
input to output of logic gate.
• It is measured in (ns)
(ii) Power dissipation (PD):
• Power drawn from power supply.
• It is measured in (mW)
(iii) Figure of Merit/speed-power product:
• It is the product of TPD and PD of a logic gate.
• It is measured in (PJ)

i.e., FOM = TPD  PD

 ns × mW = PJ
NOTE: Figure of merit (FOM) should be as low as possible for any logic family.
(iv) Fan-out/Loading factor:

• Fan-out defines the number of load gates that can be successfully driven
by output of driving gate.
(fanout)H = fanout when output = logic = 1 (fanout)L = fanout when output = logic = 0

IOH IOL
(fanout)n = (fanout)L =
IIH IIL

Fanout= min(fanoutH, fanoutL)

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Example : Given
(IOH )max = −0.4 mA, (IOL )max = 8 mA

(IIH )max = 20 A, (IIL )max = −0.1 mA

Find fanout?
OH −0.4  10−3
Sol.: fH = = = −20
IIH 20  10−6

OL 8  10−3
fL = = = −80
IIL −0.1  10−3
Here, discard the negative sign.
fanout = min (fH, fL)
fanout = min (20, 80)

fanout = 20 Ans.
(v) Noise-Margin/Noise-immunity:
• It is the maximum noise voltage that can be tolerated by input of a logic
gate without affecting the output.

 VOH  VIH  VIL  VOL

 Noise-Margin = min(NMH , NML )

Here, NMH = Noise-margin at highest level = VOH – VIH

NML = Noise margin at lower level = VIL – VOL
4. BJT-FAMILIES
i) RTL (Resistor Transistor Logic)
In RTL, “wired AND logic’ is possible
WIRED AND LOGIC  If the outputs of a two RTL gates are directly coupled
(wired), then it performs the AND operation.

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ii) DCTL (Direct Coupled Transistor Logic):

• Basic-gate: NOR-gate
• Problem of CURRENT HOGGING is associated with this logic family.
iii) DTL (Diode-Transistor Logic)

x y f
0 0 1
0 1 1
1 0 1
1 1 0
NOTE: At x = y = 1, transistor will be ON.
• Basic gate → NAND-gate
• In DTL, wired AND logic is present (same as RTL)

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iv) HTL (High Threshold Logic)

• It is the modification of DTL gate.

• It has BEST NOISE MARGIN = 7.5V

• In HTL, wired AND operation is possible.

v) TTL (Transistor Transistor Logic):

NOTE:

(1) In TTL, active pull up (transistor Q4) is used instead of passive pull-up (load

resistor) to reduce RC time constant and thus propagation delay.

(2) ON/OFF status of transistors Q2 and Q3 remains same.

(3) ON/OFF status of transistors Q3 – Q4 remains opposite. Diode (D) is used to

accomplish this.

(4) 130  resistance is used to prevent high current spikes.

(5) Clamp diodes are used to absorb any ringing (oscillations).

Open/Floating Input in TTL

• In any circuit, if any input is left open/float, then no current flows through

that input path.

NOTE:

In TTL-circuit, open/floating input acts as a logic = L

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Output Configuration of TTL

• TTL circuit is available in 3-types of output configuration.

Token-pole output Open collector output 3-state/ tristate output

• It acts as output • Passive pull up is • Special type of token pole
buffer. used. gate.
• Wired logic is not • Wired AND logic is • 3rd state = High
possible. possible. impedance state.
Example: Open collector output of 2 two input NAND gates are connected, find

output?

Solution: Wired AND Logic operation is possible in open collector.

 f = AB  CD = ABCD

vi) Schottky TTL

• In Schottky TTL, Schottky barrier diodes (SBD) are placed between the

base and collector of transistor.

• This prevents the transistors from entering into saturation region.

Therefore, the transistor operates in ACTIVE and CUT-OFF regions.

• It increase the speed of operation and very low propagation delay.

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vii) ECL (Emitter Coupled Logic)

• ECL works on negative power supply and negative voltage levels.

X Y NOR OR
0 0 1 0
0 1 0 1
1 0 0 1
1 1 0 1
NOTE:
In ECL, open floating = logic = 0
In TTL, open floating = logic = 1

ECL = Fastest

viii) I2L [Integrated Injection Logic]

• I2L has high packing density, it is because of
• Multi collector output transistor.
• pnp transistor (instead of load-resistor)
NOTE:

I2L has best Figure of Merit.

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5. MOSFET BASED LOGIC FAMILIES

a) Advantages of NMOS and PMOS over BJT:

• Lower power dissipation

• Higher fan-out

• Simpler fabrication process

• Higher pacing density

• Lower cost of fabrication.

b) Single NMOS transistor:

Input Status of Transistor Output

x Q1 f

L OFF H

H ON L

Positive Logic Negative Logic

x f x f
0 1 1 0
1 0 0 1

NOT gate
NOTE:

Single MOS circuit acts as a NOT gate.

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c) Series connection of NMOS transistor:

Inputs Status (Q) Output (H)

X y Q1 Q2 F

L L OFF OFF H

L H OFF ON H

H L ON OFF H

H H ON ON L

Assuming Positive Logic Assuming Negative Logic

X y F X y F
0 0 1 1 1 0
0 1 1 1 0 0
1 0 1 0 1 0
1 1 0 0 0 1
NAND gate NOR-Gate

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d) Parallel connection of NMOS-transistor

Inputs Status (Q) Output

X y Q1 Q2 F

L L OFF OFF H

L H OFF ON L

H L ON OFF L

H H ON ON L

Assuming Positive Logic Assuming Negative Logic

x y F x y F

0 0 1 1 1 0

0 1 0 1 0 1

1 0 0 0 1 1

1 1 0 0 0 1
NOR gate NAND gate

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Example :

Solution:
NOTE:
For NMOS:
Series = AND
Parallel = OR
N3 parallel to N4  (Q + R) series with N2

output = y = P(Q + R) + ST

e) Series connection of PMOS transistor:

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Inputs Status (Q) Output

x y Q1 Q2 F

L L ON ON H

L H ON OFF L

H L OFF ON L

H H OFF OFF L

Assuming Positive Logic Assuming Negative Logic

x y F x y f

0 0 1 1 1 0

0 1 1 1 0 1

1 0 0 0 1 1

1 1 0 0 0 1
NOR gate NAND gate
 CONCLUSION:
NOTE

Connection For NMOS For PMOS

Series AND OR
Parallel OR AND
It is for positive logic.
f) CMOS (Complementary MOS)

(i) A CMOS is obtained by connecting a PMOS and a NMOS in series.

(ii) (a) NMOS conducts when VGS (VG – VS) is positive and above VT.
(b) PMOS conducts when VGS (VG – VS) is negative and below VT.

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Properties of CMOS:
• CMOS is a combination of an n-channel FET and p channel FET [n channel FET
= NMOS]
• There is no power dissipation when input carries logical 1 signal (or) signal 0
signal.
• There is a power dissipation during transition from 0 to 1 (or) from 1 to 0.
NOT gate:

X Q1 Q2 f
0 ON OFF 1
1 OFF ON 0

On logic 0 = PMOS = ON
On logic 1 = NMOS = ON
NAND gate

X y Q1 Q2 Q3 Q4 F
0 0 ON ON OFF OFF 1
0 1 ON OFF ON OFF 1
1 0 OFF ON OFF ON 1
1 1 OFF OFF ON ON 0

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NOR GATE:

X y Q1 Q2 Q3 Q4 f
0 0 ON ON OFF OFF 1
0 1 ON OFF OFF ON 0
1 0 OFF ON ON OFF 0
1 1 OFF OFF ON ON 0
Example: Find output y = ?

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Solution:

y = A  (B+ C)

y = A + (B+ C)

y = A + BC

output = y = A + BC

CMOS Transmission gate/Bilateral Switch:

• It is obtained by connecting on NMOS and a PMOS in parallel.

N P NMOS PMOS TG f
0 1 OFF OFF Open Switch High impedance state
1 0 ON ON Close Switch X
Since, input and output can be interchanged, therefore, it is called Bilateral
switch.
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