Digital Design Course File

Geethanjali College of Engineering and
Technology
(Autonomous)
Cheeryal (V), Keesara (M), Medchal District – 501 301 (T.S)
DIGITAL DESIGN
COURSE FILE
DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING

(2019-2020)
Faculty in Charge HOD-CSE

M. Vijay Bhasker Reddy Dr. D.S.R.Murthy
Assistant Professor Professor
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Geethanjali College of Engineering and Technology
DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING
Name of the Subject: DIGITAL DESIGN
Subject CODE: 18EC2102 Programme: UG
Branch: CSE Version No: 2
Year: II Document Number : GCET/CSE
Semester: I No. of Pages: 191
Classification status (Unrestricted/Restricted ) : Unrestricted
Distribution List: Unrestricted
Prepared by :
1) Name : M Vijay Bhasker Reddy
2) Sign :
3) Design : Assistant Professor
4) Date :
Verified by : *For Q.C only
1) Name : D. Venkateswarlu 1) Name :
2) Sign : 2) Sign :
3) Design : Associate Professor 3) Design :
4) Date : 4) Date :
Approved by (HOD) :
1) Name :
2) Sign :
3) Date :
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COURSE FILE FOR DIGITAL DESIGN
Course file contents

1. Cover Page
2. Syllabus copy
3. Vision of the Department
4. Mission of the Department
5. PEOs and POs
6. Course objectives and outcomes
7. Brief notes on the importance of the course and how it fits into the curriculum
8. Prerequisites if any
9. Instructional Learning Outcomes
10. Course mapping with POs
11. Class Time Table
12. Individual Time Table
13. Lecture schedule with methodology being used/adopted
14. Detailed notes
15. Additional topics
16. University Question papers of previous years
17. Question Bank
18. Assignment Questions
19. Unit wise Quiz Questions and long answer questions
20. Tutorial problems
21. Known gaps ,if any and inclusion of the same in lecture schedule
22. Discussion topics , if any
23. References, Journals, websites and E-links if any
24. Quality Measurement Sheets
a. Course End Survey
b. Teaching Evaluation
25. Student List
26. Group-Wise students list for discussion topics
Course coordinator HOD
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2. Syllabus
DIGITAL DESIGN
UNIT I: NUMBER SYSTEMS: Number Systems, Base Conversion Methods, Binary arithmetic,
Complements of Numbers, Codes-Binary Codes, Binary Coded Decimal (BCD) Code and its
Properties, Unit Distance Codes, Alpha Numeric Codes, Error Detecting and Correcting Codes.
Boolean Algebra and Switching Functions: Switching algebra, Basic Gates, Basic Theorems and
Properties, Switching Functions, Canonical and Standard Form, Algebraic Simplification of Digital
Logic Gates. Properties of XOR Gates, Universal Gates, Multilevel NAND/NOR realizations.
UNIT II: Minimization of switching functions: Introduction, Minimization with theorems, The
Karnaugh Map Method – Three, Four, Five and Six Variable maps. Prime Implicants and essential
Prime Implicants. Don’t care map entries, using the map for simplifying Boolean expressions, Tabular
method, partially specified expressions, Multi-output minimizations.
UNIT III: Design of Combinational Circuits: Adders, Subtractors, Multiplexers, Realization of

Switching Functions using Multiplexers, De-multiplexers, Decoders, Encoders, Priority Encoder,
Comparators, Parity Generators, Code Converters, Static Hazards and Hazard Free Realizations.
UNIT IV: Synthesis of Symmetric Networks: Relay Contacts, Analysis and Synthesis of Contact
Networks, Symmetric Networks, Identification of Symmetric Functions and realization of the same.
Threshold Logic: Threshold Element, Capabilities and Limitations of Threshold logic, Elementary
Properties, Synthesis of threshold networks (Unate function, Linear seperability, Identification and
realization of threshold functions, Map based synthesis of two-level Threshold networks).
UNIT V: Sequential Machines Fundamentals: Introduction, NAND/NOR latches, SR, JK, JK Master
slave, D and T Flip-flops, Excitation functions of SR, JK, JK Master Slave, D and T Flip-flops, State
table, State Diagram, State Assignment, Finite State Model - Basic Definitions. Synthesis of
Synchronous Sequential circuits - Sequence Detector, Serial Binary adder, Binary counter and Parity bit
generator.
Counters and Shift Registers: Ripple Counter, Shift Registers and their types, Ring Counters, Twisted
Ring Counters.
TEXT BOOKS:
1. “Switching and Finite Automata Theory”, Zvi Kohavi & Niraj K. Jha, 2nd Edition, 2009, Cambridge
University Press.
2. “Digital Design”, Morris Mano, PHl, 3rd Edition.
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3. Vision of the Department
To produce globally competent and socially responsible computer science engineers contributing to
the advancement of engineering and technology which involves creativity and innovation by
providing excellent learning environment with world class facilities.
4. Mission of the Department

1. To be a center of excellence in instruction, innovation in research and scholarship, and service to
the stake holders, the profession, and the public.
2. To prepare graduates to enter a rapidly changing field as a competent computer science engineer.
3. To prepare graduate capable in all phases of software development, possess a firm understanding
of hardware technologies, have the strong mathematical background necessary for scientific
computing, and be sufficiently well versed in general theory to allow growth within the discipline
as it advances.
4. To prepare graduates to assume leadership roles by possessing good communication skills, the
ability to work effectively as team members, and an appreciation for their social and ethical
responsibility in a global setting.
5. PROGRAM EDUCATIONAL OBJECTIVES (PEOs) OF C.S.E.

DEPARTMENT
1. To provide graduates with a good foundation in mathematics, sciences and engineering
fundamentals required to solve engineering problems that will facilitate them to find
employment in industry and / or to pursue postgraduate studies with an appreciation for lifelong
learning.
2. To provide graduates with analytical and problem solving skills to design algorithms, other
hardware / software systems, and inculcate professional ethics, inter-personal skills to work in a
multi-cultural team.
3. To facilitate graduates to get familiarized with the art software / hardware tools, imbibing
creativity and innovation that would enable them to develop cutting-edge technologies of multi-
disciplinary nature for societal development.
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PROGRAM OUTCOMES (CSE)
Program Outcomes
1. Engineering knowledge: Apply the knowledge of mathematics, science, engineering
fundamentals, and an engineering specialization to the solution of complex engineering
problems.
2. Problem analysis: Identify, formulate, review research literature, and analyze complex
engineering problems reaching substantiated conclusions using first principles of
mathematics, natural sciences, and engineering sciences.
3. Design/development of solutions : Design solutions for complex engineering problems

and design system components or processes that meet the specified needs with
appropriate consideration for the public health and safety, and the cultural, societal, and
environmental considerations.
4. Conduct investigations of complex problems: Use research-based knowledge and research

methods including design of experiments, analysis and interpretation of data, and synthesis of
the information to provide valid conclusions.
5. Modern tool usage: Create, select, and apply appropriate techniques, resources, and
modern engineering and IT tools including prediction and modeling to complex engineering
activities with an understanding of the limitations.
6. The engineer and society: Apply reasoning informed by the contextual knowledge to
assess societal, health, safety, legal and cultural issues and the consequent responsibilities
relevant to the professional engineering practice.
7. Environment and sustainability: Understand the impact of the professional engineering

solutions in societal and environmental contexts, and demonstrate the knowledge of, and
need for sustainable development.
8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and
norms of the engineering practice.
9. Individual and team work: Function effectively as an individual, and as a member or leader
in diverse teams, and in multidisciplinary settings.
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10. Communication: Communicate effectively on complex engineering activities with the
engineering community and with society at large, such as, being able to comprehend and write
effective reports and design documentation, make effective presentations, and give and receive
clear instructions.
11. Project management and finance: Demonstrate knowledge and understanding of the
engineering and management principles and apply these to one’s own work, as a
member and leader in a team, to manage projects and in multidisciplinary environments.
12. Life-long learning : Recognize the need for, and have the preparation and ability to
engage in independent and life-long learning in the broadest context of technological change.
6. Course Objectives and Outcomes

Course Objectives:
Develop ability to
1. Understand basic concepts of various number systems used in digital systems.

2. Understand Boolean algebra and various Boolean simplification theorems.
3. Understand simplification of Boolean functions using k-map and tabular method.
4. Understand design and analysis of combinational and sequential logic circuits.
5. Understand symmetric functions and design the same using relay contacts.
6. Understand Threshold logic and design switching functions using threshold elements.
Course Outcomes (COs):

At the end of the course, student would be able to
CO1. Perform conversions from one number system to another.

CO2. Simplify switching functions using Boolean minimization theorems, map method and tabulation
method.
CO3. Analyze and design combinational logic circuits and the effect of Static Hazards on these circuits.
CO4. Synthesize symmetric functions using relay contact networks.
CO5. Design switching circuits using threshold elements.
CO6. Analyze and Design Sequential logic Circuits.
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7. Brief importance of the Course and how it fits into the curriculum
a. What role does this course play within the Program?

 This course strengthens logical thinking, analysis and design capabilities of the students.
 This is a fundamental course which helps in understanding the subsequent courses, namely,
Computer Architecture and Organization.(Theory and lab).
b. How is the course unique or different from other courses of the Program?
 This is the only course wherein students learn the basic concepts of logic design, which is used
in all future Digital Systems courses and their applications.
 Another unique feature of the course is it promotes critical thinking and logical reasoning and
nothing needs to be remembered/memorized.
c. What essential knowledge or skills should they gain from this experience?
 Students acquire design capabilities of Combinational and Sequential logic circuits along with
their application so essential for design of all advanced digital systems.
d. What knowledge or skills from this course will students need to have mastered to perform
well in future classes or later (Higher Education / Jobs)?
 Analytical and design skills of combinational and sequential circuits, PLDs and Threshold logic
circuits.
e. Why is this course important for students to take?
 In order to understand all other digital systems, thorough comprehension of this course is
fundamental.
f. What is/are the prerequisite(s) for this course?
 Common sense and an inclination to think logically.
g. When students complete this course, what do they need know or be able to do?
 Able to design, analyze and evaluate the digital circuits.
h. Is there specific knowledge that the students will need to know in the future?
 In future, students have to apply these concepts in the design of systems that use
Microprocessors and Microcontrollers.
i. Are there certain practical or professional skills that students will need to apply in the future?
 YES. Some of the mini or major projects are generally required to design hardware circuits to
check the intended output/performance of the project.
j. Five years from now, what do you hope students will remember from this course?
 Analytical thinking and logical reasoning and techniques employed in the analysis and design
of digital systems.
k. What is it about this course that makes it unique or special?
 It is the only fundamental course that facilitates students in the attainment of all levels of
Bloom's taxonomy.
l. Why does the program offer this course?
 This is the basic course in Digital Design field. Without this course, students cannot design any
digital system
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 This course is a prerequisite for Computer Architecture and Organization.
m. Why can’t this course be “covered” as a sub-section of another course?
 It is not possible as it covers many topics such as different types of numbers systems, their
conversions, Boolean theorems, techniques used to design digital systems, logic design and
simplification, different types of combinational and Sequential circuits and if one tries to cover
these as part of another course, it would be too heavy to be taught in one semester.
n. What unique contributions to students’ learning experience does this course make?
 It helps in executing mini and major projects that involve digital systems during the later years
of the program.
o. What is the value of taking this course? How exactly does it enrich the program?
 This course plays a vital role in design and development of digital systems in the discipline of
Computer science and electronics and communication Engineering which is so essential and
useful to the development of society and this course also helps for the student’s professional
career growth in terms of professional career.
This course makes significant contributions to the following program outcomes:
 an ability to apply knowledge of mathematics, science, and engineering,
 an ability to design and conduct experiments, as well as to analyze and interpret data,
 an ability to design a system, component, or process to meet desired needs within
realistic constraints
 an ability to identify, formulate, and solve engineering problems,
 an ability to use the techniques, skills, and modern engineering tools necessary for
engineering practice.
p. What are the major career options that require this course
Digital system design, an advanced course for which Logic and switching theory course is a
pre-requisite and is key for many careers in engineering and technology. Specific occupations
that employ switching circuits include:
 ASIC design engineer
 Assembly language programmer
 VLSI design engineer
 Embedded systems designer
 Digital systems designer/engineer
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Scope
• The purpose of this course is that we:

 Learn what’s under the hood of an electronic component
 Learn the principles of digital design
 Learn to systematically debug increasingly complex designs
 Design and build a digital system
8. Prerequisites
NONE
9. Instructional Learning Outcomes

Learning outcomes are the key abilities and knowledge that will be assessed.
Unit - I
Number Systems
1. Introduction
The first part of this unit introduces the material to be studied later. In addition to getting an
overview of the material in the first part of the course, you would be able to explain
a. The difference between analog and digital systems and advantages of digital systems over
analog systems.
b. The difference between combinational and sequential circuits.
c. Why two-valued signals and binary numbers are commonly used in digital systems.
2. Number systems and conversion
When you complete this module, you would be able to solve the following types of problems.
a. Given a positive integer, fraction, or mixed number in any base (2 through 16); convert to any
other base. Justify the procedure used by using a power series expansion for the number.
b. Add, subtract, multiply, and divide positive binary numbers. Explain the addition and
subtraction process in terms of carries and borrows.
c. Write negative binary numbers in signed magnitude, 1s / 9s complement, and 2s / 10s
complement forms. Add signed binary numbers using 1s / 9s complement, and 2s / 10s
complement arithmetic. Justify the methods used. State when an overflow occurs.
3. Codes and Conversion
1. Represent a decimal number in binary-coded-decimal (BCD), (6, 4, 2, -3) code, (2, 4, 2, 1)
code, excess-3 code, Gray code, (8, 4, -2, -1) code etc. Given a set of weights, construct a
weighted code. Explain self-complementing codes.
2. Explain error detecting code such as Parity bit and error correcting code such as hamming code.
Given a data word, and during its transmission, if it is corrupted producing a single bit error,
detect the error and correct it using Hamming code.
Boolean Algebra and Switching Functions
A list of 15 laws and theorems of Boolean algebra is given in this unit. When you complete this unit,
you should be familiar with and be able to use any of these laws. Specifically, you would be able to
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1. Explain the basic operations and laws of Boolean algebra.
2. Relate these operations and laws to circuits composed of AND gates, OR gates, and inverters.
Also relate these operations and laws to circuits composed of switches.
3. Prove any of the theorems using a truth table or give an algebraic proof if appropriate.
4. Apply these laws to the manipulation of algebraic expressions including:
a. Multiplying out an expression to obtain a sum of products.
b. Factoring an expression to obtain a sum of products.
c. Simplifying an expression by applying these laws.
d. Finding the complement of an expression.
5. Define the exclusive – OR and equivalence operations. State, prove, and use the Boolean
identities that concern operations.
6. Use the consensus theorem to delete terms from and add terms to a switching expression.
7. Given an equation, prove algebraically that it is valid or show that it is not valid.
Unit- II
Minimization of Switching Functions
When you complete this unit, you would be able to do the following.
1. Given a word description of the desired behavior of a logic circuit, write the output of the
circuit as a function of the input variables. Specify this function as an algebraic expression or by
means of a truth table, as is appropriate.
2. Given a truth table, write the function (or its complement) as both a minterm expansion
(standard sum or products) and a maxterm expansion (standard product of sums). Be able to use
both alphabhetic and decimal notation.
3. Given an algebraic expression for a function, expand it algebraically to obtain the minterm or
maxterm form.
4. Given one of the following minterm expansion for F, minterm expansion for F’, maxterm
expansion for F, or maxterm expansion for F’, find any of the other three forms.
5. Write the general form of the minterm and maxterm expansion of a function of n variables.
6. Explain why some functions contain “don’t care” or "optional" terms.
Karnaugh Maps
1. Given a function (completely or incompletely specified) of three to five variables, plot it on a
Karnagh map. The function may be given in minterm, maxterm, or algebraic form.
2. Determine the essential prime implicants of a function from a map.
3. Obtain the minimum sum-of-products or minimum product-of-sums form of a function from the
map.
4. Determine all of the prime implicants of a function from a map.
5. Understand the relation between operations performed using the map and the corresponding
algebraic operations.
Quine-McCluskey Method
1. Find the prime implicants of a function by using the Quine-McCluskey method. Explain the
reasons for the procedures used.
2. Define prime implicant.
3. Given the prime implicants, find the essential prime implicants and a minimum sum-of-
products expression for a function, using a prime implicants chart.
4. Minimize an incompletely specified function, using the Quine-McCluskey method.
5. Find a minimum sum-of-products expression for a function, using the method of map-entered
variables.
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Unit-III
Combinational Logic Circuit Design
1. Explain the operation of a Half adder and a Half subtractor and derive logic equations for these
modules and realize the same.
2. Explain the operation of a full adder and a full subtractor and derive logic equations for these
modules and realize the same.
3. Draw a block diagram for a parallel adder or subtractor.
4. Design a 4-bit Carry Look ahead adder
5. Design BCD adder.
6. Design a minimal two-level or multi-level circuit of AND and OR gates to realize a given
function. (Consider both circuits with an OR gate at the output and circuits with an AND gate at
the output.)
7. Design or analyze a two-level gate circuit using any one of the four basic forms (AND-OR,
NAND-NAND, OR-AND, NOR-NOR).
8. Analyze and design multi-level NAND-gate or NOR-gates, and conversely, by adding or
deleting inversion bubbles.
9. Convert circuits of AND and OR gates to circuits of NAND gates or NOR gates, and
conversely, by adding or deleting inversion bubbles.
10. Design a minimal two-level, multiple-output AND-OR, OR-AND, NAND-NAND, or NOR-
NOR circuit using Karnaugh maps.
11. Explain the function of multiplexer. Implement multiplexer using logic gates.
12. Explain the operation of a decoder, encoder and priority encoder. Realize the same using logic
gates.
13. Use a decoder with added gates to implement a set of logic functions.
14. Use a multiplexer to implement a logic function.
15. Design BCD to Seven segment display circuit.
16. Define Static-0 and Static-1 Hazards. Given a combinational circuit, find all of the static 0 – and
1-hazards. For each hazard, specify the order in which the gate outputs must switch in order for
the hazard to actually produce a false output.
17. Given a switching function, realize it using a two-level circuit which is free of static and
dynamic hazards (for single input variable changes).
Unit-IV
Synthesis of Symmetric Networks
When you complete this module, you would be able to do the following:
1. Define and explain symmetric functions and their properties.
2. Synthesize symmetric networks using relay contacts.
3. Identify symmetric functions and synthesize the same using relay contacts.
Threshold Logic
When you complete this module, you would be able to do the following
1. Explain the logic of threshold gate and its impact on logic design.
2. Explain the capabilities and limitations of Threshold Logic in realizing switching functions.
3. Explain Unate functions, and linear separability. Identify Unate functions and apply the same
along with linear separability to Threshold logic.
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4. Explain the incredible power of Threshold gate (in realizing switching functions) that can
replace a large number of conventional logic gates by realizing switching functions using single
and multiple threshold gates.
Unit – V
Sequential Machine Fundamentals
1. Distinguish clearly between Synchronous and Asynchronous Sequential Circuits
2. Explain the operation of S-R and gated latches which are used as memory elements that are basic
building blocks in sequential circuits.
3. Explain the operation of D, S-R, J-K, and T flip-flops and convert from the other.
4. Make a table and derive the characteristics (next-state) equation for such latches and flip-flops.
State any necessary restrictions on the input signals.
5. Show how latches and flip-flops can be constructed using gates. Analyze the operation of a flip-
flop that is constructed of gates and latches.
6. Explain the operation of binary counters. Show how to build them using flip-flops and gates, and
analyze their operation.
7. Given the present state and desired next state of a flip-flop, determine the required flip-flop
inputs.
8. Given the desired counting sequence for a counter, derive the flip-flop input equations.
9. Explain the procedures used for deriving flip-flop input equations.
10. Construct a timing diagram for a counter.
11. Design a sequence detector, serial binary adder and parity bit generator, and realize the same
using hardware.
12. Given a sequential circuit, write the next-sate equations for the flip-flops and derive the state
graph or state table. Using the state graph, determine the state sequence and output sequence for a
given input sequence.
Counters and Shift Registers:
1. Design of ripple counter using different types of flip-flops.
2. Explain the operation of shift registers, show how to build them using flip-flops, and analyze their
operation. Construct a timing diagram for a shift register.
3. Design ring counter and twisted ring counter using shift registers.
10. DD COURSE MAPPING WITH PEOs AND POs
Mapping of Course with Programme Educational Objectives
S.No Course code Semester PEO 1 PEO 2 PEO 3
1 DD 18EC2102 I √ √ -
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Mapping of Course outcomes with Programme outcomes:
*When the course outcome weightage is < 40%, it will be given as moderately correlated (L).
*When the course outcome weightage is >40 &< 60%, it will be given as moderately correlated (M).
*When the course outcome weightage is >60%, it will be given as strongly correlated (H).
POs 1 2 3 4 5 6 7 8 9 10 11 12
STLD
CO 1: H H H - - - - - M M M M
CO 2: H H H M M L - - M M M M
CO 3: H H H M M L - - M M M M
CO 4: H H H - - - - - M M M M
CO 5: H H H - - - - - M M M M
CO 6: H H H - - - - - M M H H
11. Class Time Table
12. Individual Time Table
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13. Lecture schedule with methodology being used/adopted
Methodology Adopted or Used:
No. of Teaching
S. No. Unit No. Topic Covered
Periods Aids
1. PART-A: Number Systems Number Systems 1 BB
2. Base Conversion Methods 2 BB
3. Binary arithmetic 1 BB
4. Complements of Numbers 1 BB
Codes-Binary Codes,
5. 1 BB
Binary Coded Decimal (BCD) Code and its Properties,
7. Unit Distance Codes, Alpha Numeric Codes 1 BB
8. Error Detecting and Correcting Codes 2 BB
9. UNIT-1 PART-B: Boolean Algebra and Switching Functions: Switching algebra 1 BB
10. Basic Theorems and Properties 2 BB
11. Switching Functions 2 BB
12. Canonical and Standard Form 2 BB
13. Algebraic Simplification of Digital Logic Gates 2 BB
14. Properties of XOR Gates, Universal Gates, 2 BB
15. Multilevel NAND/NOR realizations. 2 OHP
Minimization of switching functions
16. 2 BB
Introduction, The Minimization with theorem.
17. The Karnaugh Map Method – Four, Five and six Variable maps. 2 OHP
18. UNIT-2 Prime and essentials implicants. 2 BB
19. Don’t care map entries, using maps for simplifying 1 BB
20. Tabular method, partially specified expressions. 2 BB
Design of Combinational Circuits
21. 2 BB
Design using Conventional Logic gates: Data Selector, Adders
22. Encoders, Priority Encoder, 1 OHP
23. Decoders, Comparators 1 OHP
UNIT-3
Multiplexers, De-multiplexers, realization of switching functions using
24. 2 OHP / PPT
MUX,
25. Parity generators and code converters. 1 BB
26. Multi-output minimizations, Hazards and Hazard Free Realizations. 1 BB
PART-A :Synthesis of Symmetric Networks:
27. 2 BB
Relay Contacts, Analysis and Synthesis of Contact Networks.
28. Symmetric Networks 1 BB
29. Identification of Symmetric Functions. 1 BB
UNIT-4 PART-B:Threshold Logic:
30. 1 BB
Threshold Elements, Capabilities and Limitations of Threshold logic
Elementary Properties, Synthesis of threshold networks (Unate Functions,
31. Linear Seperability, Identification and realization of threshold functions, 2 PPT
Map based synthesis of two level networks).
PART-A: Sequential Machines Fundamentals:
32. Introduction, State table, State Assignment, Finite State Model-Basic 1 BB
Definitions.
33. Memory Elements and their Excitation Functions-SR flip-flop 1 BB
34. JK flip-flop 1 BB
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No. of Teaching
S. No. Unit No. Topic Covered
Periods Aids
35. T flip-flop, D flip-flop, 1 BB
36. Clock timing and Master Slave flip-flop. 1 OHP / PPT
37. Synthesis of Synchronous Sequential circuits-Sequence Detector 1 OHP / PPT
38. Binary counter, Parity bit generator. 1 OHP / PPT
39. PART-B: Counters and Shift Registers: Ripple Counter, Ring Counters 1 BB/ Video
UNIT-5
40. Twisted Ring Counter 1 BB/ Video
41. Shift Registers and their types 1 BB/ Video
42. Ring Counter using Shift Register 1 BB/ Video
Total number of Classes required 60
BB – Black Board
PPT - Power Point Presentation
Video- Video Lecture
(B) Micro plan

Text/ Remarks
Unit No. of Teaching
S.No. Topic Covered Reference
No. Periods Aids
Book
1. PART-A: Number Systems Number Systems 1 BB T1, 1.1
2. Base Conversion Methods 2 BB T1,1.1
3. Binary arithmetic 1 BB T1, 1.1
4. Complements of Numbers 1 BB T2, 1.5
Codes-Binary Codes, T1, 1.2
5. Binary Coded Decimal (BCD) Code and its Properties,
1 BB
T2, 1.7
7. Unit Distance Codes, Alpha Numeric Codes 1 BB T2, 1.7
T1, 1.3
8. Error Detecting and Correcting Codes 2 BB &
T2, 7.4
9. Tutotial 1
UNIT PART-B: Boolean Algebra and Switching Functions:
10. Switching algebra
1 BB T1, 3.1
-1
T1, 3.1
11. Basic Theorems and Properties 2 BB &
T2, 2.3
12. Switching Functions 1 BB T1, 3.2
13. Canonical and Standard Form 1 BB T2, 2.5
14. Tutotial 1
15. Algebraic Simplification of Digital Logic Gates 1 BB T2, 2.4
16. Properties of XOR Gates, Universal Gates, 1 BB T1, 3.2
17. Multilevel NAND/NOR realizations. 1 OHP T2, 3.6
18. Tutotial 1
19. Revision of Unit I 1
UNIT Minimization of switching functions
20. -2 Introduction, The Minimization with theorem.
2 BB T1, 4.1,
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Text/ Remarks
No. Periods Aids
Book
T1, 4.2
&
21. The Karnaugh Map Method, Five and six Variable maps. 2 OHP
T2, 3.1, 3.2,
3.3
T1, 4.2
22. Prime and essentials implicants. 2 BB &
T2 3.2
23. Tutorial 1
24. Don’t care map entries, using the maps for simplifying 1 BB T1, 4.2
25. Tabular method, partially specified expressions. 2 BB T1,4.4, 4.5
26. Tutorial and Revision 2
PART-A: Design of Combinational Circuits T1, 5.2, 5.4
27. Design using Conventional Logic gates: Data Selector, 1 BB &
Adders T2, 4.4
T1, 5.2
28. Encoders, Priority Encoder, 1 OHP &
T2, 4.9
T1, 5.2
29. UNIT Decoders, Comparators 1 OHP &
-3 T2 4.8, 4.7
Multiplexers, De-multiplexers, realization of switching OHP /
30. functions using MUX
2
PPT
T2 4.10
31. I MID ECAMINATIONS 1

32. Parity generators and code converters. 1 BB T2, 3.8, 4.3
Multi-output minimizations, Hazards and Hazard Free
33. Realizations.
1 BB T2, 9.7
34. Tutorial 1
PART-A :Synthesis of Symmetric Networks:
35. Relay Contacts, Analysis and Synthesis of Contact 2 BB T1, 5.5, 5.6
Networks.
36. Symmetric Networks 1 BB T1, 6.2
37. Identification of Symmetric Functions. 1 BB T1, 6.3
UNIT PART-B:Threshold Logic:
38. -4 Threshold Elements, Capabilities and Limitations of 1 BB T1, 7.1
Threshold logic
Elementary Properties, Synthesis of threshold networks
(Unate Functions, Linear Seperability, Identification and
39. realization of threshold functions, Map based synthesis
2 PPT T1, 7.2
of two level networks).
40. PART-A: Sequential Machines Fundamentals: T1, 9.1, 9.2
Introduction, State table, State Assignment, Finite State 1 BB &
Model-Basic Definitions. T2, 5.4
41. Tutorial 1
T1, 9.3
Memory Elements and their Excitation Functions-SR
42. flip-flop
1 BB &
UNIT T2, 5.3
-5 JK flip-flop 1 BB T1, 9.3
43.
&
T2, 5.3
44. T flip-flop, D flip-flop, 1 BB T1, 9.3
&
T2, 5.3
45. Clock timing and Master Slave flip-flop. 1 OHP / T1, 9.3
PPT &
T2, 5.3
Page 17 of 191
Text/ Remarks
No. Periods Aids
Book
T1, 9.4
Synthesis of Synchronous Sequential circuits-Sequence OHP /
46. Detector
1
PPT
&
T2, 5.7
T1, 9.3
OHP /
47. Binary counter, Parity bit generator. 1
PPT
&
T2, 5.7, 6.4
48. Tutorial 1
PART-B: Counters and Shift Registers: Ripple
49. Counter, Ring Counters
1 BB/ Video T2, 6.3, 6.5
50. Twisted Ring Counter 1 BB/ Video T2, 6.5

51. Shift Registers and their types 1 BB/ Video T2, 6.1, 6.2
52. Ring Counter using Shift Register 1 BB/ Video T2, 6.5
53. Tutorial and Revision 1
54. REVISION and DISCUSSION 4
14. Detailed Notes

Unit-I
Part A: Number System
Number Systems
Convenient as the decimal number system generally is, its usefulness in machine computation is
limited because of the nature of practical electronic devices. In most present digital machines, the
numbers are represented, and the arithmetic operations performed, in a different number system called
the binary number system. This section is concerned with the representation of numbers in various
systems and with methods of conversion from one system to another.
Number Representation
An ordinary decimal number actually represents a polynomial in powers of 10.For example, the
number 123.45 represents the polynomial
123.45 = 1 × 102 + 2 × 101 + 3 × 100 + 4 × 10−1 + 5 × 10−2.
This method of representing decimal numbers is known as the decimal number system, and the number
10 is referred to as the base (or radix) of the system. In a system whose base is b, a positive number N
represents the polynomial
where the base b is an integer greater than 1 and the a’s are integers in the range 0 ≤ ai ≤ b − 1. The
sequence of digits aq−1aq−2 · · · a0 constitutes the integer part of N, while the sequence a−1a−2 · · · a−p
constitutes the fractional part of N . Thus, p and q designate the number of digits in the fractional and
integer parts, respectively. The integer and fractional parts are usually separated by a radix point. The
digit a−p is referred to as the least significant digit while aq−1 is called the most significant digit.
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When the base b equals 2, the number representation is referred to as the binary number system. For
example, the binary number 1101.01 represents the polynomial
1101.01 = 1 × 23 + 1 × 22 + 0 × 21 + 1 × 20 + 0 × 2−1 + 1 × 2−2,

that is,
1101.01 = ∑ai2i
where i = -2 to 3, a−2 = a0 = a2 = a3 = 1 and a−1 = a1 = 0.
A number N in base b is usually denoted (N)b. Whenever the base is not specified, base 10 is implicit.
Below table shows the representations of integers 0 through 15 in several number systems.
The complement of a digit a, denoted a’ , in base b is defined as

a' = (b − 1) − a.
That is, the complement a is the difference between the largest digit in base b and digit a. In the binary
number system, since b = 2, 0 = 1 and 1 = 0.
In the decimal number system, the largest digit is 9. Thus, for example, the complement 1 of 3 is 9 − 3 =
6.
Base Conversion Methods
Suppose that some number N , which we wish to express in base b2, is presently expressed in base b1.
In converting a number from base b1 to base b2, it is convenient to distinguish between two cases. In the
first case b1 < b2, and consequently base-b2 arithmetic can be used in the conversion process. The
conversion technique involves expressing number (N )b1 as a polynomial in powers of b1 and evaluating
the polynomial using base-b2 arithmetic.
When b1 > b2 it is more convenient to use base-b1 arithmetic. The conversion procedure will be
obtained by considering separately the integer and fractional parts of N . Let (N )b1 be an integer whose
value in base b2 is given by:
To find the values of the a’s, let us divide the above polynomial by b2.
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Thus, the least significant digit of (N )b2 , i.e., a0, is equal to the first remainder. The next most
significant digit, a1, is obtained by dividing the quotient Q0 by b2, i.e.,
The remaining a’s are evaluated by repeated divisions of the quotients until Qq−1 is equal to zero. If N is
finite, the process must terminate.
If (N )b1 is a fraction, a dual procedure is employed. It can be expressed in base b2 as follows:

(N )b1 = a−1b2−1 + a−2b2−2 + · · · + a−p b2−p .
The most significant digit, a−1, can be obtained by multiplying the polynomial by b2:
b2 · (N )b1 = a−1 + a−2b2−1 + · · · + a−p b2−p+1.
If the above product is less than 1 then a−1 equals 0; if the product is greater than or equal to 1 then a−1
is equal to the integer part of the product. The next most significant digit, a−2, is found by multiplying
the fractional part of the above product part by b2 and determining its integer part; and so on. This
process does not necessarily terminate since it may not be possible to represent the fraction in base b2
with a finite number of digits.
Example We wish to express the numbers (432.2)8 and (1101.01)2 in base 10. Thus
(432.2)8 = 4 × 82 + 3 × 81 + 2 × 80 + 2 × 8−1 = (282.25)10,
(1101.01)2 = 1 × 23 + 1 × 22 + 0 × 21 + 1 × 20 + 0×2−1 + 1 × 2−2 = (13.25)10.
In both cases, the arithmetic operations are done in base 10.
Example The above conversion procedure is now applied to convert (548)10 to base 8. The ri in the
table below denote the remainders. The first entries in the table are 68 and 4, corresponding,
respectively, to the quotient Q0 and the first remainder from the division (548/8)10. The remaining
entries are found by successive division.
Thus, (548)10 = (1044)8. In a similar manner we can obtain the conversion of (345) 10 to (1333)6, as
illustrated in the table below.
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Indeed, (1333)6 can be reconverted to base 10, i.e.,
(1333)6 = 1 × 63 + 3 × 62 + 3 × 61 + 3 × 60 = 345
Example To convert (0.3125)10 to base 8, find the digits as follows:
Thus (0.3125)10 = (0.24)8.

Similarly, the computation below proves that (0.375)10 = (0.011)2:
Example To convert (432.354)10 to binary, we first convert the integer part and then the fractional part.
For the integer part we have
Hence (432)10 = (110110000)2. For the fractional part we have
Consequently (0.354)10 = (0.0101101 · · ·)2. The conversion is usually car-ried up to the desired
accuracy. In our example, reconversion to base 10 shows that
(110110000.0101101)2 = (432.3515)10
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A considerably simpler conversion procedure may be employed in converting octal numbers (i.e.,
numbers in base 8) to binary and vice versa. Since 8 = 23, each octal digit can be expressed by three
binary digits. For example, (6)8 can be expressed as (110)2, etc. The procedure of converting a binary
number into an octal number consists of partitioning the binary number into groups of three digits,
starting from the binary point, and to determine the octal digit corresponding to each group.
Example
(123.4)8 = (001 010 011.100)2,
(1010110.0101)2 = (001 010 110.010 100) = (126.24)8.
A similar procedure may be employed in conversions from binary to hexa-decimal (base 16), except
that four binary digits are needed to represent a single hexadecimal digit. In fact, whenever a number is
converted from base b1 to base b2, where b2 = b1k , k digits of that number when grouped may be
represented by a single digit from base b2.
Binary Arithmetic
The binary number system is widely used in digital systems. Although a detailed study of digital
arithmetic is beyond the scope of this book, we shall present the elementary techniques of binary
arithmetic. The basic arithmetic operations are summarized in Table 1.2, where the sum and carry,
difference and borrow, and product are computed for every combination of binary digits (abbreviated
bits) 0 and 1.
Binary addition is performed in a manner similar to that of decimal addition. Corresponding bits are
added and if a carry 1 is produced then it is added to the binary digits at the left.
Example The addition of (15.25)10 and (7.50)10 in binary proceeds as follows:
In subtraction, if a borrow of 1 occurs and the next left digit of the minuend (the number from which a
subtraction is being made) is 1 then the latter is changed to 0 and subtraction is continued in the usual
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manner. If, however, the next left digit of the minuend is 0 then it is changed to 1, as is each successive
minuend digit to the left which is equal to 0. The first minuend digit to the left, which is equal to 1, is
changed to 0, and subtraction is continued.
Example The subtraction of (12.50)10 from (18.75)10 in binary proceeds as follows:
Just as with decimal numbers, the multiplication of binary numbers is per-formed by successive
addition while division is performed by successive sub-traction.
Example Multiply the binary numbers below:
Example Divide the binary number 1000100110 by 11001.
Complements of Numbers
In digital computers to simplify the subtraction operation and for logical manipulation complements are
used. There are two types of complements for each radix system: The radix complement and
diminished radix complement. The first is referred as the r’s complement and the second as the (r-1)’s
complement. For example, in binary system we substitute base vale 2 in place of r to refer
complements as 2’s complement and 1’s complement. In decimal number system, we substitute base
value 10 in place of r to refer complements as 10’s complement and 9’s complement.
Advantage of performing subtraction by the compliment method is reduction in the hardware.( instead
of addition and subtraction, only adding circuit‘s are needed.) i.e, subtraction is also performed by
Page 23 of 191
adders only. Instead of subtracting one number from other, the compliment of the subtrahend is added
to minuend. In sign magnitude form, an additional bit called the sign bit is placed in front of the
number. If the sign bit is 0, the number is positive, If it is a 1, the number is negative.
1’s Complement Representation:

The 1’s complement of a binary number is the number that results when we change all 1’s to zeros and
the zeros to ones.
2’s Complement Representation:

The 2’s complement is the binary number that results when we add 1 to the 1’s complement. It is given
as:
2’s Complement = 1’s Complement + 1
The 2’s complement is used to represent negative numbers.
Codes
 Binary Codes
Although the binary number system has many practical advantages and is widely used in digital
computers, in many cases it is convenient to work with the decimal number system, especially
when the communication between human being and machine is extensive, since most numerical
data generated by humans is in terms of decimal numbers. To simplify the problem of
communication between human and machine, several codes have been devised in which decimal
digits are represented by sequences of binary digits.
Weighted codes
In order to represent the 10 decimal digits 0, 1, . . . , 9, it is necessary to use at least four binary
digits. Since there are 16 combinations of four binary digits, of which 10 combinations are used, it
is possible to form a very large number of distinct codes. Of particular importance is the class of
weighted codes, whose main characteristic is that each binary digit is assigned a decimal “weight,”
and, for each group of four bits, the sum of the weights of those binary digits whose value is 1 is
equal to the decimal digit which they represent. If w1, w2, w3, and w4 are the given weights of the
binary digits and x1, x2, x3, x4 the corresponding digit values then the decimal digit N = w4x4 + w3x3
+ w2x2 + w1x1 can be represented by the binary sequence x4x3x2x1. The sequence of binary digits that
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represents a decimal digit is called a code word. Thus, the sequence x4x3x2x1 is the code word for
N . Three weighted four-digit binary codes are shown in Table 1.3.
The binary digits in the first code in Table 1.3 are assigned weights 8, 4, 2, 1. As a result of this
weight assignment, the code word that corresponds to each decimal digit is the binary equivalent of
that digit; e.g., 5 is represented by 0101, and so on. This code is known as the binary-coded-
decimal (BCD) code. For each code in Table 1.3, the decimal digit that corresponds to a given code
word is equal to the sum of the weights in those binary positions that are 1’s rather than 0’s. Thus,
in the second code, where the weights are 2, 4, 2, 1, decimal 5 is represented by 1011,
corresponding to the sum 2 × 1 + 4 × 0 + 2 × 1 + 1 × 1 = 5. The weights assigned to the binary
digits may also be negative, as in the code (6, 4, 2, −3). In this code, decimal 5 is represented by
1011, since 6 × 1 + 4 × 0 + 2 × 1 − 3 × 1 = 5.
It is apparent that the representations of some decimal numbers in the (2, 4, 2, 1) and (6, 4, 2, −3)
codes are not unique. For example, in the (2, 4, 2, 1) code, decimal 7 may be represented by 1101
as well as 0111. Adopting the representations shown in Table 1.3 causes the codes to become self-
complementing. A code is said to be self-complementing if the code word of the “9’s complement of
N ”, i.e., 9 − N , can be obtained from the code word of N by interchanging all the 1’s and 0’s. For
example, in the (6, 4, 2, −3) code, decimal 3 is represented by 1001 while decimal 6 is represented
by 0110. In the (2, 4, 2, 1) code, decimal 2 is represented by 0010 while decimal 7 is represented by
1101. Note that the BCD code (8, 4, 2, 1) is not self-complementing. It can be shown that a
necessary condition for a weighted code to be self-complementing is that the sum of the weights
must equal 9. There exist only four positively weighted self-complementing codes, namely, (2, 4, 2,
1), (3, 3, 2, 1), (4, 3, 1, 1), and (5, 2, 1, 1). In addition, there exist 13 self-complementing codes
with positive and negative weights.
Nonweighted codes
There are many nonweighted binary codes, two of which are shown in Table 1.4. The Excess-3
code is formed by adding 0011 to each BCD code word.
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Thus, for example, the representation of decimal 7 in Excess-3 is given by 0111 + 0011 = 1010.
The Excess-3 code is self-complementing and possesses a number of properties that made it
practical in early decimal computers.
In many practical applications, e.g., analog-to-digital conversion, it is desirable to use codes in
which the code words for successive decimal integers differ in only one digit. Codes that have
such a property are referred to as cyclic codes. The second code in Table 1.4 is an example of such
a code. (Note that in this, as in all cyclic codes, the code word representing the decimal digits 0
and 9 differ in only one digit.) A particularly important cyclic code is the Gray code. A four-bit
Gray code is shown in Table 1.5.
The feature that makes this cyclic code useful is the simplicity of the procedure for converting from the
binary number system into the Gray code, as follows.
Let gn · · · g2g1g0 denote a code word in the (n + 1)th-bit Gray code, and let bn · · · b2b1b0 designate the
corresponding binary number, where the subscripts 0 and n denote the least significant and most significant
digits, respectively. Then, the ith digit gi can be obtained from the corresponding binary number as follows:
gi = bi ⊕ bi+1, 0 ≤ i ≤ n − 1,
gn = bn,
where the symbol ⊕ denotes the modulo-2 sum, which is defined as follows:
For example, the Gray code word that corresponds to the binary number 101101 is found to be 111011 in a manner indicated
in the following diagram:
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Thus, to convert from Gray code to binary, start with the leftmost digit and proceed to the least significant
digit, setting bi = gi if the number of 1’s preceding gi is even and setting bi = gi if the number of 1’s
preceding gi is odd. (Note that zero 1’s counts as an even number of 1’s.) For example, the Gray code word
1001011 represents the binary number 1110010. The proof that the preceding conversion procedures does
indeed work is left to the reader as an exercise.
The n-bit Gray code is a member of a class called reflected codes. The term “reflected” is used to designate
codes which have the property that the n-bit code can be generated by reflecting the (n − 1)th-bit code, as
illustrated in Fig. 1.1. The two-bit Gray code is shown in Fig. 1.1a. The three-bit Gray code (Fig. 1.1b) can
be obtained by reflecting the two-bit code about an axis at the end of the code and assigning a most
significant bit of 0 above the axis and 1 below the axis. The four-bit Gray code is obtained in the same
manner from the three-bit code, as shown in Fig. 1.1c.
Fig. 1.1 Refection of Gray Code
 Binary Coded Decimal Code and its Properties

Binary Coded Decimal or BCD as it is more commonly called, is another process for converting
decimal numbers into their binary equivalents.
The advantage of the Binary Coded Decimal system is that each decimal digit is represented by a
group of 4 binary digits or bits in much the same way as Hexadecimal. So for the 10 decimal digits
(0-to-9) we need a 4-bit binary code. Binary coded decimalis not the same as hexadecimal.
Whereas a 4-bit hexadecimal number is valid up toF16representing binary11112, (decimal 15),
binary coded decimal numbers stop at binary10012. This means that although 16 numbers (24) can
be represented using four binary digits, in the BCD numbering system the six binary code
combinations of:1010(decimal 10),1011(decimal 11),1100(decimal 12),1101(decimal
13),1110(decimal 14), and1111(decimal 15) are classed as forbidden numbers and can not be used.
The main advantage of binary coded decimal is that it allows easy conversion between decimal
(base-10) and binary (base-2) form. However, the disadvantage is that BCD code is wasteful as the
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states between1010 (decimal 10), and1111(decimal 15) are not used. Nevertheless, binary coded
decimal has many important applications especially using digital displays.
In the BCD numbering system, a decimal number is separated into four bits for each decimal digit
within the number. Each decimal digit is represented by its weighted binary value performing a
direct translation of the number. So a 4-bit group represents each displayed decimal digit from0000
for a zero to1001for a nine.
So for example,35710(Three Hundred and Fifty Seven) in decimal would be presented in Binary
Coded Decimal as:
35710=0011 0101 0111(BCD)

Then we can see that BCD uses weighted codification, because the binary bit of each 4-bit group
represents a given weight of the final value. In other words, the BCD is a weighted code and the
weights used in binary coded decimal code are8,4,2,1, commonly called the8421 codeas it forms
the 4-bit binary representation of the relevant decimal digit.
Binary Coded Decimal Representation of a Decimal Number
Then the relationship between decimal (denary) numbers and weighted binary coded decimal digits
is given below.
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 Unit Distance Codes
Gray code is a non-weighted code & is not suitable for arithmetic operations. It is not a BCD code .
It is a cyclic code because successive code words in this code differ in one bit position only i.e, it is
a unit distance code. It is also a reflective code i.e, both reflective & unit distance.
 Alpha Numeric Codes

These codes are used to encode the characteristics of alphabet in addition to the decimal digits. It is
used for transmitting data between computers & its I/O device such as printers, keyboards & video
display terminals. Popular modern alphanumeric codes are ASCII code & EBCDIC code.
 Error Detecting and Correcting Codes

In the codes presented so far, each code word consists of four binary digits, which is the minimum
number needed to represent the 10 decimal digits. Such codes, although adequate for the
representation of decimal digits, are very sensitive to the transmission errors that may occur
because of equipment failure or noise in the transmission channel. In any practical system there is
always a finite probability of occurrence of a single error. The probability that two or more errors
will occur simultaneously, although nonzero, is substantially smaller. We, therefore, restrict our
discussion mainly to the detection and correction of single errors.
Error-detecting codes
In a four-bit binary code, the occurrence of a single error in one of the binary digits may result in
another, incorrect but valid, code word. For example, in the BCD code (see above), if an error
occurs in the least significant digit of 0110 then the code word 0111 results and, since it is a valid
code word, it is incorrectly interpreted by the receiver. If a code possesses the property that the
occurrence of any single error transforms a valid code word into an invalid code word, it is said to
be a (single-)error-detecting code. Two error-detecting codes are shown in Table 1.6.
Error detection in either code in Table 1.6 is accomplished by a parity check. The basic idea in a
parity check is to add an extra digit to each code word of a given code so as to make the number of
1’s in each code word either odd or even. In the codes of Table 1.6 we have used even parity. The
even-parity BCD code is obtained directly from the BCD code of Table 1.3. The added bit, denoted
p, is called the parity bit. The 2-out-of-5 code consists of all 10 possible combinations of two 1’s in
a five-bit code word. With the exception of the code word for decimal 0, the 2-out-of-5 code of
Table 1.6 is a weighted code and can be derived from the (1, 2, 4, 7) code.
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In each of the codes in Table 1.6 the number of 1’s in a code word is even. Now, if a single error
occurs it transforms the valid code word into an invalid one, thus making the detection of the error
straightforward. Although parity check is intended only for the detection of single errors, it, in fact,
detects any odd number of errors and some even numbers of errors. For example, if the code word
10100 is received in an even-parity BCD message, it is clear that the message is erroneous, since
such a code word is not defined although the parity check is satisfied. We cannot determine,
however, the original transmitted word.
In general, to obtain an n-bit error-detecting code, no more than half the possible 2 n combinations
of digits can be used. The code words are chosen in such a manner that, in order to change one
valid code word into another valid code word, at least two digits must be complemented. In the case
of four-bit codes this constraint means that only eight valid code words can be formed of the 16
possible combinations. Thus, to obtain an error-detecting code for the 10 decimal digits, at least
five binary digits are needed. It is useful to define the distance between two code words as the
number of digits that must change in one word so that the other word results. For example, the
distance between 1010 and 0100 is three, since the two code words differ in three bit positions. The
minimum distance of a code is the smallest number of bits in which any two code words differ.
Thus, the minimum distance of the BCD or the Excess-3 codes is one, while that of the codes in
Table 1.6 is two. Clearly, a code is an error-detecting code if and only if its minimum distance is
two or more.
Error-correcting codes
For a code to be error-correcting, its minimum distance must be further increased. For example,
consider the three-bit code which consists of only two valid code words, 000 and 111. If a single
error occurs in the first code word, it could become 001, 010, or 100. The second code word could
be changed by a single error to 110, 101, or 011. Note that in each case the invalid code words are
different. Clearly, this code is error-detecting since its minimum distance is three. Moreover, if we
assume that only a single error can occur then this error can be located and corrected, since every
error results in an invalid code word that can be associated with only one of the valid code words.
Thus, the two code words 000 and 111 constitute an error-correcting code whose minimum distance
is three. In general, a code is said to be error-correcting if the correct code word can always be
deduced from the erroneous word. In this section, we shall discuss a type of single-error-correcting
codes known as Hamming codes.
If the minimum distance of a code is three, then any single error changes a valid code word into an
invalid one, which is distance one away from the original code word and distance two from any
other valid code word. Therefore, in a code with minimum distance three, any single error is
correctable or any double error detectable. Similarly, a code whose minimum distance is four may
be used for either single-error correction and double-error detection or triple-error detection. The
key to error correction is that it must be possible to detect and locate erroneous digits. If the
location of an error has been determined then, by complementing the erroneous digit, the message
is corrected.
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The basic principles in constructing a Hamming error-correcting code are as follows. To each group
of m information or message digits, k parity-checking digits, denoted p1, p2, . . . , p k , are added to
form an (m + k)-digit code. The location of each of the m + k digits within a code word is assigned
a decimal value; one starts by assigning a 1 to the most significant digit and m + k to the least
significant digit. Then k parity checks are performed on selected digits of each code word. The
result of each parity check is recorded as 1 or 0, depending, respectively, on whether an error has or
has not been detected. These parity checks make possible the development of a binary number, c1c2
· · · ck , whose value is equal to the decimal value assigned to the location of the erroneous digit
when an error occurs and is equal to zero if no error occurs. This number is called the position (or
location) number.
The number k of digits in the position number must be large enough to describe the location of any
of the m + k possible single errors, and must in addition take on the value zero to describe the “no
error” condition. Consequently, k must satisfy the inequality 2k ≥ m + k + 1. Thus, for example, if
the original message is in BCD where m = 4 then k = 3 and at least three parity-checking digits
must be added to the BCD code. The resultant error-correcting code thus consists of seven digits. In
this case, if the position number is equal to 101, it means that an error has occurred in position 5. If,
however, the position number is equal to 000, the message is correct.
In order to be able to specify the checking digits by means of only mes-sage digits and
independently of each other, they are placed in positions valid code words, 000 and 111. If a single
error occurs in the first code word, it could become 001, 010, or 100. The second code word could
be changed by a single error to 110, 101, or 011. Note that in each case the invalid code words are
different. Clearly, this code is error-detecting since its minimum distance is three. Moreover, if we
assume that only a single error can occur then this error can be located and corrected, since every
error results in an invalid code word that can be associated with only one of the valid code words.
Thus, the two code words 000 and 111 constitute an error-correcting code whose minimum distance
is three. In general, a code is said to be error-correcting if the correct code word can always be
deduced from the erroneous word. In this section, we shall discuss a type of single-error-correcting
codes known as Hamming codes.
If the minimum distance of a code is three, then any single error changes a valid code word into an
invalid one, which is distance one away from the original code word and distance two from any
other valid code word. Therefore, in a code with minimum distance three, any single error is
correctable or any double error detectable. Similarly, a code whose minimum distance is four may
be used for either single-error correction and double-error detection or triple-error detection. The
key to error correction is that it must be possible to detect and locate erroneous digits. If the
location of an error has been determined then, by complementing the erroneous digit, the message
is corrected.
The basic principles in constructing a Hamming error-correcting code are as follows. To each group
of m information or message digits, k parity-checking digits, denoted p1, p2, . . . , p k , are added to
form an (m + k)-digit code. The location of each of the m + k digits within a code word is assigned
a decimal value; one starts by assigning a 1 to the most significant digit and m + k to the least
Page 31 of 191
significant digit. Then k parity checks are performed on selected digits of each code word. The
result of each parity check is recorded as 1 or 0, depending, respectively, on whether an error has or
has not been detected. These parity checks make possible the development of a binary number, c1c2
· · · ck , whose value is equal to the decimal value assigned to the location of the erroneous digit
when an error occurs and is equal to zero if no error occurs. This number is called the position (or
location) number.
The number k of digits in the position number must be large enough to describe the location of any
of the m + k possible single errors, and must in addition take on the value zero to describe the “no
error” condition. Consequently, k must satisfy the inequality 2k ≥ m + k + 1. Thus, for example, if
the original message is in BCD where m = 4 then k = 3 and at least three parity-checking digits
must be added to the BCD code. The resultant error-correcting code thus consists of seven digits. In
this case, if the position number is equal to 101, it means that an error has occurred in position 5. If,
however, the position number is equal to 000, the message is correct.
In order to be able to specify the checking digits by means of only mes-sage digits and
independently of each other, they are placed in positions1, 2, 4, . . . , 2k−1. Thus, if m = 4 and k = 3
then the checking digits are placed in positions 1, 2, and 4 while the remaining positions contain the
original (BCD) message bits. For example, in the code word 1100110, the checking digits (in
boldface) are p1 = 1, p2 = 1, p3 = 0, while the message digits are 0, 1, 1, 0, which correspond to
decimal 6.
We shall now show how the Hamming code is constructed, by constructing the code for m = 4 and
k = 3. As discussed above, the parity-checking digits must be specified in such a way that, when an
error occurs, the position number will take on the value assigned to the location of the erroneous
digit. Table 1.7 lists the seven error positions and the corresponding values of the position number.
It is evident that if an error occurs in position 1, or 3, or 5, or 7, the least significant digit, i.e., c3, of
the position number must be equal to 1. If the code is constructed so that in every code word the
digits in positions 1, 3, 5, and 7 have even parity, then the occurrence of a single error in any of
these positions will cause an odd parity. In such a case, the least significant digit of the position
number is recorded as 1. If no error occurs among these digits, a parity check will show an even
parity and the least significant digit of the position number is recorded as 0.
From Table 1.7, we observe that an error in positions 2, 3, 6, or 7 should result in the recording of a
1 in the center of the position number. Hence, the code must be designed so that the digits in
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positions 2, 3, 6, and 7 have even parity. Again, if the parity check of these digits shows an odd
parity then the corresponding position-number digit, i.e., c2, is set to 1; otherwise it is set to 0.
Finally, if an error occurs in positions 4, 5, 6, or 7 then the most significant digit of the position
number, i.e., c1, should be a 1. Therefore, if digits 4, 5, 6, and 7 are designed to have even parity, an
error in any of these digits will be recorded as a 1 in the most significant digit of the position
number. To summarize the situation regarding the checking digits pi :
p1 is selected so as to establish even parity in positions 1, 3, 5, 7;
p2 is selected so as to establish even parity in positions 2, 3, 6, 7;
p3 is selected so as to establish even parity in positions 4, 5, 6, 7.
The code can now be constructed by adding the appropriate checking digits to the message digits.
Consider, for example, the message 0100 (i.e., decimal 4), as shown in the table below.
Thus checking digit p1 is set equal to 1 so as to establish even parity in positions 1, 3, 5, and 7.
Similarly, it is evident that p2 must be 0 and p3 must be 1, so that even parity is established,
respectively, in positions 2, 3, 6, and 7 and 4, 5, 6, and 7. The Hamming code for the decimal digits
coded in BCD is shown in Table 1.8.
Error location and correction are performed for the Hamming code in the fol-lowing manner.
Suppose, for example, that the sequence 1101001 is transmitted but, owing to an error in the fifth
position, the sequence 1101101 is received. The location of the error can be determined by
performing three parity checks as follows:
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Thus, the position number formed as c1c2c3 is 101, which means that the location of the error is in
position 5. To correct the error, the digit in position 5 is complemented and the correct message
1101001 is obtained.
It is easy to prove that the Hamming code constructed as shown above is a code whose distance is
three. Consider, for example, the case where the two original four-bit (code) words differ in only
one position, e.g., 1001 and 0001. Since each message digit appears in at least two parity checks,
the parity checks that involve the digit in which the two code words differ will result in different
parities and hence different checking digits will be added to the two words, making the distance
between them equal to three. For example, consider the two words below.
The two words differ in only m1 (i.e., position 3). Parity checks 1-3-5-7 and 2-3-6-7 for these two
words will give different results. Therefore, the parity-checking digits p1 and p2 must be different
for these words. Clearly, the foregoing argument is valid in the case where the original code words
differ in two of the four positions. Thus, the Hamming code has a distance of three.
If the distance is increased to four, by adding a parity bit to the code in Table 1.8 in such a way that
all eight digits have even parity, the code may be used for single-error correction and double-error
detection in the following manner. Suppose that two errors occur; then the overall parity check is
satisfied but the position number (determined as before from the first seven digits) will indicate an
error. Clearly, such a situation indicates the existence of a double error. The error positions,
however, cannot be located. If only a single error occurs, the overall parity check will detect it.
Now, if the position number is 0 then the error is in the last parity bit; otherwise, it is in the position
given by the position number. If all four parity checks indicate even parities then the message is
correct.
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Unit I
Part B: Boolean Algebra and Switching Functions
Switching algebra
The basic concepts of switching algebra will be introduced by means of a set of postulates, from which
we shall derive useful theorems and develop necessary tools that will enable us to manipulate and
simplify algebraic expressions.
Fundamental postulates
The basic postulate of switching algebra is the existence of a two-valued switch-ing variable that can
take either of two distinct values, 0 and 1. Precisely stated,
if x is a switching variable then
These values are often referred to as the truth values of x.
A switching algebra is an algebraic system consisting of the set {0, 1}, two binary1 operations called
OR and AND, denoted by the symbols + and · respectively, and one unary operation called NOT,
denoted by a prime.
The definitions of the OR and AND operations are as follows:
Thus the OR combination of two switching variables x + y is equal to 1 if the value of either x or y is 1
or if the values of both x and y are 1. The AND combination of these variables x · y is equal to 1 if and
only if the values of x and y are both equal to 1. The result of the OR operation is very often called the
(logical) sum or union and may be denoted by ∪ or ∨. The result of the AND operation is referred to as
the (logical) product or intersection, and is denoted by ∩ or ∧. We shall generally omit the dot · and
write xy to mean x · y.
The NOT operation, which is also known as complementation, is defined as follows:
The preceding postulates and definitions of switching operations enable us to derive many useful
theorems and develop an entire algebraic structure that may be advantageously applied to switching
circuits.
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Basic Theorems and Properties
The first property that drastically differs from the algebra of real numbers and accounts for the special
characteristics of switching algebra, is the idempotent law for a switching variable x:
To prove this property, we shall employ perfect induction. Perfect induction is a method of proof
whereby a theorem is verified for every possible combination of values that the variables may assume.
Since x is a two-valued variable, x + x = x may assume the values 1 + 1 = 1 and 0 + 0 = 0. These
equations, being identities, clearly verify the validity of Eq. (3.1), and similarly for Eq. (3.2) we have 1
· 1 = 1 and 0 · 0 = 0.
If x is a switching variable, then
The following two pairs of relations establish the commutativity and asso-ciativity of switching
operations. The convention adopted for parenthesizing is that of ordinary algebra, where x + y · z means
x + (y · z) and not (x + y) · z. Let x, y, and z be switching variables. Then
In addition, for every switching variable x,
The properties established by Eqs. (3.2) through (3.12) can be proved by the method of perfect
induction. The actual proofs are left to the reader as exercises. It is the associative law which enables us
to extend the definitions of the AND and OR operations to more than two variables, i.e., we write T = x
+ y + z to mean that T equals 1 if any of x, y, or z, or any combination thereof, equals 1.
In switching algebra, multiplication distributes over addition and addition distributes over
multiplication – a property known as the distributive law:
To verify Eq. (3.13) for every possible combination of values of x, y, and z, it is convenient to tabulate
these combinations in a table called a truth table or table of combinations. Since every variable may
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assume one of two values, 0 or 1, the truth table for the three variables contains 2 3 = 8 combinations.
These combinations are tabulated in the leftmost column of Table 3.1.
The value of x(y + z) is computed for every possible combination of x and y + z. The value of xy + xz is
computed independently by adding the entries in columns xy and xz. Since the two different methods of
computation yield identical results, as shown in the two rightmost columns, Eq. (3.13) is verified.
We observe that all the preceding properties are grouped in pairs. Within each pair, one statement can
be obtained from the other by interchanging the OR and AND operations and replacing the constants 0
and 1 by 1 and 0, respectively. Any two statements or theorems that have this property are called dual,
and this quality of duality that characterizes switching algebra is known as the principle of duality. It
stems from the symmetry of the postulates and definitions of switching algebra with respect to the two
operations and two constants. The implication of the concept of duality is that it is necessary to prove
only one of each pair of statements because its dual is, henceforth, proved.
Switching expressions and their manipulation

By a switching expression we mean the combination of a finite number of switching variables (x, y,
etc.) and constants (0, 1) by means of switching operations (+, ·, and ). More precisely, any switching
constant or variable is a switching expression, and if T1 and T2 are switching expressions then so are T1
, T2 , T1 + T2, and T1T2. No other combinations of variables and constants are switching expressions.
The properties to be presented below in Eqs. (3.15) through (3.20) provide the basic tools for the
simplification of switching expressions. They establish the notion of redundancy and, like all the
preceding properties, they appear in dual forms. Equation (3.15) and its dual (3.16) express the
absorption law of switching algebra.
The method of proof by perfect induction is efficient, as long as the number of combinations for which
the statement is to be verified is small. In other cases, algebraic procedures are more appropriate, such,
for example, as are demonstrated in the following proof of Eq. (3.15).
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Another property of switching expressions, important in their simplification, is the following:
Equation (3.17) is proved as follows.
The consensus theorem is noteworthy in that it is used frequently in the simplification of switching
expressions. It is stated in the following two equations:
The extra term yz in Eq. (3.19) is known as the consensus.
The preceding properties permit a variety of manipulations on switching expressions. In particular, they
enable us (whenever possible) to convert an expression into an equivalent one with fewer literals,
where by a literal we mean an appearance of a variable or its complement. For example, while the left-
hand side of Eq. (3.19) consists of six literal appearances; its right-hand side consists of only four
appearances. If the value of a switching expression is independent of the value of some literal xi , then
xi is said to be redundant. Equations (3.1) through (3.20) provide, among other things, the tools for
manipulating expressions so as to eliminate redundant literals
It is important to observe that no inverse operations are defined in switching algebra and, consequently,
no cancellations are allowed. For example, if A + B = A + C, the equality of B and C is not implied; in
fact, if A = B = 1 and = 0 then 1 + 1 = 1 + 0, but B =C. Similarly, B is not necessarily equal to if AB =
AC.
Example Simplify the expression
by eliminating redundant literals.
Hence, T (x, y, z) is actually independent of the values of x and y and depends only on z.
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De Morgan’s theorems
The rules governing complementation operations are summarized by three theorems. The first is the
involution theorem:
Proof Equation (3.21) is obvious by perfect induction.
De Morgan’s theorems for two variables are
Proof The proof of Eq. (3.22) follows by perfect induction, using the truth table of Table 3.2;
(x + y) and x y are computed independently and are shown to be identical for all possible combinations
of values of x and y. The proof of Eq. (3.23) then follows by the principle of duality.
For n variables, Eqs. (3.22) and (3.23) can be expressed as follows: the complement of any expression
can be obtained by replacing each variable and element with its complement and, at the same time,
interchanging the OR and AND operations, that is,
Equation (3.24) is known as the general De Morgan’s theorem and its proof follows immediately from
Eq. (3.22) and mathematical induction on the number of operations.
Example In order to simplify the expression
it is necessary first to apply De Morgan’s theorem and then to multiply out the expressions in
parentheses:
Hence, T = 1 independently of the values of the variables.
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Example Prove the following identity:
From the application of Eq. (3.19) to x y + yz, it follows that the term x z may be added to the left-
hand side of the equation; i.e., the equation becomes
Another application of Eq. (3.19) to the first, third, and fourth terms in the augmented left-hand side
of the equation shows that yz is redundant. After elimination of yz, the left-hand side of the equation is
identical to its right-hand side (i.e., both consist of identical terms), and thus the proof is complete.
Switching Functions
Definitions
Let T (x1, x2, . . . , xn) be a switching expression. Since each of the variables x1, x2, . . . , xn can
independently assume either of the two values 0 or 1, there are 2n combinations of values to be
considered in determining the values of T . In order to determine the value of an expression for a given
combination, it is only necessary to substitute the values for the variables in the expression. For
example, if
then, for the combination x = 0, y = 0, z = 1, the value of the expression is 1 because T (0, 0, 1) = 0’1 +
01’ + 0’0’ = 1. In a similar manner, the value of T may be computed for every combination, as shown
in the right-hand column of Table 3.3.
If we now repeat the above procedure and construct the truth table for the expression
we find that it is identical to that of Table 3.3. Hence, for every possible combination of variables, the
value of the expression is identical to the value of . Thus different
switching expressions may represent the same assignment of values specified by the right-hand column
of a truth table. The values assumed by an expression for all the combinations of variables x1, x2, . . . ,
xn define a switching function. In other words, a switching function f (x1, x2, . . . , xn) is a
correspondence that associates an element of the algebra with each of the 2 n combinations of variables
x1, x2, . . . , xn. This correspondence is best specified by means of a truth table. Note that each truth
table defines only one switching function, although this function may be expressed in a number of
ways.
The complement f (x1, x2, . . . , x n) is a function whose value is 1 whenever the value of f (x1, x2, . . . ,
xn) is 0, and 0 whenever the value of f is 1. The sum of two functions f (x1, x2, . . . , xn) and g(x1,
x2, . . . , xn) is 1 for every combination in which either f or g or both equal 1, while their product is
equal to 1 if and only if both f and g equal 1. If a function f (x1, x2, . . . , xn) is specified by means of a
truth table, its complement is obtained by comple-menting each entry in the column headed f . New
functions that are equal to the sum f + g and the product f g are obtained by adding or multiplying the
corresponding entries in the f and g columns.
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Example Two functions f (x, y, z) and g(x, y, z) are specified in columns f and g of Table 3.4. The complement
f’, the sum f + g, and the product f. g are specified in the corresponding columns.
Simplification of Expressions
The truth table assigns to each combination of variable values a specific switch-ing element.
Consequently, all the properties of switching elements (Eqs. (3.1) through (3.24)) are valid when the
elements are replaced by expressions. For example, xy + xyz = xy by virtue of the property established
in Eq. (3.15).
First, apply the consensus theorem, Eq. (3.19), to the first three terms of T, letting x, y, and z replace
A’, C’ , and BD, respectively. As a result the third term, BC’D, is redundant. Next, apply the
distributive law, Eq. (3.13), to the fourth and fifth terms. This gives the expression AD’ (B’ + BC).
Letting x and y replace B’ and C’, respectively, and applying Eq. (3.17) yields AD’ (B’ + C). No other
literal is redundant; thus the simplest expression for T is
First apply Eq. (3.17) to the first two terms and to the last two terms. This yields
The next step in the simplification is not as obvious; in order to simplify T , it is first necessary to
expand it. Since
we have
The application of Eq. (3.15) to the first and last terms results in the elimi-nation of the last term.
Now apply Eq. (3.19) to the second, third, and fourth terms, letting x, y, and z replace D, B, and AC,
respectively. This step eliminates ABC and yields
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Canonical and Standard Form
Canonical Forms
Truth tables have been shown to be the means for describing switching functions. An expression
representing a switching function is derived from the table by finding the sum of all the terms that
correspond to those combinations (i.e., rows) for which the function assumes the value 1. Each term is
a product of the variables on which the function depends. Variable xi appears in uncomplemented form
in the product if it has value 1 in the corresponding combination, and it appears in complemented form
if it has value 0. For example, the product term that corresponds to row 3 of Table 3.5, where the values
of x, y, and z are 0, 1, and 1, is x’ yz.
The sum of all product terms for the function defined by Table 3.5 is
A product term that, as for each term in the above expression, contains each of the n variables as
factors in either complemented or uncomplemented form is called a minterm. Its characteristic property
is that it assumes the value 1 for exactly one combination of variables. If we assign to each of the n
variables a fixed arbitrary value, either 0 or 1, then, of the 2 n minterms, one and only one minterm will
have value 1 while all the remaining 2n − 1 minterms will have value 0, because they differ by at least
one literal, whose value is 0, from the minterm whose value is 1. The sum of all minterms derived from
those rows for which the value of the function is 1 takes on the value 1 or 0 according to the value
assumed by f.
Therefore, this sum is in fact an algebraic representation of f. An expression of this type is called a
canonical sum of products or disjunctive normal expression.
Switching functions are usually expressed in a compact form, obtained by listing the decimal codes
associated with the minterms for which f = 1. The decimal codes are derived from the truth tables by
regarding each row as a binary number; e.g., the minterm x’ yz’ is associated with row 010, which,
when interpreted as a binary number, is equal to 2. The function defined by Table 3.5 can thus be
expressed as
where∑( ) means that f (x, y, z) is the sum of all the minterms whose decimal code is one of the
numbers given within the parentheses.
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A switching function can also be expressed as a product of sums. This is accomplished by considering
those combinations for which the function is required to have the value 0. For example, the sum term x
+ y + z’ has the value 1 for all combinations of x, y, and z, except for x = 0, y = 0, and z = 1, when it has
the value 0. Any similar term assumes the value 0 for only one combination. Consequently, a product of
such sum terms will assume the value 0 for precisely those combinations for which the individual terms
are 0. For all other combinations, the product-of-sum terms will have the value 1. A sum term that
contains each of the n variables in either a complemented or an uncomplemented form is called a
maxterm. An expression formed of the product of all maxterms for which the function takes on the
value 0 is called a canonical product of sums or conjunctive normal expression.
In each maxterm, a variable xi appears in uncomplemented form if it has the value 0 in the
corresponding row in the truth table, and it appears in complemented form if it has the value 1. For
example, the maxterm that corresponds to the row whose decimal code is 1 in Table 3.5 is x + y + z’ .
The canonical product-of-sums expression for the function defined by Table 3.5 is given by
This function can also be expressed in a compact form by listing the combinations for which f is to
have value 0, i.e.,
Where П( ) means the product of all maxterms whose decimal code is given within the parentheses.
One way of obtaining the canonical forms of any switching function is by means of Shannon’s
expansion theorem (also called Shannon’s decomposition theorem), which states that any switching
function f (x1, x2, . . . , xn) can be expressed as either
Or
Proof this proceeds by perfect induction. Let x1 be equal to 1; then x1 equals 0 and Eq. (3.25) becomes
an identity, i.e.,
Similarly, substituting x1 = 0 and x1 = 1 also reduces Eq. (3.25) to an identity and thus the theorem is
proved.
If we now apply the expansion theorem with respect to variable x2 to each of the two terms in Eq.
(3.25), we obtain
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The expansion of the function about the remaining variables yields the dis-junctive normal form. In a
similar manner, repeated applications of the dual expansion theorem, Eq. (3.26), to f (x1, x2, . . . , xn)
about its variables x1, x2, . . . , xn yield the conjunctive normal form.
A simpler and faster procedure for obtaining the canonical sum-of-products form of a switching
function is summarized as follows.
1. Examine each term; if it is a minterm, retain it, and continue to the next term.
2. In each product that is not a minterm, check the variables that do not occur; for each xi that does
not occur, multiply the product by (xi + xi ).
3. Multiply out all products and eliminate redundant terms.
The canonical product-of-sums form is obtained in a dual manner by expressing the function as a
product of factors and adding the product xi xi to each factor in which the variable xi is missing. The
expansion into canonical form is obtained by repeated applications of Eq. (3.14).
In some instances, it is desirable to transform a function from one form to another. This transformation
can be accomplished by writing down the truth table and using the previously described techniques. An
alternative method, which is based on the involution theorem (x ) = x, is illustrated by the following
example.
Example Determine the canonical sum-of-products form for T (x, y, z) = x y + z + xyz. Applying rules
1–3, we obtain
Example Let us determine the canonical product-of-sums form of
Using the above procedure,
Example Find the canonical product-of-sums form for the function
Using the involution theorem,
The complement T’ consists of those minterms that are not contained in the expression for T , i.e.,
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Algebraic Simplification of Digital Logic Gates, Properties of XOR Gates,
The EXCLUSIVE OR, denoted ⊕, is a binary operation on the set of switching elements. It assigns
value 1 to two arguments if and only if they have complementary values; that is, A ⊕ B = 1 if either A
or B is 1 but not when both A and B are 1. It is evident that the EXCLUSIVE-OR operation assigns to
each pair of elements its modulo-2 sum; consequently, it is often called the modulo-2 addition
operation. The following properties of the EXCLUSIVE OR are direct consequences of its definition:
In general, the modulo-2 addition of an even number of elements whose value is 1 gives 0 and the
modulo-2 addition of an odd number of elements whose value is 1 gives 1. The usefulness of the
modulo-2-addition operation will become evident in subsequent chapters, and especially in the analysis
and design of linear sequential machines.
Logic Gates
Logic gates are fundamental building blocks of digital systems. Logic gate produces one output level
when some combinations of input levels are present. & a different output level when other combination
of input levels is present. In this, 3 basic types of gates are there. AND OR & NOT
The interconnection of gates to perform a variety of logical operation is called Logic Design. Inputs &
outputs of logic gates can occur only in two levels.1,0 or High, Low or True , False or On , Off. A table
which lists all the possible combinations of input variables & the corresponding outputs is called a
Truth Table. It shows how the logic circuits output responds to various combinations of logic levels at
the inputs. Level Logic, a logic in which the voltage levels represent logic 1 & logic 0.Level logic may
be Positive Logic or Negative Logic. In Positive Logic the higher of two voltage levels represent logic
1 & Lower of two voltage levels represent logic 0.In Negative Logic the lower of two voltage levels
represent logic 1 & higher of two voltage levels represent logic 0.
In TTL (Transistor-Transistor Logic) Logic family voltage levels are +5v, 0v.Logic 1 represent +5v &
Logic 0 represent 0v.
AND Gate:
It is represented by “.” (dot) . It has two or more inputs but only one output. The output assumes the
logic 1 state only when each one of its inputs is at logic 1 state. The output assumes the logic 0 state
even if one of its inputs is at logic 0 state. The AND gate is also called an All or Nothing gate.
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Symbol: Truth Table:
Boolean
Expression:
Y= A.B
IC 7408 contains 4 two input AND gates

IC 7411 contains 3 three input AND gates
IC 7421 contains 2 four input AND gates
OR Gate:
It is represented by “+” (plus) It has two or more inputs but only one
output. The output assumes the logic 1 state only when one of its inputs is
at logic 1 state. The output assumes the logic 0 state even if each one of its
inputs is at logic 0 state. The OR gate is also called an Any or All gate. Also
called an inclusive OR gate because it includes the condition both the
inputs can be present
Symbol
Truth Table Boolean
Expression
Y=A+B
IC 7432 Contains 4 two input OR gates.
NOT Gate:
It is represented by “ ―” (bar). It is also called an Inverter. It has only one
input and one output. Whose output always the compliment of its input.
The output assumes logic 1 when input is logic 0 and output assume logic 0
when input is logic 1.
Symbol Truth Table
Boolean
A Y
Expression
0 1
1 0
Y = A’ or
Logic circuits of any complexity can be realized using only AND, OR ,

NOT gates. Using these 3 called AND-OR-INVERT i.e, AOI Logic
circuits.
Universal Gates
The universal gates are NAND, NOR. Each of which can also realize Logic
Circuits Single handedly. NAND-NOR called Universal Building Blocks..
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Both NAND-NOR can perform all the three basic logic functions. AOI
logic can be converted to NAND logic or NOR logic.
NAND Gate:
NAND assumes Logic 0 when each of inputs assume logic 1.
NAND gate mean NOT AND i.e, AND output is NOTed.
NAND→AND & NOT gates
Symbol
Truth Table
Boolean
Expression:
Y =(A .B)’
Bubbled OR gate: Bubbled OR gate is OR gate with inverted inputs. The

output of this is same as NAND gate.
Y=A‘+ B‘=(AB)‘
Bubbled NAND Gate: Bubbled NAND gate is NAND gate with inverted
inputs. The output of this is same as OR gate.
Y=A‘. B‘= ((A+B)‘)’ = A + B
NOR Gate:
NOR assumes Logic 1 when each of inputs assume logic 0.
NOR gate is NOT gate with OR gate. i.e, OR gate is NOTed.
NOR gate mean NOT OR i.e, OR output is NOTed.
NOR→OR & NOT gates
Symbol
Truth Table
A BY
0 0 1
0 1 0 Boolean Expression
1 0 0 Y = (A+B)’
1 1 0
Bubbled AND gate: AND gate with inverted inputs. The AND gate with
inverted inputs is called as Bubbled AND gate. So a NOR gate is equivalent
to a Bubbled AND Gate. A Bubbled AND gate is also called a negative
AND gate. Since its output assumes the HIGH state only when all its inputs
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are in LOW state, a NOR gate is also called active-LOW AND gate. Output
Y is 1 only when both A & B are equal to 0.i.e, only when both A‘ and B‘
are equal to 1.
Y = (A’ . B’) = (A + B)’
Bubbled NOR Gate: Bubbled NOR gate is NOR gate with inverted inputs.
The output of this is same as AND gate.
Y=A‘+ B‘= ((A.B)‘)’ = A.B
IC 7402 is 4 two input NOR gate

IC 7427 is 3 three input NOR gate
IC 7425 is 2 four input NOR gate
Exclusive OR (XOR) Gate:

It has 2 inputs& only 1 output. It assumes output as 1 when input is not
equal called anti-coincidence gate or inequality detector.
Symbol
Truth Table
Boolean
Expression
The high outputs are generated only when odd number of high inputs is
present. This is why x-or function also known as odd function.
TTL IC 746 has 4 x-OR gate
CMOS IC 74C8C has 4 X-OR gates.
The EX-NOR Gate:

It is X-OR gate with a NOT gate. It has two inputs & one output logic
circuit. It assumes output as 0 when one if inputs are 0 & other 1.It can be
used as an equality detector because it outputs a 1 only when its inputs are
equal.
Symbol Truth Table
Boolean
Expression
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TTL IC74LS266 contain 4 Each X-NOR gates.
CMOS 74C266 contain 4 Each X-NOR gates.
High speed CMOS IC 74HC266 contain 4 each X-NOR gates.
Multilevel NAND/NOR realizations.

Two level implementation:
Case (I): The implementation of a logic expression such that each one of
the inputs has to pass through only two gates to reach the output is called
Two-level implementation.
6. Both SOP , POS forms result in two-level logic
7. Two level implementation can be with AND, OR gates or only
NAND or with only NOR gates
8. Boolean expression with only NAND gates requires that the
function be in SOP form.
xample: Implement the Function F= AB+CD using AND-OR Logic and
NAND-NAND Logic
(a) AND – OR Logic (b) NAND – NAND Logic
Example: The implementation of the form: F=XY‘+X‘Y+Z using AND-

OR logic and NAND- NAND logic .
(a) AND – OR Logic (b) NAND – NAND Logic
Case (II): The implementation of Boolean expressions with only NOR

gates requires that the function be in the form of POS form.
Example: Implementation of the function (A+B)(C‘+D‘)using OR-AND

logic and NOR- NOR logic.
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(a) OR – AND Logic (b) NOR – NOR Logic
Example: Implementation of the function
using OR-AND logic and NOR- NOR logic.
(a) OR – AND Logic (b) NOR – NOR Logic
Summary:
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Unit II
Minimization of Switching Functions
Introduction:
The aim in simplifying a switching function f (x1, x2, . . . , xn) is to find an
expression g(x1, x2, . . . , xn) which is equivalent to f and which minimizes
some cost criteria. There are various criteria to determine minimal cost.
The most common are:
1. the minimum number of appearances of literals (recall that a literal is a
variable in complemented or uncomplemented form);
2. the minimum number of literals in a sum-of-products (or product-of-
sums) expression;
3. the minimum number of terms in a sum-of-products expression,
provided that there is no other such expression with the same number of
terms and fewer literals.
In subsequent discussions, we shall adopt the third criterion and restrict our
attention to the sum-of-products form. Of course, dual results can be
obtained by employing the product-of-sums form instead. Note that the
expression xy + xz + x’ y’ is minimal according to criterion 3, although it
may be written as x(y + z) + x’ y ‘, which requires fewer literals.
Consider the minimization of the function f (x, y, z) given below. A

combination of the first and second product terms yields x’ z ‘(y + y ‘) = x’
‘z . Similarly, combinations of the second and third, fourth and fifth, and
fifth and sixth terms yield a reduced expression for f :
This expression is said to be in an irredundant form, since any attempt to

reduce it, either by deleting any of the four terms or by removing a literal,
will yield an expression that is not equivalent to f . In general, a sum-of-
products expression, from which no term or literal can be deleted without
altering its logic value, is called an irredundant, or irreducible, expression.
The above reduction procedure is not unique, and a different combination
of terms may yield different reduced expressions. In fact, if we combine the
first and second terms of f , the third and sixth, and the fourth and fifth, we
obtain the expression
In a similar manner, by combining the first and fourth terms, the second and
third, and the fifth and sixth, we obtain a third irredundant expression,
While all three expressions are irredundant, only the latter two are minimal.
Consequently, an irredundant expression is not necessarily minimal, nor is
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the minimal expression always unique. It is, therefore, desirable to develop
procedures for generating the set of all minimal expressions, so that the
appropriate one may be selected according to other criteria (e.g., the
distribution of gate loads, etc.).
Minimization with theorems:

Axioms and Laws of Boolean algebra:
Axioms and postulates of Boolean Algebra are a set of Logical expressions
that are accepted without proof and upon which a set of useful theorems are
built.
Axioms for AND Axioms for OR 4. 1 + 1 = 1
operation: operation: Axioms for NOT
1. 0 . 0 = 0 1. 0 + 0 = 0 operation:
2. 0 . 1 = 0 2. 0 + 1 = 1 1. 1’ = 0
3. 1 . 0 = 0 3. 1 + 0 = 1 2. 0’ = 0
4. 1. 1 = 1
a. Laws - (A’)’ = A
Complement b. Laws – AND c. Laws –OR
operation: operation: operation:
0’ = 1 A . 0 = 0 (Null A+0=A
1’ = 0 law) A+1=A
If A = 0, then A’ = A .1 = A
A+A=A
1 A.A=A
If A = 1, then A’ = A . A’ = 0 A + A’ = 1
0
d. Commutative law
i. A+B=B+A
This law states that A OR B is same as B OR A.
A
B
A+ = B+
B A
B A
Truth Table:
A B A+B B+A
0 0 0 0
0 1 1 1
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1 0 1 1
1 1 1 1
ii. A.B = B.A

This law states that A . B is same as B . A.
A B
A.B = B.A
B A
Truth Table:
A B A.B B.A
0 0 0 0
0 1 0 0
1 0 0 0
1 1 1 1
Commutative law can be extended to any number of variables.
e. Associative law:
(A + B) + C = A + ( B + C)
A OR B ored with C is Truth Table:
same as A ORed with B A B C A+ (A+B)+C B+C A +
OR C/ B (B+C)
0 0 0 0 0 0 0
0 0 1 0 1 1 1
0 1 0 1 1 1 1
0 1 1 1 1 1 1
The above logic is same 1 0 0 1 1 0 1
as the below one.
1 0 1 1 1 1 1
1 1 0 1 1 1 1
1 1 1 1 1 1 1
Similarly, (A.B).C = A. (B.C)

This law can be extended to any number of variables.
f. Distributive law:
a. A ( B + C ) = A.B + A.C
This law states that ORing of several variables and ANDing the
result with a single variable is equivalent to ANDing that single
variable with each of the several variables and then ORing the
products.
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Truth Table:
A B C B+C A(B+C) AB AC AB+AC
0 0 0 0 0 0 0 0
0 0 1 1 0 0 0 0
0 1 0 1 0 0 0 0
0 1 1 1 0 0 0 0
1 0 0 0 0 0 0 0
1 0 1 1 1 0 1 1
1 1 0 1 1 1 0 1
1 1 1 1 1 1 1 1
b. A + BC = (A+B).(A+C)
This law states that ANDing of several variables and ORing the
result with a single variable is equivalent to ORing that single
variable with each of the several variables and then ANDing the
same.
Proof:
RHS : (A+B)(A+C) = A.A + A.C+ A.B + B.C = A + AC + AB + BC
= A ( 1 + C + B) + BC
= A + BC = LHS
Hence Proved.
g. Redundant Literal Rule: If A= 0, then 0.0 = 0 = A

A + A’B = A + B If A=1, then 1.1 = 1 = A
Proof: This law states that
A + A’B = (A+A’)(A+B) ANDing of a variable with
by Distributive law itself is equal to that
= 1. (A+B) = A + B variable only.
Similarly, A ( A’+ B) = AB
Proof: A (A’ + B) = A.A’ + Similarly, A+A = A
A.B = 0 + AB = AB If A=0, then A+A = 0 + 0 =
0=A
If A = 1, then A + A = 1 + 1
=1=A
h. Idempotence Law: This law states that ORing
A.A = A of a variable with itself is
equal to that variable only.
i. Absorption law:
a. A + A.B = A
This law states that ORing of a variable (A) with ANDing of
that variable AND another variable B is equal to that variable
itself (A).
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A + A.B = A(1+B) =
A.1 = A
Truth table:
A B A.B A+A.B
0 0 0 0
0 1 0 0
1 0 0 1
1 1 1 1
i.e. A + any logic = A
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b. A(A+B) = A
This law states that ANDing of a variable (A) with the one of that
variable (A) ORed with another variable (B) is equal to that variable
itself (A).
Truth table:
A B A+B A(A+B)
0 0 0 0
0 1 1 0
1 0 1 1
1 1 1 1
A(A+B) = A.A + A.B = A

(1+B) = A
j. Consensus Theorem:
i) AB + A’C + BC = AB Proof:
+ A’C LHS = (A+B)(A’+C)
Proof : (B+C)
LHS = AB + A’C + BC ( A + = (A.A’ + AC + A’B+
A’) BC)(B+C)
= AB + A’C + BCA + BCA’ = (AC+A’B+BC)
= AB (1+C) + A’C (1 + B) (B+C)
= AB + A’C = RHS =
Similarly, AB + A’C + BCD = ABC+AC+A’B+A’BC
AB + A’C +BC+BC
=AC+A’B+BC
RHS = (A+B)(A’+C)
=A.A’+AC+A’B+BC
=AC+A’B+BC
ii) (A+B)(A’+C)(B+C) = LHS = RHS
(A+B)(A’+C)
k. Transposition Theorem:
AB + A’C = (A+C)(A’+B)
Proof:
RHS = (A+C)(A’+B)
= A.A’ + A.B + A’.C + BC
= 0 + A’C+AB+BC
= A’C + AB+ BC (A + A’)
= AB + ABC +A’C + A’BC
= AB + A’C = LHS
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l. DeMorgan’s Theorem:
(X+Y)’ = X’.Y’
This law states that the complement of a sum of variables is equal to
product of their individual complements. This law can be represented
using logic gates as
X Y X+Y (X+Y)’ X’ Y’ X’.Y’
0 0 0 1 1 1 1
0 1 1 0 1 0 0
1 0 1 0 0 1 0
1 1 1 0 0 0 0
Truth Table:
It shows that the NOR gate is equivalent to a bubbled AND gate.

Similarly, (X.Y)’ = X’ + Y’
This law states that complement of the product of variables is equal
to the sum of their individual complements. Schematically, (X.Y)’ =
X’ + Y’ is represented as
Truth Table:
X Y (X.Y)’ X’ Y’ X’ + Y’
0 0 1 1 1 1
0 1 1 1 0 1
1 0 1 0 1 1
1 1 0 0 0 0
From the above truth table, column 3 is equal to column 6. Hence,

(AB)’ = A’ + B’
Steps to be followed to DeMorganize a given function:
Identify the function as a SOP or POS.
Complement the individual terms and change the SOP to POS or
vice-versa.
Check the individual terms whether they require DeMorganization.
If so, repeat it again till there is no such requirement.
Examples: Apply De Morgan’s theorem to get the complement of the following

Boolean functions:
i. F = (A + B’).(C + D’) ii. F = [(AB)’] (CD +E’F) . {(AB)’ +
To get F’, Change the sign and (CD)’}]’
take complements F’ = [(AB)’]’ + (CD +E’F)’ +
F’ = (A + B’).(C + D’) {(AB)’ + (CD)’}’
= (A + B’)’ + (C + D’)’ = AB + {(CD)’.(E’F)’}+ (AB.CD)
= A’.B + C’.D = AB + (C’ +D’).(E+F’) + ABCD
= AB(1+CD) + (C’ +D’).(E+F’)
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=AB + (C’ +D’).(E+F’) =(X + Y).Z’
iv. Simplify F =[ ( X’ + Z) . (XY)’]’

iii. F= {(X.Y’)’}.Y’ + Z Ans: F =[ ( X’ + Z) . (XY)’]’
F’ =[ {(X.Y’)’}.Y’ + Z]’ = [ ( X’ + Z)]’ + [(XY)’]’
= [ {(X.Y’)’}.Y’]’ . Z’ = X.Z’ + XY
= [{(X.Y’)’}’ +Y] . Z’ =X ( Y + Z’)
=[X.Y’+Y].Z’
Duality:
An algebraic expression in Boolean algebra which is obtained from any valid
expression by interchanging OR & AND operation and replacing ‘1’ by ‘0’ and ‘0’
by ‘1’ is also valid. This property is called Duality principle.
For example,
1) x+1 = 1, then its duality is 3) x + x’ = 1, then its duality is
x.0 = 0 x.x’=0
2) x+x = x, then its duality is 4) x + xy = x, then its duality is
x.x = x x.(x+y) = x
Simplify the following Boolean functions using theorems:

1) A + B + AC + AB = AB
= A ( 1 + C + B) + B 3) A’B + (A+B)
=A+B =A’B + A + B
as 1 + any = B (A’ +1) +A
Boolean expression = 1. = B + A = A+B.
2) A (AB + B) 4) AB’C + AB’ + C
= A { B ( A + 1)} = AB’ (C + 1) + C
= A. AB = AB’ + C (as 1 + C = 1)
5) AB + C + (A+B+C)
= A + AB + B + C + C
= A (1+B) + B + C (as C + C = C)
=A+B+C (as 1 + B = 1)
6) (A+C+D)(A+C+D’)(A+C’+D)(A+B’)
= (A.A + A.C + A.D’ +A.C+ C.C+CD’+A.D+C.D+D.D’).(A+C’+D).
(A+B’)
=(A +A.C+A.D’+A.C+ C + CD’ +C.D +0)(A+C’+D).(A+B’) as A.A =A
& D.D’= 0
={A(1+C+D’+C) + C (1 +D’+D)}.(A+C’+D).(A+B’)
=(A + C)(A+C’+D).(A+B’) as 1 +
any function = 1
= (A.A + AC’ + AD + AC + C.C’ + CD).(A+B’)
= (A + AC’ + AD + AC + 0+CD)(A+B’)
={A(1+C’+D+C)+CD}.(A+B’)
=(A+CD).(A+B’)
=A+AB’ + ACD + B’CD
= A(1+B’+CD) + B’CD
=A + B’CD
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II: Find the complement of the following:
1) (BC’ + A’D)(AB’+CD’) 2) AB’ + C’D’
Ans: 1). The complement is =AB’ + AC + A’C’ + A’D
{(BC’ + A’D) + BD + B’D’ + CD’ + BC’
(AB’+CD’)}’
= (BC’ + A’D)’ +
(AB’+CD’)’ Ans: 2). The complement is
=(BC’)’.(A’D)’ + (AB’)’. (AB’ + C’D’)’
(CD’)’ = (AB’)’ . (C’D’)’
=(B’+C)(A+D’)+(A’+B). = (A’+B).(C+D)
(C’+D) = A’C + A’D + BC + BD.
=(AB’+ AC + B’D’+CD’)
+ (A’C’ + A’D + BC’ +
BD)
The Karnaugh Map (K-MAP) Method:

For any complex digital logic circuit the algebraic expression will be also
very complex. And from this expression implementation of hardware is also
very difficult and cost effective. So if we can minimize the expression then
it will reduce the complexity and also reduce the number of gate used to
make the hardware. The expression can be minimized by implementing
Boolean algebra and also minimized by another method which is called the
map method. And the map method is very simple and straightforward
procedure for minimizing Boolean functions. This map method is also
known as the Karnaugh map or K-map
Karnaugh map can be drawn depending upon the number of variables
present in that expression. It may be
 Two variable Karnaugh map.
 Three variable Karnaugh map.
 Four variable Karnaugh map.
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In the case of a minterm Karnaugh map, ‘1’ is placed in all those squares
for which the output is ‘1’, and ‘0’ is placed in all those squares for which
the output is ‘0’. 0s are omitted for simplicity. An ‘X’ is placed in squares
corresponding to ‘don’t care’ conditions. In the case of a maxterm
Karnaugh map, a ‘1’ is placed in all those squares for which the output is
‘0’, and a ‘0’ is placed for input entries corresponding to a ‘1’ output.
Again, 0s are omitted for simplicity, and an ‘X’ is placed in squares
corresponding to ‘don’t care’ conditions.
The choice of terms identifying different rows and columns of a Karnaugh
map is not unique for a given number of variables. The only condition to be
satisfied is that the designation of adjacent rows and adjacent columns
should be the same except for one of the literals being complemented. Also,
the extreme rows and extreme columns are considered adjacent.
Important points to be remembered to group inside Karnaugh map.
 Biggest decimal number in the given function decides, which K-Map is
to be used. For instance, a single variable can define only two decimal
values 0 and 1, with maximum value as 1. Two variables can define
22=4 values, 0, 1, 2 and 3, with maximum value as 3. So if a given
function has 4 as the biggest decimal number, it cannot be defined by
two variables. We need to use 3 variables because by using 3 variables,
we can have 23= 8 decimal values with 7 as the maximum value.
 Try to cover all 1′s even if they become part of more than 1 loop.
 Look for the biggest loop at first. So if a K-Map has an Octet, it should
be circled first, followed by quads if any, followed by pairs if any.
 Pair eliminates 1 variable, Quad eliminates 2 variables and an Octet
eliminates 3variables.
 While looping, one visualize folding the K-Map like a paper and can
loop 1′s present in left most and right most columns of the same row.
 Also visualize overlapping K-Map in case of 5 and 6 variable K-Maps.
 Fold and overlap the K-Map only in horizontal and vertical direction
but not in diagonal.
 ‘Don’t care’ entries can be used in accounting for all of 1-squares to
make optimum groups. They are marked ‘X’ in the corresponding
squares. It is, however, not necessary to account for all ‘don’t care’
entries. Only such entries that can be used to advantage should be used.
A decimal numerical value is assigned to each cell and the labeling of the
cells is done in such a manner that only one variable changes at a time. A
‘0’ denotes a complemented variable and “1” an uncomplemented variable.
K-Map can be created for 3-variable, 4-variable, 5-variable and so on. A k-
variable K-Map has 2k cells. Below diagram is of a 3-variable K-Map:
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At a time only one variable is changing from complemented to un-
complemented & vice-versa as we move from one cell to next.
Looping adjacent 1’s for simplification
The expression for output Y can be simplified by properly combining those
squares in the K-Map which contain 1s. The process of combining those 1s
is called looping.
Pairs – Looping groups of Two 1s
Any adjacent pair of cells marked by a 1 in a K-Map can be combined into
one term and one variable is eliminated which is changing i.e. from A to A’
or B’ to B etc.Any single logical 1 on the map represents AND function.
The total expression corresponding to the logical 1s of a map are the OR
function (sum) of the various variable terms, which covers all the logical 1
in the map.
F = Σ(2,3) = AB’ + AB = A (B’ + B) = A
An example of 2-variable K-Map. A 2-variable K-Map will have 22 = 4
cells.
Boolean expression derived from K-Map = A

Since variable B is changing from B’ to B, it is eliminated right away.
Quad – Looping groups of Four 1s
Four cells that are marked as a 1, they can be combined into one term and
two variables can be eliminated. A group of four 1s that are horizontal or
vertical or form a square in the K-Map is called a Quad.
Octet – Lopping groups of Eight 1s
A group of eight 1s that are adjacent to each other is called an octet. When
an octet is looped in a four variable map, 3 of 4 variables are eliminated
because only one variable remains unchanged.
Some important definitions:
Minimal Sum
A sum of products (SOP) expression such that no SOP expression for Y has
fewer product terms and any SOP expression with the same number of
product terms has at least as many literals. This is what we are trying to
produce through the use of Karnaugh maps.
Implicant
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A normal product term that implies Y.
Example: For the function Y = AB + ABC + BC, the implicants are AB,
ABC, and BC because if any one of those terms are true, then Y is true.
Prime Implicant
An implicant of Y such that if any variable is removed from the implicant,
the resulting term does not imply Y.
Example: Y=AB+ABC+BC
Ans:
Prime Implicants: AB, BC. Not a prime implicant: ABC
ABC is not a prime implicant because the literal A can be removed to give
BC and BC still implies Y. Conversely AB is not a prime implicant
because you can't remove either A or B and have the remaining term still
imply Y.
In truth tables the prime implicants are represented by the largest
rectangular groups of ones that can be circled. If a smaller subgroup is
circled, the smaller group is an implicant, but not a prime implicant.
PI Theorem
A minimal sum is a sum of prime implicants.
Distinguished 1-Cell
An input combination that is covered by 1 prime implicant. In terms of
Karnaugh maps, distinguished 1-cells are 1's that are circled by only 1
prime implicant.
Essential Prime Implicant
A prime implicant that that includes one or more distinguished one cells.
Essential prime implicants are important because a minimal sum contains
all essential prime implicants.
3 Variable K-Map:
A 3-variable K-Map will have23= 8 cells. The number of variables is
decided by the biggest decimal number in a given function. A function F
which has maximum decimal value of 7, can be defined and simplified by a
3-variable Karnaugh Map.
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Boolean Table for 3 Variables
3-Variable K-Map
Page 63 of 191
First cell is denoted by 0, second by 1 and then third by 3 and not by 2. This
is because, A’BC (ANDing of first row A’ and third column BC)
corresponds to decimal number 3 in the boolean table. Similarly, second
row, third column ABC is denoted by 7 and not by 6.
Example of 3-Variable K-Map
Given function, F = Σ (1, 2, 3, 4, 5, 6)
Since the biggest number in this function is 6, it can be defined by 3
variables.
Draw K-Map for this function by writing 1 in cells that are present in
function and 0 in rest of the cells.
apply rules for simplifying K-Map. So, first look for an octet i.e. 8 adjacent
1′s. There is none, then look for a quad i.e. 4 adjacent 1′s. Again, there is
none, hence look for pairs. There are 3 pairs circled in red.
(1,3) – A’C (Since B is the changing variable between these two cells, it is
eliminated)
(2,6) – BC’ (Since A is the changing variable, it is eliminated)
(4, 5) – AB’ (Since C is the changing variable, it is eliminated)
Thus, F = A’C + BC’ + AB’.
4-Variable K-Map
A 4-variable K-Map will have 24 = 16 cells. A function F which has
maximum decimal value of 15, can be defined and simplified by a 4-
variable Karnaugh Map.
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Boolean Table for 4 Variables
4-variable K-Map
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Example 1 of 4-Variable K-Map
Given function, F = Σ (0, 4, 6, 8, 10, 15)
Since, the biggest number is 15, 4 variables are required to define this
function.
Applying rules of simplifying K-Map, there are no Octets and Quads. There
are 3 pairs, circled in red.
(0, 4) – A’C'D’ (Since B is the changing variable between these two cells, it
is eliminated)
(4, 6) – A’BD’ (Since C is the changing variable, it is eliminated)
(8, 10) – AB’D’ (Since C is the changing variable, it is eliminated)
There is 1 in cell 15, which cannot be looped with any adjacent cell, hence
it can not be simplified further and left as it is.
15 = ABCD
Thus, F = A’C'D’ + A’BD’ + AB’D’ + ABCD

Given function, F = Σ (0, 1, 3, 5, 6, 9, 11, 12, 13, 15)
function.
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Applying rules of K-Map, there is no octet. There are 2 quads and there are
3 pairs.
(1, 5, 13, 9) – C’D (Since A and B are changing variables, they are
eliminated)
(9, 11, 13, 15) – AD (Since B and C are changing variables, they are
eliminated)
(0, 1) – A’B'C’ (Since D is the changing variable, it is eliminated)
(1, 3) – A’B'D (Since C is the changing variable, it is eliminated)
(12, 13) – ABC’ (Since D is the changing variable, it is eliminated)
There is 1 in cell 6, which cannot be looped with any adjacent cell, hence it
can not be simplified further and left as it is.
6 = A’BCD’
Thus, F = C’D + AD + A’B'C’ + A’B'D + ABC’ + A’BCD’

Given function, F = Σ (0, 2, 3, 4, 5, 7, 8, 9, 13, 15)
function.
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Applying rules of simplifying K-Map, there is no octet. There are 1 quad
and 3 pairs.
(5, 7, 13, 15) – BD (Since A and C are changing variables, they are
eliminated)
(0, 4) – A’C'D’ (Since B is the changing variable, it is eliminated)
(2, 3) – A’B'C (Since D is the changing variable, it is eliminated)
(8, 9) – AB’C’ (Since D is the changing variable, it is eliminated)
Thus, F = BD + A’C'D’ + A’B'C + AB’C’

Given function, F = Σ (0, 3, 4, 6, 7, 9, 12, 14, 15)
function.Draw K-Map for this function by writing 1 in cells that are present
in function and 0 in rest of the cells.
Applying rules of simplifying K-Map, there is no octet. There are two

quads and two pairs.
(4, 6, 12, 14) – BD’ (Since A and C are changing variables, they are
eliminated)
(6, 7, 14, 15) – BC (Since A and D are changing variables, they are
eliminated)
(0, 4) – A’C'D’ (Since B is the changing variable, it is eliminated)
(3, 7) – A’CD (Since B is the changing variable, it is eliminated)
There is 1 in cell 9, which cannot be looped with any adjacent cell, hence it
cannot be simplified further and left as it is.
9 – AB’C'D
Thus, F = BD’ + BC + A’C'D’ + A’CD + AB’C'D
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Karnaugh Map Examples to find Prime Implicants, Distinguished 1-
Cells, Essential Prime Implicants, Minimal Sums
In the following examples the distinguished 1-cells are marked in the upper
left corner of the cell with an asterisk (*). The essential prime implicants
are circled in blue, the prime implicants are circled in black, and the non-
essential prime implicants included in the minimal sum are shown in red.
Example 1
Prime Implicants: 5
Distinguished 1-Cells: 2
Essential Prime Implicants: 2
Minimal Sums: 1
Y = A'CD' + AC'D + BCD
Example 2
Prime Implicants: 7
Distinguished 1-Cells: 2
Essential Prime Implicants: 2
Minimal Sums: 1
Y = B'D' + AD' + A'C'D + BCD

5-Variable K-Map
A 5-variable K-Map will have 25 = 32 cells. A function F which has

maximum decimal value of 31, can be defined and simplified by a 5-
variable Karnaugh Map.
Page 69 of 191
Boolean Table For 5 Variables
Page 70 of 191
Given function, F = Σ (1, 3, 4, 5, 11, 12, 14, 16, 20, 21, 30)
Since, the biggest number is 30, 5 variables are required to define this function.
Draw K-Map for this function by writing 1 in cells that are present in function and 0 in rest of
the cells.
Applying rules of simplifying K-Map, there is no octet. There is one quad that is obtained by
visualizing second square on first, there are 4 adjacent cells – 4,5,20 and 21. The octet is
highlighted by a blue connecting line. There are 5 pairs. Similar to quad, there is one pair
between two squares which is highlighted by the blue connecting line.
(4, 5, 20, 21) – B’CD’ (Since A & E are the changing variables, it is eliminated)
(12, 14) – A’BCE’ (Since D is the changing variable, it is eliminated)
(14, 30) – BCDE’ (Since A is the changing variable, it is eliminated)
(3, 11) – A’C'DE (Since B is the changing variable, it is eliminated)
(16, 20) – AB’D'E’ (Since C is the changing variable, it is eliminated)
(1, 3) – A’B'C’E (Since D is the changing variable, it is eliminated)
Thus, F = B’CD’ + A’BCE’ + BCDE’ + A’C'DE + AB’D'E’ + A’B'C’E

Given function, F = Σ (0, 1, 2, 3, 8, 9, 16, 17, 20, 21, 24, 25, 28, 29, 30, 31)
Since, the biggest number is 30, 5 variables are required to define this function.Draw K-Map
for this function by writing 1 in cells that are present in function and 0 in rest of the cells.
Applying rules of simplifying K-Map, there are 2 octets. First one is in square 2 circled in red.
Another octet is between 2 squares highlighted by blue connecting lines. There are 2 quads
between each of the squares.
(16, 17, 20, 21, 28, 29, 24, 25) – AD’ (Since B, C and E are changing variables, they are
eliminated)
(0, 1, 8, 9, 16, 17, 24, 25) – C’D’ (Since A, B and E are changing variables, they are eliminated)
(0, 1, 2, 3) – A’B'C’ (Since D and E are changing variables, they are eliminated)
(28, 29, 30, 31) – ABC (Since D and E are changing variables, they are eliminated)
Thus, F = AD’ + C’D’ + A’B'C’ + ABC
6-Variable K-Map
A 6-variable K-Map will have 26= 64 cells. A function F which has maximum decimal value of
63, can be defined and simplified by a 6-variable Karnaugh Map.
For 6 variables
 A = 0 for decimal values 0 to 31 and A = 1 for 31 to 63.
 B = 0 for decimal values 0 to 15 and 32 to 47. B = 1 for decimal values 16 to 31 and 48
to 63.
A 6-variable K-Map is drawn as below:
Visualize each of these squares one on another and figure out adjacent cells.
Given function, F = Σ (0, 2, 4, 8, 10, 13, 15, 16, 18, 20, 23, 24, 26, 32, 34, 40, 41, 42, 45, 47,
48, 50, 56, 57, 58, 60, 61)
Since, the biggest number is 61, 6 variables are required to define this function.
Draw K-Map for this function by writing 1 in cells that are present in function and 0 in rest of
the cells.
Applying rules of simplifying K-Map, there is one loop which has 16 1′s – containing 1′s at all
the corners of all 4 squares. We obtain it by visualizing all the 4 squares over one another but
only in horizontal or vertical direction (not diagonal) and figuring out adjacent cells. All the 1′s
in corners are circled in green.
There are 4 pairs, one in fourth square at bottom-right and other 3 are between the squares and
are highlighted by blue connecting line.
(0, 2, 8, 10, 16, 18, 24, 26, 32, 34, 40, 42, 48, 50, 56, 58) – D’F’ (A, B, C and E are changing
variables, so they are eliminated)
(41, 45, 57, 61) – ACE’F (B & D are changing variables, so they are eliminated)
(13, 15, 45, 47) – B’CDF (A & E are changing variables, so they are eliminated)
(0, 4, 16, 20) – A’C'E’F’ (B & D are changing variables, so they are eliminated)
(56, 57, 60, 61) – ABCE’ (D and F are changing variables, so they are eliminated)
There is 1 in cell 23, which cannot be looped with any adjacent cell, hence it cannot be
simplified further and left as it is.
23 = A’BC’DEF
Thus, F = D’F’ + ACE’F + B’CDF + A’C'E’F’ + ABCE’ + A’BC’DEF
DON’T CARE CONDITIONS
Functions that have unspecified output for some input combinations are called incompletely
specified functions. Unspecified minterms of functions are called ‘don’t care’ conditions. We
simply don’t care whether the value of 0 or 1 is assigned to F for a particular minterm. ßDon’t
care conditions are represented by X in the K-Map table. Don’t care conditions play a central
role in the specification and optimization of logic circuits as they represent the degrees of
freedom of transforming a network into a functionally equivalent one.
Example of the Use of a Karnaugh Map with Don’t Care Conditions
Design a circuit with four inputs D, C, B, A that are natural 8421-binary encoded with D as the
most-significant bit. The output F is true if the month represented by the input (0,0,0,0 =
January, 1011 = December) is a vacation month . Vacation is on Christmas, Easter, July,
birthday (September), or friend’s birthday (May). Since Easter can occur in either March or
April, we have to include both months.
Step 1: The truth table
Construct a truth table. Note that binary input 1100 to 1111 (12 to 15) do not represent valid
months and cannot occur. Although the output F should be 0 for these months since the output
does not represent a vacation month, it does not matter whether we choose F as 0 or 1. So, we
put x in the output column to represent don’t care and we can later choose x as 0 or 1 to
simplify the logic.
D C B A MONTH F
0 0 0 0 JAN 0
0 0 0 1 FEB 0
0 0 1 0 MAR 1
0 0 1 1 APR 1
0 1 0 0 MAY 1
0 1 0 1 JUN 0
0 1 1 0 JULY 0
0 1 1 1 AUG 0
1 0 0 0 SEP 1
1 0 0 1 OCT 0
1 0 1 0 NOV 0
1 0 1 1 DEC 1
1 1 0 0 X
1 1 0 1 X
1 1 1 0 X
1 1 1 1 X
Step 2 The Karnaugh map
put 1s in the squares where F = 1, an x in don’t care squares and leave the remaining squares
(that contain a zero) empty.
Step 3 The simplified Karnaugh map
The next step is to simplify the Karnaugh map by creating the smallest number of the largest
groups of 1s. All 1s must be included in at least one group. Any 1 can be in more than none
group. x can be treated as a 1 if we can use it to make a larger group.
This solution is not unique because one could have created other groupings of 1s (but none
simpler than this).
Step 4 Read the sum-of-product terms from the Karnaugh map

F = DB’A’ + CA’ + DBA’ + DC’B’
Quine McCluskey Tabulation Method:
The Quine McCluskey tabulation method is a very useful and convenient tool for simplification
of Boolean functions for large numbers of variables. The Karnaugh map method is a very useful
and convenient tool for simplification of Boolean functions as long as the number of variables
does not exceed four. But for case of large number of variables, the visualization and selection
of patterns of adjacent cells in the Karnaugh map becomes complicated and too much difficult.
For those cases Quine McCluskey tabulation method takes vital role to simplify the Boolean
expression. The Quine McCluskey tabulation method is a specific step-by-step procedure to
achieve guaranteed, simplified standard form of expression for a function.
Consider the Boolean expression F= (0,1,2,3,5,7,8,10,14,15) and To minimize by Quine
McCluskey tabulation method.
 To start with we have to make table and kept all the numbers in same group whose binary
numbers containing equal 1s. Like 1,2,8 (0001,0010,1000) are in same group because all
has equal 1s in their binary number. See in below table

Add another column to right side of that table naming 1 st Now between two groups
depending upon number of 1s, we have to find similar number with only one position
change to 0 to 1. See the binary number of 1 (0001) from first group and 3 (0011) from
second group. Both the numbers are similar only second bit position from LSB change 0 to
1. So in new column we should write (1, 3) 00-1 (in place of number change we put “–“on
that). In this way we have to check entire table and make new column accordingly.

Again add another column to right side of that table naming 2 nd and now between two
groups from 1st column, we have to find similar number with only one position change to 0
to 1. See the binary number of (0,1) (000-) and (2,3) (001-). Both the numbers are similar
only second bit position from LSB change 0 to 1. So in new column we should write (0, 1,
2, 3) 00– (in place of number change we put “–“ on that). In this way we have to check
entire table and make new column accordingly.

Mark those combinations that are used in 2ndLike for first one (0,1,2,3), the used
combinations are 0,1 and 2,3 from 1stcolumn.

The final table is drawn for getting the simplified Boolean expression. The table is drawn
with all combination of 2nd column and unused portion of 1st

Strike of the rows for which cross is found in more than one column, i.e.first row is striked
since 0, 2 are available in row 2 similarly 1,3 are available in 3 rd row , But don’t strike the
rows which has only one cross in a column.

Now we can get the simplified Boolean expression from above table and it’s correspond
2nd column value. We have to take uncut row with its 2ndcolumn value and convert it with
ABCD variable. Like if 0 is found take complement value, 1 for uncomplement value and
“–“for no variable.
0, 8,2,10(- 0 – 0)=B’D’
1,3,5,7(0 – – 1) = A’D
14, 15 (1 1 1 -)=ABC
Hence F =B’D’+A’D+ABC
Partially Specified Expressions: These are the expressions which not are not completely
specified i.e, the output is not specified for all the combinations of the input .These expressions
involve the don’t care conditions and simplified like expressions with don’t care conditions.
Multi-output minimizations:
The multi output minimization is getting multiple outputs from a set of given inputs and
utilizing the intermediate stages of the expression as a common wherever required. Example :
BCD to 7 segment driver, where the input is a 4 bit a number and the outputs are 7 driving
individual LEDs of the 7 segment.
Unit III
PART A: Design of Combinational Circuits
Design using Conventional Logic gates, Data Selectors, Encoders, Priority Encoder, Decoders,
comparators, Adders, multiplexers, De-multiplexers, realization of switching functions using MUX,
Parity generators and code converters. Static Hazards and Hazard Free Realizations.
Memory Elements and Programmable Logic Devices:

Types of Memory Elements (RAM and ROM). Basic PLDs - ROM, PROM, PLA and PAL.
Realization of Switching functions using PLDs.
Comparators
An n-bit comparator is a circuit that compares the magnitude of two numbers X and Y. It has three
outputs f1, f2, and f3, such that: f1 = 1 if (if and only if ) X > Y ; f2 = 1 if X = Y ; f3 = 1 if X < Y . As an
example, consider an elementary 2-bit comparator, as in Fig. 5.4a.
The circuit has four inputs x1, x2, y1 and y2, where x1 and y1 denote the most significant digit of X and
Y, respectively. The logic equations may be determined with the aid of the map in Fig. 5.4b, where the
values 1, 2, and 3 are entered in appropriate cells to denote, respectively, f1 = 1, f2 = 1, and
The circuit for f1 is shown in Fig. 5.4c. Similar circuits are obtained for f2 and f3.
The reader can verify that X >Y, i.e. f1 = 1, when the most significant bit of X is larger than
that of Y , i.e., x1 > y1, or when the most significant bits are equal but the least significant bit of
X is larger than that of Y , namely, x1 = y1 and x2 > y2. In a similar way, we can determine the
conditions for f2 = 1 and f3 = 1.
This line of reasoning can be further generalized to yield the logic equations for a 4-bit
comparator.
A 4-bit comparator is shown in Fig. 5.5a. It has 11 inputs, four representing X, four representing
Y , and three connected to the outputs f1, f2, and f3 of the preceding 4-bit stage. Three such
stages can be connected in cascade, as shown in Fig. 5.5b, to obtain a 12-bit comparator. Initial
conditions are inserted at the inputs of the comparator corresponding to the least significant bits
in such a way that the outputs of this comparator will depend only on the values of its own x’s
and y’s.
Data selectors
Multiplexer is essentially an electronic switch that can connect one out of n inputs to the
output. The most important application of the multiplexer is as a data selector. In general, a
data selector has n data input lines D0, D1, . . . , Dn−1, m select digit inputs s0, s1, . . . , sm−1, and
one output. The m select digits form a binary select number ranging from 0 to 2m − 1, and when
this number has the value k then Dk is connected to the output. Thus this circuit selects one of n
data input lines, according to the value of the select number, and in effect connects it to the
output. Clearly, the number of select digits must equal m = log2 n, so that it can identify all the
data inputs.
Data selectors have numerous applications. For example, they may be used to connect one out
of n input sources of a device to its output. As we shall subsequently show, data selectors may
also be used to implement all Boolean functions.
A block diagram for a data selector with eight data input lines is shown in Fig. 5.6a. The select
number consists of the three digits s2s1s0. Thus, for example, when s2s1s0 = 101 then D5 is to be
connected to the output, and so on. The Enable (or Strobe) input “enables” or turns the circuit
on. A logic diagram for this data selector is shown in Fig. 5.6b. Such a unit provides the
complement z of the output as well as the output z itself. The Enable input turns the circuit on
when it assumes the value 0.
Implementing switching functions with data selectors
An important application of data selectors is the implementation of arbitrary switching
functions. As an example, we shall show how functions of two variables can be implemented by
means of the data selector of Fig. 5.7. Clearly, in this circuit, if s = 0 then z assumes the value of
D0 and if s = 1 then z assumes the value of D1. Thus, z = sD1 + s D0. Now, suppose that we want
to implement the EXCLUSIVE-OR operation A ⊕ B. This can be accomplished by connecting
variable A to the input s and variables B and B to D0 and D1, respectively. In this case z = AB +
A B = A ⊕ B. Similarly, if we want to implement the NAND operation z = A + B then we
connect variable A to s and variable B to D1; D0 is connected to a constant 1. Clearly, z =AB + A
1=A+B.
In a similar manner, a judicial choice of inputs will implement any of the 16 different two-variable
functions (see Table 3.6). In general, to implement an n-variable function we require a data selector
with n − 1 select inputs and 2n−1 data inputs. Hence, for example, to implement all three-variable
functions we require a data selector with two select inputs, s1 and s2, and 23−1 = 4 data inputs, D0,
D1, D2, and D3. The output of such a data selector is
z = s1s2D0 + s1s2D1 + s1s2D2 + s1s2D3.
The reader can verify that, if we connect variables A and B to s1 and s2, respectively, and
variables C and C to D0 and D3, respectively, and assign constants 1 to D1 and 0 to D0 then the
circuit will realize the function
z =A B C + AB + ABC = AC + B C.
In general, then, to implement an n-variable function we assign n − 1
vari-ables to the select inputs, one to each such input. The last variable and the constants 0 and
1 are assigned to the data inputs in such a way that together with the select input variables they
will yield the required function. Such an implementation is usually possible when at least one
variable is available in both its complemented as well as its uncomplemented form; otherwise, a
larger data selector may be required. Implementations of functions of five or more variables are
usually accomplished by means of a multi-level arrangement of several smaller standard data
selectors.
Priority Encoders:
A priority encoder is a device with n input lines and log2 n output lines. The input lines
represent units which may request service. When two lines pi and pj , such that i > j , request
service simultaneously, line pi has priority over line pj . The encoder produces a binary output
code indicating which of the input lines requesting service has the highest priority. An input line
pi indicates a request for service by assuming the value 1. A block diagram for an eight-input
three-output priority encoder is shown in Fig. 5.8a.
The truth table for this encoder is shown in Fig. 5.8b. In the first row, only p0 requests service
and, consequently, the output code should be the binary number zero to indicate that p0 has
priority. This is accomplished by setting z4z2z1 = 000. The fourth row, for example, describes the
situation where p3 requests service while p0, p1, and p2 each may or may not request service
simultaneously. This is indicated by an entry 1 in column p3 and don’t-cares
in columns p0, p1, and p2. No request of a higher priority than p3 is present at this time. Since in
this situation p3 has the highest priority, the output code must be the binary number three.
Therefore, we set z1 and z2 to 1 while z4 is set to 0. (Note that the binary number is given by N =
4z4 + 2z2 + z1.) In a similar manner the entire table is completed.
From the truth table, we can derive the logic equations for z1, z2, and z4. Starting with z4, we find
that
z4 = p4p5p6p7 + p5p6p7 + p6p7 + p7.
This equation can be simplified to
z4 = p4 + p5 + p6 + p7.
For z2 and z1, we find
z2 = p2p3p4p5p6p7 + p3p4p5p6p7 + p6p7 + p7 = p2p4p5
+ p3p4p5 + p6 + p7,
z1 = p1p2p3p4p5p6p7 + p3p4p5p6p7 + p5p6p7 + p7 = p1p2p4p6

+ p3p4p6 + p5p6 + p7.
An implementation of such an encoder is given in Fig. 5.8c. In this encoder, the inputs are given
in complemented form. The circuit also has an Enable signal and contains an output z0 that
indicates whether any requests are present. Specifically, z0 = 0 if there is no request and z0 = 1 if
there are one or more requests present. It is possible to combine several such encoders, by
means of external gating, to handle more than eight inputs
Decoders
A decoder is a combinational circuit with n inputs and at most 2n outputs. Its characteristic
property is that for every combination of input values, only one output value will be equal to 1
at any given time. Decoders have a wide variety of applications in digital technology. They may
be used to route input data to a specified output line, as, for example, is done in memory
addressing, where input data are to be stored in (or read from) a specified memory location.
They can be used for some code conversions. Or they may be used for data distribution, i.e.,
demultiplexing, as will be shown later. Finally, decoders are also used as basic building blocks
for implementing arbitrary switching functions.
Figure 5.9a illustrates a basic 2-to-4 decoder. Clearly, if w and x are the input variables then
each output corresponds to a different minterm of two variables. Two such 2-to-4 decoders plus
a gate-switching matrix can be connected, as shown in Fig. 5.9b, to form a 4-to-16 decoder.
Switching matrices are very widely used in the design of digital circuits.
Not all decoders have exactly 2n outputs. Figure 5.10 describes a decimal decoder that converts
information from BCD to decimal. It has four inputs w,
x, y, and z, where w is the most significant and z the least significant digit, and 10 outputs, f0
through f9, corresponding to the decimal numbers. In designing this decoder, we have taken
advantage of the don’t-care combinations, f10 through f16, as can be verified by means of the
map in Fig. 5.10b. Another implementation of decimal decoders is by means of a partial-gate
matrix, as shown in Fig. 5.11.
A decoder with exactly n inputs and 2n outputs can also be used to
implement any switching function. Each output of such a decoder realizes one distinct min
term. Thus, by connecting the appropriate outputs to an OR gate, the required function can be
realized. Figure 5.12 illustrates the implementation of the function f (A, B, C, D) = (1, 5, 9, 15)
by means of a complete decoder, i.e., one with n inputs and 2n outputs.
A decoder with one data input and n address inputs is called a demultiplexer. It directs the
input data to any one of the 2n outputs, as specified by the n-bit
input address. A block diagram for a demultiplexer is shown in Fig. 5.13. A demultiplexer with
four outputs is shown in Fig. 5.3.When larger-size decoders are needed, they can usually be
formed by inter-connecting several smaller decoders with some additional logic.
Adders_sutractors:
Digital computers perform a variety of information-processing tasks. Among the functions en
countered are the various arithmetic operations. The most basic arithmetic operation is the
addition of two binary digits. This simple addition consists of four possible elementary
operations:
0+ 0 = 0, 0 + 1 = 1,1 + 0 = 1, and 1 +1 = 10. The first three operations produce a sum of one
digit, but when both augend and addend bits are equal 10 1 . the binary sum consists of two
digits. The higher significant bit of this result is called a carry, When the augend and addend
numbers contain more significant digits the carry obtained from the addition of two bits is
added to the next higher order pair of significant bits . A combinational circuit that performs the
addition of two bits is called a half adder, One that performs the addition of three bits (two
significant bits and a previous carry) is full adder. The names of the circuits stern from the fact
that two half adders can be employed to implement a full adder. A binary adder- subtractor is a
combinational circuit that performs the arithmetic operations of addition and subtraction with
binary numbers. We will develop this circuit by means of a hierarchical design. The half adder
design is carried OUI first, from which we develop the full adder. Connecting n full adders in
cascade produces a binary adder for two c -bit numbers. The subtraction circuit is included in a
complementing circuit.
Half Adder
From the verbal explanation of a half adder. we find that this circuit needs two binary inputs
and two binary outputs. The input variables designate the augend and addend bits; the output
variables produce the sum and carry. We assign symbols .r and y to the two inputs and S (for
sum) and C (for carry) to the outputs. The truth table for the half adder is listed in Table 4.3.The
C output is I only when both inputs are 1. The S output represents the least significant bit of the
sum. The simplified Boolean functions for the two outputs can be obtained directly from the
truth table. The simplified sum-of-products expressions are S = x 'y + xy',C = x )'The logic
diagram of the half adder implemented in sum of products is shown in Fig. 4.5 (a),It can be also
implemented with an exclusive-OR and an AND gate as shown in Fig. 45(b).This form is used
to show that two half adders can be used to construct a full adder.
A full adder is a combinational circuit that forms the
arithmetic sum of three bits. It consists of three inputs and two out
puts. Two of the input variables, denoted by x and y, represent the
two significant bits to be added. The third input c represents the
carry from the previous lower significant position. two outputs
are necessary because the arithmetic sum of three binary digits
ranges in value from0 to 3 and binary 2 or 3 needs two digit. The
two outputs are designated by the symbols S for sum and C for
carry. The binary variable S gives the value of the least significant
bit of the sum.
The binary variable C gives the output carry. The truth
table of the full adder is listed in table 4.4.
The eight rows under the input variables designate all possible
combinations of the three variables. The output variables are
determined from the arithmetic sum of the input bits. When all
input bits are 0, the output is 0.The S output is equal to 1 when
only one input is equal to 1 or when all three inputs are equal 1.
The C output has a carry of 1 if two or three inputs are equal to 1.
The input and output bits of the combinational circuit have
different interpretations at various stages of the problem. On the
one hand. physically. the binary signals of the inputs are
considered binary digits to be added arithmetically to form a two-
digit sum at the output. On the other hand the same binary
values are considered as variables of Boolean functions when
expressed will the truth table or when the circuit is implemented
with logic gates. The map for the output, of the full adder are
shown in Fig. 4.6. The simplified expressions are
The logic diagram for the full adder implemented in sum-of-

products form is shown in Fig. 4.7. It can also be implemented
with two half adders and one OR gate. as shown in Fig.4.8.The S
output from the second half adder is the exclusive-OR of z and the
output of the first half adder giving
Binary Adder
A binary adder is a digital circuit that produces the arithmetic sum

of two binary numbers. It can be constructed with full adders
connected in cascade. with the output carry from each full adder
connected to the input carry of the next full adder in the chain.
Figure 4.9 shows the interconnection of four full-adder (FA)
circuits to provide a four-bit binary ripple carry adder. The augend
bits of A and the addend bits of B are designated by subscript
numbers from right to left with subscript 0 denoting the least
significant bit. The carries are connected in a chain through the
full adders. The input carry to the adder is Co. and it ripples
through the full adders to the output carry C4 The S outputs
generate the required sum bits. An two-bit adder requires n full
adders with each output carry connected to the input carry of the
next higher order full adder.
To demonstrate with a specific example. consider the two binary
numbers A = 101 1 and B = 00 11. Their sum S = 1110 is formed
with the four-bit adder as follows:
The bits are added with full adders. starting from the least
significant position (subscript 0). 10 to form the sum bit and carry
bit. The input carry Co in the least significant position must be 0.
The value of C;-+l in a given significant position is the output
cart)' of the full adder. This value is transferred into the input carry
of the full adder that adds the bits one higher significant position
to the left. The sum bits are thus generated starting from the
rightmost position and are available as soon as the corresponding
previous carry bit is generated. All the carries must be generated
for the correct sum bits to appear at the outputs.
The four-bit adder is a typical example of a standard component. It
can be used in many applications involving arithmetic operations.
Observe that the design of this circuit by the
classical method would require a truth table with 29 = 5 12 entries.
since there are nine inputs to the circuit. By using an iterative
method of cascading a standard function, it is possible to obtain a
simple and straightforward implementation
Carry Propagation
The addition of two binary numbers in parallel implies that all the
bits of the augend and addend are available for computation at the
same time. As in any combinational circuit, the signal must
propagate through the gates before the correct output sum is
available in the output terminals. The total propagation time is
equal to the propagation delay of a typical gate times the number
of gate levels in the circuit. The longest propagation delay time in
an adder is the time it takes the carry to propagate through the full
adders. Since each bit of the sum output depends on the value of
the input carry the value of Sj at any given stage in the adder will
be in its stead y-state final value only after the input carry to that
stage has been propagated. In this regard consider output S3 in
Fig. 4.9. Inputs A3 and BJ are available as soon as input signals
are applied to the adder. However, input carry C3 does no (settle
to its final value until C2 is available from the previous stage.
Similarly, C2 has to wait for C1and so on down 10 Co- Thus, only
after the carry propagates and ripples through all stages will the
last output 5J and carry Col settle to their final correct value . The
number of gate levels for the carry propagation can be found from
the circuit of the fulladder. The circuit is redraw n with different
labels in Fig. 4.10 for convenience. The input and
output variables use the subscript i to denote a typical stage of the

adder . The signals at P; and G, settle to their steady -state values
after they propagate through their respective gates, These two
signs are common to all full adder and depend only on the input
augend and addend bits.
The signal from the input carry Cj 10 the out put carry Cj- 1
propagates through an AND gate and an OR gate. which
contribute two gate levels. If there are four full adders in the adder.
the output carry C4 would have 2 x 4 =- 8 gate levels from Co to
C4' For an n-bit adder. there are 2n gate levels for the carry to
propagate from input to output.
The carry propagation lime is an import ant attribute of the adder
because it limits the speed
with which two numbers are added . Although the adder for that
matter any combinational circuits will always have some value at
its output terminals the outputs will not be correct unless the
signals are given enough time to propagate through the gates
connected from the inputs 10 the outputs. Since all other
arithmetic operations are implemented by successive additions the
time consumed during the addition process is critical.
An obvious solution for reducing the carry propagation del ay time
is to employ faster gate s with reduced delays. However, physical
circuits have limit to their capability. Another solution is to
increase the complexity o f the equipment in such a way that the
carry delay time is reduced. There are several techniques for
reducing the carry propagation time in a parallel adder. The most
widely used technique employs the principle o f carry look ahead
IOR ie. Consider the circuit of the full adder shown in Fig. 4.10. If
we define 1'01.'0 new binary variables
Gi, is called a carry generate and it produces a carry of 1 when

both A, and B, are 1. regardless f the input carry)' C,. Pi’s called
carry propagate because it determines whether a carry into rage i
will propagate into stage i .... I (i.e .. whether an assertion of Ci
will propagate to an assertion of Ci-tl. We now write the Boolean
functions for the carry )' outputs o f each stage and substitute the
value of each C; from the previous equations:
Since the Boolean function for each out put carry is expressed in
sum-of-products form. each function can be implemented with one
level of AND gates followed by an OR gate (or by a two- level
NAND).1lle three Boolean functions for C t. C2• and C) are
implemented in the carry lookahead generator shown in Fig. 4 .11.
shows that this circuit can add in less time because C1 doe s not
have to wait for C2 and C. to propagate: in fact. C" is propagated
at the same time as C 1 and C2. This gain in speed of operation is
achieved at to be expense of additional complexity (hardware)
The construction of a four-bit adder with a carry lookahead
scheme is shown in Fig. 4.12. Each sum output requires two
exclusive-OR gates. The output of the first exclusive-OR gate
generates the 11 variable, and the AND gate generates the
G1variable. The carries are propagated through the carry look
ahead generator (similar 10 that in Fig. 4. 11) and applied as
inputs to the second exclusive-OR gate. All output carries are
generated after a delay through two levels of gates. Thus, outputs
5 1through 53 have equal propagation delay times. The two-level
circuit for the output carry C4 is not shown. This circuit can easily
be derived by the equation substitution method.
DECODERS
Discrete quantities of information are represented in digital

systems by binary codes. A binary code of n bits is capable of
representing up to 2" distinct elements of coded information. A
decoder is a combinational circuit that converts binary information
from" input Hence to a maxi mum of 2" unique output line c. If
the bit coded information is unused combination the decoder may
have fewer than 2" outputs. The decoders presented here are called
n-to-m-line decoders, where m :s: 2". Their purpose is to generate
me2" (or fewer) minterms of n input variables. The name decoder
is used in conjunction with other code converters. such as a BCD-
to-seven-segment decoder. As an example consider the three-to-
eight-line decoder circuit of Fig. 4.18. The three inputs are
decoded into eight outputs each representing one of the minterms
of the three input variables. The three inverters provide the
complement of the inputs, and each one of the eight AND gates
generates one of the minterms. A particular application of this
decoder is binary-to-octal conversion.
The input variables represent a binary number. and the outputs represent the eight dig its of a number in
the octal number system. However, a three-to-eight-line decoder can be used for decoding all three-bit
code to provide eight outputs, one for each element of the code. The operation of the decoder may be
clan lied by the truth table listed in Table 4.6. For each possible input combination, there are seven
outputs that are equal 10 0 and only one that is equal (0 I. The output whose value is equal 10 I
represents the minterm equivalent of the binary number currently available in the input lines. Some
decoders arc constructed with NAND gates. Since a NAND gate produces the AND operation with an
inverted output. it becomes more economical to generate the decoder minterms in their complemented
form. Furthermore decoders include one or more enable inputs to control the circuit operation. A two-
to-four-line decoder with an enable input constructed with NAND gates is shown in Fig. 4.19. The
circuit opera tes with complemented outputs and a complement enable input.
The decode r is enabled when E is equ al to 0 (i.e.. active-low enable ). As indicated by the truth table
only one output can be equal to 0 at any given time; all other outputs are equal 10 I. The output whose
value is equal to 0 represents the minterm selected by inputs A and B. The circuit is disabled when E is
equal 10 I. regardless of the values of the other two inputs. When the circuit is disabled. none of the
outputs are equal 10 0 and none of the minterms are selected .
In general a decoder may operate with complemented or un complemented outputs. The enable input
may be activated with a 0 or with a 1 signal. Some decoders have two or more enable inputs that must
satisfy a given logic condition in only to enable the circuit.
A decode r with enable input can function as a demultiplexer\ a circuit that receives information from a
single line and directs to one of 2" possible output lines. The selection of a specific output is
controlled by the bit combination of n selection lines. The decoder of Fig. 4.19 can function as a o ne-
to-four-line demultiplexer when E is taken as a data input line and A and B are taken as the selection
input s. The single input variable E has a pat h 10 all four outputs. but the input information is directed
10 only one of the output lines as specified by the bi nary combination of the two selection lines A and
B. This feature can be verified from the truth tab le of the circuit. For example, if the selection lines AB
= 10, will be the same as the input value E. while all other outputs are maintained at I. Because decoder
and demultiplexer operations are obtained from the same circuit. a decoder with an enable input is
referred to as a decoder-demultiplexer. Decoders with enable inputs can be connected together to form
a larger decoder circuit. Figure 4.20 shows two 3-to-8-line decoders with enable inputs connected to
form a 4-10-16 line decoder. When w = 0. the top decoder is enabled and the other is disabled. The
bottom decoder outputs are all O's. and the top eight outputs generate minterms 0000 to 011 1. When w
= 1 , the en able conditions are reversed: The bottom decoder outputs generate minterms 1000 to 1111,
while the outputs of the top decoder are all D's. This example demonstrates the usefulness of enable
inputs in decoders and other combinational logic components. In general enable inputs are a convenient
feature for interconnecting two or more standard components for the purpose of combining them into
a similar function with more inputs and outputs
Combinational logic Implementation
A decoder provides the 2" minterms of n input variables. Each asserted output of the decoder is
associated with a unique pattern of input bits. Since any Boolean function can be expressed in
sum-of-minterms form a decoder that generates the minterms of the function together with an
external OR gate that forms their logical sum. provide a hardware implementation of the
function. In this way any combinational circuit with I I inputs and m outputs ca n be implemented
with an II-l<l-2"-line decoder and m OR gates. The procedure for implementing a combinational
circuit by means of a decoder and OR gates requires that the Boolean function for the circuit be-
expressed as. a sum of minterms. A decode r is then chosen that generates all the minterms of the
input variable". The inputs to each OR gate are selected from the decoder oring to the list of
minterms of each function. This procedure will be illustrated by an example that implements a
full-adder circuit. From the truth tab le of the full adder (see Table 4.4). we obtain the functions
for the combinational circuit in sum-of-minterms form :
Since there are three input s and a total of eight min terms we need
a three-to-eight-line decoder. The implement at ion is shown in Fig. 4.2 1. The- decoder generates
the eight minterms for x. y. and z. The OR gate for output S forms the logical sum of minterms 1.
2. 4. and 7. The OR gate for output C forms the logical sum of minterms 3. 5. 6. and 7. A function
with a long list of minterms requires an OR gate- with a large number of inputs. A function
having a list of k. minterms can be expressed in it complemented from F' with 2" - k. minterm s.
If the number of min terms in the function is greater than 2"/2. then F' can be expressed with
fewer minterms. In such a case. it is advantageous to use a OR gate to sum the min terms of F' .
The output of the OR gate complements this sum and generates the normal output F. l f NAN D
gate s are used for the decode r. as in Fig. 4.19. then the external gates must be NAND gates
instead of OR gates. This is because a two-level AND gate circuit implements a sum-of-minterms
function equivalent to a two-level AND-OR circuit.
4 .10 ENCODERS
An encoder is a digital circuit that performs the inverse operation of a decoder. An encoder has 2"
(or fewer) input lines and output lines. The output lines. as an aggregate. generate the binary
code corresponding 10 the input value. An example of an encoder is the octal-to-binary encoder
whose truth table is given in Table 4.7. It has eight inputs (one for each of the octal digits) and
three outputs that generate the corresponding binary number. It is assumed that only one input has
a value of 1 at any given time. The encode r can be implemented with OR gates whose inputs
are determined directly from the truth table. Output c is equal to I when the input octal digit is I.
3. 5. or 7. Output ) is I for octal digits 2. 3. 6. or 7. and output x is I for digits 4. 5. 6. or 7. These
condition s can be expressed by the following Boolean output functions:
z = Dj + D3 + D5 + D7
y = D1 + D3+ D6+ D7
.r = D4 + D5 + Do + D7
The encoder can be implemented with three OR gates. The encoder defined in Table 4.7 has the
limitation that only one input can be active at any given time. If two inputs are active
simultaneously. the output produces an undefined combination.
For example: If DJ and Db are I simultaneously the output of the encoder will be 111 because all
three outputs are equal 10 I. The output II I does not represent either binary 3 or binary 6. To
resolve this ambiguity, encoder circuits must establish an input priority to ensure that only one
input is encoded. If we establish a higher priority for inputs with higher subscript numbers, and if
both lJ) and Do are 1 at the same time, the output will be 110 because D6 has higher priority than
Dl. Another ambiguity in the octal-to-binary encode r is that an output with all O's is generated
when all the inputs arc 0; but this output is the same as when Do is equal to I. The discrepancy
can be resolved by providing one more output to indicate whether at least one input is equal 10 1 .
Priority Encoder
A priority encoder is an encode r circuit that includes the priority function. The operation of the priority
encoder is such that if two or more inputs are equal to I at the same time. the input having the highest
priority will take precedence. The truth table of a four-input priority encoder is given in Table 4.8. In
addition to the two outputs .r and y. the circuit has a third output designated by V which is a valid bit
indicator that is set to I when one or more inputs are equal to I. If all input s are 0, there is no valid
input and V is equal to 0 .The other two outputs are not inspected when equals 0 and are specified as
don't -care conditions. Note that whereas X's in output columns represent don ' t-care conditions, the X
's in the input columns are useful for representing a truth table in condensed form. Instead of listing all
16 minterms of four variables, the truth table uses an X 10 represent either 1 or 0. For example, x100
represents the two minterms 0100 and 1100.According to Table 4.8, the higher the subscript number,
the higher the priority of the input. Input D has the highest priority. so, regardless of the values of the
other inputs.
For example.the fourth row in the table, with inputs XX10. represent s the
four minterms 0010,01 10, 10 10, and 11 10. The simplified Boolean
express ions for the priority encoder are obtained from the maps. The
condition for output V is an OR function of all the input variables. The
priority encoder is implemented in Fig. 4.23 according to the following
Boolean
functions:
Multiplexers:
A multiplexer is a combinational circuit that selects binary information
from one of many input lines and directs it to a single output line. The
selection of a particular input line is controlled by a set of selection lines.
Normally there are 2n input lines and II selection lines whose bit
combinations determine which input is selected.
A two-to-one-line multiplexer connects one of two l -bit sources to a
common destination, as shown in Fig. 4.24. The circuit has two data input
lines. one output line. and one selection line S. When 5 = 0. the upper AND
gate is enabled and 10 has a path to the output. When S = I, the lower AND
gate is enabled and 11has a path to the output. The multiplexer acts like
an electronic switch that selects one of two sources . The block diagram of
a multiplexer is sometimes depicted by a wedge-shaped symbol. as shown
in Fig. 4.24(b). It suggests visually how a selected one of multiple data
sources is directed into a single destination. The multiplexer is often labeled
"MUX" in block diagrams. A four-to-one-line multiplexer shown in Fig.
4.25. Each of the four Inputs I0 through I3 is applied 10 one input or an
AND gate. Selection lines S, and So are decoded to select
particular AND gate .The outputs of the AND gate arc applied to a single
OR gate that provides the one -line output The function table lists the input
that is passed to the output for each combination of the binary selection
values . To demonstrate the operation of the circuit consider the case when
S1 S0 = 10. The AND gate associated with input I 2 has two of its inputs
equal to 1 and the third input connected to I2. The other three AND gates
have at least one input equal to 0. which makes their outputs equal to 0.
The output of the OR gate is now equal to the value of I 2. providing a path
from the selected input to the output. A multiplexer is also called a delta
selector, since it selects one of many inputs and steers the binary
information to the output line. The AND gates and inverters in the
multiplexer resemble a decoder circuit and indeed they decode the
selection input lines. In general a 2"-to- l-line multiplexer is constructed
from an,1-10-2"decoder by adding 2"input lines to it one to each AND
gate. T be outputs of the AND gates are applied to single OR gate. The
size of a multiplexer is specified by the number 2"of its data input line
and the single output line. The two selection lines arc implied from the 2"
data lines. As in decoders, multiplexers may have an enable input to
control the operation of the unit. When the enable input is in the inactive
mode the outputs are disabled and when it is in the active the circuit
functions as a normal multiplexer. Multiplexer circuit its can he combined
with common selection inputs to provide multiple-bit Selection logic.
The circuit has four multiplexers each capable of selecting one of two
input lines. Output Yo can be selected to come from either input A0 or
input B0. Similarly output Y, may haw the value of A 1or 8,. and won.
Input selection line S selects one of the lines in each of the four
multiplexers. The enable input E must be active (i.e asserted) for normal
operation. Although the circuit contains two z-to-1-line multiplexers, we
are more likely to view it a-s 3 circuit that selects one of two -l-bit set of
data lines. As shown in the function table the unit is enabled when E = 0.
Then. if S = 0.the four A input have a path to the four outputs. If. by
contrast. 5 I the four B inputs are applied to the outputs. 1be outputs have
3111's when E I. regard 101’s of the value of 5.
OTH ER TWO-LEVEL IMPLEMENTATION S
The types of gates most often found in integrated circuits are NAND and
NOR gates. For this reason NAND and NOR logic implementations are the
most Important from a practical point of view. Some (but not all) NAND or
NOR gates al low the possibility of a wire connection between the outputs
of two gates to provide a specific logic function. This type of logic is called
wired logic. For example open-collector TTL NAND gates when tied
together perform wired AND logic.(The open-collector TTL gale is shown
in Chapter 10. Fig.10.1) The wired AND logic performed with two NAND
gates is depicted in Fig. 3.28(a). The AND gate is drawn with the lines
going through the center of the gate to distinguish it from a conventional
gate. The wired-AND gate is not a physical gate but only a symbol to
designate the function obtained from the indicated wired connection. The
logic function implemented by the circuit of Fig. 3.28(a) is
A wired-logic gale does not produce a physical second-level gate. since it is

just a wire connect ion. Nevertheless, for discussion purposes, we will
consider the circuits of Fig 3.28 as two-level implementations. The first
level consists of NAND(or NOR) gates and the second level has a sing le
AND(or OR) gate . The wired connection in the graphic symbol will be
omitted in subsequent discussions.
Nondegenerate Forms
It will be instructive from a theoretical point of view to find out how
many two-level combinations of gates are possible. We consider four
types of gates: AND,OR,NAND and) NOR. If we assign one type of gate
for the first level and one type for the second level . We find that there
are 16 possible combinations of two- level forms. (The same type of gate
ca n be in the first and second levels. as in a NAND-NAND
implementation.) Eight of these combinations are said to be degenerate
forms because they degenerate to a single operation. This can be seen
from a circuit with AND gates in the first level and an AND gate in the
second level. The output of the circuit is merely the AND function of all
input variables. The remaining eight nandegenerate forms produce an
implementation in sum-of-products form or product-of-sums form . The
eight nondegenerate forms are as follows:
AND-OR
NAND-NAND
NOR-OR
OR-NAND
OR- AND
NOR-NOR
NAND-AND
AN D-NOR
The first gate listed in each of the forms constitutes a first level in the
implementation. The second gate listed is a single gate placed in the IC
next level. Note that any two (forms listed on the same line are duals of
each other. The AND-OR and OR-AND form s are the basic two-level
forms discussed in Section 3.4. The NAND-NAND and NOR- NOR
forms were presented in Section3.6.The remaining four forms are
investigated in this section.
AND-OR-INVERT Implementation
The two forms NAND-AND and AND-NOR are equivalent and can be
treated together. Both perform (he AND-OR- INVERT function as
shown in Fig. 3.29. The AND-NOR form resembles the AND-OR form.
but with an inversion done by the bubble in the output of the NOR gate.
It implements the function
F=(AB+CD+E)'
By using the alternative graphic symbol for the NOR gate. we obtain the
diagram of
Fig. 3.29(b). Note that the single variable E is not complemented, because
the only change
made is in the graphic symbol of the NOR gate. Now we move the bubble
from the input terminal of tile second-level gate to the output terminals of
the first-level gates. An inverter is needed for the single variable in order to
compensate for the bubble. Alternatively, the inverter can be removed.
provided that input E is complemented. The circuit of Fig. 3.29(c) is a
NAND-AND form and was shown in Fig. 3.28 to implement the AND-OR-
INVERT function. An AND-OR implementation requires an expression in
sum-of-products form. The AND-OR- INVERT implementation is similar,
except for the inversion. Therefore, if tile complement of the function is
simplified into sum-of-products form (by combining the D's in the map). it
will be possible to implement F' with the AND-OR part of the function.
When F' passes through the always present output inversion (the INVERT
pan ), it will generate the output F of the function. An example for the
AND-OR- INVERT implementation will be shown subsequently.
OR-AND-INVERT Implementation
The OR- NAND and NOR..QR forms per form the OR- AND-INVERT
function, as shown in Fig. 3.30. The OR-NAND form resembles the OR-
AND form, except for the inversion done by the bubble in the NAND
gate. It implements the function
F = [(A + S)( e + D)E]'
By using the alternative graphic symbol for the NAND gate, we obtain the
diagram of
Fig. 3.30(b). The circuit in (c) is obtained by moving the small circ les from
the inputs of the second-level gate to the outputs of the first-level gates. The
circuit of Fig. 3.30(c) is a NOR-OR form and was shown in Fig. 3.28 to
implement the OR-AND-INVERT function. The OR- AND-INVERT
implementation requires an express ion in product-of-sums form. If the
complement of the function is simplified into that form, we can implement
F' with the OR- AND part of the function. When F' passes through the
INVERT part. we obtain the complement of F', or F, in the output.
HAZARDS
In designing asynchronous sequential circuits, care must be taken to

conform with certain restrictions and precautions 10 ensure that the circuits
operate properly. The circuit must be operated in fundamental mode with
only one input changing at any time and must be free of critical races. In
addition, there is one more phenomenon. called a hazard, that may cause
the circuit to malfunction . Hazards are unwanted switching transients that
may appear at the output of a circuit because different paths exhibit
different propagation delays. Hazards occur in combinational circuits,
where they may cause a temporary false output value. When they occur in
asynchronous sequential circuits. hazards may result in a transition 10 a
wrong stable state. It is therefore necessary 10 check for possible hazard s
and determine whether they can cause improper operations. If so, then steps
must be taken to eliminate their effect.
Hazards In Combinational Circuit

A hazard is a condition in which a change in a single variable produces a
momentary change in output when no change in output should occur. The
circuit of Fig. 9.33(a) depicts the occurrence of a hazard. Assume that all
three inputs are initially equal to I . This causes the output of gate I 10 be I ,
that of gate 2 to be 0 and that of the circuit 10 be 1. Now consider a change
in x 2 from I to O. Then the output of gale I changes 10 0 and that of gate 2
changes to I, leaving the output at I. However, the output may momentarily
go 10 0 if the propagation delay through the inverter is taken into
consideration. The delay in the inverter may cause the output of gate I to
change to 0 before the output of gate 2 changes to
I . In that case. both inputs

of gate 3 are momentarily equal to 0. causing the output to go to 0 for the
short time during which the input signal from X2 is delayed while it is
propagating through the Inverter circuit. The circuit of Fig. 9.33(b) is a
NAND implementation of the Boolean function in Fig. 9.33b) and it has a
hazard for the same reason . Because gates I and 2 are NAND gates their
outputs are the complement of the outputs o f the corresponding AND
gates. When X2 changes from 1 to 0 both inputs of gate3 may be equal to 1.
cau sing the output to produce a momentary change to 0 when it should
have stayed at I. The two circuits shown in Fig. 9.33 implement the
Boolean function in sum-of-products form :
Y=x1x2+x2’x3
This type of implementation may cause the output to go to 0 when it should
remain a I. If, however, the circuit is implemented instead in product-of-
sums form (see Section 3.5) namely.
Y=(x1+x2)(x2’+x3)
then the output may momentarily go to 1 when it should remain 0. The first
case is referred to as static-hazard and the second case as static-hazard. A
third type of hazard, known as dynamic hazard, causes the output to change
three or more times when it should change from 1 to 0 or from 0 to 1.
Figure 9,34 illustrates the three type s of hazard s. When a circuit is
implemented in sum-of -products form with AND-OR gates o r with
NAND gates the removal of static l-hazard guarantees that no static O-
hazards or dynamic hazard s will occur. A hazard can be detected by
inspection of the map of the particular circuit. To illustrate. Consider the
map in Fig. 9.35(a). which is a plot of the (unction implemented in Fig.
9.33 . The change in X2 from I 100 moves the circuit from minterm 111 to
minterm 101 be hazard exists because the change in input results in a
different product term covering the two min terms
Minterm 111 is covered by the product term implemented in gate I of Fig.

9.33. and minterm 101 is covered by the product term implemented in gate
2. Whenever the circuit must move from one product term to another. there
is a possibility of a momentary interval when neither term is equal to l,
giving rise to an undesirable 0 output. The remedy for eliminating a hazard
is to enclose the two mm terms in question with another product term that
overlaps both groupings. This situation is shown in the map of Fig. 9.35(b).
where the two minterms that cause the hazard are combined into one
product term. The hazard-free circuit obtained by such a configuration is
shown in Fig. 9.36. The extra gate in the circuit generates the product term
XIX). In general, hazards in combinational circuits can be removed by
covering any two minterms that may produce a hazard with a product term
common to both. The removal of hazards requires the addition of redundant
gates to the circuit.
Hazards In Sequential Circuits
In normal combinational-circuit design associated with synchronous
sequential circuits. hazards are of no concern, since momentary erroneous
signals are not generally troublesome. However. if a momentary incorrect
signal is fed back in an asynchronous sequential circuit. it may cause the
circuit to go to the wrong stable state. This situation is illustrated in Fig.
9.37. If the circuit is in total stable state )'x lx2 = II t and input X2 changes
from I to u. the next total stable stale should be 110. However . because of
the hazard. output Y may go to 0 momentarily. If this false signal feeds
back into gate 2 before the output of the inverter goes to I. the output of
gate 2 will remain at 0 and the circuit will switch to the incorrect total
stable stale 010.This malfunction can be eliminated by adding an extra gate,
as is done in Fig. 9.36.
Hazards In Sequential Circuits

In normal combinational-circuit design associated with synchronous
sequential circuits. hazards are of no concern, since momentary erroneous
signals are not generally troublesome. However. if a momentary incorrect
signal is fed back in an asynchronous sequential circuit. it may cause the
circuit to go to the wrong stable state. This situation is illustrated in Fig.
9.37. If the circuit is in total stable state )'x lx2 = II t and input X2 changes
from I to u. the next total stable stale should be 110. However . because of
the hazard. output Y may go to 0 momentarily. If this false signal feeds
back into gate 2 before the output of the inverter goes to I. the output of
gate 2 will remain at 0 and the circuit will switch to the incorrect total
stable stale 010.This malfunction can be eliminated by adding an extra gate,
as is done in Fig. 9.36.
Implementation with SR Latches
Another way to avoid static hazards in asynchronous sequential circuits is
10 implement the circuit with SR latches. A momentary 0 signal applied to
the S or R inputs of a NOR latch will have no effect on the state of the
circuit. Similarly. a momentary I signal applied to the S and R inputs of a
NAND latch will have no effect on the state of the latch. In Fig. we
observed that a two-level sum-of-products expression implemented with
NAND gates may have a static I-hazard if both inputs of gate 3 go to I,
changing the output from I to 0 momentarily. But if gate 3 is part of a latch,
the momentary I signal will have no effect on the output, because a third
input to the gate will come from the complemented side of the latch that
will be equal too and thus maintain the output at I. To clarify what was just
said, consider a NAND SR latch with the following Boolean functions for S
and R:
S = AB + CD
R = A'C
Since this is a NAND latch, we must apply the complemented values to the
inputs:
S= (AB + CD)' = (AB)'(CD)'
R=(A'C)'
This implementation is shown in Fig. 9.38(a). S is generated with two

NAND gates and one AND gate. The Boolean function for output Q is
Q = (Q'S)' =[Q'(AB)'(CD)']'
This function is generated in Fig. 9.38(b) with two levels of NAND gates.
If output Q is equal to I. then Q' is equal to. If two of the three inputs go
momentarily to I, the NAND gate associated with output Q will remain at I
because Q' is maintained ill O. Figure 9.38(b) shows a typical circuit that
can be used to construct asynchronous sequential circuits. The two NAND
gates forming the latch normally have two inputs. However, if the 45 5 or
functions contain two or more product terms when expressed as a sum of
products, then the corresponding NAND gate of the SR latch will have
three or more inputs. Thus the two terms in the original sum-of-products
expression for5 are AD and CD and each is implemented with a NAND
gate whose output is applied to the input of the NAND latch. In this way,
each slate variable requires a two-level circuit of NAND gates. The first
level consists of NAND gates that implement each product term in the
original Boolean expression of S and R. The second level forms the cross-
coupled connection of the SR latch with inputs that come from the outputs
of each NAND gate in the first level.
Essential Hazards
Thus far, we have considered what are known as static and dynamic
hazards. Another type of hazard that may occur in asynchronous sequential
circuits is called an essential hazard. This type of hazard is caused by
unequal delays along two or more paths that originate from the same input.
An excessive delay through an inverter circuit in comparison to the delay
associated with the feedback path may cause such a hazard. Essential
hazards cannot be corrected by adding redundant gates as in static hazards.
The problem that they impose can be corrected by adjusting the amount of
delay in the affected path. To avoid essential hazards each feedback loop
must be handled with individual care to ensure that the delay in the
feedback path is long enough compared with delays of other signals that
originate from the input terminals. This problem tends to be specialized, as
it depends on the particular circuit used and the size of the delays that are
encountered in its various paths.
PART B- Memory Elements and Programmable Logic Devices:
A memory unit is a device to which binary information is transferred for

storage and from which information is retrieved when needed for
processing. When data processing takes place. Information from memory
is transferred to selected registers in the processing unit. Intermediate and
final results obtained in the processing unit are transferred back to be stored
in memory. Binary information received from an input device is stored in
memory and information transferred to an output device is taken from
memory. A memory unit is a collection of cells capable of storing a large
quantity of binary information. There are two types of memories that are
used in digital systems: random-access memory (RAM and read-only
memory (ROM). RAM: stores new information for later use. The PROM is
of storing new information in to memory is referred to as a memory write
operation. The process of transferring the stored information out of memory
is referred to as a memory read operation. RAM can perform both write and
read operations. ROM can perform only the read operation. This means
that suitable binary information is already stored inside memory and can be
retrieved or read at any time. However, that information cannot be altered
by writing. ROM is a programmable logic device (PLO).The binary
information that is stored within such a device is specified in some fashion
and then embedded within the hardware in a process is referred to
reprogramming the device. The word "programming" here refers to a
hardware procedure which specifics the bits that are inserted into the
hardware configuration of the device. ROM is one example of a PLD.
Other such units are the programmable logic array (PLA). programmable
array logic (PAL), and the field-programmable gate array (FPGA). A PLD
is an integrated circuit with internal logic gates connected through
electronic paths that behave similarly to fuses. In the original state of the
device all the fuses are intact. Programming the device Involves blowing
those fuses along the paths that must be removed in order to obtain
The particular configuration of the desired logic function . In this chapter,

we introduce the configuration of PLOs and indicate procedures for their
use in the design of digital systems. We also present CMOS FPGAs, which
are configured by downloading a stream of bits into the device to configure
transmission gates to establish the internal connectivity required by a
specified logic function (combinational or sequential). Atypical Pill may
have hundreds to millions of gates interconnected through hundreds to
thousands of internal paths. In order to show the internal logic diagram of
such a device in a concise form, it is necessary to employ a special gate
symbology applicable to array logic.Figure7.1shows the conventional and
array logic symbols for a multiple-input OR gate. Instead of having
multiple input lines into the gate. we draw a single line entering the gate.
The input lines are drawn perpendicular to this single line and are
connected to the gate through internal fuses. In a similar fashion, we can
draw the array logic for an AND gate. This type of graphical representation
for the inputs of gates will be used throughout the chapter in array logic
diagrams.
RANDOM -ACCESS MEMORY
A memory unit is a collection of storage cells. together with associated

circuits needed to transfer information into and out of a device. The
architecture of memory is such that information can be selectively retrieved
from any of its internal locations. The time it takes to transfer information
to or from any desired random location is always the same-hence the name
random access memory, abbreviated RAM. In contrast, the time required to
retrieve information that is stored on magnetic tape depends on the location
of the data. A memory unit stores binary information in groups of bits
called word/so A word in memory is an entity of bits that move in and out
of storage as a unit. A memory word is a group of I's and D's and may
represent a number, an instruction, one or more alphanumeric characters. or
any other binary-coded information. A group of 8 bits is called a byte. Most
computer memories use words that are multiples of 8 bits in length. Thus a
l6·bit word contains two bytes and a 32-bit word is made up of four bytes.
The capacity of a memory unit is usually stated as the total number of bytes
that the unit can store. Communication between memory and its
environment is achieved through data input and output lines, address
selection lines, and control lines that specify the direction of transfer. A
block diagram of a memory unit is shown in Fig. 7.2. The n data input lines
provide the information to be stored in memory. and the n data output lines
supply the information coming out of memory. The k address lines specify
the particular word chosen among the many available. The two control
inputs specify the direction of transfer desired: The Write input causes
binary data to be transferred into the memory and the Read input causes
binary data to be transferred out of memory .
Fig 2: Block diagram of Memory unit.
The memory unit is specified by the number of words it contains and the
number of bits in each word. The address lines select one particular word.
Each word in memory is assigned an identification number is called an
address starting from 0 up 10 24 -1. where k is the number of address lines.
The selection of a specific word inside memory is done by applying the
k·bit address to the address lines. An internal decoder accepts this address
and open the paths needed to select the word specified. Memories vary
greatly in size and may range from 1.024 words. requiring an address of
10bits to 232words requiring 32 address bits. It is customary to refer to the
number of words (or bytes) in memory with one of the measures K (kilo),
M (mega) and G (giga). K is equal to 2 10.=1k M is equal to 220 and G is
equal to 230. Thus. (64k= 216. 2M=221. and 4G = 232). Consider for example
a memory unit with a capacity of IK words of 16 bits each. Since IK=1.02-t
= 210and 16bits constitute two bytes. we can say that the we can
accommodate 2K bytes. Figure shows possible contents of the first three
and the last
Three words of this memory. Each word contains 16 bits that can be
divided into two bytes. The words are recognized by their decimal address
from 0 to 1,023. The equivalent binary address consists of 10 bits. The first
address is specified with ten 0's: the last address is specified with ten l’s.
because 1023 in binary is equal to 1111111 111.A word in memory is
selected by its binary address. When a word is read or written, the memory
operates on all 16bits as a single unit. The 1K X 16 memory of Fig. 7.3 has
10 bits in the address and 16 bits in each word. As another example a 64K
X 10 memory will have 16 bits in the address (since 64K = 216) and each
word will consist of 10 bits. The number of address bits needed in a
memory is dependent on the total number of words that can be stored in the
memory and is independent of the number of bits in each word. The
number of bits in the address is determined from the relationship 2* e m.
where m is the total number of words and k is the number of address bits
needed to satisfy the relationship.
Types of Memories
The mode of access of a memory system is determined by the type of

components used. In a random-access memory, the word locations may be
thought of as being separated in space. each word occupying one particular
location. In a sequential-access memory. me information stored in some
medium is not immediately accessible, but is available only at certain
intervals of time. A magnetic disk or tape unit is of this type. Each memory
location passes me read and write heads in turn. but information is read out
only when the requested word has been reached.
In a random-access memory, the access time is always the same regardless

of the particular location of the word. In a sequential-access memory. the
time it takes to access a word depends on the position of the word with
respect to the position of the read head: therefore the access time is
variable. Integrated circuit RAM units are available in two operating
modes: static and dynamic. Static RAM (SRAM consists essentially of
internal latches that store the binary information. The stored information
remains valid as long as power is applied to the unit. Dynamic RAM
(DRAM) stores the binary information in the form of electric charges on
capacitors provided inside the chip by MOS transistors. The stored charge
on the capacitors tends to discharge with time and the capacitors must be
periodically recharged by refreshing the dynamic memory. Refreshing is
done by cycling through the words every few milliseconds to restore the
decaying charge. DRAM offers reduced power consumption and larger
storage capacity in a single memory chip. SRA M is easier to use and has
shorter read and write cycles. Memory units that lose stored information
when power is turned off are said to be volatile, CMOS integrated circuit
RAMs, both static and dynamic. are of this category, since the binary cells
need external power to maintain the stored information. In contrast, a
nonvolatile memory, such as magnetic disk retains its stored information
after the removal of power, This type of memory is able to retain
information because the data stored on magnetic components are
represented by the direction of magnetization. which is retained after power
is turned off
ROM is another nonvolatile memory, A nonvolatile memory enables digital

computers to store programs that will be needed again after the computer is
turned on. Programs and data that cannot be altered are stored in ROM.
while other large programs are maintained on magnetic dish. The latcr
programs are transferred into the computer RAM as needed. Before the
power is turned off. the binary information from the computer RAM is
transferred to the disk so that the information will be retained.
READ-ONLY MEMORY
A ROM is essentially a memory device in which permanent binary

information is stored. The binary information must be specified by the
designer and is then embedded in the unit to form the required
interconnection pattern. Once the pattern is established. it stays within the
unit even when power is turned off and on again. A block diagram of a
ROM consisting of k inputs and n output s is shown in Fig. 7.9. The inputs
provide the address for memory. and the outputs give the data bits of the
stored word that is selected by the address. The number of words in a ROM
is determined from the fact that k address input lines are needed to specify
2k words. Note that ROM does not have data inputs. because it does not
have a write operation. Integrated circuit ROM chips have one or more
enable inputs and sometimes come with three-state outputs to facilitate the
construction of large arrays of ROM. Consider. for example. a 32 X 8
ROM. The unit consists of 32 words of 8 bits each. There are five input
lines that form the binary numbers from 0 through 31 for the address.
Figure 7.10 shows the internal logic construction of this ROM. The five
inputs are decoded into 32 distinct outputs by means ofa5X32 decoder.
Each output of the decoder represents a memory address.
The 32 outputs of the decoder are connected to each of the eight OR gates.
The diagram shows the array logic convention used in complex circuits.
(See Fig. 6.1.) Each OR gate must be considered as having 32 inputs. Each
output of lhe decoder is connected to one of the inputs of each OR gate.
Since each OR gate has 32 input connections and there are 8 OR gates, the
ROM contains 32 x 8 = 256 internal connections. In general a 2 1 X n
ROM will have an internal k X 2 1 decoder and n OR gates. Each OR gate
has 2k inputs, which are connected to each of the outputs of the decoder.
The 256 intersections in Fig.7.10 are programmable. A programmable
connection between two lines is logically equivalent to a switch that can be
altered to be either closed (meaning that the two lines are connected) or
open (meaning that the two lines are disconnected). The programmable
intersection between two lines is sometimes called a cross point. Various
physical devices are used to implement cross point switches. One of the
simplest technologies employs a fuse that normally connects the two points.
but is opened or "blown" by the application of a high-voltage pulse into the
fuse. The internal binary storage of a ROM is specified by a truth table that
shows the word content in each address. For example the content ofa32 X 8
ROM may be specified with a truth table similar to the one shown in Table
7.3.The truth table shows the five inputs under which are listed all 32
addresses. Each address stores a word of 8 bits. which is listed in the
outputs columns. The table shows only the first four and the last four words
in the ROM. The complete table must include the list of all 32 words. The
hardware procedure that programs the ROM blows fuse links in accordance
with a given truth table. For example programming the ROM according to
the truth table given by Table 7.3 results in the configuration shown in Fig.
7.11. Every 0 listed in the truth table
specifies the absence of a connection and every I listed specifies a path that
is obtained by a connection. For example the table specifies the eight-bit
word 10110010 for permanent storage at address 3. The four 0's in the
word are programmed by blowing the fuse links between output 3 of the
decoder and the inputs of the OR gates associated with outputs A(i. AJ• A2.
and Ao. The four l's in the word are marked with a X to denote a temporary
connection, in place of a dot used for a permanent connection in logic
diagrams. When the input of the ROM is 000 II. all the outputs of the
decoder are 0 except for output 3, which is at logic I. The signal equivalent
to logic I at decoder output 3 propagates through the connections to the OR
gate outputs of A ,. A3. A4. and A ].The other four outputs remain at 0 .The
result is that the stored word 10II00 are 0l’s applied to the eight data
outputs.
Combinational Circuit Implementation In Section 4.9. it was shown that a

decoder generates the 2K minterms of me k input variables. By inserting
OR gales to sum the minterms of Boolean functions. we were able to
generate any desired combinational circuit. The ROM is essentially a
device that includes both me decoder and the OR gates within a single
device to form a minterm generator. By choosing connections for those
minterms which are included in the function, the ROM outputs can be
programmed to represent the Boolean functions of the output variables in a
combinational circuit. The internal operation of a ROM can be interpreted
in two ways. The first interpretation is that of a memory unit that contains a
fixed pattern of stored words. The second interpretation is mat of a unit
which implements a combinational circuit. From this point of view. each
output terminal is considered separately as the output of a Boolean function
expressed as a sum of minterms. For example. the ROM of Fig.7.11 may be
considered 10 be a combinational circuit with eight outputs. each a function
of the five input variables. Output A, can be expressed in sum of minterms
as
The three dots represent minterms 4 through 27, which are not specified in
the figure. IA connection marked with X in the figure produces a minterm
for the sum. All other cross points are not connected and are not included in
the sum. In practice, when a combinational circuit is designed by means of
a ROM. it is not necessary to design the logic or to show the internal gate
connections inside the unit All that the designer has to do is specify the
particular ROM by its ie number and provide me applicable truth table. The
truth table gives all the information for programming the ROM. No internal
logic diagram is needed to accompany the truth table.
Design a combinational circuit using a ROM. The circuit accepts a three-bit

number and outputs a binary number equal to the square of the input
number. The first step is to derive the truth table of the combinational
circuit. In most cases this is all that is needed. In other cases, we can use a
partial truth table for the ROM by utilizing certain properties in the output
variables. Table 7.4 is the truth table for the combinational circuit. Three
inputs and six outputs are needed to accommodate all possible binary
numbers. We note that output Bo is always equal to input Ao. so there is no
need to generate Bo with a ROM. since it is equal to an input variable.
Moreover, output B is always 0. so this output is a known constant. We
actually need to generate only four outputs with the ROM the other two are
readily obtained. The minimum size of ROM needed must have three inputs
and four outputs. Three inputs specify eight words, so the ROM must be of
size 8 x 4. The ROM implementation is shown in Fig. 7.I2. The three inputs
specify eight words of four bits each. The truth table in Fig. 7.12(b)
specifies the information needed for programming the ROM. The block
diagram
Types of ROMs
The required paths in a ROM may be programmed in four different ways.

The first is called mask programming and is done by the semiconductor
company during the last fabrication process of the unit. The procedure for
fabricating a ROM requires that the customer fill out the truth table he or
she wishes the ROM to satisfy. The truth table may be submitted in a
special form provided by the manufacturer or in a specified format on a
computer output medium. The manufacturer makes the corresponding mask
for the paths to produce the 1's and 0's according to the customer's truth
table. This procedure is costly because the vendor charges the customer a
special fee for custom masking the particular ROM. For this reason, mask
programming is economical only if a large quantity of the same ROM
configuration is to be ordered. For small quantities, it is more economical
to use a second type of ROM called programmable read-only memory or
PROM. When ordered, PROM units contain all the fuses intact. giving all
l’s in the bits of the stored words. The fuses in the PROM are blown by the
application of a high-voltage pulse to the device through a special pin. A
blown fuse defines a binary 0 state and an intact fuse gives a binary I state.
This procedure allows the user to program the PROM in the laboratory to
achieve the desired relationship between input addresses and stored words.
Special instruments called PROM programmers are available commercially
to facilitate the procedure. In any case, all procedures for programming
ROM’s are hardware procedures, even though the word programming is
used. The hardware procedure for programming ROMs or PROMs is
irreversible and once programmed it be fixed pattern is permanent and
cannot be altered.
Once a bit pattern has been established the unit must be discarded if the bit
pattern is to be changed. A third type of ROM is the erasable PROM or
EPROM. which can be restructured to the initial state even though it has
been programmed previously. When the EPROM is placed under a special
ultraviolet light for a given length of time. the shortwave radiation
discharges the internal floating gates that serve as the programmed
connections. After erasure, the EPROM returns to its initial state and can be
reprogrammed to a new set of values. The fourth type of ROM is the
electrically erasable PROM (EEPROM or E2PROM). This device is like the
EPROM except that the previously programmed connections can be erased
with an electrical signal instead of ultraviolet light. The advantage is [hat
the device can be erased without removing it from its socket. Hash memory
devices are similar to EEPROMs. but have additional built-in circuitry to
selectively program and erase the device in-circuit, without the need for a
special programmer. They have widespread application in modern
technology in cell phones. digital camera setup boxes. digital TV.
telecommunications. Non volatile data storage. and microcontrollers. Their
low consumption of power makes them an attractive storage medium for
laptop and notebook computers. Flash memories incorporate additional
circuitry, too. allowing simultaneous erasing of blocks of memory. for
example, of size 16 Kbytes to 64 Kbytes. Like EEPROMs flash memories
are subject to fatigue. typically having about 105 block erase cycles.
Combinational PLDs
The PROM is a combinational programmable logic device (PLD}-an

integrated circuit with programmable gates divided into an AND array and
an OR array to provide an AND-OR sum of-product implementation. There
are three major types of combinational PLDs. differing in the placement of
the programmable connections in the AND-OR array. Figure 1.13shows the
configuration of the three PLDs. The PROM has a fixed AND array
constructed as a decoder and a programmable OR array. The programmable
OR gates implement the Boolean functions in sum-of-min terms form. The
PAL has a programmable AND array and a fixed OR array. The AND gates
are programmed to provide the product terms for the Boolean functions.
which are logically summed in each OR gate. The most flexible PLD is the
PLA. in which both the A.'<0 and OR arrays can be programmed. The
product terms in the AND array may be shared by any OR gate to provide
the required sum-of-products implementation. The names PAL and PLA
emerged from different vendors during the development of PLDs. The
implementation of combinational circuits with PROM was demonstrated in
this section. The design of combinational circuits with PLA and PAL is
presented in the next two sections.
PROGRAMMABLE LOGIC ARRAY (PLA)
The PLA is similar in concept to the PROM. except that the PLA does not
provide full decoding of the variables and does not generate all the min
terms. The decoder is replaced by an array of AND gates that can be
programmed to generate any product term of the input variables. The
product terms are then connected 10 OR gates to provide the sum of
products for the required Boolean functions. The internal logic of a PLA
with three inputs and two outputs is shown in Fig. 7.14. Such a circuit is
too small to be useful commercially, but is presented here to demonstrate
the typical logic configuration of a PLA. The diagram uses the array logic
graphic symbols for complex circuits. Each input goes through a buffer-
inverter combination, shown in the diagram with a composite graphic
symbol, that has both the true and complement outputs. Each input and its
complement are connected to the inputs of each AND gate, as indicated by
the intersections between the vertical and horizontal lines. The outputs of
the AND gates are connected to the inputs of each OR gate. The output of
the OR gate goes to an XOR gate, where the other input can be
programmed to receive a signal equal to either logic I or logic O. The
output is inverted when the XOR input is connected to 1 (since x $ 1 = x').
The output does not change when the XOR input is connected to 0 (since x
$ 0= x). The particular Boolean functions implemented in the PLA of Fig.
7.14 are F1 = AB' + AC + A'BC' F, ~ (AC + BC)'
The product terms generated in each AND gate are listed along the output
of the gate in the diagram. The product term is determined from the inputs
whose cross points are connected and marked with a X. The output of an
OR gate gives the logical sum of the selected product terms. The output
may be complemented or left in its true form, depending on the logic being
realized. The fuse map of a PLA can be specified in a tabular form. For
example, the programming table that specifies the PLA of Fig.7.14 is listed
in Table 7.5.The PLA programming table consists of three sections. The
first section lists the product terms numerically. The second section
specifies the required paths between inputs and AND gates. The third
section specifies the paths between the AND and OR gates. For each output
variable, we may have a T'(for true] or C (for complement) for
programming the XOR gate. The product terms listed on the left are not
part of the table; they are included for reference only. For each product
term. The inputs are marked with I, 0, or - (dash). If a variable in the
product term appears in the form in which it is true, the corresponding input
variable is marked with a 1. If it appears complemented the corresponding
input variable is marked with a 0. If the variable is absent from the product
term, it is marked with a dash.
The paths between the inputs and the AND gates are specified under the
column head "Inputs" in the programming table. A I in the input column
specifies a connection from the input variable to the AND gate. A 0 in the
input column specifies a connection from the complement of the variable to
the input of the AND gate, A dash specifies a blown fuse in both the input
variable and its complement. It is assumed that an open terminal in the
input of an AND gate behaves like a I, The paths between the AND and
OR gates are specified under the column head "Outputs," The output
variables are marked with l's for those product terms which are included in
the function, Each product term that has a I in the output column requires a
path from the output of the AND gate to the input of the OR gate. Those
marked with a dash specify a blown fuse, It is assumed that an open
terminal in the input of an OR gate behaves like a 0. Finally a T (true)
output dictates that the other input of the corresponding XOR gate be
connected to 0, and a C (complement) specifies a connection to I. The size
of a PLA is specified by the number of inputs. the number of product
terms, and the number of outputs. Atypical integrated circuit PLA may have
16 inputs, 48 product terms, and eight outputs. For n inputs, k product
terms and m outputs, the internal logic of the PLA consists of n buffer-
inverter gates, k AND gates, m OR gates, and m XOR gates. There are 2n x
k connections between the inputs and the AND array, k x m connections
between the AND and OR arrays. and m connections associated with the
XOR gates. In designing a digital system with a PLA, there is no need to
show the internal connections of the unit as was done in Fig. 7.14.All that is
needed is a PLA programming table from which the PLA can be
programmed to supply the required logic. As with a ROM, the PLA may be
mask programmable or field programmable. With mask programming. the
customer submits a PLA program table to the manufacturer, This table is
used by the vendor to produce a custom-made PLA that has the required
internal logic specified by the customer. A second type of PLA that is
available is the field-programmable logic array, or FPLA, which can be
programmed by the user by means of a commercial hardware programmer
unit. In implementing a combinational circuit with a PLA, careful
investigation must be undertaken in order to reduce the number of distinct
product terms. since a PLA has a finite number of AND gates. This can be
done by simplifying each Boolean function to a minimum number of terms.
The number of literals in a term is not important, since all the input
variables are available anyway. Both the true value and the complement of
each function should be simplified 10 see which one can be expressed with
fewer product terms and which one provides product terms that are
common to other functions.
Implement the following two Boolean functions with a PLA: FI(A,B,C)

= L (0,1,2,4)
F(A, B,C) =L (0, 5,6,7)
The 1.....0 functions are simplified in the maps of Fig. 7.15. Both the true
value and the complement of the functions arc simplified into sum-of-
products form. The combination that gives the minimum number of product
terms is F1 = (A B + AC + BC)' and F2 = AB + AC + A'B'C' .This
combination gives four distinct product terms: AB. AC, B C' and A'B'C'.
The PLA programming table for the combination is shown in the figure.
Note that output PI is the true output, even though a C is marked over it in
the table. This is because F1 is generated with an AND-OR circuit and is
available at the output of the OR gate. The XOR gate complements the
function to produce the true F1 output.
he combinational circuit used in Example 7.2 is too simple for

implementing with a PLA. It was presented merely for purposes of
illustration. A typical PLA has a large number of inputs and product terms.
The simplification of Boolean functions with so many variables should be
carried out by means of computer-asserted simplification procedures, The
computer-aided design program simplifies each function and its
complement 10 a minimum number of terms. The program then selects a
minimum number of product terms that cover all functions in the form in
which they are true or in their complemented form. The PLA programming
table is then generated and the required fuse map obtained. The fuse map is
applied to an FPLA programmer that goes through the hardware procedure
of blowing the internal fuses in the integrated circuit.
PROGRAMMABLE ARRAY LOGIC (PAL)
The PAL is a programmable logic device with a fixed OR array and a

programmable AND array. Because only the AND gates are programmable,
the PAL is easier to program than. but is not as flexible as the PLA. Figure
7.16 shows. the logic configuration of a typical PAL with four inputs and
four outputs. Each input has a buffer- inverter gale. and each output is
generated by a fixed OR gate. There are four sections in the unit. each
composed of an AND-OR array that is three wide. the term used to indicate
that there arc three programmable AND gates in each section and one fixed
OR gate. Each AND gate has 10 programmable input connections shown in
the diagram by 10 vertical lines intersecting each horizontal line. The
horizontal line symbolizes the multiple-input configuration of the AND
gate. One of the outputs is connected to a buffer-inverter gate and then fed
back into two inputs of the AND gates. Commercial PAL devices contain
more gates than the one shown in Fig. 7.16. A typical PAL integrated circuit
may have eight inputs. Eight outputs and eight sections each consisting of
an eight-wide AND-Or array. The output terminals are sometimes driven by
three-state buffers or inverters. In designing with a PAL. the Boolean
functions must be simplified to fit into each section. Unlike the situation
with a PLA. a product term cannot be shared among two or more OR gates.
Therefore each function can be simplified by itself, without regard to
common product terms. The number of product terms in each section is
fixed and if the number of ten us in the function is too large it may be
necessary to use two sections to implement one Boolean function. As an
example of using a PAL in the design of a combinational circuit. consider
me following Boolean functions given in sum-of-minterms form:
each to conform with the PAL of Fig. 7.16. The first two sections need only
two product terms to implement the Boolean function. The last section for
output z, needs four product terms. Using the output from w, we can reduce
the function 10 three terms. The fuse map for the PAL as specified in the
programming table is shown in Fig. 7,17, For each I or 0 in the table, we
mark the corresponding intersection in the diagram with the symbol for an
intact fuse. For each dash. we mark the diagram with blown fuses in both
the true and complement inputs. If the AND gate is not used, we leave all
its input fuses intact. Since the corresponding input receives both the true
value and the complement of each input variable. we have AA' '" 0 and the
output of 1heA.''D gate is always 0. As with all PLDs. the design with PALs
is facilitated by using computer-aided design techniques. The blowing of
internal fuses is a hardware procedure done with the help of special
electronic instruments.
Unit – IV
Part A: Synthesis of Symmetric Networks
Relay Contacts, Analysis and Synthesis of Contact Networks, Symmetric
Networks, Identification of Symmetric Functions and realization of the same.
Relay Contacts: Combinational networks can be constructed by
semiconductor switches (like BJTs / FETs) or Mechanical switches (Relay
contacts). The comparisons of these two types are given below:
Relay contacts Semiconductor switches
Bidirectional (as the contact is a mechanical type, the Unidirecti
flow can be in both the directions of the switch) onal.
Slow ( relay switch ON & OFF times are large) Fast
Not useful in computer applications, as speed of Can be used in all

operation is important. Useful in slow applications applications.
like Traffic lights control, elevators etc.
Relay operation:
A Relay is a electromechanical device, which contains a coil and one or
more contacts. When the coil is excited by applying the rated voltage, the
coil will become an electromagnet and changes the position of the contact
by attracting it. If the excitation is removed, the contact will go back to
normal position due to a spring action. The different types of contacts are
NO (Normally open), NC ( Normally closed) and Transfer contact ( Change
over ). The symbols are as given below.
Using relays, implementing some Basic logic functions is given below:
Analysis and Synthesis of Contact Networks:

Analysis of two terminal contact network means, the determination of its
transfer function. The networks which have more than two terminals, the
transfer function is determined for each pair of terminals. The Synthesis is
the converse of its analysis. The desired network performance is specified
by a switching expression and the corresponding circuit is derived.
a. Analysis of series parallel networks:

As shown above, if two contacts are in series, T = x.y (an AND logic) and
if two contacts are in parallel, T = x + y (an OR logic). If the parameter is to
be in complemented function, NC contact is used and if it is non-
complemented, NO contact is used. Any switching function can be
implemented using these series parallel networks as described below:
Ex: Analyze the below switching logic circuit.

In the upper portion, two parallel circuits are there each with a serial circuit.
It is y'.z + z'.y. This is in series with w'. The switching function is (y'.z + z'.
y) . w'
The lower portion has three parallel paths and the switching function is w +
y' + (z' . x')
The upper portion and the lower portion are in parallel and these two
parallel paths are in series with x'. Hence, the transfer function of the given
circuit is
T = x' . {(y'.z + z'. y) . w' + w + y'+ z' . x'}
By simplifying the above,
T= w'x'y'z + w'x'yz' + wx' + wy' + wx'z'
= x' (w+y'+z')
The simplified circuit is
b. Analysis of non-series-parallel networks:

The analysis given above will not be applicable for non-series-parallel
networks ( i.e. bridge type networks). The analysis is done in two ways – i.e
using tie sets and using cut sets.
Ex: Analyze the following circuit using tie sets:

The analysis is done by tracing all paths from one terminal to the other. The
path from terminal i to terminal j is possible in different ways, which are
known as tie sets. If any one or more of these paths are ON, the path from
input to output exists. These paths are
w.x, w.v.z, y.v.x, and y.z.
Hence, T = wx + wvz+ yvx + yz.

In this case, we get the expression in SOP form.
Analysis of the above network using cut sets:
It is the duality of the above analysis. Here, all cut paths are shown, so that
if any of these paths are open (OFF), the output is 0. Dotted lines are
through the network contacts, so as to separate all possible links between
the inputs and the outputs. The transfer function in this case is POS form by
expressing these cuts as sums. These cuts are : w+y, x+z, w+v+z, x+v+y
and the transfer function is
T = (w+y).(x+z).(w+v+z).(x+v+y).
Synthesis of Contact networks:

The requirements of the required network are to be expressed in the form of
switching network. Based on the description of the requirement, truth table
is to be prepared and the same is to be simplified and a corresponding series
parallel network is obtained. A minimal function gives cost effective
solution. A minimal function means – minimum number of literals and
using transfer contacts (change over contacts – meaning both complement
and non-complement contacts). Once the minimal series-parallel function is
achieved, the same is realized using the Relay contacts, as explained above.
Symmetric Networks:
Definitions: A switching function of n variables f(x1,x2,........xn) is called
symmetric or totally symmetric if and only if it is invariant under any
permutation of variables ;
It is called partially symmetric in the variables xi,xj, where {xi,xj} is a
subset of {x1,x2,........xn} , if and only if the interchange of the variables xi,
xj leaves the function unchanged.
Example: f(a,b,c)=a’b’c+ab’c’+a’bc’ is symmetric because interchange
between variables doesn’t change the function. Where as
f(a,b,c) = a’b’c+ab’c’ is partially symmetric in the variables a and c.
The variables in which a function is symmetric are called the variables of
symmetry.
A symmetric function is denoted Sa1,a2...ak(x1,x2,........xn), where S
designates the property of symmetry, the superscripts a1,...ak designate the
a-numbers, and (x1,x2,........xn) designates the variables of symmetry.
Example-1: The function f(a,b,c)=a’b’c+a’bc’+ab’c’ assumes the value
‘1’when and only when one out of its three variables is ‘1’.
This function is denoted as S1(a,b,c), similarly the symmetric function S
1,3 (a,b,c) is f(a,b,c)=abc+a’b’c+ab’c’+a’bc’
Definition-2: Let f1(a,b,c,d) = S 0,2,4 (a,b,c,d) and f2(a,b,c,d) = S 3,4
(a,b,c,d)
then f3(a,b,c,d) = f1+f2 = S 0,2,3,4 (a,b,c,d) and f4(a,b,c,d) = f1*f2 = S 4
(a,b,c,d).
The complement of the symmetric function is also a symmetric function
whose a-numbers are included in the set {0,1..n}and not included in the
original function.
for example S’ 0,2,4 (a,b,c,d) = S 1,3 (a,b,c,d) for set of {0,1,2,3,4}.
Representation of symmetric functions:

The basic network for symmetric function is shown below. Network is
drawn for four variables and it can be extended for n variables. It is a multi
output network consisting of a single input and 5 output numbered from 0
to 4 .
• Network which realizes symmetric function is called symmetric network.
Contacts of symmetric network are arranged in such a way that input can
propagate in two directions.
-From bottom to top
-And from left to right
Contacts of the operated relays (NO type) shifts input upward to successive
level, while contacts of the un- operated relays (NC type) shifts input to the
right.
These properties of the symmetric function make it possible to simplify the
network in the various ways.
Realization of Symmetric functions:
Switch Realization of the Lattice Realization of symmetric
symmetric function: function:
Example of symmetric network, Function realization and Synthesis:
Let us realize symmetric function S1,4(a,b,c,d)

-It is necessary to join output terminals labeled 1 and 4 .
-It is required to delete all unused terminal.
-Minimal network of the function can be achieved
-This simplified network represents the Boolean function
f=a’b’c’d+a’b’cd’+a’bc’d’+ab’c’d’+abcd.
This simplification of symmetric network is called synthesis of symmetric
network.
Synthesis of symmetric network:

Observation:
Mirror image function of any symmetric function is symmetric for same

negated variable for which original function is symmetric.
Identification of Symmetric Functions:
The procedure for identifying symmetric function is as follows:
1. Obtain column sums
a. if more than two different sums occur (case 1), the function is not
symmetric.
b. If two different sums occur (case 2), compare the total of these two sums
with the number of rows in the table. If they are not equal (case 2a), the
function is not symmetric. If they are equal (case 2b), complement the
columns corresponding to either one of the column sums (preferably the
one of fewer occurrences) and continue to step 2.
c. If all column sums are identical (case 3), compare their sum with one-
half the number of rows in the table. If they are not equal (case 3a),
continue to step 2. If they are equal, continue to step 3.
2. Obtain row sums and check each for sufficient occurrence, that is if a is
one row sum and n is the number of variables, then that row sum much n!/
(n-a)!a! Times.
a. If any row sum does not occur the required number of times, the function
is not symmetric.
b. If all row sums occur the required number of times, the function is
symmetric, its a-numbers are given by the different row sums in column a.
and its variables of symmetry are given at the top of the table.
3. Obtain row sums and check each for sufficient occurrence.
a. If all row sums occur the required number of times, the function is
symmetric.
b. If any row sum does not occur the required number of times, expand the
function about any of its variables – that is, find functions g and h such that
f = x'g + xh. Write g and in tabular form and find their column sums.
Determine all variable complementations required for the identifications of
symmetries in g and h. Test f under the same variable complementations. If
all row sums occur the required number of times, f is symmetric; if any row
sum does not occur the required number of times, f is not symmetric.
Examples:
1. f(x,y,z) = ∑ (1,2,4,7).
The truth table is The sum of all columns is equal

(case 3). Their sum is 6 which is
x y z Row Sum not equal to ½ of the number of
0 0 1 1 row (case 3a). Go to step 2:
0 1 0 1 Check for the row sums for
sufficient occurrence i.e. n!/(n-a)!
1 0 0 1
a! I.e 3! / (3-1)!.1! = 3 and 3! /
1 1 1 3 (3-3)!.3! = 1. Both the row sums
2 2 2 Column Sum occur the required number of
times, so the function is
symmetrical and can be expressed
as S1,2 (x,y,z).
2. f(w,x,y,z) = ∑(0,1,3,,5,8,10,11,12,13,15).
The truth table is two sums is 10 which is equal
to the number of rows (case
w x y z Row Sum
2b). We have to complement
0 0 0 0 0 x and y ( whose column sum
is less)
0 0 0 1 1
0 0 1 1 2 w x' y' z Row Sum
0 1 0 1 2 0 1 1 0 2
1 0 0 0 1 0 1 1 1 3
1 0 1 0 2 0 1 0 1 2
1 0 1 1 3 0 0 1 1 2
1 1 0 0 2 1 1 1 0 3
1 1 0 1 3 1 1 0 0 2
1 1 1 1 4 1 1 0 1 3
6 4 4 6 Column Sum 1 0 1 0 2
1 0 1 1 3
The sum of columns is not equal
and these are two different sums 1 0 0 1 2
(case 2). The sum of these 6 6 6 6 Column sum
Go to step 2 : Check for the row sums for sufficient occurrence i.e. n!/(n-a)!
a! I.e 4! / (4-2)!.2! = 6 and 4! / (4-3)!.3! = 4. Both the row sums occur the
required number of times, so the function is symmetric and can be
expressed as f(w,x,y,z) = S2.,3 (w,x',y',z).
If columns w and x are complemented, then the function can be expressed

as:
f(w,x,y,z) = S1,2 (w',x,y,z').
Part B: Threshold Logic
Threshold Element, Capabilities and Limitations of Threshold logic,
Elementary Properties, Synthesis of threshold networks (Unate function,
Linear seperability, Identification and realization of threshold functions,
Map based synthesis of two-level Threshold networks).
Introduction:
Threshold elements are another type of switching elements. Logic Circuits
constructed using threshold elements usually consists of fewer elements
and simpler interconnections compared to conventional gates. The
conventional gates logic is specified by Boolean algebra where as the logic
with threshold gates are specified by mathematical equations. All basic
logical gates and universal gates can be implemented using a Threshold
gate (XOR gate cannot be implemented using a single Threshold gate).
Also, some simpler Boolean logics can be implemented using a single
Threshold gate.
Threshold Elements:
A threshold element has n two-valued inputs x1, x2,..., xn and a single two
valued output y. Its internal parameters are a threshold T where as each
weight wi associated with a particular input variable xi. These values of T
and xi may be any real, finite, positive or negative numbers. The relation of
a threshold element is defined as follows:
where the sum and product operations are conventional arithmetic ones.
The sum is called the weighted sum of the element.

Threshold element Symbol:
Example:
Write the input output relation of the Threshold gate given below and
obtain the switching funtion for the same.
Ans: The inputs are the three x 1, x2 and x3 with multiplication factors -1, 2
and 1. The Threshold value T is ½. The output Y is calculated as for the
following table.
For the output Y, 1 is entered if the weighted sum is greater than ½.

Otherwise, 0 is entered.
Y = f ( x1, x2, x3) = ∑(1,2,6,7) = x1'.x3 + x2 ( after simplification).
A majority gate is a special type of Threshold element. A Three input
majority gate produces an output value 1 if a majority of its inputs (i.e. two
or three ) are one. It implements a majority function.
A minority gate produces an output value 1 if a majority of its inputs are at
0. It implements a minority function.
Capabilities and Limitations of Threshold Logic:

The Threshold elements are more powerful than conventional gates. Their
higher capability is due to the ability of a single threshold element to realize
a larger class of functions than a realizable one by any single conventional
gate. Any type of conventional gate can be realized using a Threshold gate
with different weights and Threshold value. For Example, a two input
NAND gate can be realized by a single Threshold element with weights -1,
-1 and Threshold value T = -3/2. Similarly, an OR gate can be realized with
unity weights and T = 1/2.
A Threshold gate realizing a NAND gate:
Because of wide range of weights and threshold values, a large class of

switching functions can be realized by a single Threshold element.
However, every switching function cannot be realized by a single
Threshold element.
Example: A function that cannot be realizable by a single Threshold
element:
Consider the function f(x1, x2, x3, x4) = x1.x2 + x3.x4 with weights w1, w2, w3
and w4 and Threshold value T. Then the output value of this element must
be 1 for each of the input combination x 1x2x3'x4' and x1'x2'x3x4 and the
output is to be 0 for x1'x2x3'x4 and x1x2'x3x4'. Thus
The above two requirements are conflicting and no Threshold element can
be realized for the above function.
Hence, if a switching function 'f' is given, it has to be checked first, whether
it is realizable with a single Threshold function and if it is realizable, then
appropriate weights and the Threshold value is to be calculated. This is
done by identifying 2n linear simultaneous inequalities from the truth table
and solving them. For the input combinations for which f=1, the weighted
sums have to exceed or equal to T and for f=0, the weighted sums have to
be less than T. If a solution ( not necessarily unique) to the above
inequalities exists, it provides values for the weights and Threshold value.
If, no solution exists then f is not a Threshold function.
Example: For the function f(x1, x2, x3) = ∑(0, 1, 3) . Check whether this
function is realizable and if so, find the weights.
Ans: The truth table for the above function is
As per the combinations 2 and 4, T must be negative and w1 and w2 are also
to be negative. From combinations 3 and 5, w 2 has to be greater than w1.
From combination 1, w3 is greater than or equal to T. Hence, the relations
are
where w3 may be positive. If the weights are restricted to integer values
with smallest magnitudes, then
w2 = -1, w1 = -2, T = -1/2, and w3 =1.
With the above weights and Threshold value, all the combinations are
satisfied and hence, f is a Threshold function.
A switching function that can be realized by a sing threshold element is

called a threshold function.
Limitations of Threshold logic: The limitation is its sensitivity to

variations in the circuit parameters. Therefore, the maximum number of
inputs and the Threshold value T are to be restricted and care is to be taken
to increase the difference between the values of the weighted sums.
Elementary Properties
Property 1: For a given Threshold function, if one of the input is
complemented, the same function can be realized by a single Threshold
element by negating the weight of that inverted input and subtracting the
value of the weight of that inverted input from the Threshold value T.
Consider a function f(x1, x2, .., xj, .. , xn) which is realized by V1 = {w1,
w2, .., wj, .., wn; T}and if xj input is complemented, then, f(x1, x2, .., xj', ..,
xn) can be realized by V2 = {w1, w2, …, -wj, .., wn; T-wj}.
The above property gives various other conclusions like the following:
Property 2: If a function is realizable by a single threshold element, then,

by an appropriate selection of complemented and uncompleted input
variables, it is possible to obtain a realization by an Threshold element
whose weights have the desired sign changes and changing the Threshold
value.
Property 3: If a function is realizable by a single threshold element, then it
is realizable by an element with only positive weights ( by having input
variables in bot complemented and uncompleted forms).
Property 4: If a function f(x1, x2, .., xn) is realizable by a single threshold
element whose weight Threshold vector V1 = { w1, w2, …, wn; T}, then its
complement f'(x1, x2, .., xn) is realized by a single Threshold element with
weight-Threshold vector V2 = { -w1, -w2, …, -wn; -T}.
Synthesis of Threshold Networks

The methods for the identification and realization of threshold functions
and the synthesis of networks of threshold elements ( called as threshold
networks) is done in the following ways:
 Unate function
A function f(x1, x2, .. xn) is said to be positive in a variable x, if there exists
a disjunctive or conjunctive expression for the function in which xi appears
only in uncompleted form. A function f(x1,x2,..xn) is said to be negative in xi
if there exists a disjunctive or conjunctive expression for f in which x i
appears only in complemented form. If f is either positive or negative in x i,
then it is said to be unate in xi. No variable appears in both its
complemented and uncompleted form.
Ex 1: The function f= x1x2' + x2x3' is positive in x1 and negative in x3 but is

not unate in x2.
If a function f(x1, x2, .., xn) is unate in each of its variables, then it is called
Unate function.
Ex 2: The function f = x1'x2 + x1.x2.x3' is unate because by simplification, f
= x1'.x2 + x2.x3' has no variable in both its complemented and uncompleted
form.
Ex 3: The function f = x1. x2' + x1'.x2 is clearly not unate.
If f (x1, x2, …, xn) is positive in xi, then it can be expressed as
If f (x1, x2, .., xn) is negative in xi, then it can be expressed as
Hence, the existence of two such functions, g1 and h1 ( g2 and h2), is a

necessary and sufficient condition for f to be positive (negative) in xi.
Geometric representation of Unate functions:

Unate functions can be represented in a better way as a cube. For an n
variable function, an n cube with 2n vertices is used, each vertices
representing a min term. A line is drawn between every pair of vertices that
differ in just one variable.If the function assumes 1 value, that vertices is
called true vertices and if the function assumes 0 value, that vertices is
called false vertices.
Ex: Function f = x'.y' + x.z, then the Geometric representation is as follows:
It is a three variable function. Hence, 3 dimensional cube is required. The
bolder lines connecting the two pairs of true vertices i.e. the pair (1,1,1) and
(1,0,1) and the pair (0,0,1) and (0,0,0) represent the cubes xz and x'y'
respectively.
A Three-cube representing f=x'y' + xz.
 Linear seperability
If an n cube representation for threshold function with vertices, with a
linear equation
w1x1 + w2x2 + … + wnxn = T correspond to an (n-1) dimensional hyper
plane that cuts the n-cube, then
f=0 when w1x1 + w2x2 + … + wnxn < T and
f=1 when w1x1 + w2x2 + … + wnxn >= T
and the hyper plane separates the true vertices from the false ones.
A switching function whose true vertices can be separated by a linear
equation from its false ones is called a linearly separable function and the
functional property that makes such a separation is called a linearly
separable function.
 Identification and Realization of Threshold Functions:

To find out whether a given function is a Threshold function and if it is, to
calculate the values of the weights and Threshold value:
a. Test for the Unateness of the given function. Get the minimal form of the
given switching function (both its complement and non-complement of any
variable does not exist).
Ex: Given function f = x1.x2.x3'.x4 + x2.x3'.x4'
simplifying it, f = x1.x2.x3' + x2.x3'.x4'
This is a unate function, as no variable exists in both complement and non-
complement form.
b. Convert the given function into another function which has all variables
in non-complement form only.
ϕ = x1.x2.x3 + x2.x3.x4
c. Find out all minimal True and maximal false vertices of ϕ.
There are two minimal vertices (1, 1, 1, 0) and (0, 1, 1, 1).
The false vertices are (1, 1, 0, 1), (1, 0, 1, 1) and (0, 1, 1, 0).
d. Check whether the function ϕ is linearly separable and if it so, find an
appropriate set of weights and threshold, which is necessary to determine
the coefficients of the separating hyper plane.
In the above example, p = 2 and q = 3, there are six inequalities and these
are:
From the above, the following are the constraints that must be observed.
Letting w1 = w4 = 1 and w2 = w3 = 2, then T must be smaller than 5 but
larger than 4. Selecting T=9/2, then the weight-threshold vector for ϕ V = {
1, 2, 2, 1; 9/2}.
e. convert this weight-threshold vector to one that corresponds to the
original function f.
Then the weight-threshold vector will be V = { 1,2,-2,-1; 9/2 -2-1} = { 1,2,-
2,-1; 3/2}
 Map based synthesis of two level Threshold networks:

If a given switching function cannot be realized with a single Threshold
function, then this non-threshold function will be decomposed into two or
more factors of which each is a Threshold function.
For a function of 3 or 4 variables, the identification problem is solved by
detecting certain which are admissible for Threshold functions, as given
below:
If the 1-cells of the given function follow any of the above patterns, then
that function can be realized using a Threshold element. Otherwise, the 1-
cells pattern is divided into two admissible patterns.
Ex: Let f (x1, x2, x3, x4) = sigma (2, 3, 6, 7, 10, 12, 14, 15)
The map for this function exhibiting two admissible patterns is
The threshold elements for realizing each of the admissible patterns are as
below, as per the realization of the Threshold function described above.
The Threshold logic realization for the function f is
The weight of g in the second element is determined by computing the

minimal weighted sum that can occur in the second element when g has the
value 1. Since f must have the value 1 whenever g does, this minimal
weighted sum must be larger than the threshold of the second element. In
this case, the minimal weighted sum is wg, and it occurs when x1 = x2 = 0
and x3 = x4 = 1. Clearly, wg must be larger than 5/2 and, therefore, the value
wg = 3 has been selected.
UNIT V
Part A: Sequential Machines Fundamentals
Introduction:
In combinational circuits, the output depends upon the present inputs only.
In sequential circuits, the outputs depend not only upon the present inputs,
but also upon the previous conditions.
In sequential circuits, memory elements (generally Flip-flops) are used as
storage elements, to keep the previous conditions. This stored condition is
given as feedback at the input to generate the next condition.
Block diagram of a Sequential circuit

Sequential circuits are of two types: Asynchronous sequential circuits
where no clock is used for state transfer and Synchronous Sequential
circuits where clock is used for operation.
State table:
In Sequential circuits, the effect of all previous inputs on the outputs is
represented by a state of the circuit. Thus, the output of the circuit at any
time depends upon its current state and input. These also determine the next
state of the circuit .The relationship that exists among the inputs, outputs,
present states and next states can be specified by either a State Table or the
State Diagram.
The state Table representation of a sequential circuit consists of three

sections labeled present state, next state and output. The present state
designates the state of Flip-flops before the occurrence of a clock pulse.
The next state shows the states of Flip-flops after the clock pulse, and the
output section lists the value of the output variables during the present state.
An example of a state table is as follows:
State Assignment:
State Assignment procedures are concerned with methods for assigning
binary values to states in such a way as to reduce the number of states of
the sequential circuit. This is helpful when a sequential circuit is viewed
from its external input-output terminals. Such a circuit may follow a
sequence of internal states, but the binary values of the individual states
may be of no consequence as long as the circuit produces the required
sequence of outputs for any given sequence of inputs.
Finite State Model – Basic Definitions

A sequential logic function has a “memory” feature and takes into account
past inputs in order to decide on the output. The Finite State Machine is an
abstract mathematical model of a sequential logic function. It has finite
inputs, outputs and number of states.
The sequence of operations are defined by a state table or state diagram.

The example of a state diagram for different types of flip-flops is shown
below:
SR Flip-flop:
T Flip-flop:
D Flip-flop:
JK Flip-flop:
Memory elements and their Excitation Functions;

In sequential circuits, memory elements are required to preserve the
previous state status, so that this can be used for the generation of the next
stats. Generally used memory elements are Flip-flops. SR, D, T and JK flip-
flops are studied here with symbol, circuit diagram using NAND gates,
Timing Diagram, Truth table, excitation table and characteristic equation
for each of these Flip-flops.
1. SR Flip-flop (Set-Reset Flip-flop)
Symbol
Timing Diagram
Circuit diagram: Truth table:
Operation: It has two inputs S and R.

When ever clock is there, if S = 1 ( set is given) and R = 0, the output goes
to 1.
If S=0, R = 1( Reset is given), the output goes to 0.
If S=0, R=0, ( either Set is not given, Reset is not given), the output will not
change and will be same as the earliesr stage.
If S=1, R=1, indicating to Set and Reset the Flip-flop, Output cannot be
predicted. This condition should not be given.
Excitation table
Qn Qn+1 S R Remarks
0 0 0 X Reset the output / No
change
0 1 1 0 Set the output
1 0 0 1 Reset the output
1 1 X 0 Set the output / No
change
Characteristic Equation:
Qn+1 = S + R’.Qn
2. D Flip-flop (Data Flip-flop / Delay Flip-flop):
Symbol
Timing diagram
Truth table:
Circuit diagram
Operation:
It has one input: D. During the clock active time, the output is strobed with
whatever input is given at D.
Excitation Table:
Qn Qn+1 D Remarks Characteristic Equation:

0 0 0 Data loaded as 0
3. JK Flip-flop:
Symbol Timing Diagram
Truth Table:
Operation:
JK Flip-flop is a combination of SR Flip-flop and T Flip-flop. It is an

improvement from SR flip-flop where 1-1 condition is used to Toggle the
output.
Excitation Table:
Characteristic Equation
Qn Qn+1 J (set) K(Reset) Remarks
0 0 0 X No change / Reset
0 1 1 X Toggle / set
1 0 X 1 Toggle / Reset
1 1 X 0 No change / set
4. T Flip-flop (Toggle Flip-flop):

Timing Diagram
Symbol
Circuit diagram:
Truth Table:
Operation:
It has one input T. When ever clock is given, the output toggles if T=1.
Otherwise, there is no change in the output.
Excitable Table:
Qn Qn+1 T Remarks
0 0 0 No change in the output
0 1 1 Output toggles Characteristic Equation:
1 0 1 Output toggles
1 1 0 No change in the output
Clock Timing
The Setup time: the setup time is the amount of time that an input signal
(to the device) must be stable (unchanging) before the clock ticks in order
to guarantee minimum pulse width and thus avoid possible metastability.
Hold time: The hold time is the amount of time that an input signal must be
stable (unchanging) after the clock tick in order to guarantee minimum
pulse width and thus avoid possible metastability.
Master slave Flip-flop:
Although JK Flip-flop is an improvement on the clocked SR Flip-flop, it
still suffers from timing problem classed “Race”. In 1,1 input for J and K, if
the output Q changes state before the timing pulse of the clock input has
time to go “OFF”, then output goes on ON and OFF. This is called Racing
problem. To avoid this, the timing period T must be kept as short as
possible, which is difficult. Master Slave Flip-flop solves this problem.
In Master-slave Flip-flop, two JK Flip-flops are used. The first Flip-flop
transfers data during the +ve edge of the clock cycle which is transferred to
the final output by the 2nd Flip-flop during the -ve edge of the clock cycle.
As the final output changes at the end of the clock cycle, racing is avoided.
Circuit Diagram:
Block Diagram:
Timing Diagram:
Synthesis of Synchronous Sequential Circuits:

For Synchronous Sequential circuits, the following procedure is used for
Design.
Draw the state diagram
Draw the State table (excitation table) for each output.
Draw the K -Map for each output
Draw the circuit.
A. Sequence detector:
Design of the 11011 Sequence Detector
A sequence detector accepts as input a string of bits: either 0 or 1.
Its output goes to 1 when a target sequence has been detected.
There are two basic types: overlap and non-overlap.
In an sequence detector that allows overlap, the final bits of one sequence
can be the start of another sequence.
11011 detector with overlap X 11011011011
Z 00001001001
11011 detector with no overlap Z 00001000001
Problem: Design a 11011 sequence detector using JK flip-flops. Allow

overlap.
Step 1 – Derive the State Diagram and State Table for the Problem
Step 1a – Determine the Number of States
We are designing a sequence detector for a 5-bit sequence, so we need 5
states. We label these states A, B, C, D, and E. State A is the initial state.
Step 1b – Characterize Each State by What has been Input and What is
Expected
State Has Awaiting

A -- 11011
B 1 1011
C 11 011
D 110 11
E 1101 1
Step 1c – Do the Transitions for the Expected Sequence

Here is a partial drawing of the state diagram. It has only the sequence
expected. Note that the diagram returns to state C after a successful
detection; the final 11 are used again.
Note the labeling of the transitions: X / Z. Thus the expected transition

from A to B has an input of 1 and an output of 0.
The transition from E to C has an output of 1 denoting that the desired
sequence has been detected.
The sequence is 1 1 0 1 1.
Step 1d – Insert the Inputs That Break the Sequence The sequence is 1 1 0
1 1.
Each state has two lines out of it – one line for a 1 and another line for a 0.
The notes below explain how to handle the bits that break the sequence.
State A in the 11011 Sequence Detector
State A is the initial state. It is waiting on a 1.

If it gets a 0, the machine remains in state A and continues to remain there
while 0’s are input.
If it gets a 1, the machine moves to state B, but with output 0.
State B in the 11011 Sequence Detector

If state B gets a 0, the last two bits input were “10”.
This does not begin the sequence, so the machine goes back to state A and
waits on the next 1.
If state B gets a 1, the last two bits input were “11”. Go to state C.
State C in the 11011 Sequence Detector

If state C gets a 1, the last three bits input were “111”.
It can use the last two to be the first two 1’s of the sequence 11011, so the
machine stays in state C awaiting a 0.
If state C gets a 0, the last three bits input were “110”. Move to state D.
State D in the 11011 Sequence Detector

If state D gets a 0, the last four bits input were “1100”. These 4 bits are not
part of the sequence, so we start over.
If state D gets a 1, the last four bits input were “1101”. Go to state E.
State E in the 11011 Sequence Detector

If state E gets a 0, the last five bits input were “11010”. These five bits are
not part of the sequence, so start over.
If state E gets a 1, the last five bits input were “11011”, the target sequence.
If overlap is allowed, go to state C and reuse the last two “11”.
If overlap is not allowed, go to state A, and start over.
Step 1e – Generate the State Table with Output
Step 2 – Determine the Number of Flip-Flops Required

We have 5 states, so N = 5. We need three flip-flops.
Step 3 – Assign a unique 3-bit binary number (state Assignment) to each

state. Straigh forward assignment:
A = 000
B = 001
C = 010
D = 011
E = 100
Non-sequential assignment:
States A and D are given even numbers. States B, C, and E are given odd
numbers. The assignment is as follows.
A = 000
B = 001
C = 011 States 010, 110, and 111 are not used.
D = 100
E = 101
Step 4 – Generate the Transition Table With Output
Step 4a – Generate the Output Table and Equation

The output table is generated by copying from the table just completed.
The output equation can be obtained from inspection. As is the case with
most sequence detectors, the output Z is 1 for only one combination of
present state and input. Thus we get Z = X . Y2 .Y1 ’ .Y0. This can be
simplified by noting that the state 111 does not occur, so the answer is Z =
X . Y2 .Y0.
Step 5 – Separate the Transition Table into 3 Tables, One for Each Flip-Flop
We shall generate a present state / next state table for each of the three
flipflops; labeled Y2, Y1, and Y0. It is important to note that each of the
tables must include the complete present state, labeled by the three bit
vector Y2Y1Y0.
D2 = X’.Y1 + X.Y2.Y0 ’
D1 = X .Y0
D0 = X
Step 6- Decide on the type of flip-flops to be used. The problem stipulates

JK flip-flops, so we use them.
Steps 7 and 8 are skipped in this lecture.

Step 9 – Summarize the Equations
Z = X.Y2.Y0
J2 = X’.Y1 and K2 = X’ + Y0
J1 = X.Y0 and K1 = X’
J0 = X and K0 = X’ .
Step 10 – Draw the Circuit using JK Flip-flops
Here is the same design implemented with D flip-flops.
A. Serial Binary adder: Please Refer Kohavi Section : 9.1

B. Binary Counter:
Design a 3 bit up counter using T Flip-flops:
3 bit requires 8 states. There are no inputs from the external circuits. State
changes on every clock edge.
State Diagram: Next state Maps and
simplification:
For T Flip-flops, the excitation

State Table: table is
T = Q XOR Q+
In the present requirement,

QA toggles when B=C=1
QB toggles when C=1
QC togges on every clock edge.
The circuit diagram is
C. Parity Bit Generator:
A Sequential parity checker : an 8th bit is added to each group of 7 bits such
that the total number of 1 bits are 1 for odd parity. If any odd number of bits
in the 8 bit block changes value, then the presence of this error can be
detected. A parity checker for serial data is designed as follows:
Block diagram:
State Diagram: State table:

S0: even number of 1s received
so far
S1: odd number of 1s received so
far.
Since only two states are there, one flip-flop is sufficient.

The excitation table for T flip- from this table, T is 1 whenever X
flop is as below: is 1.
The circuit is as follows:
Unit V
Part B: Counters and Shift Registers
Ripple Counter, Shift Registers and their types, Ring Counters, Twisted
Ring Counters.
Introduction:
Counter: Counters are circuits that cycle through a specified number of
states.
Two types of counters:
(A) synchronous (parallel) counters
(B) asynchronous (ripple) counters
Ripple counters (Asynchronous counters) allow some flip-flop outputs to
be used as a source of clock for other flip-flops.
Synchronous counters apply the same clock to all flip-flops.
Asynchronous counters: the flip-flops do not change states at exactly the
same time as they do not have a common clock pulse. These are also
known as ripple counters, as the input clock pulse “ripples” through the
counter – cumulative delay is a drawback.
n
n flip-flops gives a MOD (modulus) 2 counter. (Note: A MOD-x counter
cycles through x states.)
Output of the last flip-flop (MSB) divides the input clock frequency by the
MOD number of the counter, hence a counter is also a frequency divider.
Example:
4-bit Ripple Binary Counter (Negative Triggering):
Block Diagram using JK Flip-flops:
Timing Diagram:
Operation:
The JK Flip-Flop is configured as T Flip-Flop. In fact, any type of Flip-
Flop can be used in Counters, if they are configured as T Flip-Flop. As both
the J and K are shorted together and given to logic 1, the Flip-Flop output
toggles whenever the input clock changes from 1 to 0 (Negative-edge
triggering). Based on the given clock CLK to FF0, the Q0, and the output
of FF0 changes when ever the clock goes from 1 to 0. The Q0 (output of
FF0) is given as clock to FF1. Hence, Q1, the output of FF1 changes when
even Q0 changes from 1 to 0 (after every two clock pulses) and so on. The
timing diagram is shown above.
Shift Registers and their types:

This sequential device loads the data present on its inputs and then moves
or “shifts” it to its output once every clock cycle, hence the name Shift
Register.
A shift register basically consists of several single bit “D-Type Data
Latches”, one for each data bit, either a logic “0” or a “1”, connected
together in a serial type daisy-chain arrangement so that the output from
one data latch becomes the input of the next latch and so on.
Data bits may be fed in or out of a shift register serially, that is one after the
other from either the left or the right direction, or all together at the same
time in a parallel configuration.
The number of individual data latches required to make up a single Shift
Register device is usually determined by the number of bits to be stored
with the most common being 8-bits (one byte) wide constructed from eight
individual data latches.
Shift Registers are used for data storage or for the movement of data and
are therefore commonly used inside calculators or computers to store data
such as two binary numbers before they are added together, or to convert
the data from either a serial to parallel or parallel to serial format. The
individual data latches that make up a single shift register are all driven by
a common clock (Clk) signal making them synchronous devices.
Generally, shift registers operate in one of four different modes with the
basic movement of data through a shift register being:
A. Serial-in to Parallel-out (SIPO) - the register is loaded with serial
data, one bit at a time, with the stored data being available at the
output in parallel form.
B. Serial-in to Serial-out (SISO) - the data is shifted serially “IN”
and “OUT” of the register, one bit at a time in either a left or right
direction under clock control.
C. Parallel-in to Serial-out (PISO) - the parallel data is loaded into
the register simultaneously and is shifted out of the register serially
one bit at a time under clock control.
D. Parallel-in to Parallel-out (PIPO) - the parallel data is loaded
simultaneously into the register, and transferred together to their
respective outputs by the same clock pulse.
The effect of data movement from left to right through a shift register can
be presented graphically as:
Also, the directional movement of the data through a shift register can be
either to the left, (left shifting) to the right, (right shifting) left-in but right-
out, (rotation) or both left and right shifting within the same register
thereby making it bidirectional.
A: Serial-in to Parallel-out (SIPO) Shift Register
4-bit Serial-in to Parallel-out Shift Register:
The operation is as follows. Lets assume that all the flip-flops (FFA to FFD)
have just been RESET (CLEAR input) and that all the outputs QA to QD
are at logic level “0” ie, no parallel data output.
If a logic “1” is connected to the DATA input pin of FFA then on the first
clock pulse the output of FFA and therefore the resulting QA will be set
HIGH to logic “1” with all the other outputs still remaining LOW at logic
“0”. Assume now that the DATA input pin of FFA has returned LOW again
to logic “0” giving us one data pulse or 0-1-0.
The second clock pulse will change the output of FFA to logic “0” and the
output of FFB and QB HIGH to logic “1” as its input D has the logic “1”
level on it from QA. The logic “1” has now moved or been “shifted” one
place along the register to the right as it is now at QA.
When the third clock pulse arrives this logic “1” value moves to the output
of FFC (QC) and so on until the arrival of the fifth clock pulse which sets
all the outputs QA to QD back again to logic level “0” because the input to
FFA has remained constant at logic level “0”.
The effect of each clock pulse is to shift the data contents of each stage one
place to the right, and this is shown in the following table until the
complete data value of 0-0-0-1is stored in the register. This data value can
now be read directly from the outputs of QA to QD.
Then the data has been converted from a serial data input signal to a
parallel data output. The truth table and following waveforms show the
propagation of the logic “1” through the register from left to right as
follows.
Basic Data Movement Through A Shift Register
Clock Pulse No. QA QB QC QD

0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 0 0 1 0
4 0 0 0 1
5 0 0 0 0
Note that after the fourth clock pulse has ended the 4-bits of data (0-0-0-1)
are stored in the register and will remain there provided clocking of the
register has stopped. In practice the input data to the register may consist of
various combinations of logic “1” and “0”. Commonly available SIPO IC’s
include the standard 8-bit 74LS164 or the 74LS594.
B. Serial-in to Serial-out (SISO) Shift Register

This shift register is very similar to the SIPO above, except were before the
data was read directly in a parallel form from the outputs QA to QD, this
time the data is allowed to flow straight through the register and out of the
other end. Since there is only one output, the DATA leaves the shift register
one bit at a time in a serial pattern, hence the name Serial-in to Serial-Out
Shift Register or SISO.
The SISO shift register is one of the simplest of the four configurations as it
has only three connections, the serial input (SI) which determines what
enters the left hand flip-flop, the serial output (SO) which is taken from the
output of the right hand flip-flop and the sequencing clock signal (Clk). The
logic circuit diagram below shows a generalized serial-in serial-out shift
register.
4-bit Serial-in to Serial-out Shift Register:
This type of Shift Register acts as a temporary storage device or it can act
as a time delay device for the data, with the amount of time delay being
controlled by the number of stages in the register, 4, 8, 16 etc or by varying
the application of the clock pulses. Commonly available IC’s include the
74HC595 8-bit Serial-in to Serial-out Shift Register all with 3-state outputs.
C. Parallel-in to Serial-out (PISO) Shift Register:

The Parallel-in to Serial-out shift register acts in the opposite way to the
serial-in to parallel-out one above. The data is loaded into the register in a
parallel format in which all the data bits enter their inputs simultaneously,
to the parallel input pins PA to PD of the register. The data is then read out
sequentially in the normal shift-right mode from the register at Q
representing the data present at PA to PD.
This data is outputted one bit at a time on each clock cycle in a serial
format. It is important to note that with this type of data register a clock
pulse is not required to parallel load the register as it is already present, but
four clock pulses are required to unload the data.
4-bit Parallel-in to Serial-out Shift Register:

As this type of shift register converts parallel data, such as an 8-bit data
word into serial format, it can be used to multiplex many different input
lines into a single serial DATA stream which can be sent directly to a
computer or transmitted over a communications line. Commonly available
IC’s include the 74HC166 8-bit Parallel-in/Serial-out Shift Registers.
D. Parallel-in to Parallel-out (PIPO) Shift Register

The final mode of operation is the Parallel-in to Parallel-out Shift Register.
This type of shift register also acts as a temporary storage device or as a
time delay device similar to the SISO configuration above. The data is
presented in a parallel format to the parallel input pins PA to PD and then
transferred together directly to their respective output pins QA to QA by the
same clock pulse. Then one clock pulse loads and unloads the register. This
arrangement for parallel loading and unloading is shown below.
4-bit Parallel-in to Parallel-out Shift Register

The PIPO shift register is the simplest of the four configurations as it has
only three connections, the parallel input (PI) which determines what enters
the flip-flop, the parallel output (PO) and the sequencing clock signal (Clk).
Similar to the Serial-in to Serial-out shift register, this type of register also
acts as a temporary storage device or as a time delay device, with the
amount of time delay being varied by the frequency of the clock pulses.
Also, in this type of register there are no interconnections between the
individual flip-flops since no serial shifting of the data is required.
Universal Shift Register
Today, there are many high speed bi-directional “universal” type Shift
Registers available such as the TTL 74LS194, 74LS195 or the CMOS 4035
which are available as 4-bit multi-function devices that can be used in
either serial-to-serial, left shifting, right shifting, serial-to-parallel, parallel-
to-serial, or as a parallel-to-parallel multifunction data register, hence the
name “Universal”.
These universal shift registers can perform any combination of parallel and
serial input to output operations but require additional inputs to specify
desired function and to pre-load and reset the device. A commonly used
universal shift register is the TTL 74LS194 as shown below.
Shift Register Summary: to summarize about Shift Registers
(A) A simple Shift Register can be made using only D-type flip-
Flops, one flip-Flop for each data bit. Even if other Flip-Flops are to
be used, then they are to be configured as D Flip-Flops.
(B) The output from each flip-Flop is connected to the D input of the
flip-flop at its right.
(C) Shift registers hold the data in their memory which is moved or
“shifted” to their required positions on each clock pulse.
(D) Each clock pulse shifts the contents of the register one bit
position to either the left or the right.
(E) The data bits can be loaded one bit at a time in a series input (SI)
configuration or be loaded simultaneously in a parallel configuration
(PI).
(F) Data may be removed from the register one bit at a time for a
series output (SO) or removed all at the same time from a parallel
output (PO).
(G) One application of shift registers is in the conversion of data
between serial and parallel, or parallel to serial.
(H) Shift registers are identified individually as SIPO, SISO, PISO,
PIPO, or as a Universal Shift Register with all the functions combined
within a single device.
Ring Counter:
Ring counter is a type of counter composed of a type of circular shift
register. The output of the last shift register is fed to the input of the first
register.
There are two types of ring counters:
2) A straight ring counter connects the output of the last shift register to
the first shift register input and circulates a single one (or zero) bit
around the ring. For example, in a 4-register ring counter, with initial
register values of 1000, the repeating pattern is: 1000, 0100, 0010,
0001, 1000... . Note that one of the registers must be pre-loaded with a
1 (or 0) in order to operate properly.
Circuit Diagram:
Timing Diagram:
A twisted ring counter, also called switch-tail ring counter, walking ring counter, Johnson
counter or Möbius counter, connects the complement of the output of the last shift register to the
input of the first register and circulates a stream of ones followed by zeros around the ring. For
example, in a 4-register counter, with initial register values of 0000, the repeating pattern is: 0000,
1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000...
Johnson counters are often favoured, not just because they offer twice as many count states
from the same number of shift registers, but because they are able to self-initialize from the all-
zeros state, without requiring the first count bit to be injected externally at start-up. The
Johnson counter generates a Gray code, a code in which adjacent states differ by only one
bit.Four-bit ring counter sequences
Straight Ring/ Overbeck Counter Twisted Ring/ Johnson Counter

State Q0 Q1 Q2 Q3 State Q0 Q1 Q2 Q3
0 1 0 0 0 0 0 0 0 0
1 0 1 0 0 1 1 0 0 0
2 0 0 1 0 2 1 1 0 0
3 0 0 0 1 3 1 1 1 0
0 1 0 0 0 4 1 1 1 1
1 0 1 0 0 5 0 1 1 1
2 0 0 1 0 6 0 0 1 1
3 0 0 0 1 7 0 0 0 1
0 1 0 0 0 0 0 0 0 0
Page 158 of 191

Block diagram of Twisted Ring Counter:
Note the inversion of the Q signal from the last shift register before feeding
back to the first D input, making this a Johnson counter.
Timing Diagram:
Page 159 of 191

15. Additional topics
1.
16. University previous Question papers of Previous Years
Code No.16EC2103 AR16
GEETHANJALI COLLEGE OF ENGINEERING AND TECHNOLOGY(Autonomous)

B.Tech II year I semester Examinations
Switching Theory and Logic Design
(common to ECE,EEE,CSE)
Time: 3hrs Max.marks:70
Note: This question paper consists of two parts A and B

Part A is compulsory which carries 20 marks. Answer all questions in Part A.
Part B consists of 5 units. Answer any one full question from each unit.
Each question carries 10 marks and may have a, b, c, d sub questions
PART –A: Each carries 2m (10x2=20 marks)
1. a) Determine the possible base of the numbers in the operation 302/20=12.1

b) Reduce the expression A’B(D’+C’D)+B(A+A’CD) to one literal.
c) What are static hazards?
d) Construct full adder using decoder.
e) What is the difference between characteristic table and excitation table?
f) Show the characteristic equation for the true output of JK flip-flop is Q(t+1)=JQ’+K’Q
g) How many bit counter is needed to provide a clock with cycle time of 50ns if the clock
generator produces pulses at a frequency of 80MHz?
h) Compare Synchronous and Asynchronous Counters.
i) What are compatible states?
j) What is a twisted Ring Counter?
PART B: (50marks)
2 a) State De-Morgan laws

b) Perform the following arithmetic operations in binary using signed 2’s complement
representation for negative numbers (i) (+62)+(-23) (ii) (-62)-(-23).
c) Encode the information character 01101110101 according to the 15 bit Hamming code
[2+4+4]
OR
3 a) Obtain the 1’s and 2’s complement of the binary numbers 10000000 and 00000001.
b) Show that a positive logic NAND gate is a negative logic NOR gate and Vice versa.
c) Obtain the truth-table of the function (xy+z)(y+xz) and express the function in sum of min
terms and product of max terms.
[2+4+4]
4 a) For the function F(w,x,y,z)=∑(1,2,3,5,13)+ ∑ᵠ(6,7,8,9,11,15), find the minimal sum of products
and product of sums expression
b) Implement the function F(A,B,C,D) = ∑(0,1,3,4,6,8,15) using 4x1 MUX
[5+5]
OR
5 a) Design a 3-input majority circuit using multiplexer whose output is equal to 1 if the input
variables have more 1’s than 0’s. The output is 0 otherwise.
b) Find the min terms of the function wxy+x’z’+w’xz by plotting the function in a map
[5+5]
6 a) Compare Sequential and Combinational circuits.

b) Design a JK flip-flop using D flip-flop. 2-to-1 line MUX and Invertor. [4+6]
OR
7 a) What is the difference between a Latch and Flip-Flop?

b) Explain the positive Edge triggered D Flip-Flop with asynchronous reset.
[5+5]
8) a) A sequential circuit with 2 D flip-flops A & B, 2 inputs X&Y and one output Z is specified by
A(t+1) =x’y+xA, B(t+1)=x’B+xA, z=B. Draw the logic diagram and list the state table. Draw
the state diagram.
b) What is a Universal Shift Register?
[8+2]
OR
9) a) Design a Counter using T flip-flops with a repeated sequence 0, 1,3,7,6,4.

b) Show that a Johnson counter with n flip-flops produces a sequence of 2n states.
10) a) Draw a multilevel NAND circuit for expression F=(AB’+CD’)E+BC(A+B)

b) Reduce the given expression to a minimum number of literals
(i) (BC’+A’D)’ (AB’+CD’)’
(ii) AB’ + CD(A+B)’ [5+5]
OR
11 a) Draw the diagram of mod-10 Asynchronous counter using T-flip flops and explain its working.
b) Draw the logic diagramof a 4-bit ring counter using JK flip flops and explain its working
[5+5]
17. Question Bank
UNIT-I
UNIT- I Part A
1. Convert the following numbers in the way specified below:
(a) (1431)8 to base 10
(b) 11001010.0101 to base 10
(c) 11001101.0101 to base 8 and base 4
(d) (1984)10 to base 8
(e) (1776)10 to base 6
(f) (53.1575)10 to base 2
(g) (3.1415 · · ·)10 to base 8 and base 2
2. (a) Given that (16)10 = (100)b, determine the value of b.
(b) Given that (292)10 = (1204)b, determine the value of b.
(c) What is the radix if solutions to the quadratic equation x2 – 11x + 22 = 0 is x = 3 and x = 6.
(d) What is the radix if solutions to the quadratic equation x2 – 10x + 31 = 0 is x = 5 and x = 8.
(e) A person on Saturn possessing 18 fingers has a property worth (1,00,000)18. He has 3
daughters and two sons. He wants to distribute half of the money equally to his sons and
remaining half to his daughters equally. How much his each son and each daughter will get in
Indian Currency.
(f) An Indian started on an expedition to SATURN with Rs. 100000. The expenditure on
SATURN will be in the ratio of 1:2:7 for food, clothing and travelling. How much he will be
spending on each item in the currency of SATURN?
(g)A group of students who went on expedition to planet MARS have found the ruins of a
civilization. They saw a quadratic equation 5X2-50X+125=0, whose roots were X=5,8 when the
equation was solved by Martians. This they found strange mathematics as they found the roots to
be X=5,5 since they have ten fingers. How many fingers did the Martians have?
3. Given binary numbers a = 1010.1, b = 101.01, and c = 1001.1, Perform the following binary
operations:
4. Each of the following arithmetic operations is correct in at least one number system. Determine
the possible bases of the numbers in each operation.
(a) 1234 + 5432 = 6666
(b) 41/3 = 13
(c) 33/3 = 11
(d) 23 + 44 + 14 + 32 = 223
(e) 302/20 = 12.1
(f) √41 = 5
5. Encode each of the 10 decimal digits 0,1,..9 by means of the following weighted codes:
6311
7 3 2 -1
7 3 1 -2
5 4 -2 -1
8 7 -4 -2
Determine which of the above codes is self-complementing.
6. Generate even and odd parity for the decimal digits 0 thru 9.
7. Hamming code – generation and correction:
8. Addition of two numbers which are in BCD code.
Unit I – Part B:
1. Find the values of the two-valued variable A,B,C and D by solving the set of simultaneous
equations.
A’+AB=0
AB=AC
AB+AC’+CD=C’D
2. Prove that if w’x+yz’=0, then
wx + y’(w’+z’) = wx + xz + x’z’+ w’y’z
3. Define the connective * for the two valued variables A,B, and C as follows:
A*B = AB + A’B’
Let C = A*B, Determine which of the following is valid.
a. A = B*C
b. B = A * C
c. A*B*C = 1
4. The dual fd of a function f(x1,x2,…, xn) is obtained by interchanging the operations of logical
addition and multiplication and by interchanging the constants 0 and 1 within any expression for
that function
a. Show that fd = f’(x’1,x’2,..,x’n).
b. Find a three variable function that is its own dual. Such a function is called self-dual.
c. Prove that for any function f and any two valued variable A, which may or may not be a
variable in f, the function
g = Af + A’fd
is self dual.
5. A. Show that f(A,B,C) = A’BC + AB’ + B’C’ is a universal operation.
B. Assuming that a constant value 1 is available, show that f(A,B) = A’B (together with the
constant) is a universal operation.
6. Prove that if a function f(x1,x2,…, xn) is represented in a canonical sum-of-products form then
all OR operations may be replaced by EXCLUSIVE OR operations.
7. A safe has five locks, v,w,x,y and z, all of which must be unlocked for the safe to open. The keys
to the locks are distributed among five executives in the following manner
Mr. A has keys for locks v and x
Mr. B has keys for locks v and y
Mr. C has keys for locks w and y
Mr. D has keys for locks x and z
Mr. E has keys for locks v and z
a. Determine the minimum number of executives required to open the safe.
b. Find all the combinations of executives that can open the safe. Write an expression
f(A,B,C,D,E) which specifies when the safe can be opened as a function of what executives
are present.
c. Who is the “essential executive” with out whom the safe cannot be opened.
8. You are presented with a set of requirements under which an insurance policy will be issued. The
applicant must be:
 A married female 25 years old or over, or
 A female under 25, or
 A married male under 25 who has been involved in a car accident, or
 A married male 25 years or over who has not been involved in a car accident.
The variables w,x,y, and z assume the truth value 1 in the following cases:
w=1 if applicant has been involved in a car accident
x =1 if the applicant is married
y = 1 if applicant is a male
z = 1 if applicant is under 25
a. You are asked to find an algebraic expression which assumes the value 1 whenever the policy
should be issued.
b. Simplify algebraically he above expression and suggest a simpler set of requirements.
9. Five soldiers A, B, C, D and E volunteer to perform an important military task if their following
conditions are satisfied.
a. Either A or B or both must go.
b. Either C or E but not both, must go
c. Either both A an C go or neither goes
d. If D goes, then E must also go
e. If B goes, then A and D must also go.
Define the variables A, B, C, D, E so that an unprimed variables will mean that the corresponding
soldier has been selected to go. Determine the expression which specifies the combinations of the
volunteers who can get the assignment.
UNIT - II
1. Each of the following functions actually represents a set of four functions, corresponding to the various
assignments of the don’t care terms.
f1(w,x,y,z) = Ʃ (1,3,4,5,9,10,11) + Ʃ ǿ(6,8)
f2(w,x,y,z) = Ʃ (0,2,4,7,8,15) + Ʃ ǿ(9,12)
a. Find f3 = f1 . f2 How many functions does f3 represent?
b. Find f4 = f1 + f2. How many functions does f4 represent?
c. Simplify the above functions, their product, and their sum.
2. Let f = Ʃ (5,6,13) and f1 = Ʃ (0,1,2,3,5,6,8,9,10,11,13). Find f2 such that f =
f1.f2’ Is f2 unique? If not indicate all possibilities.
3. Given the network of the below figure, determine the functions f2 and f3 if f1
= xz = xz and the overall transmission function is to be f(w,x,y,z) = Ʃ
(0,4,9,10,11,12)
4. Find the simplest function g(A,B,C,D) that will make the function f = ABC +
(AC+B)D + g(A,B,C,D) self dual.
5.Use the map method to simplify the following function.
F2(v,w,x,y,z) = Ʃ (0,1,2,4,5,9,11,13,15,16,18,22,23,26,29,30,31)
6.The five variable map can be constructed of two disjoint four variable maps
which correspond to the fifth variable and its complement. Simplify the function
T(v,w,x,y,z) = Ʃ (1,2,6,7,9,13,14,15,17,22,23,25,29,30,31)
Whose maps are given in below figure.
7.Use the tabulation procedure to generate the set of prime implicants and to
obtain all minimal expressions for the following functions.
a. f2(v,w,x,y,z) = Ʃ (0,1,3,8,9,13,14,15,16,17,19,24,25,27,31)
b. f4(v,w,x,y,z) = Ʃ (1,5,6,7,9,13,14,15,17,18,19,21,22,23,25,29,30)
c. f5(w,x,y,z) = Ʃ (0,1,5,7,8,10,14,15)
8.Apply the branching method to find a minimal expression for
F(v,w,x,y,z) = Ʃ (0,4,12,16,19,24,27,28,29,31)
9. Prove that if x and y are switching variables, then
a) x+y = x y xy
b) x = x 1
10. Derive a procedure to transform an expression the EXCLUSIVE OR operation
to an equivalent switching expression containing only AND, OR and NOT
operation. Apply your procedure to the expression
f=x y z
11. The table shown below is a Prime implicant table for f(a,b,c,d), in which
someof the row and column headings are unknown. It is known, however, that
the table has a row for each prime implicant of f and has column for each
minterm for which f has a value 1.
a) Find with the aid of a map all the minterms and prime implicants that
correspond, respectively, to the columns and rows with unknown headings.
b) Is your solution to a unique?
c) Find the minimal expression for f.
12. Given a combinational network with four inputs A,B,C, and D, three
intermediate outputs Q,P and R and two outputs T1 and T2 as shown in the
below figure.
a) Assuming that G1 and G2 are both AND gates, show the map for the
smallest function Pmin (i.e.with minimum minterms) which makes it
possible to produce T1 and T2.
b) Shown maps for q and R which correspond to the aboe Pmin Indicate
eplcitily the don’t care positions.
c) Assuming that G1 and g2 are both OR gates, find the largest Pmax and
show the corresponding maps for Q and R.
d) Can both T1 and T2 be produced if G1 is an AND gate and G2 is an OR
gate? Or when G1 is an OR gate and G2 an AND gate?
13.Given the gate T whose logical properties are defined by the amp as shown
below.
a) Prove that, if the logical value 1 is given, then any switching funcaiton can
be realized by means of T gates; that is T gates plus logical value 1 are
functionally complete.
b) Realize by means of two T gates the function
f(w,x,y,z) = Ʃ (0,1,2,4,7,8,9,10,12,15)
Hint : Realize 0s of f.
UNIT- III
UNIT- III Part A:
1. You are supplied with just one NOT gate and an unlimited amount of AND and OR gates and
are required to design a circuit that realizes the expression
T (w, x, y, z) = w’x + x’y + xz’
Only unprimed variables are available as inputs.
Hint: You may find the map of T helpful.
2. A certain four-input gate, called a LEMON gate, realizes the switching Function
LEMON(A,B,C,D) = BC(A + D). Assume that the input variables are available in both primed
and unprimed form.
(a) Show a realization of the function f (w, x, y, z) = Ʃ(0, 1, 6, 9, 10, 11, 14, 15) with only
three LEMON gates and one OR gate.
(b)Can all switching functions be realized with LEMON and OR logic?
Hint: Draw the map for LEMON and utilize possible “patches” (coverings of the
minterms of f with the LEMON function) on the map of f.
3. A three-input gate, BOMB, whose characteristics are shown in Fig. P5.7, has been mass
produced by an unfortunate company. Experimental evidence shows that input combinations
101 and 010 cause the gate to physically explode. Your task is to determine whether the gate is
completely useless or can be externally modified such that it may be efficiently used to
implement any switching function without causing explosions.
4. A logic module A, shown in Fig. P5.8, operates as follows: output yi = 1if i inputs out of x0,
x1, x2 are equal to 1. Design unit B in such a way that the overall logic function of unit C will
be to produce an output zi = 1 iff i inputs out of x0, x1, x2,x3 are equal to 1.
5. Given a logic module A that compares the magnitudes of two 3-bit numbers, X3 = x1x2x3 and
Y3 = y1y2y3, where x3 and y3 are the least significant bits. Module A has two outputs G3 and
S3, such that: G3 = 1 if X3 > Y3; S3 = 1 if X3 < Y3; and G3 = S3 = 0 if X3 = Y3.
(a) Design a logic unit B such that together with module A it will serve as a comparator for two
four-bit numbers, X4 = x1x2x3x4 and Y4 = y1y2y3y4, as shown in Fig. P5.9.
(a) Find expressions forG4 and S4 in terms of the inputs to unit B and showa realization
of these expressions using only NAND gates.
(b) Show a realization of module A by means of only units of type B. Assume that the
constants 0 and 1 are available.
6. Analyze the two-output circuit shown in Figure below. Indicate the logicexpression associated
with every gate output.
7. A communication system is designed to transmit just two code words, A = 0010 and B = 1101.
However, owing to noise in the system, the received word may have as many as two errors.
Design a combinational circuit that receives the words and that can correct one error and
detect the existence of two errors. Specifically, design the circuit in Fig. P5.19 in such a way
that output A will be equal to 1 if the received word is A, output B will be equal to 1 if the
received word is B, and output C will be equal to 1 if the word received has two errors and
thus cannot be corrected.
8. Design and implement a three bit parallel parity-bit generator.

9. Design a converter which sends a four bit input on line x which receives a sequence of binary
digits that must be distributed into four different output terminals with external control.
( serial-to-parallel converter )
UNIT- III Part B:

1. Tabulate the PLA programming table for the four Boolean functions listed below. Minimize
the number of product terms.
A(x ,y, z)= Ʃ(1,2,4,6)
B(x, y, z) = Ʃ(0,1,6,7)
C(x, y, z) = Ʃ(2,4,5,6,7)
D(x, y, z) = Ʃ(1,2,3,5,7)
2. Draw a PLA circuit to implement the functions

F1= A’B+Ac’+A’B’C’
F2= (AC+AB+BC)’
3. Derive the PLA programming table for the combinational circuit that squares a 4 bit
number Minimize the number of product terms.
4. A half adder is a device capable of performing the addition of two bits. It has two binary
inputs, A and B, and two outputs, S and C0. (Note that there is no carry into the half adder.)
(a) Write truth tables that define the half adder and derive logic expressions for S and C0.
(b) Assuming that only uncomplemented inputs are available, show an implementation of the
half adder that requires only three two-input AND or OR gates and one NOT gate.
(c) Under the above assumption, design the half adder using no more than five NAND
gates or NOR gates, but not both together.
UNIT- IV
UNIT- IV Part -A
1.Find all cut and tie sets for the circuit shown in the below figure. What function T is realized by
this circuit?
Prove that any contact realization of T must contain at least one contact d. Generalize your
argument to determine the necessity of contacts for other literals.
Find a minimum contact, series-parallel realization for T.
2.Find the minimal contact networks equivalent to the following diagram.
3.For the network shown below, find an equivalent contact network with only 11 contacts.
4.Design a switching circuit which can turn a lamp ON or OFF from three different locations
independently. Denote the switches x,y, and z, as shown below.(Four transfer contacts are
sufficient)
5.For each of the following functions, find a contact realization which rquires as few springs as
possible.
a. T(w,x,y,z) = Σ(0,4,6,8,9,12) (11 springs)
b. T(w,x,y,z) = Σ(3,7,8,9,13) (11 springs)
c. T(w,x,y,z) = Σ(5,6,7,9,10,11,13,14) (4 transfer contacts)
d. T(w,x,y,z) = Σ(5,6,8,10,11,12,13,14,15) (13 springs)
e. T(w,x,y,z) = Σ(5,6,7,9,10,11,12) (14 springs)
6. Utilizing the expansion theorem, express the following as symmetric functions:
a. A’S0,1,4(B,C,D,E) + AS’0,3,4(B,C,D,E)
b. A’S0,1,4(B,C,D,E) + AS0,3,4(B,C,D,E)
c. A’S0,1,4(B,C,D,E) + AS’0,3,4(B’,C’,D’,E’)
7. For each of the following functions, find a contact-network realization with minimum number of
contacts.
a. S1,4 (w,x,y,z)
b. S0,1,3(w,x,y,z)
c. S2,3,5(v,w’,x,y’,z)
8. Find a minimal contact network which realizes the symmetric function S1,3 (x1,x2,x3,x4,x5)
9. Realize each of the functions below using full adders and gates.
a. f1(x1, …., x5)=S3,4,5(x1, …, x5)
b. f1(x1, …., x7)=S2,4,6(x1, …, x7)
c. f1(x1, …., x9)=S1,3,5,7,9(x1, …, x9)
10. Let f1(x1,x2,…,xn) and f2(x1,x2,…,xn) be both symmetric functions. Which of the following
functions is also necessarily symmetric?
F1 + f2; f1.f2; f1 f2
Under what conditions will the above functions be symmetric if f1 is symmetric, but f2 is not?
11. Show that the following functions are symmetric. Find a two output realization which uses only
five transfer contacts.
a. T1(w,x,y) = Σ(1,2,4,7)
b. T2(x,y,z) = Σ(0,3,5,6)
12. Design a minimal, three output contact network to realize the functions shown below. Ten transfer
contacts should be sufficient.
a. T1(w,x,y,z) = Σ(0,1,2,4,8)
b. T2(w,x,y,z) = Σ(3,5,6,9,10,12)
c. T3(w,x,y,z) = Σ(7,11,13,14,15)
13. Determine which of the following functions is symmetric and identify its a- numbers and
variables of symmetry.
a. f(x1,x2,x3,x4,x5) = Σ(0,3,5,6,10,12,15,18,20,23,25,30)
b. f(x1,x2,x3) = Σ(0,2,3,4,5,7)
c. f(x1,x2,x3,x4) = Σ(0,5,6,9,10,15)
UNIT IV Part-B:
1. Find the function f(x1,x2,x3,x4) realized by each of the threshold networks shown in the below
figure. Show the map of each function.
2. By examining the linear inequalities, determine which of the following functions a threshold
function is, and for each one that is, find the corresponding weight-threshold vector.
a. f1(x1,x2,x3) = Σ(1,2,3,7)
b. f2(x1,x2,x3) = Σ(0,2,4,5,6)
c. f3(x1,x2,x3) = Σ(0,3,5,6)
3. For each of the functions of the above problem, which is realizable by a single threshold
element, find a realization for f”( x1’,x2,x3).
4. A. Determine the function f(x1,x2,x3,x4) realized by the network shown in the below figure.
B. show that f(x1,x2,x3,x4) can be realized by a single threshold element. Find such element.
5. Prove that if f(x1,x2,…, xn) is a threshold function with weight-threshold vector V 1 = {w1,w2,
…, wn;T}, then its dual, fd(x1,x2,…, xn) is also a threshold function. Determine its weight-
threshold vector.
6. Prove that if f is a threshold function, then so is
G = xi’f + xi.fd
Where xi may or may not be a member of the set { x1,x2,…, xn }. Find the weight-threshold
vector of g.
7. Which of the following functions is Unate? Show its minimal form.
a. f1(x1,x2,x3,x4) = Σ(1,2,3,8,9,10,11,12,14)
b. f2(x1,x2,x3,x4) = Σ(0,8,9,10,11,12,13,14)
c. f3(x1,x2,x3,x4) = Σ(2,3,6,10,11,12,14,15)
8. For each of the following functions, find a two element cascade realization of the type
illustrated in the below figure.
a. f1(x1,x2,x3,x4) = Σ(2,3,6,7,8,9,13,15)
b. f2(x1,x2,x3,x4) = Σ(0,3,4,5,6,7,8,11,12,15)
UNIT- V
1. Analyze the synchronous circuit of below figure: (clock not shown but is implicit)
a ) Write down the excitation and output functions.

b) Form the excitation and state tables.
c) Give a word description of the circuit operation.
2. A long sequence of pulses enters a two-input two-output synchronous sequentialcircuit, which

is required to produce an output pulses z = 1 whenever the sequence 1111 occurs.
Overlapping sequences are accepted; for example, if the input sequence is 01011111 · · ·, the
required output sequence is 00000011 · · ·.
(a) Draw a state diagram.
(b) Select an assignment and show the excitation and output tables.
(c) Write down the excitation functions for SR flip-flops, and draw the corresponding
logic diagram.
3. Construct the state diagram for a two-input eight-state machine that is to produce an output z
= 1 whenever the last string of five input contains exactly three 1’s and string starts with two
1’s. After each string that starts with two 1’s, analysis of the next string will not start until the
end of this string of five symbols, whether it produces an output value 1 or not. For example,
if the input sequence is 11011010 then the output sequence is 00000000, while an input
sequence 10011010 produces an output sequence 00000001.
4. Design a two-input, two-output synchronous sequential circuit that produces an output symbol
z = 1 whenever any of the following input sequences occurs: 1100, 1010, or 1001. The circuit
resets to its initial state after an output symbol 1 has been generated.
(a) Form the state diagram or table. (Seven states are sufficient.)
(b) Choose an assignment, and show the excitation functions for JK flip-flops.
5. Design a Two-input, Two-output synchronous sequential circuit that examines the input
sequence in nonoverlapping strings having three input symbols each and produces an output
symbol 1 that is coincident with the last input symbol of the string if and only if the string
consisted of either two or three 1’s. For example, if the input sequence is 010101110, the
required output sequence is 000001001. Use SR flip-flops in your realization.
6. Design a modulo-8 counter that counts in the way specified in Table. Use JK flip-flops in your
realization.
Table
Decimal Gray code
0 000
1 001
2 011
3 010
4 110
5 111
6 101
7 100
7. Construct the state diagram for a synchronous sequential machine that can be used to detect
faults in coded messages of the 2-out-of-5 type. That is, the machine examines the messages
serially and produces an output symbol 1 whenever an illegal message of five binary digits is
detected.
8. When a certain serial binary communication channel is operating correctly, all blocks of 0’s
are of even length and all blocks of 1’s are of odd length. Show the state diagram or table of a
machine that will produce an output symbol z = 1 whenever a discrepancy from the above
pattern is detected. The following is an example.
X: 0 0 1 0 0 0 1 1 1 0 1 1 0 0 · · ·
Z: 0 0 0 0 0 0 1 0 0 0 1 0 1 0 · · ·
17. Question Bank (Unit-wise)

UNIT - 1
1) Convert the fallowing numbers with the indicated bases to decimal (4310)5 and (198)12.
2) Express the fallowing numbers in decimal (10110.0101)2, (16.5)16 and (26.24)8
3) Find the 9’s and 10’s complement for the following decimal numbers
(A) 98127634 (B) 72049900 (C) 10000000 (D) 00000000
4) Obtain 1’s and 2’s complement for the following binary
(A) 11101010 (B) 01111110 (C) 00000001 (D) 10000000
5) Represent the unsigned decimal numbers 965 and 672 in BCD and show the steps necessary
to form their sum.
6) Formulate the weighted binary code for the decimal digits using weights 6,3,1,1.
7) Represent the decimal number 6027 in (A) BCD (B) Excess-3 (C) 2421
code.
8) Represent “COLLEGE” as stream of ASCII characters.
9) Decode the fallowing ASCII code:
1001010 1100001 1101110 1100101 0100000 1000100 1101111 1100101.
10) Perform the subtraction on the following unsigned numbers using 10’s complement of
subtrahend where the result should be negative, 10’s complement it and affix a minus. Verify
your answer.
(A) 7188-3049 (B) 150-2100 (C) 2997-7992(D) 1321-375.
11) Perform subtraction on the following unsigned binary numbers using 2’s complement.
(A) 11011-11001 (B) 11100-10101 (C)1011-110000 (D) 101010-101011
UNIT - 2
1) Simplify the boolean expression to a miniman no. of literals

(A) ABC+A’B+ABC’ (B) X’YZ+XZ (C)(X+Y)’(X’+Y’) (D) XY+X(WZ+WZ’)
(E) (BC’+A’D)(AB’+CD’)
2) Draw the logical diagram for the following boolean expression
(I) Y=A’B’+B(A+C) (B) Y=BC+AC’ (C)Y=A+CD (D)Y=(A+B))(C’+D)
3) Express the following function in the sum of minterms and product of minterms
F(A,B,C,D)=B’D+A’D+BD
4) Express the following component of functions in sum of minterms
(A) F(A,B,C,D)=∑(0,2,6,11,13,14) (B) F(X,Y,Z)=π(0,3,6,7)
5) Express the following to other canonical form
(A) F(X,Y,Z)=∑(1,3,7) (B) F(A,B,C,D)=π(0,1,2,34,,6,12)
6) Convert the following function into sum of products and product of sums
(A) (AB+C)(B+C’D) (B) X’+X(X+Y’)(Y+Z’)
UNIT – 3
1. Simplify the following Boolean functions, using 3-variable maps

(A) F(X,Y,Z)=∑(0,1,5,7) (B)F(X,Y,Z)=∑(1,2,3,6,7)
2. Simplify the following Boolean functions, using X- maps
(A) F(X,Y,Z)=∑(2,3,6,7) (B)F(A,B,C,D)=∑(3,7,11,13,14,15)
3. Simplify the following Boolean functions, using 4-variable maps
(C) F(W,X,Y,Z)=∑(1,4,5,6,12,14,15) (B)F(A,B,C,D)=∑(0,2,4,5,6,7,8,,10,13,15)
4. Find the prime implicates for F(A,B,C,D)=∑(0,2,3,5,7,8,,10,11,14,15).
5. Simplify the following Boolean functions in product of sums
(A) F(W,X,Y,Z)=∑(0,2,5,6,7,8,10) (B)F(A,B,C,D)=π(1,3,5,7,13,15)
6. Simplify the following expression and implement them with two-level NAND gate circuits
AB’+ABD+ABD’+A’C’D’+A’BC’.
7. Draw the logic diagram using only two-input NAND gates to implement the following
expression (AB+A’B’)(CD’+C’D)
8. Implement the following Boolean function F, using the two-level forms (A) NAND-AND
(B)AND-NOR(C) OR-NAND (D) NOR-OR
F(A,B,C,D)=∑(0,1,2,3,4,8,9,12).
9. Implement the following Boolean function with EX-OR and AND gates
F=AB’CD+A’BCD’+AB’C’D+A’BC’D.
10. A certain memory has a capacity of 16k X 32. How many words does if store what is the
number of bits per word. How many memory cells does it contain?
11. What is the capacity of the memory that has 1b address inputs four data inputs and four data
outputs?
12. Given 32 X 8 ROM chip with an enable input, show the external connections necessary to
construct 128 X 8 ROM with four chips and a decoder.
13. Design a RAM system of 4k X 8 bit capacity using 2k X 4 RAM devices with read/write, chip
enable(CE) and output enable (OE) controls.
14. Draw the structure of PLA for designing a BCD to seven segment Decoder.
15. Draw the circuit diagram for PLA to implement the following functions
f1 (A, B, C) = ∑m (1, 4, 6, 7)
f2 (X, Y, Z) = ∑m (0, 2, 4, 6).
UNIT – 4
1. What is Symmetric Networks?

2. Write the Symmetric Functions
3. Explain Threshold Elements.
4. Explain Synthesis of threshold networks
UNIT – 5
1) Construct a 64-to-1 multiplexer using (A) 8X1 multiplexer (B) 4X1 multiplexer.
2) Design a logic circuit that has 3 inputs A, B and C and whose output will be high only when a
majority of the inputs are high.
3) Implement the following using appropriate type of multiplexer
(A) ∑0,1,2,8,9,10,11,13 (B) ∑0,1,5,7,10,11,12,13.
4) Construct 6X64 DEMUX using (A) 3X8 demuxes (B) 4X16 demuxes
5) Implement the following using Demux/decoder
(A) ABNCD’+A’BC+AB’C’ (B) ∑(0,1,3,4,8,9,10) (C) ∑(1,3,5,6,11,14,15).
6) Construct the following convertors (A) BCD-to-Octal (B) binary to decimal
7) Implement the full subtractor function using two 4X1 muxs.
8) Design a sequence generator to generate the sequence 1101

9) What is the clock frequency if the period of the wave at C is 24ns? There are 8 clocks in one
cycle of C.
10) Design a synchronous counter which count in the fallowing sequence 0, 2, 4, 6 , 7, 0.
11) Design a divide by 6 counter using T flip-flop.
12) Design a universal shift generator with 4 D flip-flops.
13) Describe the working of JK, D, T flip-flops.
14) a) How many flip -flops required to build a binary counter that counts from 0 to 1023.
b) If the counter initially at zero, what count will be hold after 2060 pulses.
15) Design a MOD 12 ripple counter using JK flip-flops having only clear control.
16) Design amodulo-5 synchronous counter slipping 010,100 and 101 states of binary counter
using JK flip-flops and NAND gates.
17)) Design a counter using D flip-flops that goes through states 3, 4, 6, 7, 3.
18) Design a 3-bit synchronous up/down counter using JK flip-flops.
19) Write the steps in design the asynchronous sequential circuit.

20) The Boolean functions for the inputs of an SR latch are
S=X’1X’2X3+X1X2X3
R=X1X’2+X2X’3.
Obtain the circuit diagram using a minimum no. of AND gates.
18. Assignment Questions (Unit-wise)

UNIT- 1
1) Convert the fallowing numbers

a) 10101100111.0101 to base 10.
b) (153.513)10 = ( )8
c) Find (3250-73532)10 using 10’s complement.
d) Divide 01100100 by 00011001
e) Given that (292)10=(1204)B determine ‘B’/
2) Convert the decimal numbers 250.5, 12.0625, 104, 673.23 to binary, base-3, base-4, base-7,,
base-8, base-16.
3) Is it possible to construct a 5411 weighted code and also 6321 weighted code? Justify your
answer.
4) Convert the following numbers to decimal (1001001.011)2, (12121)3, (1032.2)4, (4310)5,
(0.342)6, (50)7, (8.3)9.
5) Subtract the following numbers using 2’s & 1’s complement
a) 5250-321 (b) 753-864 (c) 3570-2100 (d) 20-1000.
6) Reduce the following expression to three literals [(CD)’+A]’+A+CD+AB.
7) Simplify to a sum of 3 terms A’C’D’+AC’+BCD+A’CD’+A’BC+AB’C’.
8) Given that AB+AB=C show that AC’+A’C=B.
9) Express the following to other canonical form
(B) F(X,Y,Z)=∑(1,3,7) (B) F(A,B,C,D)=π(0,1,2,34,,6,12)
10) Convert the following function into sum of products and product of sums
(B) (AB+C)(B+C’D) (B) X’+X(X+Y’)(Y+Z’)
UNIT -2
1) Simplify the following using K-map method

b) F(A,B,C,D,E)=∑(0,2,4,6,9,,11,13,15,17,21,25,27,29,31).
c) F(A,B,C,D,E)=∑(0,1,4,5,16,17,21,25,29).
2) Simplify the following functions and implement it with NAND gates

a) F1 = AC’+ACE+ACE”+A’CD’+A’D’E’
b) F1 = (B’+D’)(A’+C’+D)(A+B’+C’+D)(A’+B+C’+D’)
c) F=∑(0,6)
3) Simplify the following Boolean functions, using 4-variable maps
(D) F(W,X,Y,Z)=∑(1,4,5,6,12,14,15) (B)F(A,B,C,D)=∑(0,2,4,5,6,7,8,,10,13,15)
4) Draw the logic diagram using only two-input NAND gates to implement the following
expression (AB+A’B’)(CD’+C’D)
UNIT -3
1) Design a full adder by using two half adders

2) Design a full sub tractor by using two half subtractors.
3) Design a combinational circuit for a 4-bit magnitude comparator.
4) Implement the following function with a multiplexer F(A,B,C,D)=∑(0,1,3,4,8,9,15).
5) Design a combinational circuit for an octal-to-binary encoder.
6) Design BCD-to-decimal decoder.
7) A combinational circuit is defined by the functions
F1(A,B,C) = ∑(3,5,6,7)
F2(A,B,C) = ∑(0,2,4,7)
8) Implement the circuit with a PLA having 3 inputs, four product6 terms and two outputs.
9) Explain in detail Sequential programmable devices.

10) What is ROM. Write about different types of ROMs?
11) Explain PLA and Error detection & Error correction.
12) Explain in detail hazards in combinational networks.
13) Find the circuit diagram that has no static hazards and implement the Boolean function
F(A,B,C,D)=∑(0,2,6,7,8,10,12).
UNIT – 4
1. What is Symmetric Networks?

2. Write the Symmetric Functions
3. Explain Threshold Elements.
4. Explain Synthesis of threshold networks
UNIT - 5
1) What is flip-flop? Design basic flip-flop circuit with NAND gates.

2) What is a Master-Slave flip-flop? Design a clocked master slave JK flip-flop.
3) Define latch and mention the similarities and differences between flip-flop and latches
4) Define a Ripple Counter. Design BCD ripple counter.
5) Design a 4-bit bi-directional shift register with parallel load.
6) What is a shift register? Draw the block diagram and timing diagram of a shift register that
shows the serial transfer of information from register A to register B.
7) Design a 4-bit register with parallel load using D flip-flop.
8) Explain race-free state assignment hazards.
9) Explain design procedure for Asynchronous Sequential Logic.
10) The Boolean functions for the inputs of an SR latch are
S=X’1X’2X3+X1X2X3
R=X1X’2+X2X’3.
Obtain the circuit diagram using a minimum no. of AND gates.

19 Unit wise Quiz Questions and long answer questions
Unit-1
1. The excess-3 code of decimal 7 is represented by [ D]
(A) 1100 (B) 1001 (C) 1011 (D) 1010
2. Karnaugh map is used for the purpose of [ C]

(A) Reducing the electronic circuits used (B) To map the given Boolean logic function
(C) Minimizing terms in a Boolean expression (D) maximizing terms of a Boolean expression
3. (2479.859)10 = [B ]
(A)(AAF.DBE76)16 (B) (9AF.DBE76)16 (C) (9AF.DBE79)16 (D) All
4. How many numbers in the BCD are forbidden numbers [A ]

(A)6 (B) 4 (C) 8 (D)All
5. Which of the following conversion method is known as Double Dabble method [ B]

(A) Binary to decimal (B) Decimal to binary (C) Decimal to Hexadecimal (D) None
6. The minimum number of bits required to represent negative numbers in the range of -1 to -11 using
2’s complement arithmetic is [ d]
(a)2 (b) 3 (c) 4 (d) 5
7. The following code is not a BCD code. [a ]
(a)Gray code (b) Xs-3 code (c) 8421 code (d) All of these
8. A 15-bit hamming code requires [a ]
(a)4 parity bits (b) 5 parity bits (c) 15 parity bits (d) 7 parity bits
9. Which of the following Boolean algebraic expressions is incorrect? [ B]
(a) A+AB=A+B (b) A+AB=B (c) (A+B)(A+C)=A+BC (d) (A+B)(A+B)=A
10. A literal is a ________________ variable. [ d]

(A) complemented (B) uncomplemented (C) both (D) A or B
11. (0.93) 10 = ( ___________ ) 8 [ B]
(A) 0.55 (B) 0.7341 (C) 0.17 (D) 0.258
12. In Binary Addition, 1 + 1 = ______________ [ A]
(A) 10 (B) 1 (C) 0 (D) All
13. Which of the following codes uses 7 bits to represent a character [A ]

a. ASCII b. BCD c. EBCIDIC d. GRAY
14. If (123)5 = (X3)y then the possible values of x are [ D]
a.4 b.1 c.3 d.2
15. Which of the following are not weighted codes [C ]
a. Octal number b. Decimal number c. Excess 3 code d. Binary number
Unit-2
1. How to Obtain a NAND Gate [D]

(A)NOT + XOR (B)AND + NOR (C) NOT + NOR (D) AND + NOT
2. According to Basic law of Boolean algebra which of the following are correct [C ]
(A)(A+A).B=A (B) A.(A+B)=A (C) Both A&B (D)None
3. The gates required to build a half adder are [C ]
(A) EX-OR gate and NOR gate (B) EX-OR gate and OR gate
(C) EX-OR gate and AND gate (D) Four NAND gates
4. In digital ICs, Schottky transistors are preferred over normal transistors because of their [A ]
(A) Lower Propagation delay (B) Higher Propagation delay
(C) Lower Power dissipation (D) Higher Power dissipation
5. T he logic expression (A+B) ()AB+ can be implemented by giving the inputs A and B to
a two-input [C ]
(a) NOR gate (b) NAND gate (c) X-OR gate (d) X-NOR gate
m
6. In simplification of a Boolean function of n variables, a group of 2 adjacent 1s leads to a term
with [ D]
(a)m-1 literals less than the total number of variables
(b)m+1 literals less than the total number of variables
(c)n+m literals d)n-m literals
7. The NAND – NAND realization is equivalent to [B ]
(a)AND – NOT realization (b) AND – OR realization
(c)OR – AND realization (d) NOT – OR realization
8. The minimum number of bits required to code 2n distinct quantities is [a ]
(A) n (B) 2n (C) n2 (D) none
9. The operator precedence for evaluating Boolean expressions is [C ]
(A) parentheses, NOT, OR, AND (B) parentheses, AND , OR, NOT
(C) parentheses, NOT, AND, OR (D) parentheses, OR, AND, NOT
10. A literal is a primed variable. [A ]
(A) TRUE (B) FALSE (C) both (D) none
11. The operator symbol ‫ס‬ ‫ ס‬indicates [D ]
(A) equality (B) coincidence (C) Ex-clusive NOR (D) All
Unit-3
1. For the design of a combination circuit with four outputs using only NAND gates, the number of k
– maps required for the simplification process is [D ]
(a)0 (b) 1 (c) 2 (d) 4
2. A de - multiplexer is used to [C ]
(a)Perform arithmetic division b)Select data from several inputs and route it to a single output
(c)Select data from single inputs to one of the many outputs d)perform parity checking
3. A BCD to XS – 3 code converter can be designed using [B ]
(a) a 16:1 multiplexer (b) a 1:16 de multiplexer
(c) two 16:1 multiplexers (d) none of the above
4. Half - Adder circuit needs _____ binary inputs and ____binary outputs. [ C]
(A) 1, 1 (B) 1, 2 (C) 2, 2 (D) 2,1
5. NAND gate is also called as [B ]
(A) Inverter (B) Bubbled – OR (C) Bubbled – AND (D) All
6. Minimum number of Nand gates required to construct full adder [A ]
a.9 b.10 c.11 d.12
7. Any given Boolean expression can be implemented by using [D ]

a. Only NAND gates b. Only NOR gates c. Only AND gates d. both A and B
8. Which of the following logic families is well suited for high speed operation [ B]
a. TTL b. ECL c. MOS d. CMOS
9. In combinational logic circuits, memory unit in required [ B]
(A) True (B) False (C) both (A+B) (D) None
Unit-4
1. A Binary Cell has _________________ stable states. [B ]

(A) 4 (B) 2 (C) 3 (D) 1
2. The register AX is used as [ C]

a. offset storage b. default counter c. accumulator d. none
3. Which of the following is not a register [B ]
a. Accumulator b. Buffer c. Stack pointer d. Program counter
4. A n-stage ripple counter will count up to [A ]
(A) 2n (B) 2n-1 (C) n (D) 2n-1
5. Popular application of flip-flop is [D ]
(A) Transfer registers (B) Counters (C) Shift registers (D) All
6. In a positive edge triggered JK flip-flop, a low J and a low K produces [A ]
(A) No change (B) Low state (C) High state (D) None
7. It is difficult to design an asynchronous sequential circuit because [ C]
(A) External clock is to be provided (B) It is more complex
(C) Involve stability problem (D) All
8. Register is a [B ]
(A) Set of capacitors (B) Ttemporary storage unit (C)Both A&B (D)None
9. Types of sequential circuit(s) [C ]
(A) Synchronous (B) Asynchronous (C) Both A&B (D) None
10. The number of flip-flops required in a decade counter is [B ]
(A) 3 (B) 4 (C) 8 (D) 10
11. Examples of sequential systems [D ]
(A) ATM (B) Traffic light (C) Vending machine (D) All
12. Identify the storage element (s) [C ]
(A) Latches (B) Flip-flops (C) Both A&B (D) None
13. Unwanted switching transients at the output are [B ]
(A) Race conditions (B) Hazards (C) Both A&B (D) None
14. Which of the following flip-flop is used as latch? [ D]
a) j-k flip-flop b) master-slave flip-flop c) T flip-flop d) D flip-flop
15. When an inverter is placed between the inputs of an S-R flip-flop, the resulting flip- flop is a
__________ [D ]
a) j-k flip-flop b) master-slave flip-flop c) T flip-flop d) D flip-flop
16. A shift register using flip-flops is called as_________ [C ]
a) Dynamic shift register b) flip-flop c) Static shift register d) buffer shift register
17. A serial adder can be designed______________ [ D]
a) using only gates b) using only flip-flops
c) combinational circuit d) sequential circuit
18. An ASM chart consists of______ [A ]
a) state, decision & conditional output boxes b) only decision boxes
c) only decision & conditional output boxes d) only state boxes
19. ASM chart represents____________ [ C]
a) gates b) multiplexers c) synchronous sequential circuit d) only flip-flops
20. An ASM chart can be________ [ D]
a) converted into a state diagram b) converted into a state table
c) implemented using gates and flip-flop d) converted as (a) and (b) and can be implemented as (c)
21. A FF has _______stable states.

[ A]
(A) 2 (B) 3 (C) 1 (D) 4
22. Synchronous counters are _____ than asynchronous counters [B ]
(A) slower (B) Faster (C) both (A+B) (D) None
23. The speed of operation for ripple counters in [A ]
(A) high (B) low (C) medium (D) worst
24. Serial Adder is an example for ____________ logic circuit. [A ]
(A) Sequential (B) combinational (C) FF (D) counter
n
25. If maximum modulus of a counter is 2 , then no. of FFs required would be [C ]
(A) n / 2 (B ) n2 (C) n (D) n / 4
26. Ripple counter is _______________________ counter. [A ]
(A) asynchronous (B) synchronous (C) both (A+B) (D) none
27. Races exist in ____________________ machines. [B ]
(A) asynchronous (B) synchronous (C) both (A+B) (D) none
Unit-5
1. In a RAM, information can be stored [A ]
(A) By the user, number of times (B) By the user, only once
(C) By the manufacturer, a number of times (D) By the manufacturer only once
2. Addressing mode used in instruction ADD X Y is [A ]

a. absolute b. immediate c. indirect d. index
3. An 8×4 ROM contains a decoder of size_________ [A ]
a) 3×8 b) 8×4 c) 8×8 d) 3×4
4. PLA consists of__________ [D ]
a) AND matrix b) OR matrix c) invert/non-invert matrix d) all of the above
5. When power supply of a ROM is switched off, its contents______________ [ C]
a) become all zero b) become all one c) remain intact d) are unpredictable
6. The memory constructed using only gates is [ D]

A. ROM B. RAM C. Cache D. Registers
7. Identify Non volatile Random access storage [B ]

A.RAM B.ROM C.EEPROM D.PLA
8. _____ is a RAM which performs association operation apart from read / write [ D]
A. DRAM B. CAM(content addressable memory) C. SRAM D. Bipolar RAM
9. Word length is based on ___________ [D ]
A. Size of the computer and RAM B. Size of RAM C. Size of IDE channel D. none
10. Storage capacity of a memory device is _______ [B ]
n m mn
A. (2 )*m B.(2 )*n C.2mn D.2
Note: n – number of address lines
m - number of bits in each location
11. Identify Random access memory from the following [B ]
A. CD ROM B. Floppy Disk C. Magnetic Tape D. ROM
20 TUTORIAL TOPICS
(UNIT-1)
Tutorial 1:
4. Binary conversions
5. Binary codes
6. Logic implementation using gates
Tutorial 2:
1. Number base conversations
2. K-maps
3. Don’t care conditions
Tutorial 3:
1. NAND & NOR Gates
2. SOP and POS
3. Minimizations
Tutorial 4:
1. Flipflops
2. Latches
3. Binary adder
Tutorial 5:
1. Combinational circuits
2. Decimal adder
3. Magnitude comparator
Tutorial 6:
1. Binary subtractor and multiplications
2. Mulplexers
3. Demultiplexers
Tutorial 7:
5. Synthesis of contact networks
6. Symmetric functions
7. Symmetric Networks
Tutorial 8:
1. Shift registers
2. Ripple counters
3. State reductions
Tutorial 9:
1. PLA
2. PAL
3. ROM and RAM
21 Known gaps ,if any
1.counter Design with examples .
2 . practical exposer on logic gates
22. Discussion topics , if any

# Error Correction and error detected using HAMMING CODE
23. References, Journals, websites and E-links if any
Suggested Books
Text books
1. DIGITAL DESIGN – Third edition, M Morris Mano, Pearson Education/PHI.
2. Switching and Finite Automata Theory by Zvi. Kohavi, 2nd edition, Tata McGraw Hill.
3. Switching and Logic Design, C.V.S. Rao, Pearson Education.
4. Digital Principles and Design – Donald D.Givone, Tata McGraw Hill, Edition.
5. Fundamentals of Digital Logic & Micro Computer Design , 5TH Edition, M.
Rafiquzzaman John Wiley.
Subject Experts
Thomas L. Floyd
John P. Hayes
List of relevant Journals

1 Integration of an online digital logic design lab for it education
Conference ON Information Technology Education (formerly CITC ) archive
Proceedings of the 9 th ACM SIGITE conference on Information Technology

education
2 Digital And Analog Circuit Simulation with Ksimus
www.linuxjournal.com/.../digital-and-analog-circuit-simulation-ksimus
24. Quality Measurement Sheets (to be enclosed after the semester)

a. Course End Survey
b. Teaching Evaluation
25. Student List

26. Group-Wise students list for discussion topics

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Geethanjali College of Engineering and

DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING

Faculty in Charge HOD-CSE

Name of the Subject: DIGITAL DESIGN

Subject CODE: 18EC2102 Programme: UG

Branch: CSE Version No: 2

Year: II Document Number : GCET/CSE

Semester: I No. of Pages: 191

Classification status (Unrestricted/Restricted ) : Unrestricted

Distribution List: Unrestricted

1) Name : M Vijay Bhasker Reddy

3) Design : Assistant Professor

Verified by : *For Q.C only

1) Name : D. Venkateswarlu 1) Name :

3) Design : Associate Professor 3) Design :

Course file contents

Course coordinator HOD

UNIT III: Design of Combinational Circuits: Adders, Subtractors, Multiplexers, Realization of

4. Mission of the Department

5. PROGRAM EDUCATIONAL OBJECTIVES (PEOs) OF C.S.E.

3. Design/development of solutions : Design solutions for complex engineering problems

4. Conduct investigations of complex problems: Use research-based knowledge and research

7. Environment and sustainability: Understand the impact of the professional engineering

6. Course Objectives and Outcomes

1. Understand basic concepts of various number systems used in digital systems.

Course Outcomes (COs):

CO1. Perform conversions from one number system to another.

a. What role does this course play within the Program?

• The purpose of this course is that we:

 Learn the principles of digital design

 Learn to systematically debug increasingly complex designs

 Design and build a digital system

9. Instructional Learning Outcomes

10. DD COURSE MAPPING WITH PEOs AND POs

Mapping of Course with Programme Educational Objectives

S.No Course code Semester PEO 1 PEO 2 PEO 3

11. Class Time Table

12. Individual Time Table

Methodology Adopted or Used:

PPT - Power Point Presentation

Video- Video Lecture

(B) Micro plan

31. I MID ECAMINATIONS 1

50. Twisted Ring Counter 1 BB/ Video T2, 6.5

14. Detailed Notes

1101.01 = 1 × 23 + 1 × 22 + 0 × 21 + 1 × 20 + 0 × 2−1 + 1 × 2−2,

The complement of a digit a, denoted a’ , in base b is defined as

If (N )b1 is a fraction, a dual procedure is employed. It can be expressed in base b2 as follows:

Example To convert (0.3125)10 to base 8, find the digits as follows:

Thus (0.3125)10 = (0.24)8.

Hence (432)10 = (110110000)2. For the fractional part we have

Example The addition of (15.25)10 and (7.50)10 in binary proceeds as follows:

Example Divide the binary number 1000100110 by 11001.

1’s Complement Representation:

2’s Complement Representation:

Fig. 1.1 Refection of Gray Code

 Binary Coded Decimal Code and its Properties

35710=0011 0101 0111(BCD)

Binary Coded Decimal Representation of a Decimal Number

 Alpha Numeric Codes

 Error Detecting and Correcting Codes

These values are often referred to as the truth values of x.