NOTE : ALL TEXT DETALIS (and Circuit )ARE FOR YOUR WRITE UP IN

YOUR RECORD
EXP 9: Design of NOR GATE
Aim: To design 2 Input CMOS NOR Gate using 130nm Technology
Software EDA tool used:

1. Mentor Graphics-“ IC Station” (Pyxis Tool for IC Schematic and Layout designs) and
2. IC Verification tools such as ELDO( Simulation Tool) and Calibre nmDRC, Calibre
nmLVS, Calibre xRC for Physcial design verifications.

Circuit Diagram of 2 input CMOS NOR Gate:

Note:

1. Explain in brief its operation and also address its W/L values of MOSFETS that are available in
schematic screenshot

2. ALL screen shots are for printouts and take print out as it is and paste (attach them) in your
record (tool name must be appeared)
Two Input CMOS NOR GATE Schematic design:

Two Input CMOS NOR GATE Symbol Creation:

Two Input CMOS NOR GATE Test bench Schematic for Simulation:

Simulation Result of Two Input CMOS NOR GATE:

Layout Design of Two Input CMOS NOR GATE:

Results:
CMOS 2 input NOR Gate has been designed at transistor level and layout level using 130nm
technology and also verified its functionality.

I. Total Power Dissipation: 19.3159 Nano WATTS for 3V Power Supply

II. Dealy : 21.175 Nano seconds
III. Chip Area : W X L= 9.6um X 6.5um=62.4 um2