Electronic Devices Quiz – 2 Notice

Exam Date: 21/11/2019 (Thursday, 5 to 6 PM)

Exam weightage: 26 Marks; Exam questions: MCQ based questions; Exam type: Open Book

Open Book components: Handwritten class notes, mentioned text book, mentioned reference book,
photocopies of only these text & reference books (strictly no other books)

Please go through the detailed syllabus (topics wise)

From PN Junction (after midsem): Depletion capacitance, Diffusion capacitance, small signal equivalent model,
Tunnel diode, Forward bias Diode current, Reverse saturation current, 1/C^2 vs Voltage plot and from there doping
concentration or built-in potential calculation, Metal-Semiconductor contacts - Schottky diode and Ohmic contacts,
Forward bias Schottky Diode current, Reverse saturation current, Barrier height, and depletion width and internal
electric field of Schottky diode.
From MOSCAP: Accumulation-Depletion-Inversion in MOSCAP, surface potential, condition for inversion,
depletion width, max depletion width, Capacitance-voltage characteristics, accumulation-depletion-minimum-
inversion capacitances, metal-semiconductor work-function difference, flatband voltage, threshold voltage, effect of
fixed oxide charges on MOSCAP, and effects of N+ or P+ polysi Gate on MOSCAP.
From MOSFETs: Basic difference between Enhancement mode and depletion mode MOSFET, Transfer
characteristics of MOSFET, Sub-threshold condition, Output characteristics, pinch off condition, Saturated drain
voltage and its relation with Gate and Threshold voltages, Drain current in active and saturation regions,
Transconductance (both in active & saturation regions), Output resistance, MOSFET small signal equivalent circuit
(both at low and high frequencies), Cut-off frequency in high frequency small signal equivalent circuit, effect of
source resistance on drain current, effect of short channel on MOSFET performances (surface scattering, drain
induced barrier lowering and its drain current relation), and how to further tune threshold voltage in MOSFET -
Effect of Body bias on threshold voltage; Effects of n+ polysilicon and p+ polysilicon gate on the threshold voltage
of n or p-channel MOSFETs (enhancement mode).
From JFETs: JFET Transfer characteristics - Drain current vs gate voltage (fixed drain voltage), transconductance,
Pinch off during transfer characteristics (turn off the device), channel conductance, depletion width in equilibrium
and with gate bias, corresponding internal pinch-off voltage, pinch-off voltage (applied gate voltage for which pinch-
off gets occurred), JFET output characteristics - Drain current vs drain voltage (fixed gate voltage) – active region,
saturation region, and cut-off region, depletion width with gate & drain bias, corresponding internal pinch-off
voltage, and drain saturation voltage (applied drain voltage for which pinch-off gets occurred).
Note: In class, for MOSFET, I have considered P-substrate (or n-channel) enhancement mode MOSFET, but go
through the N-substrate (or P-channel) MOSFET as well. On the other side, for JFET, I have considered n-channel
JFET, but go through the p-channel JFET. The operation will just be opposite; however the polarity in formulas will
be changed.
Seating arrangements:
Room F-102 & F-103: Only ECE (strictly NO EEE & INSTR) – 4 students/bench
Room F-105: Only EEE (Strictly NO ECE & INSTR) – 4 students/bench
Room F-104: Remaining EEE after F-105 + Remaining INSTR after F-107 (Strictly NO ECE) – 4
students/bench
Room F-107: Only INSTR (Strictly NO ECE & EEE) – 1 student/bench

Let’s maintain this seating arrangement so that I could track all the papers easily. Thanks!
Instructor In-charge