Lab Manual: COURSE TITLE: - COURSE CODE

LAB MANUAL
COURSE TITLE: _________________________________

COURSE CODE: ___________
STUDENT NAME:
REG. NO:
SECTION:
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING

AIR UNIVERSITY ISLAMABAD
Lab Objectives
Lab # Lab Experiments
1 Characteristics of BJT and MOSFET
2 BJT as Common Emitter Amplifier
3 BJT as Common Collector Amplifier
4 BJT as Common Base Amplifier
5 BJT Current Mirror
6 Widlar Current Source
7 Wilson Current Mirror
8 Frequency Response of Common Emitter Amplifier
9 Frequency Response of Common Source Amplifier
10 BJT Differential Amplifier
11 Multistage Amplifier
12 Class A Output Stage
13 Class B Output Stage
14 Open Ended Lab

AIR UNIVERSITY
EXPERIMENT NO 1
Lab Title
Student Name: Reg. No:
Objective:
LAB ASSESSMENT:
Excellent Good Average Satisfactory Unsatisfactory

Attributes
(5) (4) (3) (2) (1)
Ability to Conduct
Experiment
Ability to assimilate the
results
Effective use of lab
equipment and follows
the lab safety rules
Total Marks: Obtained Marks:
LAB REPORT ASSESSMENT:

Attributes
(5) (4) (3) (2) (1)
Data presentation
Experimental results
Conclusion

Date: Signature:
EXPERIMENT NO 1
Characteristics of Bipolar Junction Transistor (BJT)

andMOSFET
Objectives:
 To determine transistor type (npn, pnp), terminals, and material using a digital
multimeter(DMM).
 To study the behavior of transistor as a switch.
 To examine the properties of a MOSFET.
 To observe the effect of various biasing schemes.
Equipment:
 Transistor
 MOSFET
 Digital Multimeter
 Resistors
Discussion:
Bipolar Junction Transistor (BJT):

Bipolar transistors are made of either Silicon (Si) or Germanium (Ge). Their structure
consists of two layers of n-type material separated by a layer of p-type material (npn), or of
two layers of p-material separated by a layer of n-material (pnp). In either case, the center layer
formsthe base of the transistor, while the external layers form the collector and the emitter of
the transistor. It is this structure that determines the polarities of any voltages applied and the
direction of the electron or conventional current flow. The arrow at the emitter terminal of the
transistor symbol for either type of transistor points in the direction of conventional current
flow.One part of this experiment will demonstrate how you can determine the type of transistor,
its material, and identify its three terminals.
The relationships between the voltages and the currents associated with a bipolar
junction transistor under various operating conditions determine its performance. These
relationships are collectively known as the characteristics of the transistor. As such, they are
published by the manufacturer of a given transistor in a specification sheet.
It is one of the objectives of this lab to experimentally measure these characteristics
andto compare them with their published values.
The three terminals of a transistor are following:

 Collector
 Base
 Emitter
 NPN Transistor:
NPN is one of the two types of bipolar transistors, in which the letters "N" and "P"
referto the majority charge carriers inside the different regions of the transistor. Most bipolar
transistors used today are NPN, because electron mobility is higher than hole mobility in
semiconductors, allowing greater currents and faster operation.
NPN transistors consist of a layer of P-doped semiconductor (the "base") between two
N-doped layers. A small current entering the base in common-emitter mode is amplified in the
collector output. In other terms, an NPN transistor is "on" when its base is pulled high relative
to the emitter.
The arrow in the NPN transistor symbol is on the emitter leg and points in the
directionof the conventional current flow when the device is in forward active mode.
NPN BJT structure creates two p-n junctions. The junction between the n-type collector
and the p-type base is called the Collector-Base Junction (CBJ). Note for the CBJ, the anode is
the base, and the cathode is the collector. However, the junction between the n-type emitter
and the p-type base is called the Emitter-Base Junction (EBJ). Note for the EBJ, the anode is
the base, and the cathode is the emitter.
 PNP Transistor:
PNP transistors consist of a layer of N-doped semiconductor between two layers of P-

doped material. A small current leaving the base in common-emitter mode is amplified in the
collector output. In other terms, a PNP transistor is "on" when its base is pulled low relative
tothe emitter.
The arrow in the PNP transistor symbol is on the emitter leg and points in the direction
ofthe conventional current flow when the device is in forward active mode.
PNP BJT structure creates two p-n junctions. For the pnp BJT, the anode of the CBJ
isthe collector, and the cathode of the CBJ is the base. Likewise, the anode of the EBJ is the
emitter, and the cathode of the EBJ is the base.
MOSFET:
Previously, we have been considering BJTs, besides BJT, another more important three
terminal device is Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) or MOS.
MOSFETs are used more widely in industry for implementing digital designs. They are
preferred in industry because of their size (smaller), ease of manufacture and lesser power
utilization. MOSFET technology allows placement of approximately 2 billion transistors on a
single IC and therefore forms the backbone of very large scale integration (VLSI).
 Basic Structure and Principle of Operation:

The n-type Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) consists of
a source and a drain, two highly conducting n-type semiconductor regions which are isolated
from the p-type substrate by reversed-biased p-n diodes. A metal (or polycrystalline) gate
covers the region between source and drain, but is separated from the semiconductor by the
gate oxide. The basic structure of an n-type MOSFET and the corresponding circuit symbol
are shown below.
It can be seen in the figure that the source and the drain regions are identical. It is the
applied voltages which determine which n-type region provides the electrons and becomes the
source, while the other n-type region collects the electrons and becomes the drain. The voltages
applied to the drain and gate electrode as well as to the substrate by means of a back contact,
are referred to as the source potential, as also indicated in the figure.
A top view of the same MOSFET is shown below where the gate length, L, and gate
width, W, are identified. Note that the gate length does not equal the physical dimension of the
gate, but rather the distance between the source and drain regions underneath the gate. The
overlap between the gate, the source and drain region is required to ensure that, the inversion
layer forms a continuous conducting path between the source and drain region. Typically this
overlap is made as small as possible in order to minimize its parasitic capacitance.
The typical current versus voltage (I-V) characteristics of a
MOSFET
The flow of electrons from the source to the drain is controlled by the voltage applied
to the gate. A positive voltage applied to the gate, attracts electrons to the interface between
thegate dielectric and the semiconductor. These electrons form a conducting channel between
the source and the drain, called the inversion layer. No gate current is required to maintain the
inversion layer at the interface since the gate oxide blocks any carrier flow. The net result is
that the current between drain and source is controlled by the voltage which is applied to the
gate.
 Modes of Operation and Voltage Transfer Characteristic Curve:

Three regions exist in VTC.
 VGS < Vt (Cut off)
 VOV = VGS – Vt < 0
 ID = 0
 Vout = VDD
 Vt < VGS < VDS + Vt (Saturation)
 VOV = VGS – Vt > 0
 ID = ½ kn(VGS – Vt)2
 VDS >> VOV
 Vout = VDD – IDRD
 VDS + Vt < VGS < VDD (Triode)
 VOV = VGS – Vt > 0
 ID = kn(VGS – Vt – VDS)VDS
 VDS > VOV
 Vout = VDD – IDRD
MOS transistor acts as an amplifier in Saturation region and as an inverter in Triode and
Cutoff regions.
 Biasing a MOSFET:
For a MOSFET to act as an amplifier, a proper DC bias point is required. The DC bias
circuit is to ensure the MOSFET in saturation with a proper collector current ID. ID however, is
dependent on a number of factors which also includes physical factors which can vary with
temperature and a number of factors.
Therefore, a number of biasing schemes have been presented. Two of which will be
covered in Lab.
(1) Biasing using Gate-to-Drain Feedback Resistor:
In this type of biasing category, a single power supply is needed. There will be no
currentbetween drain and gate. RG ensures the MOSFET in saturation (VGS=VDS). MOSFET
operating point is maintained.
The value of the feedback resistor RG affects the small-signal gain. RD acts as a negative
feedback resistor to stabilize the drain current.
(2) Biasing using Fixed VG with Source Resistor:
This configuration generates fix VG from the given power supply by making a voltage
divider. Therefore, according to the equation:
As VG is fixed, VGS would vary to keep ID fixed. In this configuration, gate resistance is
chosen to be very high to give high input impedance to the AC signal which is to be coupled
to the MOSFET. Drain resistance also need to be high in order to give high voltage gain,
however,it should not be such large that FET move away from saturation. Also, RS (Source
Resistance) is kept very high to nullify the effect of parametric changes.
 NMOS as an Inverter:
When VIN is logic 1, VOUT is logic 0. Constant nonzero current flows through the
transistor. Power is used, even though no new computation is being performed. When
VINchanges to logic 0, transistor gets cutoff. ID goes to 0. Resistor voltage goes to zero. VOUT
“pulled up” to 5 V.
Procedure:
Bipolar Junction Transistor(BJT):
 Determination of Transistor’s Type, Terminals and Material:
The following procedure will determine the type, terminals and material of a transistor.
The procedure will utilize the diode testing scale found on many modern multimeters. If no
such scale is available, the resistance scales of the meter may be used.
a. Label the transistor terminals of below figure as 1, 2 and 3. Use the transistor
without terminal identification for this part of the experiment.
b. Set the selector switch of the multimeter to the diode scale (or to the 2kΩ range if
the diode scale is unavailable).
c. Connect the positive lead of meter to terminal 1 and the negative lead to terminal 2.
Record the reading the Table.
d. Reverse the leads and record your reading.

e. Connect the positive lead to terminal 1 and the negative lead to terminal 3. Record
thereading.
f. Reverse the lead and record the reading.
g. Connect the positive lead to terminal 2 and the negative lead to terminal 3.
Recordyour reading.
h. Reverse the leads and record your reading.
i. The meter readings between two of the terminals will read high (or higher
resistance) regardless of the polarity of the meter leads connected. Neither of these
two terminalswill be the base. Based on the above calculations, record the number
of the base terminal in the table below.
j. Connect the negative lead to the base terminal and the positive lead to either of the
other terminals. If the meter reading is low (approximately 0.7 V for Si and 0.3 V
for Ge or lower resistance), the transistor type is pnp. If it is not so, then connect
the positive lead to the base terminal and the negative lead to either of the other
terminals. If the meter reading is low (approximately 0.7 V for Si and 0.3 V for Ge
or lower resistance), the transistor type is npn.
k. (1) For pnp Type: Connect the negative lead to the base terminal and the positive
lead alternatively to either of the other two terminals. The lower of the two readings
obtained indicates that the base and collector are connected. Thus, the other
terminalis the emitter. Record the terminals in the above table.
(2) For npn Type: Connect the positive lead to the base terminal and the negative
lead alternatively to either of the other two terminals. The lower of the two readings
obtained indicates that the base and collector are connected. Thus, the other
terminalis the emitter. Record the terminals in the above table.
l. If the readings in either (1) or (2) of (k) were approximately 700mV, the transistor
material is Silicon. If the readings were approximately 300mV, the material is
germanium. If the meter does not have a diode testing scale, the material cannot be
determined directly. Record the Type of Material in the above table.
 Transistor as a switch:
Connect the circuit given below. Record the readings in the table.
Vin IB IC VC
0V
5V
Table
MOSFET:
 Biasing a MOSFET:
(1) Biasing using Gate-to-Drain Feedback Resistor:
VDD = ……12v……….
RD = ……2.2k………...
RG = ……1M………...
VG VD VGS VDS Mode
(2) Biasing using Fixed VG with Source Resistor:

VDD =.......12V...........
RD = ……10K……...
RG1 = ……6.8K……..
RG2 = ……15K……..
RS = ……10K………
VG VD VGS VDS Mode
 NMOS as an Inverter:
VIN VOUT
Lab tasks:
Simulate all the given circuits in proteus and record all measurements required.
Study about characteristic curves and regions of operation of both BJT and MOSFET and include
them in lab reports.
What is pinch off voltage in MOSFETS?
What is the difference between enhancement and depletion type MOSFETS? Attach following
proteus simulation files with lab reports.
Transistor as a switch MOSFET as a switch
Transistor as an amplifier Transfer curve of MOSFET.
Biasing circuits of MOSFET with measurements.
AIR UNIVERSITY
EXPERIMENT NO 2
Lab Title
Objective:
LAB ASSESSMENT:

Attributes
(5) (4) (3) (2) (1)
Ability to Conduct
Experiment
results

Attributes
(5) (4) (3) (2) (1)
Data presentation
Conclusion

Date: Signature:
EXPERIMENT NO 2
BJT as Common Emitter

Amplifier
Objectives:
 To study the common emitter amplifier configuration.
 To simulate the circuit in Proteus.
 Implementation of common emitter circuit on Hardware.
Equipment:
 Oscilloscope
 Function Generator
 Transistor
 Resistors
 Capacitors
Discussion:
One of the earliest and important applications of bipolar transistors is in small-signal
amplifiers. These are systems that accept input signal of small amplitudes (on the order of 100
mV) and deliver larger replicas. We emphasize the use of the bipolar transistor in linear
amplifier applications. Linear amplifiers imply that, for the most part, we are dealing with
analog signals. The magnitude of an analog signal may have any value, within limits, and may
vary continuously with respect to time. A linear amplifier then means that the output signal is
equal to the input signal multiplied by a constant, where the magnitude of the constant of
proportionality is, in general, greater than unity.
 Common Emitter Amplifier Configuration:
Common Emitter Configuration

All types of Transistor Amplifiers operate using AC signal inputs which alternate
between a positive value and a negative value so some way of “presetting” the amplifier circuit
to operate between these two maximum or peak values is required. This is achieved using a
process known as Biasing. Biasing is very important in amplifier design as it establishes
the
correct operating point of the transistor amplifier ready to receive signals, thereby reducing any
distortion to the output signal.
Static or DC load line can be drawn onto the output characteristics curves to show all
the possible operating points of the transistor from fully “ON” to fully “OFF”, and to which
the quiescent operating point or Q-point of the amplifier can be found.
The aim of any small signal amplifier is to amplify all of the input signal with the
minimum amount of distortion possible to the output signal, in other words, the output signal
must be an exact reproduction of the input signal but only bigger (amplified).
To obtain low distortion when used as an amplifier, the operating quiescent point
needsto be correctly selected. This is in fact the DC operating point of the amplifier and its
position may be established at any point along the load line by a suitable biasing arrangement.
The best possible position for this Q-point is as close to the center position of the load line as
reasonably possible, thereby producing a Class A type amplifier operation, i.e. Vce = 1/2Vcc.
Consider the Common Emitter Amplifier circuit shown below.
Common Emitter Amplifier Circuit
The single stage common emitter amplifier circuit shown above uses what is commonly
called “Voltage Divider Biasing”. This type of biasing arrangement uses two resistors as a
potential divider network across the supply with their center point supplying the required Base
bias voltage to the transistor. Voltage divider biasing is commonly used in the design of bipolar
transistor amplifier circuits.
Voltage Divider Network
This method of biasing the transistor greatly reduces the effects of varying Beta, (β) by
holding the Base bias at a constant steady voltage level allowing for best stability. The
quiescent Base voltage (Vb) is determined by the potential divider network formed by the two
resistors, R1, R2 and the power supply voltage Vcc as shown with the current flowing through
both resistors.
Then the total resistance RT will be equal to R1 + R2 giving the current as i = Vcc/RT. The voltage
level generated at the junction of resistors R1 and R2 holds the Base voltage (Vb) constant at a
value below the supply voltage.
Then the potential divider network used in the common emitter amplifier circuit
divides the input signal in proportion to the resistance. This bias reference voltage can be easily
calculated using the simple voltage divider formula below:
Beta Value:
Beta is the transistor’s forward current gain in the common emitter configuration. Beta
has no units as it is a fixed ratio of the two currents, Ic and Ib. So a small change in the Base
current will cause a large change in the Collector current. One final point about Beta is
that
transistors of the same type and part number will have large variations in their Beta value. For
example, the BC107 NPN Bipolar transistor has a DC current gain Beta value of between
110and 450 (data sheet value) this is because Beta is a characteristic of their construction and
not their operation.
As the Base/Emitter junction is forward-biased, the Emitter voltage, Ve will be one
junction voltage drop different to the Base voltage. If the voltage across the Emitter resistor is
known then the Emitter current, Ie can be easily calculated using Ohm’s Law. The Collector
current, Ic can be approximated, since it is almost the same value as the Emitter current.
 Coupling Capacitors:
In Common Emitter Amplifier circuits, capacitors C1 and C2 are used as Coupling
Capacitors to separate the AC signals from the DC biasing voltage. This ensures that the bias
condition set up for the circuit to operate correctly is not affected by any additional amplifier
stages, as the capacitors will only pass AC signals and block any DC component. The output
AC signal is then superimposed on the biasing of the following stages.
A bypass capacitor, CE is also included in the Emitter leg circuit. This capacitor is an
open circuit component for DC bias meaning that the biasing currents and voltages are not
affected by the addition of the capacitor maintaining a good Q-point stability. However, this
bypass capacitor short circuits the Emitter resistor at high frequency signals and only R L plus a
very small internal resistance acts as the transistors load increasing the voltage gain to
itsmaximum. Generally, the value of the bypass capacitor, CE is chosen to provide a reactance
of at most, 1/10th the value of RE at the lowest operating signal frequency.
 A single stage Common Emitter Amplifier is also an “Inverting Amplifier” as an
increase in Base voltage causes a decrease in Vout and a decrease in Base voltage
produces an increase in Vout. In other words, the output signal is 180 degree out-of-
phase with theinput signal.
 Common Emitter Voltage Gain:
The Voltage Gain of the common emitter amplifier is equal to the ratio of the
change in the input voltage to the change in the amplifier’s output voltage. Then ΔVL is Vout and
ΔVB is Vin. But voltage gain is also equal to the ratio of the signal resistance in the Collector to
the signal resistance in the Emitter and is given as:
As the signal frequency increases, the bypass capacitor, CE starts to short out the
Emitter resistor. Then at high frequencies RE = 0, making the gain infinite.
However, bipolar transistors have a small internal resistance built into their
Emitterregion called as Re. The transistors semiconductor material offers an internal resistance
to the flow of current through it and is generally represented by a small resistor symbol shown
inside the main transistor symbol.
Transistor data sheets tell us that for small signal bipolar transistors this internal
resistance is equal to 25mV ÷ IE (25mV being the internal volt drop across the Base/Emitter
junction depletion layer).
This internal Emitter leg resistance will be in series with the external Emitter resistor,
RE.Then the equation for the transistors actual gain will be modified to include this internal
resistance so will be:
At low frequency signals, the total resistance in the Emitter leg is equal to RE + Re. At
high frequency, the bypass capacitor shorts out the Emitter resistor leaving only the internal
resistance Re in the Emitter leg resulting in a high gain. Then for our common emitter amplifier
circuit above, the gain of the circuit at both low and high signal frequencies is given as:
At Low Frequencies:
At High Frequencies:
The voltage gain is dependent only on the values of the Collector resistor, RL and the
Emitter resistance, (RE + Re). It is not affected by the current gain Beta, β of the transistor.
Procedure:
 Connect the circuit as given in the manual.
 Give an input of 40mVp-p (f = 10 kHz) to the amplifier.
 Observe the output at Oscilloscope.
 Draw the input and output waveforms.
Voltage Gain: ……………………………..

Circuit Diagram:
Where,
C1 = 0.1 μF
C2 = 0.1 μF
CE = 22 μF
R1 = 20 kΩ
R2 = 36 kΩ
RC = 2 kΩ
RE = 1.5 kΩ
RL = 1 kΩ
Vbb = 12V
Vin = 40 mVp-p (10 kHz)
LAB TASKS:
Simulate the given circuit in Proteus.
Show all the calculations along with measured values from proteus.
AIR UNIVERSITY
EXPERIMENT NO 3
Lab Title
Objective:
LAB ASSESSMENT:

Attributes
(5) (4) (3) (2) (1)
Ability to Conduct
Experiment
results

Attributes
(5) (4) (3) (2) (1)
Data presentation
Conclusion

Date: Signature:
EXPERIMENT NO 3
BJT as Common Collector Amplifier
Objectives:
 To study the common collector amplifier configuration.
 Implementation of common collector circuit on Hardware.
Equipment:
 Oscilloscope
 Power Supply
 Transistor
 Resistors
 Capacitors
Discussion:
There are three basic configurations for implementing single stage BJT
amplifiers.
 Common Emitter
 Common Collector
 Common Base
In each case, one terminal is common to both input and output signal.
 Common Collector Configuration:

In electronics, a common-collector (also known as an emitter follower or
voltage follower) amplifier is one of three basic single-stage bipolar junction
transistor (BJT) amplifier topologies. It is typically used as a voltage buffer.
Common Collector Configuration

In this circuit, the base terminal of the transistor serves as the input, the
emitter as the output, and the collector is common to both (for example, it may be
tied to ground reference or a power supply rail), hence its name. The properties are
high input impedance, a very low output impedance, a unity (or less) voltage gain
and a high current gain.
The aim of any small signal amplifier is to amplify the entire input signal with the
minimum distortion possible to the output. In other words the output signal must be an exact
reproduction of input signal but only bigger (amplified).
To clear the concepts of common collector, read this example.
It is called the common-collector configuration because (ignoring the power supply

battery) both the signal source and the load share the collector lead as a common connection
point.
It should be apparent that the load resistor in the common-collector amplifier circuit
receives both the base and collector currents, being placed in series with the emitter. Since the
emitter lead of a transistor is the one handling the most current (the sum of base and collector
currents, since base and collector currents always mesh together to form the emitter current), it
would be reasonable to presume that this amplifier will have a very large current gain
(maximumoutput current for minimum input current). This presumption is indeed correct: the
current gain for a common-collector amplifier is quite large, larger than any other transistor
amplifier configuration.
Unlike the common-emitter amplifier, the common-collector produces an output
voltage in direct rather than inverse proportion to the rising input voltage. As the input voltage
increases, so does the output voltage. More than that, a close examination reveals that the output
voltage is nearly identical to the input voltage. This is the unique quality of the common-
collector amplifier: an output voltage that is nearly equal to the input voltage. This amplifier
has a voltage gain of almost exactly unity 1.
It is simple to unde
rstand why the output voltage of a common-collector amplifier is always nearly equal
to the input voltage. Referring back to the diode-regulating diode transistor model, we see that
the base current must go through the base-emitter PN junction, which is equivalent to a normal
rectifying diode. So long as this junction is forward-biased (the transistor conducting current
in either its active or saturated modes), it will have a voltage drop ofapproximately 0.7 volts,
assuming silicon construction. This 0.7 volt drop is largely irrespective of the actual magnitude
of base current, so we can regard it as being constant.
Given the voltage polarities across the base-emitter PN junction and the load resistor,
we see that they must add together to equal the input voltage, in accordance with
Kirchhoff'sVoltage Law. In other words, the load voltage will always be about 0.7 volts less
than the input voltage for all conditions when the transistor is conducting. Cutoff occurs
at input voltagesbelow 0.7 volts, and saturation at input voltages in excess of battery (supply)
voltage plus 0.7 volts.
Because of this behavior, the common-collector amplifier circuit is also known as the
voltage-follower or emitter-follower amplifier, in reference to the fact that the input and load
voltages follow each other so closely.
Applying the common-collector circuit to the amplification of AC signals requires the
same input "biasing" used in the common-emitter circuit: a DC voltage must be added to the
AC input signal to keep the transistor in its active mode during the entire cycle. When this is
done, the result is a non-inverting amplifier.
Here is another view of the circuit, this time with oscilloscopes connected to several
points of interest:
Since this amplifier configuration doesn't provide any voltage gain (in fact, in practice
it actually has a voltage gain of slightly less than 1), its only amplifying factor is current. The
common-emitter amplifier configuration had a current gain equal to the β of the transistor,
being that the input current went through the base and the output (load) current went through
the collector, and β by definition is the ratio between the collector and base currents. In the
common-collector configuration, though, the load is situated in series with the emitter, and thus
its current is equal to the emitter current. With the emitter carrying collector current and base
current, the load in this type of amplifier has all the current of the collector running through it
plus the input current of the base. This yields a current gain of β plus 1.
A popular application of the common-collector amplifier is for regulated
DC power supplies, where an unregulated (varying) source of DC voltage is clipped
at a specified level to supply regulated (steady) voltage to a load.
 The output voltage of a common-collector amplifier will be in phase with

the input voltage, making the common-collector a non-inverting amplifier
circuit.
 The current gain of a common-collector amplifier is equal to β plus 1. The

voltage gain isapproximately equal to 1 (in practice, just a little bit less).
Procedure:
 Circuit Diagram:
Where,
C1 = 0.1μF
C2 = 0.1μF
R1 = 10kΩ
R2 = 6.8kΩ
R3 = 1kΩ
R4 = 1kΩ
VCC = 12V
Vin = 40 mVp-p (10kHz)

 Give an input of 40 mVp-p (f = 10 kHz) to the amplifier.
LAB TASKS:
Simulate the given circuit in Proteus

Show all the calculations along with measured values
from proteus. Show frequency response by simulating at
various different frequencies.
AIR UNIVERSITY
EXPERIMENT NO 4
Lab Title
Objective:
LAB ASSESSMENT:

Attributes
(5) (4) (3) (2) (1)
Ability to Conduct
Experiment
results

Attributes
(5) (4) (3) (2) (1)
Data presentation
Conclusion

Date: Signature:
EXPERIMENT NO 4
BJT as Common Base

Amplifier
Objectives:
 To study the common base amplifier configuration.
 Implementation of common base circuit on Hardware.
Equipment:
 Oscilloscope
 Power Supply
 Transistor
 Resistors
 Capacitors
Discussion:
There are three basic configurations for implementing single stage BJT amplifiers.
 Common Emitter
 Common Collector
 Common Base
In each case, one terminal is common to both input and output signal.
 Common Base Configuration:

In electronics, a common-base (also known as grounded-base) amplifier is one of
three basic single-stage bipolar junction transistor (BJT) amplifier topologies, typically
used as a current buffer or voltage amplifier.
Common Base Configuration
In this circuit, the emitter terminal of the transistor serves as the input, the collector
as theoutput, and the base is common to both (for example, it may be tied to ground
reference or a power supply rail), hence its name. The analogous field-effect transistor
circuit is the common- gate amplifier.
Basic NPN common-base circuit
To easily understand the common base amplifier, consider the following
example.
This is common-base amplifier configuration. This configuration is more complex
thanthe other two, and is less common due to its strange operating characteristics.
It is called the common-base configuration because (DC power source aside), the
signalsource and the load share the base of the transistor as a common connection point:
Perhaps the most striking characteristic of this configuration is that the input
signalsource must carry the full emitter current of the transistor, as indicated by the heavy
arrows in thefirst illustration. As we know, the emitter current is greater than any other current
in the transistor, being the sum of base and collector currents. In the last two amplifier
configurations, the signal source was connected to the base lead of the transistor, thus handling
the least current possible.
Because the input current exceeds all other currents in the circuit, including the output
current, the current gain of this amplifier is actually less than 1. In other words, it attenuates
current rather than amplifying it. With common-emitter and common-collector amplifier
configurations, the transistor parameter most closely associated with gain was β. In the
common-base circuit, we follow another basic transistor parameter: the ratio between collector
current andemitter current, which is a fraction always less than 1. This fractional value for any
transistor is called the alpha ratio, or α ratio. It obviously can't boost signal current, it only
seems reasonable to expect it to boost signal voltage.
The input and output waveforms are in phase with each other. This tells us that the
common-base amplifier is non-inverting.
The combination of very low current gain (always less than 1) and somewhat
unpredictable voltage gain conspire against the common-base design, relegating it to the few
practical applications.
Common-base transistor amplifiers are so-called because the input and output voltage
points share the base lead of the transistor in common with each other, not considering
anypower supplies. The current gain of a common-base amplifier is always less than 1. The
voltage gain is a function of input and output resistances, and also the internal resistance of the
emitter- base junction, which is subject to change with variations in DC bias voltage. Suffice
to say that the voltage gain of a common-base amplifier can be very high. The ratio of
a transistor'scollector current to emitter current is called α. Its value for any transistor is always
less than unity, or in other words, less than 1.
This configuration is used for high frequency applications because the base separates
the input and output, minimizing oscillations at high frequency. It has a high voltage gain,
relatively low input impedance and high output impedance compared to the common collector.
Procedure:
 Give an input of 40 mVp-p (f = 50 kHz) to the amplifier.
Where,
C1 = 1μF
C2 = 1μF
R1 = 82Ω
R2 = 1kΩ
R3 = 1kΩ
R4 = 47kΩ
VCC = 12V
VEE = -5V
Vin = 40 mVp-p (50kHz)

Lab tasks:
Simulate the circuit in proteus.
Observe the frequency response by simulating at 8 different frequencies and 3 different input
voltages.
Calculate the required parameters.
AIR UNIVERSITY
EXPERIMENT NO 5
Lab Title
Objective:
LAB ASSESSMENT:

Attributes
(5) (4) (3) (2) (1)
Ability to Conduct
Experiment
results

Attributes
(5) (4) (3) (2) (1)
Data presentation
Conclusion

Date: Signature:
EXPERIMENT NO 5
BJT Current Mirror
Objectives:
 To build and investigate the functionality of BJT current mirror.
Equipment:
 Power Supply
 Transistor
 Resistors
Discussion:
A current mirror is a circuit designed to copy a current through one active device
by controlling the current in another active device of a circuit, keeping the output current
constant regardless of loading. The current being 'copied' can be, and sometimes is, a
varying signal current. Conceptually, an ideal current mirror is simply an ideal current
amplifier. The current mirror is used to provide bias currents and active loads to circuits.
Biasing in integrated circuit design is based on the use of constant current sources.
On an IC chip with a number of amplifier stages a constant DC current (called a reference
current) is generated at one location and is then replicated at various other locations for
biasing the various amplifier stages through a process known as current steering. This
approach has the advantage that the effort expended on generating a predictable and stable
reference current usually utilizing a precision resistor external to the chip need not be
repeated for every amplifier stage furthermore the bias currents of the various stages track
each other in case of changes in power- supplies voltage or in temperature.
 Basic BJT Current Mirror:

In BJTs:
(1) The non-zero base current of BJT (or, equivalently, the finite β) causes an error
in the current transfer ratio of the bipolar ratio.
(2) The current transfer ratio is determined by the relative areas of emitter- base
junction of Q1 and Q2.
Let us first consider the case when β is sufficiently high so that we can neglect the
base currents. The reference current IREF is passed through the diode connected transistor
Q1 and thus establishes a corresponding voltage VBE, which in turn is applied between base
and emitter of Q2.
Now if Q2 is matched to Q1 or more specifically, if the EBJ area of Q2 is the
same asthat of Q1 and thus Q2 has the same scale current Is as Q1, then the collector
current of Q2 will be equal to that of Q1. That is:
Io = IREF
For this to happen, however, Q2 must be operating in the active mode, which in
turn isachieved so long as the collector voltage Vo is 0.3 V or so higher than that of the
emitter.
To obtain a current transfer ratio other than unity, say m, we simply arrange that the
areaof the EBJ of Q2 is m times that of Q1. In this case,
Io = mIREF
Basic BJT current

mirror
In general, the current transfer ratio is given by:
Alternatively, if the area ratio m is an integer, one can think of Q2 as equivalent to m

transistors, each matched to Q1 and connected in parallel.
Next we consider the effect of finite transistor β on the current transfer ratio. The key
point here is that since Q1 and Q2 are matched and have the same VBE, their collective currents
will be equal. The rest of the analysis is straight forward. A node equation at the collector of
Q1 yields:
Finally, since Io = Ic, the current transfer ratio can be found as:
Note that as β approaches infinity, Io/IREF approaches the nominal value of unity. For
typical value of β, however, the error in the current transfer ratio can be significant. For
instance,β = 100 results in a two percent error in the current ratio. Furthermore, the error due
to the finiteβ increases as the nominal current transfer ratio is increased.
The BJT mirror has a finite output resistance Ro:
 LM394 Supermatch Pair:

The LM194 and LM394 are junction isolated ultra-well matched monolithic NPN
transistor pairs with an order of magnitude improvement in matching over conventional
transistor pairs. The pin diagram of metal can package is shown in figure below.
Figure 1Pin Diagram of LM394

Procedure:
(i) Make the connections on the bread board as shown in figure.
(ii) Apply VCC = 12 V
(iii) Use the supermatched pair LM394.
(iv) Now with the help of DMM, measure the output current and output voltage.
(v) Fill in the required values.
Where:
VCC =
12V
RREF =
1kΩ RL
= 1kΩ
IREF = ………………...…………..
Io = ……………………………….
VCE = …………………………….
VRL = …………………………….
Lab tasks:
simulate the circuit in proteus.
Observe the mirrored current for 5 different values of reference current.
Calculate/measure the required parameters.

AIR UNIVERSITY
EXPERIMENT NO 6
Lab Title
Objective:
LAB ASSESSMENT:

Attributes
(5) (4) (3) (2) (1)
Ability to Conduct
Experiment
results

Attributes
(5) (4) (3) (2) (1)
Data presentation
Conclusion

Date: Signature:
EXPERIMENT NO 6
Widlar Current Source
Objectives:
 To build and investigate the functionality of Widlar Current Source.
Equipment:
 Power Supply
 Transistor
 Resistors
Discussion:
The two-transistor current source, also called as current mirror, is the basic building
block in the IC current source circuits.
Basic current source circuit consists of two identical transistors, operating at the same
temperature, with base and emitter terminals connected together. B-E voltage is therefore the
same for both transistors. One of the transistors (QREF) is connected as a diode. When a voltage
is applied, the B-E junction of QREF is forward biased and a reference current IREF is established.
Because the B-E voltage is the same for both the transistors a load current Io is established in
the load transistor (QO).
When the desired current (Io) is small, the Widlar current source may be a better
alternative. For instance if the required output bias current Io = 10𝜇A, then, for V+ = 5V and V-
=
-5V the required resistance value for RREF is about 930 k𝛺. In IC, resistors on the order of 1M𝛺
require large areas and are difficult to fabricate accurately. Therefore we need to replace that
resistance with one into k𝛺 range. The Widlar current source meets that objective. A voltage
difference is produced across resistor RE, so that B-E voltage of Q2 is less then B-E voltage of
Q1.A smaller B-E voltage produce a smaller collector current, which means the load current
Iois less than the reference current IREF.
The Widlar Current Source is shown in Figure:
The Widlar Current Source

For Widlar current source, the following holds:
 LM394 Supermatch Pair:

Pin diagram of LM394
Procedure:
(iv) Now with the help of DMM, measure the output current and output voltage.
Where:
VCC = 12V
RREF = 1kΩ
RO = 1kΩ
RE = 10kΩ
IREF = ………………...…………..
Io = ……………………………….
VRO = …………………………….
VRE = …………………………….
Lab tasks:
simulate the circuit in proteus.
Measure and calculate the required parameters.

AIR UNIVERSITY
EXPERIMENT NO 7
Lab Title
Objective:
LAB ASSESSMENT:

Attributes
(5) (4) (3) (2) (1)
Ability to Conduct
Experiment
results

Attributes
(5) (4) (3) (2) (1)
Data presentation
Conclusion

Date: Signature:
EXPERIMENT NO 7
Wilson Current Mirror
Objectives:
 To build and investigate the functionality of Wilson Current Mirror.
Equipment:
 Power Supply
 Transistor (2N2222)
 Resistors
Discussion:
A Wilson current mirror is a three-terminal circuit that accepts an input current at the
input terminal and provides a "mirrored" current source or sink output at the output terminal.
Themirrored current is a precise copy of the input current. It may be used as a Wilson
currentsource by applying a constant bias current to the input branch. The circuit is named
after George
R. Wilson, an integrated circuit design engineer who worked for Tektronix. Wilson devised
this configuration in 1967 when he and Barrie Gilbert challenged each other to find an
improved current mirror overnight that would use only three transistors. Wilson won the
challenge.
 Circuit Operation:
There are two principal metrics of how well a current mirror will perform as part of a
larger circuit. The first measure is the static error, the difference between the input and output
currents expressed as a fraction of the input current. Minimizing this difference is critical in
suchapplications of a current mirror as the differential to single-ended output signal conversion
in a differential amplifier stage because this difference controls the common mode and power
supply rejection ratios. The second measure is the output impedance of the current source or
equivalently its inverse, the output conductance. This impedance affects stage gain when a
current source is used as an active load and affects common mode gain when the source
providesthe tail current of a differential pair.
At first glance, the current mirror circuit shown in the figure would seem to be
backwards. In fact, however, it works quite well, although in a round-about fashion. A small
amount of the current flowing through R provides base current for Q3, enabling Q3 to conduct
current. The bulk of this current, as with any transistor, flows from emitter to collector.
Ofcourse, IC3 = IO.
At the same time, IE3 becomes the reference current for the current mirror formed by
Q1 and Q2. As we have already seen when studying the basic current mirror, IC1 = IC2,
and IE3 = IC2 + 2IB.
Wilson
Current
Mirror
This arrangement provides a form of negative feedback loop. If for any reason IO begins to
increase, IC2 must likewise increase, and IC1 will mirror that increase. This will increase the
voltage drop across R, which will in turn reduce the base voltage on Q3. That will reduce IO
again. In reality, IO cannot change that way, and the circuit does indeed operate as a current
mirror.
Before we can calculate the currents flowing through different parts of this circuit, we must
know the voltages. Fortunately, that's very easy in this case. The emitters of Q1 and Q2 are
grounded, and their bases are connected to each other as well as to the collector of Q2 and the
emitter of Q3. Therefore this common point is at a fixed voltage of VBE. In addition, the base
of Q3, which is connected to the collector of Q1, must be VBE above its emitter, which puts
its voltage at 2VBE. The collector of Q3, which provides IO, can float to any voltage
between +V and [VBE + VCE(SAT)].
Now that we know all of the fixed circuit voltages, we can determine the basic circuit
currents within the mirror circuit.
From the above, it looks as if everything can be expressed in terms of IC2, which is central
to the mirror circuit. We can use this fact to derive the relationship between IO and IREF entirely
based on β, assuming all transistors have the same parameters. The final expression becomes:
That slight difference of is generally negligible with modern high-gain transistors. This
expression shows that by splitting the base current between the two sides, the Wilson currentβ
of 100, the error is less than 0.02%.
 Output Resistance:
The use of two transistors in the output side of the Wilson current mirror affects
the output resistance of the circuit, much as an emitter resistor does. The advantage of
using Q2 in place of a resistor is that the voltage across Q2 will only be VBE regardless of
the magnitude of IO, where an emitter resistor will generally drop a higher voltage in
accordance with Ohm's Law.
Of course, the fact that Q2 is connected as a diode limits its effective resistance in this
application. Nevertheless, it does help to significantly increase the effective output resistance
of Q3. For the Wilson current mirror:
LM394 Super match Pair:

ROUT ≈ βrO/2
Pin diagram of
LM394
Procedure:
(iv) Now with the help of DMM, measure the required values of current and voltage.
 Circuit Diagram:
Where:
VCC = 12V
R = 1kΩ
RC = 1kΩ
IREF = ………………...…………..
Io = ……………………………….
IC2 = ……………………………...
VR = ……………………………...
VRC = …………………………….
VCE2 = ……………………………
VCE3 = ……………………………
AIR UNIVERSITY
EXPERIMENT NO 8
Lab Title
Objective:
LAB ASSESSMENT:

Attributes
(5) (4) (3) (2) (1)
Ability to Conduct
Experiment
results

Attributes
(5) (4) (3) (2) (1)
Data presentation
Conclusion

Date: Signature:
EXPERIMENT NO 8
Frequency Response of Common Emitter

Amplifier
Objectives:
 To study the frequency response of Common Emitter Amplifier.
 Implementation of common emitter circuit on Hardware.
Equipment:
 Oscilloscope
 Transistor (BC107)
 Resistors
 Capacitors
Discussion:
The common emitter configuration is widely used as a basic amplifier as it has both
voltage and current amplification. Resistors R1 and R2 form a voltage divider across the base
of the transistor. In order to operate transistor as an amplifier, biasing is done in such a way
that the operating point is in the active region.
The emitter resistor RE is required to obtain the DC quiescent point stability. However
theinclusion of RE in the circuit causes a decrease in amplification at higher frequencies. In
order to avoid such a condition, it is bypassed by a capacitor so that it acts as a short circuit for
AC and contributes stability for DC quiescent condition. Hence, capacitor is connected in
parallel with emitter resistance.
An amplifier amplifies the given AC signal. In order to have noiseless transmission of
a signal (without DC), it is necessary to block DC i.e. the direct current should not enter the
amplifier or load. This is usually accomplished by inserting a coupling capacitor.
 Characteristics of Common Emitter Amplifier:

 Large current gain.
 Large voltage gain.
 Large power gain.
 Current and voltage phase shift of 1800.
 Moderated output resistance.
 Frequency response:
The voltage gain of a CE amplifier varies with signal frequency. It is because the reactance of
thecapacitors in the circuit changes with signal frequency and hence affects the output
voltage.
Frequency Response Curve:

The curve drawn between voltage gain and the signal frequency of an amplifier is
known asfrequency response. The below figure shows the frequency response of a typical CE
amplifier.
From the above graph, we observe that the voltage gain drops off at low (< FL) and high (>
FH) frequencies, whereas it is constant over the mid-frequency range (FL to FH). The
frequency at which the gain drops to 70 % of its maximum value is known as the Cutoff
Frequency. FL is known as the Lower Cutoff Frequency and FH is called Higher Cutoff
Frequency. The most common tool used to represent the frequency response of any system is
the Bode plot.
At Low Frequencies (< FL):

The coupling and bypass capacitors cause the fall of the signal in the low frequency response
of the amplifier because their impedance becomes large at low frequencies. The stray
capacitances (an unavoidable and usually unwanted capacitance that exists between the parts
of an electronic component or circuit simply because of their proximity to each other) are
effectively open circuits.
The reactance of coupling capacitor C2 is relatively high and hence very small part of the signal
will pass from the amplifier stage to the load.
Moreover, CE cannot shunt the RE effectively because of its large reactance at low frequencies.
These two factors cause a drop off of voltage gain at low frequencies.
At High Frequencies (> FH):
Emitter bypass capacitors are used to short circuit the emitter resistor and thus increases the
gain at high frequency. At the high frequencies, the bypass and coupling capacitors are replaced
by short circuits. The stray capacitors and the transistor determine the response.
The capacitive reactance of base-emitters junction is low which increases the base current. This
frequency reduces the current amplification factor β. Due to this reason, the voltage gain drops
off at a high frequency.
At Mid Frequencies (FL to FH):

In the mid frequency range large capacitors are effectively short circuits and the stray
capacitors are open circuits, so that no capacitance appears in the mid frequency range. Hence
the mid bandfrequency gain is maximum.
The voltage gain of the amplifier is constant. The effect of the coupling capacitor C2 in this
frequency range is such as to maintain a constant voltage gain.
In the usual application, mid band frequency range is defined as those frequencies at which
theresponse has fallen to 3dB below the maximum gain (|A| max). These are shown as f L and
fH and are called as the 3dB frequencies (Lower and Upper Cut-Off Frequencies respectively).
Frequency points like ƒL & ƒH are related to the lower corner & the upper corner of the
amplifier which are the gain falls of the circuits at high as well as low frequencies. These
frequency points are also known as decibel points. The difference between higher cut-off and
lower cut-off frequency is referred to as Bandwidth. So the BW can be defined as:
BW = fH – fL
The dB (decibel) is 1/10th of a B (bel), is a familiar non-linear unit to measure gain & is defined
like 20log10(A). Here ‘A’ is the decimal gain which is plotted over the y-axis.
We can notice from the above graph, the output at the two cut-off frequency points will
decrease from 0dB to -3dB & continues to drop at a fixed rate. These -3dB cut-off frequency
points will describe the frequency where the o/p gain can be decreased to 70 % of its utmost
value. After that, we can properly say that the frequency point is also the frequency at which
the gain of the system has reduced to 0.7 of its utmost value.
Frequency Response -3dB Point:

The -3dB point is also known as the half-power points since the output power at this
cornerfrequencies will be half that of its maximum 0dB.
Therefore, the amount of output power delivered to the load is effectively “halved” at the cut-
off
frequency and as such the bandwidth (BW) of the frequency response curve can also be defined
as the range of frequencies between these two half-power points. For voltage gain we
use 20log10(Av), and for current gain 20log10(Ai) for calculating the gain in dB.
Procedure:
 Connect the circuit as shown in the circuit diagram.
 Set source voltage VS = 50mVp-p at 1 KHz frequency using the
functiongenerator. Observe the phase difference between input and output.
 Keeping input voltage constant, vary the frequency from 50 Hz to 1 MHz in regular
stepsand note down the corresponding output voltage. Calculate gain in dB.
 Plot the graph: gain (dB) verses Frequency.
Circuit Diagram:
Where,
CB = 10
μF
CC = 10
μF
CE = 100
μF
R1 = 100
kΩ
R2 = 10
kΩ
RC = 2.2
kΩ
RE = 1
kΩ
RL = 1
kΩ
VCC =
12V
VS = 50 mVp-p (1 kHz)
Results:
Frequency (Hz) Vo(Volts) Gain = Vo/Vs Gain(dB) = 20 log(Vo/Vs)
50
100
200
500
1k
2k
5k
10k
20k
50k
100k
200k
500k
1M
Graph (Frequency vs Gain(dB)):

AIR UNIVERSITY
EXPERIMENT NO 9
Lab Title
Objective:
LAB ASSESSMENT:

Attributes
(5) (4) (3) (2) (1)
Ability to Conduct
Experiment
results

Attributes
(5) (4) (3) (2) (1)
Data presentation
Conclusion

Date: Signature:
EXPERIMENT NO 9
Frequency Response of Common Source

Amplifier
Objectives:
 To study the frequency response of Common Source Amplifier.
 Implementation of common source circuit on Hardware.
Equipment:
 Oscilloscope
 MOSFET (BS170)
 Resistors
 Capacitors
Discussion:
When the input signal is applied at the gate terminal, then the output voltage is
amplified and obtained across the resistor at the load in the drain terminal. This is called a
common source amplifier. Here source acts as a common terminal between the input and
output. It is also known as a voltage amplifier. It produces current gain and voltage gain
according to the input impedance and output Impedance. To produce voltage gain along with
high input impedances FET’s are used in these circuits.
JFET to BJT Comparison:
JFET BJT
Gate, ( G ) Base, ( B )
Drain, ( D ) Collector, ( C )
Source, ( S ) Emitter, ( E )
Gate Supply, ( VG ) Base Supply, ( VB )
Drain Supply, ( VDD ) Collector Supply, ( VCC )
Drain Current, ( ID ) Collector Current, ( IC )
The circuit diagram of the common source amplifier with N-channel FET along with the
coupling and biasing capacitors is shown below. This circuit will be similar to the common-
emitter amplifier of Bipolar Junction transistor.
Common Source Amplifier Circuit
Its working is similar to the working of a common-emitter amplifier of the BJT circuit. The
inputsignal is applied at the gate terminal through the capacitor C1. The use of this capacitor is
to check whether the gate terminal is affected by any DC voltage of the previous stage. The
bypass capacitor C2 provides the additional gain for the AC signal. The amplified output
voltage is obtained across the resistor R3 at the load at the drain terminal of the circuit. This
amplified output voltage is coupled to the AC signal of the next stage by the capacitor C3 by
blocking or eliminating the DC components. The amplified output signal of this amplifier is
180 degrees out of phase with respect to the input signal and produces high power gain. If the
biasing arrangement is improper, then some form of distortion may appear in the amplified
output signal.
 Characteristics of Common Source Amplifier:

 Medium input Impedance
 Medium output impedance
 Medium current gain
 Medium voltage gain
 Reverse output with respect to input
 Frequency response:
Frequency Response of an amplifier shows how the gain of the output responds to input
signals at different frequencies. Generally, the frequency response analysis of a circuit or
system is shown by plotting its gain, that is the size of its output signal to its
inputsignal, Output/Input against a frequency scale over which the circuit or system is expected
to operate. Then by knowing the circuits gain, (or loss) at each frequency point helps us to
understand how well (or badly) the circuit can distinguish between signals of different
frequencies. The frequency response of common source amplifier is the most important
factor.
The capacitors and the type of FET used in the operation may affect the frequency
response ofthe amplifier.
Let us divide frequency response into three different regions:
 Low frequency region
 Mid frequency region
 High frequency region
Low frequency region:
The voltage gain of the amplifier decreases at low frequency. The decrease in gain is due to
connected capacitance i.e. Cg, Cc, and Cs.
Mid frequency region:
At mid frequency, connected capacitor Cg, Cc, Cs act as short circuit and stray capacitors act
as open circuit. Hence, gain of the amplifier is maximum and constant in this region. Therefore,
increasing the input voltage, output voltage also increases.
High frequency region:
At high frequency, voltage gain decreases due to stray capacitors.
Frequency Response Curve:

Graphical representation of frequency response curve is called Bode Plot. The frequency
response of any given circuit is the variation in its behaviour with changes in the input signal
frequency as it shows the band of frequencies over which the output (and the gain) remains
fairlyconstant. The range of frequencies either big or small between ƒ L and ƒH is called the
circuit’s bandwidth.
Frequency points ƒL and ƒH relate to the lower corner or cut-off frequency and the upper corner
or cut-off frequency points respectively are known commonly as the -3dB (decibel) points. We
see from the Bode plot above that at the two corner or cut-off frequency points, the output
drops from 0dB to -3dB and continues to fall at a fixed rate.
These -3dB corner frequency points define the frequency at which the output gain is reduced
to 70.71% of its maximum value. Then we can correctly say that the -3dB point is also the
frequency at which the systems gain has reduced to 0.707 of its maximum value.
Procedure:
 Connect the circuit as shown in the diagram.
 Apply the bias voltage VDD.
 Apply an input sine wave signal of 20mVp, 1 kHz from the function generator.
 Observe the output on Oscilloscope. Calculate the corresponding gain.
 Vary the frequency of the input signal from 10Hz to 100MHz and find the output
signalgain for different frequencies.
 Plot the Frequency VS Gain (dB) graph.
Circuit Diagram:
Where,
Cc1 = 0.22μF
Cc2 = 22 μF
CE = 100 μF
R1 = 285 kΩ
R2 = 110 kΩ
RD = 1 kΩ
RS = 220 Ω
RL = 1 kΩ
VDD= 12V
VS = 20 mVp (1 kHz)
Results:
Frequency (Hz) Vo(Volts) Gain = Vo/Vs Gain(dB) = 20 log(Vo/Vs)
10
50
100
200
500
1k
2k
5k
10k
20k
50k
100k
200k
500k
1M
10M
20M
30M
40M
50M
60M
70M
80M
90M
100M
Graph 1: Input Waveform
Graph 2: Output Waveform

AIR UNIVERSITY
EXPERIMENT NO 10
Lab Title
Objective:
LAB ASSESSMENT:

Attributes
(5) (4) (3) (2) (1)
Ability to Conduct
Experiment
results

Attributes
(5) (4) (3) (2) (1)
Data presentation
Conclusion

Date: Signature:
EXPERIMENT NO 10
BJT Differential
Amplifier
Objectives:
 To investigate the functionality of BJT differential amplifier.
Equipment:
 Power Supply
 Oscilloscope
 Transistors
 Resistors
Discussion:
An electronic circuit that is designed to amplify the difference between two voltages
measured with respect to a common reference, usually designated as ground. By convention,
the net difference of two voltages measured with respect to a common reference is
called thedifferential-mode voltage, while the sum of the voltages, usually divided by two to
give an average value, is called the common-mode voltage.
An ideal differential amplifier thus has exactly the same gain from each input to its
output, and the amplifier produces an output that is directly proportional to its differential-
mode voltage. The amplifier delivers zero output in response to common-mode voltages. If
these gains are not exactly equal, then equal (common-mode) voltages applied at each input
terminal will notbe equal at the amplifier output and their difference will not cancel completely.
The common- mode gain, the ratio of the output response of a real differential amplifier to the
input signal applied equally to each input terminal, is a measure of this gain mismatch.
Differential amplification is very useful when the signal to be amplified exists in an
electrically noisy environment, since the noise voltage is usually a common component of both
input voltages and, hence, will cancel when the difference of the amplifier inputs is taken.
For a physical differential amplifier to work properly, the electrical paths of each input
signal through the amplifier must be nearly identical. Thus, the most important requirement for
a differential amplifier is that it be constructed with transistors with closely matched electrical
characteristics. Integrated circuits with amplifier transistors physically close to each other meet
the required close matching requirement and are ideally suited for the production of differential
amplifiers.
Differential-amplifier circuits that are suitable for integrated-circuit fabrication can use
either metal oxide semiconductor field-effect transistors (MOSFETs) or bipolar junction
transistors (BJTs). The input transistor pair must be matched closely. For best performance, the
two load transistors also should be matched.
Figure 1 shows the basic BJT differential pair configuration. It consists of two matched
transistors Q1 and Q2, whose emitters are joined and biased by a constant current source I.
 How Differential Pair Works:

Now how the differential pair works, consider first the case where the two bases are
joined together and connected to a voltage vCM called a common mode voltage. This is shown
in figure 1(a) vB1 = vB2 = vCM. Since Q1 and Q2 are matched, it follows from symmetry that the
current I will divide equally between the two devices. Thus iE1 = iE2 = I/2, and the voltage at the
emitters will be vCM - VBE, where VBE is the emitter base voltage correspondingly to an emitter
current of I/2. The voltage at each collector will be VCC – (1/2)αIRC. And the difference between
the two collectors will be zero.
Now let us vary the value of the common mode input signal vCM . Obviously, as long
asQ1 and Q2 remain in the active region, the current I will still divide equally between Q1 and
Q2, and the voltage at the collectors will not change. Thus the differential pair does not respond
to common mode input signals.
Now let voltage VB2 be set to a constant value say zero and let VB1= +1V. With a bit of
reasoning it can be seen that Q1 will be on and conducting all of current I and Q2 will be off. For
Q1 to be on, the emitter has to be at +0.3V, which keeps the EBJ of Q2 reverse biased. The
collector voltages will be:
VC1 = VCC -
IC1RC1VC2 =
VCC
Let us now change VB1 = -1V. Again with some reasoning it can be seen that Q1 will turn
off and Q2 will carry all the current I. the common emitter will be at -0.7 V, which means that
EBJ of Q1 will be reversed biased 0.3 V. The collector voltages will be:
VC1= VCC
VC2 = VCC - IC2RC2
From the above, we can see that the differential pair certainly responds to difference
–mode or differential signal. In fact with relatively small difference voltages we are able to
steer
the entire biased current from one side of the pair to the other. This current steering property
of differential pair allows it to be used in logic circuits.
Now apply the sinusoidal signal to one of the base terminals and ground the
other terminal. Sinusoidal signal is of 80 mVP-P and 1 kHz. And find out the output at the
collector end.You will see that the side at which you applied the ac signal, at that end you have
got the out of phase output with respect to input and other terminal has got the output which is
in phase to the input. And both the outputs are out of phase with each other.
Figure 1
 Voltage Gain:
We have established that for small difference input voltages, the collector currents are
given by:
iC1 = IC +
gmvd/2iC2 =
IC - gmvd/2
Where Ic = αI/2
Thus the total voltages at the collectors will be:
vC1 = (VCC - ICRC) –
gmRCvd/2vC2 = (VCC -
ICRC) – gmRCvd/2
The quantities in parenthesis are simply the dc voltages at each of the two collectors.
The output voltage signal of a differential amplifier can be taken either differentially
(thatis, between the two collectors) or single-ended (that is, between one collector and ground).
If the output is taken differentially, then the differential gain (as opposed to the common-mode
gain) ofthe differential amplifier will be:
Ad =( vC1 – vC2 )/vd = -

gmRC
On the other hand, if we take the single-ended output (say, between the collector of Q1 and
ground), then the common mode gain will be given by:
ACM = vC1/vd = -1/2gmRC
Procedure:
(i) Connect the circuit as shown in figure below.
(ii) Apply Vin = 80mVP-P (f = 1kHz)
(iii) Now with the help of DMM, measure the output current and output voltage.
(iv) Fill in the required values.
Vout = …………………………….
IE1 = ………………...…………….
IE2 = ……………………………....
I = ………………………………......
AIR UNIVERSITY
EXPERIMENT NO 11
Lab Title
Objective:
LAB ASSESSMENT:

Attributes
(5) (4) (3) (2) (1)
Ability to Conduct
Experiment
results

Attributes
(5) (4) (3) (2) (1)
Data presentation
Conclusion

Date: Signature:
EXPERIMENT NO 11
Multistage Amplifier
Objectives:
 To investigate the functionality of multistage amplifier.
Equipment:
 Power Supply
 Oscilloscope
 Transistors (2N2222)
 Resistors
 Capacitors
Discussion:
There is a limit to how much gain can be achieved from a single stage amplifier. Single
stage amplifiers also have limits on input and output impedance. Multistage amplifiers are
usedto achieve higher gain and to provide better control of input and output impedances.
Two significant advantages that multistage amplifiers have over single stage amplifiers are
flexibility in input and output impedance and much higher gain.
Multistage amplifiers can be divided into two general classes, open-loop and negative
Feedback. Open-loop amplifiers are easy to understand and design but are sensitive to
environment and component variations. Negative feedback amplifiers are a bit more difficult
to understand but have the advantage of being much less sensitive to environment and
component variations. A good closed-loop amplifier begins with a good open-loop design.
For many amplifier applications it is desirable for the input impedance to be very high.
Thus, it is common for the first amplifier stage to be a common-collector, bipolar junction
transistor stage or a common-drain or even common-source field effect transistor stage.
Sometimes high input impedance is not important and the first stage may be a common-emitter.
Field effect transistors are normally used only for the input stage and for the specific application
of very high input impedance.
It is also common situation that it is desirable for the output impedance of an amplifier
to be low. A common-collector circuit is typically used. But in some cases there is no need for
very low output impedance and the last stage may be a common-emitter. For the amplifier
stages in- between it is common to employ common-emitter circuits because those can achieve
highvoltage gain.
Analysis of multistage amplifiers is performed stage at a time starting with the input
stageand progressing to the output stage. The analysis methods are identical to that of single
stage amplifiers. One point of confusion for students analyzing direct coupled amplifiers is that
the collector resistor for one stage becomes the base resistor for the next stage. In stages
involving
common-collector amplifiers some modified approaches, including some simplifying
approximations, are necessary because characteristics of common collector stages are
dependent on external impedances. An advantage of closed loop amplifiers is that
approximation errors are greatly reduced.
The design of multistage amplifiers begins at the output and progresses backwards to
the input. Initially the number of stages is not known. The design progresses with additional
stages until the requirements are met. It is common for there to be a lot of iteration in the design
and thenumber of stages might vary with each iteration.
 Multistage Amplifier:
The performance obtainable from a single stage amplifier is often insufficient for many
applications; hence several stages may be combined forming a multistage amplifier. These
stagesare connected in cascade, i.e. output of the first stage is connected to form input of second
stage, whose output becomes input of third stage, and so on.
 Overall gain:
The overall gain of a multistage amplifier is the product of the gains of the individual
stages (ignoring potential loading effects):
Gain (A) = A1 A2 A3 A4 ...

An
Alternately, if the gain of each amplifier stage is expressed in decibels (dB), the total
gainis the sum of the gains of the individual stages:
Gain in dB (A) = A1 + A2 + A3 + A4 + ... An

The following table is a summary of some different multistage amplifiers constructions
and their characteristics.
Procedure:
(ii) Apply Vin = 80mVP-P (f = 10kHz) and VCC = 12V
(iii) Now with the help of DMM, measure the output current and output voltage.
(iv) Observe the output on oscilloscope.
(vi) Draw the input and output waveforms.
Vout = ……………………………..
Iout = ………………...……………
AIR UNIVERSITY
EXPERIMENT NO 12
Lab Title
Objective:
LAB ASSESSMENT:

Attributes
(5) (4) (3) (2) (1)
Ability to Conduct
Experiment
results

Attributes
(5) (4) (3) (2) (1)
Data presentation
Conclusion

Date: Signature:
EXPERIMENT NO 12
Class A Output Stage
Objectives:
 To understand how a Class A amplifier works and analyze its output.
Equipment:
 Power Supply
 Oscilloscope
 Transistors
 Resistors
Discussion:
 Amplifier:
The term amplifier means either a circuit (or stage) using a single active device or a
complete system such as a packaged audio hi-fi amplifier.
An electronic amplifier is a device for increasing the power and/or amplitude of a
signal. It does this by taking energy from a power supply and controlling the output to match
the input signal shape but with larger amplitude. In this sense, an amplifier may be considered
as modulating the output of the power supply.
An important function of the output stage is to provide the amplifier with a low output
stage resistance so that it can deliver the output signal to the load without loss of gain. Since
the output stage is the final stage of the amplifier, it usually deals with the relatively large
signals. Thus the small signal approximations and models are not applicable or must be used
with care. Measure of goodness of design of the output stage is the total harmonic distortion it
introduces. This is the RMS value of the harmonic components of the output signal.
Power amplifier is simply an amplifier with a high power output stage. The most
challenging requirement in the design of the output stage is that it delivers the required
amountof power to the load in an efficient manner. This implies that the power dissipated in
the output stage transistors must be as low as possible.
 Classification of Output Stages:
Power amplifier circuits (output stages) are classified as A, B, AB and C for analog
designs, and class D and E for switching designs based upon the conduction angle or 'angle of
flow' 𝜃 of the input signal through the amplifying device, that is, the portion of the input signal
cycle during which the amplifying device conducts. The image of the conduction angle
isderived from amplifying a sinusoidal signal. (If the device is always on, 𝜃 = 360°.) The angle
of flow is closely related to the amplifier power efficiency.
Output stages for transistors are classified according to the collector current waveform
that results when input is applied.
(i) Class A Output Stage

(ii) Class B Output Stage
(iii) Class AB Output Stage
 Class A Amplifier:
Class A stage, whose waveform is shown in the figure below, is biased at a current Ic
greater than the amplitude of signal current. Thus transistor in class A stage conducts for the
entire cycle i.e. 360 degrees. Class A amplifying devices operate over the whole of the input
cycle such that the output signal is an exact scaled-up replica of the input with no clipping.
Class A amplifiers are the usual means of implementing small-signal amplifiers. They are not
very efficient; a theoretical maximum of 50% is obtainable with inductive output coupling and
only 25% with capacitive coupling.
In a Class A circuit, the amplifying element is biased so the device is always conducting
to some extent, and is operated over the most linear portion of its characteristic curve (known
as its transfer characteristic or transconductance (curve). Because the device is always
conducting, even if there is no input at all, power is drawn from the power supply. This is the
chief reason forits inefficiency.
The formula for calculating efficiency is:
ή = ¼ (Vo/IRL)
(Vo/VCC)
The maximum efficiency attainable is 25%. Because this is a rather low figure, the
classA output stage is rarely used in large power applications. Thus the efficiency achieved is
usually in the 10% to 20% range.
Procedure:
(ii) Apply Vin = 80mVp-p (f = 1kHz)
(iii) Now with the help of DMM, measure the output current and Vo.
Vout = ……………………………
Iin = ………………...……………
Io = ………………………………
AIR UNIVERSITY
EXPERIMENT NO 13
Lab Title
Objective:
LAB ASSESSMENT:

Attributes
(5) (4) (3) (2) (1)
Ability to Conduct
Experiment
results

Attributes
(5) (4) (3) (2) (1)
Data presentation
Conclusion

Date: Signature:
EXPERIMENT NO 13
Class B Output Stage
Objectives:
 To understand how a Class B amplifier works and analyze its output.
Equipment:
 Power Supply
 Oscilloscope
 Transistors (NPN 2N3904, PNP 2N3906)
 Resistors
Discussion:
Class B output stage is shown in the figure. It consists of a complementary pair of
transistors (that is, and npn and pnp) connected in such a way that both cannot conduct
simultaneously.
 Circuit operation:
When the input voltage VI is zero, both transistors are in cut off and the output voltage
VOis zero. As VI goes positive and exceeds about 0.5V, QN conducts and operates as
emitter
follower. In this case VO follows VI (that is VO = VI – VBEN) and QN supplies the load current. The
emitter base junction of QP will be reversed biased by the VBE of QN, which is app 0.7V. Thus
QP will be off. If the input goes negative by more than about 0.5V, QP turns on and acts as
emitter follower. Again VO follows VI (that is VO = VI + VEBP) but in this case QP supplies the load
currentand QN will be off.
We conclude that the transistors in the class B stage of figure are biased at zero current
and conduct only when the input signal is present. The circuit operates in a pushed –
pullfashion: QN pushes sources current into the load when VI is positive and QP pulls (sinks)
current from the load when VI is negative.
 Transfer characteristics:
A sketch of transfer characteristic of the class B is shown in the figure. Note that there
exists a range of VI where both transistors are cutoff and VO is zero. This band results in the
crossover distortion for the case of an input sine wave. The effect of cross over distortion will
be pronounced when the amplitude of the input signal is small. Cross over distortion in audio
amplifiers gives rise to unpleasant sounds.
Transfer Characteristics of Class B Output

Stage
The efficiency will be given by:

ή = π/4
(Vo/VCC)
It follows that the maximum efficiency is obtained when Vo is at its maximum. This
maximum is limited by the saturation of QN and QP to VCC - VCESAT = VCC. At this value of peak
output voltage, the power conversion efficiency is 78.5%. This value is much larger than
theclass A stage (25%).
Procedure:
(ii) Apply Vin = 5VP (f = 10kHz)
(iii) Now with the help of DMM, measure the output current and Vo.
Vout = ……………………………
Iin = ………………...……………
Io = ………………………………

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LAB MANUAL

COURSE TITLE: _________________________________

DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING

Lab # Lab Experiments

1 Characteristics of BJT and MOSFET

2 BJT as Common Emitter Amplifier

3 BJT as Common Collector Amplifier

4 BJT as Common Base Amplifier

5 BJT Current Mirror

6 Widlar Current Source

7 Wilson Current Mirror

8 Frequency Response of Common Emitter Amplifier

9 Frequency Response of Common Source Amplifier

10 BJT Differential Amplifier

12 Class A Output Stage

13 Class B Output Stage

14 Open Ended Lab

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Characteristics of Bipolar Junction Transistor (BJT)

Bipolar Junction Transistor (BJT):

The three terminals of a transistor are following:

PNP transistors consist of a layer of N-doped semiconductor between two layers of P-

 Basic Structure and Principle of Operation:

 Modes of Operation and Voltage Transfer Characteristic Curve:

(2) Biasing using Fixed VG with Source Resistor:

d. Reverse the leads and record your reading.

VG VD VGS VDS Mode

(2) Biasing using Fixed VG with Source Resistor:

VG VD VGS VDS Mode

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BJT as Common Emitter

 Common Emitter Amplifier Configuration:

Common Emitter Configuration

Common Emitter Amplifier Circuit

Voltage Gain: ……………………………..

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BJT as Common Collector Amplifier

 Common Collector Configuration:

Common Collector Configuration

To clear the concepts of common collector, read this example.

It is called the common-collector configuration because (ignoring the power supply

 The output voltage of a common-collector amplifier will be in phase with

 The current gain of a common-collector amplifier is equal to β plus 1. The

 Connect the circuit as given in the manual.

Voltage Gain: ……………………………..

Simulate the given circuit in Proteus

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BJT as Common Base

 Common Base Configuration:

Common Base Configuration