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Fixing Max Cap and Max Tran Violations PDF
Fixing Max Cap and Max Tran Violations PDF
Why do we check "Max CAP and Max Trans violations" only in Worst case corner, most of the times.
Hi Vikram,
Let us think when are the max tran and max cap the worse?
I hope the slew becomes worse in worst corner rather than in best corner.
Hi,
It's true. we have to calculate the possibility of (worst case)max cap and max trans violation then its
easy to design the best skew circuits..
Slew can become worse at any corner, it mainly depends on the CAP or Load that it is seeing.
In that case will CAP or load be different in MAX and MIN corners for the same net.
In worst corner, Id current flowing through the cell will be very less due to operating conditions. When
Id (drain current or drive) is less, it takes longer time to discharge/charge Cout (output cap of cell) + Cin
(input cap of next cell connecting to). Since Id is less, delay is more. This delay is cumulative as it passes
from cell to cell and results in worst slew.
I believe Max cap/Max load is constant across the corners. I never heard of operating temperature
effecting a capacitance or load value. Correct me if iam wrong and justify your answer.
Why the ASIC designer checks the max cap & max trans violations?
If you look at the liberty file, the timing value is define in an array, function of cap & trans.
If the cap & trans is outside the value define for this array, there is a violation and the tool need to
extrapolate the timing value with an internal formula.
But this internal formula is not "perfect" and for huge violation the error/difference with the "real"
timing could made an issue.
So for each cap & tran violations, the designer must check the possible impact on the timing and fix
them if necessary via ECO step.
Did you any time fix trans/cap for min corner, while doing Place and route?
I fix the max cap/trans violations in min corner when the violation occurs on a signal/net/pin which is
timing concern. Other wise, I don't care.
So, I'm parsing the list to justify or not an ECO fix or not.
This lists are part of our methodology list checks before tapeout.
Hi rca,
I want to check with you, let say a net is flagging for max cap violation, which the buffer not able to
driver the load of the net, normally we will upsize the buffer, but what will be the impact to a circuit
design if we dont fix this max cap violation? How do we really check the impact on this max cap? etc is
that to check on RV of the net and so on?
The max cap indicates that the output timing arc does not exist in the table in the liberty file and need
to be recalculate with the derivative formula. Higher the violation is higher the relative error (on the
timing) will be. Then on this particular net you could check the setup/hold time margins you have to be
more confident. Of course if the cap violation is relatively small (less than 10%), and the setup/hold has
some margin, you could treated this violation has harmless.
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maxtran
In the past forum article, there is the related topic, but still here I post the quesion.
1. optDesign -preCTS
3. CTS
5. optDesign -postCTS
I found if I set the setuptargetslack and holdtargetSlack too much, there will generate much maxCap
and maxTran violations. So I decrease the setuptargetslack and holdtargetSlack . And there is no maxCap
and maxTran violations after this step.
7. globalDetailRoute
After this step, when I use timeDesign, there existing much maxCap and maxTran violations.
Then I use fixDRCViolation to fix them, but after fix them, the setup and hold timing worsen. But if I
assure the setup and hold timing, there will be many maxCap and maxTran violations.
Is there some errors that I have made? Or is there some command option that I set wrong? How can I
fix such problem.
Hi ,
After routing is performed , instead of using fixDRVviolation command , use optDesign -postRoute -drv
option to fix transtion and cap violations. It will help you to much extent with out effecting set up and
holld
slack.
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For cap violations,check the drv report & select the pin which has cap violation in the GUI.
Now, look for the instance which is driving thsi high cap pin.
Try to upsize this instance & you should see some cap violation improvement..
If you want to reduce max_cap violations you can set max_tran to a lower value, re-optimize, then set
you max_tran back to original value and run drv check again...they should either be gone or greatly
reduced.
But these max cap violations are external which means it is there in the i/o pad so how can i upsize that
and downsize that?
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How to fix the design rule violations in clock tree synthesis using Encounter?
How can we fix the design rule violations in clock tree synthesis especially using encounter?
while doing timing analysis you have option in the form where in one can optimize drvs especially.
enable that switch. May be that can fix the problem to an extent.
The Transition viol is related to setup time. i,e to say, tht wen u fix the setup violations, the Transition
violation gets fixed up to an extent
I assume that fixing DRC (as u mentioned ) is for the clock path !!
The CTS specification file has to be written properly to fix the violations.
1) buffer transition
2) sink transition
3) MaxSkew
4) NoGating
cos the options like "buffer type" and "buffer transition" values define the length & delays of the net(in
Clock path) which the tool takes while performing the DRC checks ... !!!
hi,
the first thing is to check why encouter not fix such vios.
hi
i dont use astro, but the ability to generate cts reports should be similar. violations should show in the
beginning.
1.Max Cap
2.Max Tran
3.Max Fanout
First, one should fix Max cap, that you can do by including Max Cap statement in cts specification
file.You assign cap value for a buffer by using this statement.Cap value you decide by looking int SDC.
Even you have Max Fanout statement in cts spec file,you give fanout value by looking into SDC and
libraries.
After Max Cap is fixed mostly you will not have trans violation.
As everyone has stated, if your are getting drv violations during cts then you need to tighten your cts
constraints. What do you have set for transition/slew?
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CAN ANY ONE EXPLAIN ME ABOUT THE MAX CAP AND MAX TRANS VIOLATIONS THAT OCCUR IN
DESIGN AND HOW THEY ARE FIXED BY TOOLS ?
There are different ways to fix max cap and max trans violations. I have listed few of them
3. buffer insertion
maximum transition time for a net is the longest time required for its driving pin to change logic
values .
The maximum capacitance is a pin-level attribute used to define the maximum total capacitive load
that an output pin can drive. That is, the pin cannot connect to a net that has a total capacitance (load
pin capacitance and interconnect capacitance) greater than or equal to the maximum capacitance
defined at the pin.
DC/Back end tools will find the max value from the library. If design is having more than the limit on
lib for particular net, its a violation.
Thanks ,
But i have few more ques , like if u upsize the buffer the driving strength will increase and it can drive a
better load ( so max trans fixed on that net ) , so is this heplful in fixing max cap violations also , or tool
have to do cloning and decloning for fixing max cap violations.
And how does downsizing of sink helps, means if i dwnsize the sink i ll probably decrase the i/p cap seen
by the previous driving pin , so is this fixing max cap violations by doing this.
i am clueless ..
what is cloning? upsizing n down sizing og buffer r also used for fixing timing violation .. DRC r also
fixed with same??? i am nt clear with this
max_cap violation
Cloning is basically grouping the similar cells together , that r talking with similiar domain , upsizing
and down sizing r used for fixing timing violaitons , that i correct , but they can also be used to fix max
trans violations as if we upsize a buffer , it can drive a better load and max trans can be fixed , but to fix
max cap this is also used but dnt know how ?
Also for fixing max cap violations tool jus divide the load by adding buffer and instead of one buffer
driving larger load we have more no of buffers driving that particular load but it is distributed.
Hi,
I know that buffering will help in solving the slew violations, but there should be limit on number of
buffers added. what is the limit? what is the relation between the slew and the number of buffers
added?
according to me you are free to buffer as long as that particular path still meets timing(setup).