The PrimeTime Static Timing

Analysis Flow
To perform PrimeTime static timing analysis, follow the typical flow outlined in
Table 1.

Table 1 Typical PrimeTime Static Timing Analysis Flow

Step Task Typical commands Related

topics

1 Read in the design set search_path Working

data, which includes a set link_path With
gate-level netlist and Design
associated logic read_verilog Data
libraries link_design

2 Specify timing and set_input_delay Constrainin

design rule constraints set_output_delay g the
Design
set_min_pulse_width

set_max_capacitance

set_min_capacitance

set_max_fanout

set_max_transition

3 Specify clock create_clock Clocks

characteristics set_clock_uncertainty

set_clock_latency

set_clock_transition

4 Specify timing set_multicycle_path Timing

exceptions set_false_path Paths and
Exceptions
set_disable_timing
5 Specify the set_operating_conditions Operating
environment and set_driving_cell Conditions,
analysis conditions
such as operating set_load Delay
conditions and delay Calculation
set_wire_load_model
models

6 Specify case and mode set_case_analysis Case and

analysis settings set_mode Mode
Analysis

7 Back-annotate delay read_sdf Back-

and parasitics read_parasitics Annotation

Apply variation read_ocvm Variation

(optional) set_aocvm_coefficient
8
set_aocvm_table_group

set_ocvm_table_group

set_timing_derate

9 Specify power load_upf Multivoltag

information create_power_domain e Design
Flow
create_supply_net

create_supply_set

create_supply_port

connect_supply_net

set_voltage

10 Specify options and set si_enable_analysis true Signal

data for signal integrity read_parasitics -keep_capacitive_coupling Integrity
analysis Analysis
11 Apply options for set_latch_loop_breaker Advanced
specific design set_multi_input_ switching_coefficient Analysis
techniques Techniques
define_scaling_lib_group ,
... Advanced
Latch
Analysis,

Multi-Input
Switching
Analysis,

Scaling for
Multirail
Level
Shifter
Cells,

Fast
Multidrive
Delay
Analysis,

Parallel
Driver
Reduction

12 Check the design data check_timing Checking

and analysis setup check_constraints the
Constraints
report_design

report_port

report_net

report_clock

report_wire_load

report_path_group

report_cell

report_hierarchy

report_reference

report_lib
 13 Perform a full timing report_global_timing Reporting
analysis and examine report_timing and
the results Debugging
report_constraint Analysis
report_bottleneck Results,

report_analysis_coverage Graphical
User
report_delay_calculation
Interface
update_timing

Generate engineering set_eco_options ECO Flow

change orders (ECOs) fix_eco_drc
to fix timing violations
or recover power fix_eco_timing
14
fix_eco_power

write_changes

15 Save the PrimeTime save_session Saving a

session PrimeTime
Session

o.