KAKATIYA INSTITUTE OF TECHNOLOGY AND SCIENCE: WARANGAL-15

(An Autonomous Institute under Kakatiya University, Warangal)

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

ASSIGNMENT – V

Date of posting: 20-09-2019 Due date: 27-09-2019

Class B. Tech., V-Semester

Programme Electronics & Communication Engineering

Code-Course U14EC505 Computer Architecture

Name of the faculty J.Nandini, Assistant Professor, Department of ECE

Room No. 102-A, Block I

Contact Details Email: jalinandini@gmail.com Cell: 9494804726

Max. Marks: 15
Questions 1 – 10 for submission: CDLL MARKS CO

1 Write short notes on main memory? R 1 CO3

2 Explain the Memory hierarchy in a computer system? AP 2 CO3

3 Construct a computer system with 1024 bytes of RAM AP 2 CO3

and 512 bytes of ROM, using RAM of 256 bytes and ROM
of 512 bytes.
4 Explain the match logic for one word of associative AN 2 CO3
memory?
5 Write short notes on auxiliary memory? AP 2 CO3

6 Explain the hardware organization of associative U 2 CO3

memory in detail.
7 Explain the different types of mapping procedures used U 1 CO3
in cache memory organization.
8 Describe the virtual memory concept in detail. R 1 CO3

9 Write short notes on Interleaved Memories. R 1 CO3

10 The performance of cache memory is frequently U 1 CO3

measured in terms of