SET B Reg.

No:

MAHENDRA COLLEGE OF ENGINEERING

Salem-Campus, Attur Main Road, Minnampalli, Salem -636 106.
Year / Sem: IV/VIII
Time : 3:00 Hrs
Date: 17.04.2020
Subject Code: EC 6801
Marks : 100
Subject Name: Wireless Communication
MODEL EXAM - I
Blooms
Course
S. No Question Taxonomy
Outcomes
Level
Answer All Questions
Part A— (10 X 2=20)
1 Define EIRP Remembering CO.3
2 Explain basic link budget equation? Remembering CO.3
3 Define cell splitting Understanding CO.3
4 What is channel assignment? What are the types? Remembering CO.4
5 Define windowing Remembering CO.4
6 Define bit error rate of GMSK? Understanding CO.4
7 How the link performance can be proved? Creating CO.5
8 What are the various factor involved in the adaptive equalizer algorithm? Remembering CO.5
9 Define capacity of a fading channel? Remembering CO.4
10 What is spatial filtering? Remembering CO.5
Part B — (05 X 13=65)
11.a) i. What is the need for link calculation? Explain with suitable example 7 Remembering CO.3
ii. A mobile is located at 5 Kms away from base station and uses a 6
vertical λ/4 monopole antenna with a gain of 2.55 dB to receive
cellular radio signals. The E- field at 1Km from transmitter is Remembering
measured to 10-3V/m the carrier frequency is 900 MHz.Find the
length and effective aperture of the effective the receiving antenna
[OR]
11.b) Distinguish fast fading and slow fading in wireless channel and 13 Remembering CO.3
explain in detail

12.a) i)Describe the principle of CDMA 5 Remembering CO.4

ii) IIustrate the handoff scenario at cell boundary 8 Understanding CO.4
[OR]
12.b) Explain the principle of cellular networks and various types of 13 Applying CO.4
Handoff techniques.

i) Differentiate windowing and PAPR in OFDM systems 7 Understanding CO.4

13.a) ii) What is fading channels? Derive the expression for probability of 8 Remembering CO.3
error in flat fading channels.
[OR]
13.b) With neat block diagram, explain the OFDM transmitter and receiver. 13 CO.3
Understanding
List out its advantages and disadvantages.

14.a) i) Describe about space diversity with neat diagrams. 8 Understanding CO.5
ii) Express the LMS algorithm for an adaptive equalizer 5 Remembering
[OR]
14.b) Explain in detail about (i) Polarization diversity (ii) Time diversity 13 Understanding CO.5
(iii) Frequency Diversity

15.a) Calculate the capacity of a MIMO system in flat fading and non 13 Applying CO.4
fading channels
[OR]
15.b) Distinguish between different beam forming techniques 13 CO.5
Understanding
 PART-C (1*15=15)
16.a) With valid statements, analytically prove that the adaptive equalizers 15 Evaluating CO.4
exhibit superior performance over the conventional equalizers.
[OR]
b) With neat diagrams, explain and analyze linear equalization procedure 15 Analyzing CO.4

Subject Teacher HOD- ECE Dean-Academics

 Reg. NO

MAHENDRA COLLEGE OF ENGINEERING

Salem-Campus, Attur Main Road, Minnampalli, Salem -636 106.
Department of Electronics and Communication Engineering
Class: VII
Time : 3:00 Hrs
Date:
Subject Code: EC 6009
Marks : 100
Subject Name: Advanced Computer Architecture

MODEL EXAMINATION
Answer All Questions
Part A— (10 X 2=20)
1 What is vector processor?
2 List advantages of vector processor?
3 What is meant by CUDA ?
4 Why do we need synchronization?
5 What is technique to reduce hit time?
6 Different between write through cache and snoopy cache?
7 List the techniques used for reducing miss penalty?
8 What is temporal locality and spatial locality
9 What is the importance of memory consistency model
10 Difference between write through cache and snoopy cache?

Part B — (05 X 13=65)

11.a) i. Illustrate about Flynn’s classification with neat block diagram 7
ii. Briefly explain about types of parallelism in application 6
[OR]
11.b) Draw and explain about NVIDIA architecture GPU 13

12.a) Identify the dependencies in the below program 13

for (i=0; i<100; i=i+1)
{
Y[i] = X[i] / c; /* S1 */
X[i] = X[i] + c; /* S2 */
Z[i] = Y[i] + c; /* S3 */
Y[i] = c -Y[i]; /* S4 */
}

[OR]
12.b) Explain the NUMA architecture 13

13.a) What are the design challenges in SMT? Explain it? 13

[OR]
13.b) Explain in detail about vector architecture of data level parallelism 13

14.a) Explain in briefly about the cache memory and issues with examples 13
[OR]
14.b) How will you improve the main memory performance 13

15.a) i) Explain in detail about snooping protocols for coherency? 7

ii) How would you compare between write invalidate and write update 6
[OR]
15.b) What are the two types of memory technology? Explain in detail 13
about the same with neat block diagram

PART-C (1*15=15)
16.a) Explain in details about the needs and types of memory consistency 15
model
[OR]
16.b) Discuss in detail about various hit time reduction techniques to 15
improve cache performance

Subject Teacher HOD- ECE Dean-Academics