Verilog HDL

17EC53

BY
KAVYA A P
Asst Professor
Dept. of ECE
VVCE, Mysuru
Syllabus
Syllabus
 Course Outcomes

 Understand the overview of HDL and its modeling

concepts.
 Explain syntax, lexical conventions, data types,
modules and ports of Verilog HDL.
 Design the model of digital system using gate level
and dataflow description.
 Design and verify the digital system using behavioral
description.
 Describe the basic concepts such as design synthesis,
entities, architectures and data types in VHDL.
MODULE 1
Evolution of Computer-Aided Digital
Design

 Digital Circuit design has evolved rapidly.

 Initially Vacuum tubes were used.
 Transistors were invented.
 IC’s were invented.
Evolution of Computer-Aided Digital
Design
Scale of integration
 Small scale integration (SSI)
 Medium scale integration (MSI)
 Large scale integration (LSI)
 Very large scale integration (VLSI)
 Ultra large scale integration (ULSI)
 Giant scale Integration (GSI)
Evolution of Computer-Aided Digital
Design
 Circuits tested on breadboard and layout on paper.

 Process should be automated.

 Electronic Design Automation(EDA) techniques required.

 automatic placement and routing and simulation.

 Hardware description language

 Used to describe structure and behaviour of digital electronic
circuits
 Two types
 VHDL (VHSIC HDL)
 VHSIC Very High Speed Integrated Circuits
 Verilog
 Emergence of HDLs
 Computer programs – Fortan, Pascal, C, C++, C#, python
etc
 To describe digital circuits standard language is required
 Hardware Description Languages came into existence.
 Verilog HDL
 VHDL
 Initially only verification. Manually translate into schematic.
 Digital circuits could be described at RTL level.
 Later logical synthesis came into picture.
 Verilog HDL – IEEE standard (IEEE 1364 -2001)
Typical Design Flow
 Importance of HDLs
Advantages
1. Designs can be described at a very abstract level.
 RTL description can be written without choosing a
specification fabrication technology.

 Logic synthesis tools can automatically convert the design to

any fabrication technology.

 If new technology emerges. No need to redesign the circuit.

Put RTL description to logic synthesis tool.
 New gate level netlist can be generated.

 Optimize area and timing using logic synthesis tools

 Importance of HDLs

Advantages
2. Functional verification can be easily done.

 Modify RTL until it meets the desired functionality.

functional verification ca be done early.

 Bugs can be eliminated. Cuts down design cycle time

significantly

3. Analogous to computer programming, textual descriptions

and comments can be used.
 Popularity of Verilog HDL (why
Verilog HDL?)

 Easy to learn and easy to use.

 Similar in syntax to C programming.

 Allows different levels of abstraction to be mixed in same model.

 Most popular logic synthesis tools support Verilog HDL

 All fabrication vendors provide Verilog HDL libraries.

 Programming Language Interface (PLI) is a powerful feature

that allows the user to write custom code to interact with the
internal data structures of Verilog.
Hierarchical Modeling Concepts

Design Methodologies

 Top down design

 Bottom up design
 Design Methodologies

Top Down Design Methodology

 Define the top level block and identify the sub- blocks
necessary to build the top-level block.

 Further subdivide the sub-blocks until come to leaf cells.

 Leaf cells are the cells which are the cells that cannot
further be divided.
 Top Down Design Methodology
Top-level
block

Sub-block1 Sub-block2 Sub-block3 Sub-block4

Leaf Leaf Leaf Leaf Leaf Leaf Leaf Leaf

Cell Cell Cell Cell Cell Cell Cell Cell
 Design Methodologies

Bottom-Up design methodology

 Identify the building blocks that are available to us.

 Build bigger cells, using these building blocks.

 These cells are then used for higher-level blocks until we

build the top-level block in the design.
 Bottom-Up design methodology
Top-level
block

Sub-block1 Sub-block2 Sub-block3 Sub-block4

Leaf Leaf Leaf Leaf Leaf Leaf Leaf Leaf

Cell Cell Cell Cell Cell Cell Cell Cell
 Modules
 Basic building block

 It hides the internal implementation.

 Provides functionality to higher level block through its port

interface(inputs and outputs)

 Can modify module internal without affecting the rest of

the design.

 Keywords
 module
 endmodule
Module- example
 Module

 Should have module_name – identifier for the

module.

 Module_terminal_list – describes the input and

output terminals of the module.

 Internals of each module can be defined at four

levels of abstraction depending on the need of the
design.
 Module

 Levels of abstraction
 Behavioral or algorithmic level
 similar to C programming
 Implement according to desired design algorithm without concern
for hardware implementation.
 Dataflow level
 How data flows between hardware registers and how it is
processed.
 Gate level
 Implemented in terms of logic gates and interconnections between
these gates.
 Switch level
 Implemented in terms of switches, storage nodes and
interconnection between them.
 Instances

 When module is invoked – unique object is created from

the template.

 Each object has - name, variables, parameters and I/O

Interface.

 Process of creating objects from module template –

instantiation.

 Objects called as instances.

Example
Illegal Module Nesting
 Components of Simulation
 Once a design block is completed it must be tested –
simulating and checking results.

 Such block – stimulus block.(test bench)

 Good practice to keep stimulus and design block separate.

 Stimulus block also written in Verilog.

 Two styles of stimulus application are possible

 Stimulus block instantiates the design block.
 Instantiate both the stimulus and design blocks in a top level
dummy module.
Stimulus block instantiates the
design block.
 Instantiate both the stimulus and
design blocks in a top level dummy
module.
Example -4 Bit Ripple Carry Counter
Design Block
Design Block
 Stimulus Block
Stimulus and output waveforms
Stimulus block
Stimulus block
Stimulus block