Continuous Assessment Test – I

Programme Name & Branch: B.Tech – CSE

KEY

Course Name & Code: Computer Architecture and Organization & CSE2001

Class Number: Slot: G2+TG2

Faculty Name: Exam Duration: 60 Mins Maximum Marks:50

1. Suppose a processor uses the big endian representation and x is a 32-bit integer stored in
memory starting at the memory address 100. The memory is byte-addressable, each
location holding a byte. Specify in binary what would be in memory location 100, 101, 102
and 103 if the program has the statement:
int x = 2047;
Solution:
Memory location 100 = 00000000
Memory location 101 = 00000000
Memory location 102 = 00000111
Memory location 103 = 11111111

b) With the help of a suitable diagram, explain the interaction steps between the processor
registers, control unit, and memory unit during the execution of an instruction

Steps: To read and execute an instruction from main memory to processor, following
steps are required:

- The contents of PC are transferred to MAR

- A Read signal is sent to the memory
- The instruction is read out and loaded into MDR
- The contents of MDR are transferred to IR
 - Decode and execute the instruction

2. A) List the steps needed to execute the machine instruction ADD (R1, R2), R3 in terms of transfers
between the functional components of computer system and some simple control commands.
Solution:

The required steps are:

• Send the address of the instruction word from register PC to the memory and issue a Read control
command.
• Wait until the requested word has been retrieved from the memory, then load it into register IR,
where it is interpreted (decoded) by the control circuitry to determine the operation to be performed.
• Increment the contents of register PC to point to the next instruction in memory.
• Compute the sum of R1 and R2 and send the computed effective address value to the memory via
MAR and issue a Read control command.
• Wait until the requested word has been retrieved from the memory, then load it into ALU register-1.
• Issue Add control command to ALU.
• Send ALU output to R3.

b) Write a program to evaluate the following expression using an accumulator machine:

A = B + C * D * E + F with one address instruction

3.A) a) The following transfer statements specify a memory explain the memory operation in each
case. (i) R2 <- M [AR] (ii) M [AR] <- R3 (iii) R5 <- [R5]

3.B) Consider the byte registers R0 = 70H (H means Hexadecimal) and R1 = 46H. What will be the
contents of R0 and R1 after the following instructions are executed?

(i) Add R1,R0 , (ii) XOR R0,R0,

(iii) AshiftR #2, R1 (iv) RotateL #2, R0

Solution :

Consider the byte registers R0 = 70H (H means Hexadecimal) and R1 = 46H. What will be the contents
of R0 and R1 after the following instructions are executed?

(i) Add R1,R0 , R1= B6, R0=70

(ii) XOR R0,R0, R0= 0, R1= 46

(iii) AshiftR #2, R1 R0= 70, R1=11

(iv) RotateL #2, R0 R0=C1, R1= 46

4.A ) Registers R1 and R2 contain data values 600 and 840 respectively in decimal, and the word
length of the processor is 4 bytes. The effective address of the memory operand for the instruction
“LOAD R5,10(R1,R2)” will be _____

Solution:

1450 (600+840+10=1450)

4.B) b) Quantify the effect on performance that results from the use of a cache in the case of a
program that has a total of 500 instructions, including a 100-instruction loop that is executed 25
times. Determine the ratio of execution time without the cache to execution time with the cache.

Solution:
5. Perform multiplication using following methods:

(i) A = 25 and B = -35. Find A × B using bit-pair recoding multiplier method in Booth
Algorithm (Modified booth)

Now decode the multiplier 2 1

110111010

-1 -1

Check these values

B= -1 * 43 + 2* 42 -1 * 41 + 1 * 40 = 35