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Verilog Material-1 PDF
Verilog Material-1 PDF
1. Full Adder
module ha (input a, b, output sum, carry);
xor g1 (sum, a, b);
and g2 (carry, a, b);
endmodule
a. Using only Half Adders (Position / Ordered Association)
module fa_ha (input a, b, cin, output sum, carry);
wire w1,w2,w3;
ha HA1 (a, b, w1, w3),
HA2(cin, w1, sum, w2),
HA3(w2, w3, carry,);
endmodule
b. Using only Half Adders (Named Association)
module fa_ha (input a, b, cin, output sum, carry);
wire w1,w2,w3;
ha HA1 (.a(a), .b(b), .sum(w1), .carry(w3)),
HA2 (.a(cin), .b(w1), .sum(sum), .carry(w2)),
HA3 (.a(w2), .b(w3), .sum(carry), .carry());
endmodule
Test Bench
module fa_tb;
reg a,b,cin;
wire sum,carry;
fa f1(.a(a),.b(b),.cin(cin),.sum(sum),.carry(carry));
initial
begin
a=0;b=0;cin=0;
$monitor("a=%b,b=%b,cin=%b,sum=%b,carry=%b",a,b,cin,sum,carry);
#5 cin = 1;
#5 b = 1;
#5 cin = 0;
#5 a = 1;
#5 cin = 1;
#5 b = 0;
#5 cin = 0;
end
endmodule
2. Full Subtractor
module hs (input a,b, output d, bo);
wire w1;
not g1 (w1, a);
xor g2 (d, a ,b);
and g3 (bo, w1 ,b);
endmodule
4 : 16 Decoder
module dec_4_16 (input a, b, c, d, output [15:0]y);
wire w1;
not g1(w1,a);
dec_3_8 d1 (.a(b), .b(c), .c(d), .en(w1), .y(y[7:0])),
d2 (.a(b), .b(c), .c(d), .en(a), .y(y[15:8]));
endmodule
5. BCD ADDER
b. Test 4
module test4; module test4;
integer a,b,c,d,e,f; integer a,b,c,d,e,f;
initial initial
begin begin
a = 20; a = 20;
$display("%d", a); $display("%d", a);
#5 b = 50; #5 b = 50;
$display("%d",b); $display("%d",b);
end end
initial initial
begin begin
#10 c = 55; #10 c = 55;
$display("%d",c); $display("%d",c);
#15 d = 70; #15 d = 70;
$display("%d",d); $display("%d",d);
end end
initial initial
begin begin
#20 e = 75; e = 75;
$display("%d",e); $display("%d",e);
#45 f = 80; #5 f = 80;
$display("%d",f); $display("%d",f);
end end
endmodule endmodule
Output Output
a = 20 a = 20
b = 50 e = 75
c = 55 b = 50
e = 75 f = 80
d = 70 c = 55
f = 80 d = 70
14 / 01 / 2015
2. 2:1 Multiplexer
module mux2to1_bh(input a,b,sel, output reg y);
always@(a,b,sel)
begin
if(sel)
y = b;
else
y = a;
end
endmodule
testbench
module mux_2_tb;
reg a,b,s;
wire y;
mux_2 m1(.a(a),.b(b),.s(s),.y(y));
initial
begin
a=0;b=0;s=0;
$monitor("a=%b,b=%b,s=%b,y=%b",a,b,s,y);
#5 s = 1;
#5 a = 1;
#5 s = 0;
#5 b = 1;
#5 s = 1;
#5 a = 0;
#5 s = 0;
end
endmodule
3. Full Adder
a. Using if else ladder ( Blocking Assignment Statements )
module fa_bh4(input a,b,cin, output reg sum,carry);
always@(a,b,cin)
begin
if(a==0 && b==0 && cin==0)
begin
sum = 0;
carry = 0;
end
else if(a==0 && b==0 && cin==1)
begin
sum = 1;
carry = 0;
end
else if(a==0 && b==1 && cin==0)
begin
sum = 1;
carry = 0;
end
else if(a==0 && b==1 && cin==1)
begin
sum = 0;
carry = 1;
end
else if(a==1 && b==0 && cin==0)
begin
sum = 1;
carry = 0;
end
else if(a==1 && b==0 && cin==1)
begin
sum = 0;
carry = 1;
end
else if(a==1 && b==1 && cin==0)
begin
sum = 0;
carry = 1;
end
else
begin
sum = 1;
carry = 1;
end
end
endmodule
b. Using case statement ( Blocking Assignment Statements )
module fa_bh5(input a,b,cin, output reg sum,carry);
always@(a,b,cin)
begin
case({a,b,cin})
3'b000:begin
sum = 0; carry = 0;
end
3'b001:begin
sum = 1; carry = 0;
end
3'b010:begin
sum = 1; carry = 0;
end
3'b011:begin
sum = 0; carry = 1;
end
3'b100:begin
sum = 1; carry = 0;
end
3'b101:begin
sum = 0; carry = 1;
end
3'b110:begin
sum = 0; carry = 1;
end
3'b111:begin
sum = 1; carry = 1;
end
endcase
end
endmodule
c. Using if else ladder and operators ( Blocking Assignment Statements )
module fa_bh6(input a,b,cin, output reg sum,carry);
always@(a,b,cin)
begin
if(!a & !b & !cin)
begin
sum = 0;
carry = 0;
end
else if(!a & !b & cin)
begin
sum = 1;
carry = 0;
end
else if(!a & b & !cin)
begin
sum = 1;
carry = 0;
end
else if(!a & b & cin)
begin
sum = 0;
carry = 1;
end
else if(a & !b & !cin)
begin
sum = 1;
carry = 0;
end
else if(a & !b & cin)
begin
sum = 0;
carry = 1;
end
else if(a & b & !cin)
begin
sum = 0;
carry = 1;
end
else
begin
sum = 1;
carry = 1;
end
end
endmodule
Test Bench
module fa_tb;
reg a,b,cin;
wire sum,carry;
fa f1(.a(a),.b(b),.cin(cin),.sum(sum),.carry(carry));
initial
begin
a=0;b=0;cin=0;
$monitor("a=%b,b=%b,cin=%b,sum=%b,carry=%b",a,b,cin,sum,carry);
#5 cin = 1;
#5 b = 1;
#5 cin = 0;
#5 a = 1;
#5 cin = 1;
#5 b = 0;
#5 cin = 0;
end
endmodule
4. 4 : 1 Multiplexer
a. Using case statement
module mux4to1_bh_case(input a,b,c,d, input [1:0]s, output reg y);
always @(a,b,c,d,s)
begin
case(s)
2'b00:y=a;
2'b01:y=b;
2'b10:y=c;
default:y=d;
endcase
end
endmodule
Testbench
module mux4to1_bh_tb;
reg a,b,c,d;
reg [1:0]s;
wire y;
mux4to1_bh_case m1(.a(a),.b(b),.c(c),.d(d),.s(s),.y(y));
initial
begin
a=0;b=0;c=0;d=0;s=2'b00;
$monitor("a=%b, b=%b, c=%d, d=%d, s=%b, y=%b",a,b,c,d,s,y);
#5 a = 1;
#5 s = 2'b01;
#5 b = 1;a = 0; d = 1;
#5 s = 2'b10;
#5 b = 0;
#5 c = 1;
#5 c = 0;b = 1;
#5 s = 2'b11;
#5 a = 1;
#5 b = 0;d = 0;
end
endmodule
5. 3 : 8 Decoder
a. Using if else statement
module dec3to8_if(input [2:0]a, output reg [7:0]y);
always@(a)
begin
if(a==3'b000)
y = {7'b0,1'b1};
else if(a==3'b001)
y = {6'b0,1'b1,1'b0};
else if(a==3'b010)
y = {5'b0,1'b1,2'b0};
else if(a==3'b011)
y = {4'b0,1'b1,3'b0};
else if(a==3'b100)
y = {3'b0,1'b1,4'b0};
else if(a==3'b101)
y = {2'b0,1'b1,5'b0};
else if(a==3'b110)
y = {1'b0,1'b1,6'b0};
else
y = {1'b1,7'b0};
end
endmodule
b. Using case statement
module dec3to8_case(input [2:0]a, output reg [7:0]y);
always@(a)
begin
case(a)
3'b000:y=8'b00000001;
3'b001:y=8'b00000010;
3'b010:y=8'b00000100;
3'b011:y=8'b00001000;
3'b100:y=8'b00010000;
3'b101:y=8'b00100000;
3'b110:y=8'b01000000;
3'b111:y=8'b10000000;
default:y=8'b00000000;
endcase
end
endmodule
Test Bench
module dec3to8_bh_tb;
reg [2:0]a;
wire [7:0]y;
dec3to8_if dec(.a(a),.y(y));
initial
begin
a = 3'b000;
$monitor("a = %b, y = %b",a,y);
#5 a = 3'b001;
#5 a = 3'b010;
#5 a = 3'b011;
#5 a = 3'b100;
#5 a = 3'b101;
#5 a = 3'b110;
#5 a = 3'b111;
end
endmodule
6. 8 : 3 Encoder
a. Using if else statement
module enc8to3_if(input [7:0]a, output reg [2:0]y);
always@(a)
begin
if(a==8'b00000001)
y = 3'b000;
else if(a==8'b00000010)
y = 3'b001;
else if(a==8'b00000100)
y = 3'b010;
else if(a==8'b00001000)
y = 3'b011;
else if(a==8'b00010000)
y = 3'b100;
else if(a==8'b00100000)
y = 3'b101;
else if(a==8'b01000000)
y = 3'b110;
else if(a==8'b10000000)
y = 3'b111;
else
y = 3'bx;
end
endmodule
b. Using Case statement
module enc8to3_case(input [7:0]a, output reg [2:0]y);
always@(a)
begin
case(a)
8'b00000001:y = 3'b000;
8'b00000010:y = 3'b001;
8'b00000100:y = 3'b010;
8'b00001000:y = 3'b011;
8'b00010000:y = 3'b100;
8'b00100000:y = 3'b101;
8'b01000000:y = 3'b110;
8'b10000000:y = 3'b111;
default:y = 3'bxxx;
endcase
end
endmodule
Test Bench
module enc8to3_bh_tb;
reg [7:0]a;
wire [2:0]y;
enc8to3_if enc(.a(a),.y(y));
initial
begin
a = 8'b00000000;
$monitor("a = %b, y = %b",a,y);
#5 a = 8'b00000001;
#5 a = 8'b00000010;
#5 a = 8'b00000100;
#5 a = 8'b00001000;
#5 a = 8'b00010000;
#5 a = 8'b00100000;
#5 a = 8'b01000000;
#5 a = 8'b10000000;
end
endmodule
7. BCD to 7 Segment display Decoder
a. Using if else statement
module bcdto7seg_if(input [3:0]a, output reg [6:0]y);
always@(a)
begin
if(a == 4'b0000)
y = 7'b1111110;
else if(a == 4'b0001)
y = 7'b0110000;
else if(a == 4'b0010)
y = 7'b1101101;
else if(a == 4'b0011)
y = 7'b1111001;
else if(a == 4'b0100)
y = 7'b0110011;
else if(a == 4'b0101)
y = 7'b1011010;
else if(a == 4'b0110)
y = 7'b1011111;
else if(a == 4'b0111)
y = 7'b1110000;
else if(a == 4'b1000)
y = 7'b1111111;
else if(a == 4'b1001)
y = 7'b1111011;
else
y = 7'b0;
end
endmodule
b. Using case Statement
module bcdto7seg_case(input [3:0]a, output reg [6:0]y);
always@(a)
begin
case(a)
4'b0000:y = 7'b1111110;
4'b0001:y = 7'b0110000;
4'b0010:y = 7'b1101101;
4'b0011:y = 7'b1111001;
4'b0100:y = 7'b0110011;
4'b0101:y = 7'b1011010;
4'b0110:y = 7'b1011111;
4'b0111:y = 7'b1110000;
4'b1000:y = 7'b1111111;
4'b1001:y = 7'b1111011;
default:y = 7'b0;
endcase
end
endmodule
Test Bench
module bcdto7seg_tb;
reg [3:0]a;
wire [6:0]y;
bcdto7seg_case bcddec(.a(a),.y(y));
initial
begin
a = 4'b0000;
$monitor("a = %b, y = %b",a,y);
#5 a=4'b0001;
#5 a=4'b0010;
#5 a=4'b0011;
#5 a=4'b0100;
#5 a=4'b1111;
#5 a=4'b0101;
#5 a=4'b0110;
#5 a=4'b0111;
#5 a=4'b1010;
#5 a=4'b1011;
#5 a=4'b1000;
#5 a=4'b1101;
#5 a=4'b1001;
end
endmodule
19 / 01 / 2015
8. 4 – Bit Asynchronous Counter starting from latch
SR Latch using NAND gates
module srlatch(input s,r,en, output q,qbar);
wire w1,w2,w3,w4;
nand g1(w1,s,en),
g2(w2,r,en),
g3(w3,w1,w4),
g4(w4,w2,w3);
assign q = w3,
qbar = w4;
endmodule
D Latch from SR Latch
module dlatch(input d,en, output q,qbar);
wire w5;
not g5(w5,d);
srlatch d_latch(.s(d),.r(w5),.en(en),.q(q),.qbar(qbar));
endmodule
20 / 01 / 2015
9. Race Around Condition
Blocking Statements Blocking statements
module test_race(input clk); module test_race(input clk);
reg [3:0]a,b; reg [3:0]a,b;
initial initial
begin begin
a = 4'b1101; a = 4'b1101;
b = 4'b1110; b = 4'b1110;
end end
always@(posedge clk) always@(posedge clk)
begin a = b;
a = b; always@(posedge clk)
b = a; b = a;
end end
endmodule endmodule
Output Output
a = 4’b1110 a = 4’b1110
b = 4’b1110 b = 4’b1110
10. COUNTERS
a. 4 – bit synchronous counter with synchronous reset
module cntr4bit_syn_srst(input clk,rst, output reg [3:0]q);
always@(posedge clk)
begin
if(!rst)
q <= 4'b0000;
else
q <= q+1;
end
endmodule
Test Bench
module cntr4bit_syn_tb;
reg clk,rst;
wire [3:0]q;
cntr4bit_syn_srst cntr(.clk(clk),.rst(rst),.q(q));
initial
clk = 1'b0;
always
#5 clk = ~clk;
initial
begin
rst = 0;
$monitor("clk=%b, rst=%b, q=%b", clk,rst,q);
#32 rst = 1;
//#54 rst = 0;
//#80 rst = 0;
//#5 rst = 1;
end
endmodule
b. n – bit synchronous counter with synchronous reset
module cntrnbit_syn_srst #(parameter n = 8)
(input clk,rst, output reg [n-1:0]q);
always@(posedge clk)
begin
if(!rst)
q <= {n{1'b0}};
else
q <= q+1;
end
endmodule
Test Bench
module cntrnbit_syn_tb #(parameter n = 8);
reg clk,rst;
wire [n-1:0]q;
cntrnbit_syn_srst cntr(.clk(clk),.rst(rst),.q(q));
initial
clk = 1'b0;
always
#5 clk = ~clk;
initial
begin
rst = 0;
$monitor("clk=%b, rst=%b, q=%b", clk,rst,q);
#32 rst = 1;
#154 rst = 0;
#13 rst = 1;
#180 rst = 0;
#45 rst = 1;
end
endmodule
c. n – bit synchronous UPDOWN counter with asynchronous reset
module cntrnbit_ud_syn_arst #(parameter n = 8)
(input clk,rst,updown, output reg [n-1:0]q);
always@(posedge clk, negedge rst)
begin
if(!rst)
q <= {n{1'b0}};
else if(updown)
q <= q+1;
else
q <= q-1;
end
endmodule
Test Bench
module cntrnbit_ud_syn_tb #(parameter n = 8);
reg clk,rst,updown;
wire [n-1:0]q;
cntrnbit_ud_syn_arst cntr(.clk(clk),.rst(rst),.updown(updown),.q(q));
initial
clk = 1'b0;
always
#5 clk = ~clk;
initial
begin
rst = 0;updown = 1;
$monitor("clk=%b, rst=%b, updown=%b, q=%b", clk,rst,updown,q);
#32 rst = 1;
#154 rst = 0;
#25 rst = 1;
#17 updown = 0;
#80 rst = 0;
#5 rst = 1;
#18 updown = 1;
#170 rst = 0;
#17 rst = 1;
end
endmodule
FULL ADDER
a. File I / O Based Test Bench
module fa_tb_file;
reg a,b,cin;
wire sum,carry;
integer f1;
fa_bh1 fa1(.a(a),.b(b),.cin(cin),.sum(sum),.carry(carry));
initial
//f1 = $fopen("fa_lin.xls");
f1 = $fopen("fa_lin.txt");
initial
begin
a=0;b=0;cin=0;
$fmonitor(f1,$time,"a=%b,b=%b,cin=%b,sum=%b,carry=%b",a,b,cin,sum,carry);
#5 cin = 1;
#5 b = 1;
#5 cin = 0;
#5 a = 1;
#5 cin = 1;
#5 b = 0;
#5 cin = 0;
end
endmodule
module fa_tb_loop;
reg a,b,cin;
wire sum,carry;
integer f1;
fa_bh1 fa1(.a(a),.b(b),.cin(cin),.sum(sum),.carry(carry));
initial
f1 = $fopen("fa_loop.txt");
initial
begin
{a,b,cin} = 3'b000;
repeat(7)
begin
{a,b,cin} = {a,b,cin} + 3'b001;
#10 $fdisplay(f1,$time,"a=%b, b=%b, cin=%b, sum=%b,
carry=%b",a,b,cin,sum,carry);
end
end
endmodule
module fa_tb_rand;
reg a,b,cin;
wire sum,carry;
fa_bh1 fa1(.a(a),.b(b),.cin(cin),.sum(sum),.carry(carry));
initial
begin
repeat(10)
begin
a = $random();
b = $random();
cin = $random();
#5 $display("a=%b, b=%b, cin=%b, sum=%b, carry=%b",a,b,cin,sum,carry);
end
end
endmodule
module fa_tb_self;
reg a,b,cin;
wire sum,carry;
integer f1;
fa_bh1 fa1(.a(a),.b(b),.cin(cin),.sum(sum),.carry(carry));
initial
f1 = $fopen("fa_self1.txt");
initial
begin
{a,b,cin} = 3'b000;
repeat(7)
begin
{a,b,cin} = {a,b,cin} + 3'b001;
#10 $fdisplay(f1,$time,"a=%b, b=%b, cin=%b, sum=%b,
carry=%b",a,b,cin,sum,carry);
if((a+b+cin)!={carry,sum})
$fdisplay(f1,$time,"error");
else
$fdisplay(f1,$time,"success");
end
end
endmodule
Test Bench
module prienc_tb;
reg [7:0]a;
wire [2:0]y;
integer f1;
//prienc_df e(.a(a),.y(y)); // for dataflow
//prienc_if e(.a(a),.y(y)); // for if else
prienc_case e(.a(a),.y(y));
initial
//f1 = $fopen("prienc_df.txt");
//f1 = $fopen("prienc_if.txt");
f1 = $fopen("prienc_case.txt");
initial
begin
a = 8'b1;
$fmonitor(f1,$time,"a=%b,y=%b",a,y);
#10 a = 8'b0;
#10 a = 8'bxxxxxxxx;
#10 a = 8'bzzzzzzzz;
#10 a = 8'b11110000;
#10 a = 8'bxxxxxx1x;
#10 a = 8'bzzz1zzzx;
#10 a = 8'bzzz1zzzz;
#10 a = 8'bzzz1z10x;
#10 a = 8'b111100xx;
#10 a = 8'b00000010;
#10 a = 8'bzzz1x00z;
#10 a = 8'b1z1x0zx0;
#10 a = 8'b1z1x0xx0;
#10 a = 8'b1z1x00x0;
#10 a = 8'b1z1x01x0;
#10 a = 8'b1z100xx0;
#10 a = 8'b1z10000x;
#10 a = 8'b1z1z000x;
#10 a = 8'b000000x0;
#10 a = 8'b100000x0;
#10 a = 8'b000001x0;
end
endmodule
22 / 01 / 2015
23 / 01 / 2015
27 / 01 / 2015
#40 rst=1'b1;
#220 rst = 1'b0;
#20 rst = 1'b1;
end
initial
begin
#15 x=1;
#10 x=1;
#10 x=1;
#10 x=0;
#10 x=1;
#10 x=0;
#10 x=1;
#10 x=1;
#10 x=0;
#10 x=1;module fsm1101_tb;
reg clk,x,rst;
wire y;
fsm1101 f1(.clk(clk),.rst(rst),.x(x),.y(y));
initial
begin
clk=0;
end
always
begin
#5 clk=~clk;
end
initial
begin
rst = 1'b0;
#40 rst=1'b1;
#220 rst = 1'b0;
#20 rst = 1'b1;
end
initial
begin
#15 x=1;
#10 x=1;
#10 x=1;
#10 x=0;
#10 x=1;
#10 x=0;
#10 x=1;
#10 x=1;
#10 x=0;
#10 x=1;
#10 x=0;
#10 x=1;
#10 x=1;
end
endmodule
#10 x=0;
#10 x=1;
#10 x=1;
end
endmodule
b. 0111
module fsm0111
(input x,clk,rst,
output reg y);
parameter GN = 2'b00,
GOT0 = 2'b01,
GOT01 = 2'b10,
GOT011 = 2'b11;
reg [1:0]state,next;
always@(posedge clk, negedge rst)
begin
if(!rst)
state <= GN;
else
state <= next;
end
always@(state,x)
begin
case(state)
GN:if(x)
begin
next = GN;
y = 1'b0;
end
else
begin
next = GOT0;
y = 1'b0;
end
GOT0:if(x)
begin
next = GOT01;
y = 1'b0;
end
else
begin
next = GOT0;
y = 1'b0;
end
GOT01:if(x)
begin
next = GOT011;
y = 1'b0;
end
else
begin
next = GOT0;
y = 1'b0;
end
GOT011:if(x)
begin
next = GN;
y = 1'b1;
end
else
begin
next = GOT0;
y = 1'b0;
end
endcase
end
endmodule
Test Bench
module fsm0111_tb;
reg clk,x,rst;
wire y;
fsm0111 f1(.clk(clk),.rst(rst),.x(x),.y(y));
initial
begin
clk=0;
end
always
begin
#5 clk=~clk;
end
initial
begin
rst = 1'b0;
#40 rst=1'b1;
#220 rst = 1'b0;
#20 rst = 1'b1;
end
initial
begin
#15 x=1;
#10 x=0;
#10 x=1;
#10 x=1;
#10 x=1;
#10 x=0;
#10 x=0;
#10 x=0;
#10 x=1;
#10 x=1;
#10 x=1;
#10 x=1;
#10 x=0;
#10 x=1;
#10 x=1;
#10 x=1;
#10 x=1;
end
endmodule
c. 1110
module fsm_1110
(input x,clk,rst,
output reg y);
parameter GN = 2'b00,
GOT1 = 2'b01,
GOT11 = 2'b10,
GOT111 = 2'b11;
reg [1:0]state,next;
always@(posedge clk, negedge rst)
begin
if(!rst)
state <= GN;
else
state <= next;
end
always@(state,x)
begin
case(state)
GN:if(x)
begin
next = GOT1;
y = 1'b0;
end
else
begin
next = GN;
y = 1'b0;
end
GOT1:if(x)
begin
next = GOT11;
y = 1'b0;
end
else
begin
next = GN;
y = 1'b0;
end
GOT11:if(x)
begin
next = GOT111;
y = 1'b0;
end
else
begin
next = GN;
y = 1'b0;
end
GOT111:if(x)
begin
next = GOT111;
y = 1'b0;
end
else
begin
next = GN;
y = 1'b1;
end
endcase
end
endmodule
Test Bench
module fsm_1110_tb;
reg clk,x,rst;
wire y;
fsm_1110 f1(.clk(clk),.rst(rst),.x(x),.y(y));
initial
begin
clk=0;
end
always
begin
#5 clk=~clk;
end
initial
begin
rst = 1'b0;
#40 rst=1'b1;
#220 rst = 1'b0;
#20 rst = 1'b1;
end
initial
begin
#15 x=1;
#10 x=0;
#10 x=1;
#10 x=1;
#10 x=1;
#10 x=1;
#10 x=0;
#10 x=0;
#10 x=1;
#10 x=1;
#10 x=1;
#10 x=1;
#10 x=0;
#10 x=0;
#10 x=1;
#10 x=1;
#10 x=1;
#10 x=1;
end
endmodule