5 4 3 2 1

UC2B
PCIE

D D
U10 R1
U9 P_GPP_RXP0 P_GPP_TXP0 R2
P_GPP_RXN0 P_GPP_TXN0
PCIE_PRX_DTX_P1 T6 R4 PCIE_PTX_DRX_P1 0.1U_0201_6.3V6-K 1 2 CC1 PCIE_PTX_C_DRX_P1
31 PCIE_PRX_DTX_P1 PCIE_PRX_DTX_N1 P_GPP_RXP1 P_GPP_TXP1 PCIE_PTX_DRX_N1 0.1U_0201_6.3V6-K 1 PCIE_PTX_C_DRX_N1 PCIE_PTX_C_DRX_P1 31
T5 R3 2
WLAN 31 PCIE_PRX_DTX_N1 P_GPP_RXN1 P_GPP_TXN1
CC2
PCIE_PTX_C_DRX_N1 31 WLAN
PCIE_PRX_DTX_P2 T9 N1 PCIE_PTX_DRX_P2 0.1U_0201_6.3V6-K 1 2 CC3 PCIE_PTX_C_DRX_P2
28 PCIE_PRX_DTX_P2 PCIE_PRX_DTX_N2 P_GPP_RXP2 P_GPP_TXP2 PCIE_PTX_DRX_N2 0.1U_0201_6.3V6-K 1 PCIE_PTX_C_DRX_N2 PCIE_PTX_C_DRX_P2 28
T8 N2 2
LAN 28 PCIE_PRX_DTX_N2 P_GPP_RXN2 P_GPP_TXN2
CC4
PCIE_PTX_C_DRX_N2 28 LAN
P7 N4
+1.05VS P6 P_GPP_RXP3 P_GPP_TXP3 N3
P_GPP_RXN3 P_GPP_TXN3
RC1 1 2 196_0402_1% P_TX_ZVDD U7 U6 P_RX_ZVDD 196_0402_1% 1 2 RC3
P_ZVDDP P_ZVSS/P_RX_ZVDDP

PCIE_CRX_GTX_P0 P10 M2 PCIE_CTX_GRX_P0 0.22U_0201_6.3V6-K 1 2 PX@ CC5 PCIE_CTX_C_GRX_P0

15 PCIE_CRX_GTX_P0 PCIE_CRX_GTX_N0 P_GFX_RXP0 P_GFX_TXP0 PCIE_CTX_GRX_N0 0.22U_0201_6.3V6-K 1 PCIE_CTX_C_GRX_N0 PCIE_CTX_C_GRX_P0 15
P9 M1 2 PX@ CC6
15 PCIE_CRX_GTX_N0 P_GFX_RXN0 P_GFX_TXN0 PCIE_CTX_C_GRX_N0 15
C C
PCIE_CRX_GTX_P1 N6 L1 PCIE_CTX_GRX_P1 0.22U_0201_6.3V6-K 1 2 PX@ CC7 PCIE_CTX_C_GRX_P1
15 PCIE_CRX_GTX_P1 PCIE_CRX_GTX_N1 P_GFX_RXP1 P_GFX_TXP1 PCIE_CTX_GRX_N1 0.22U_0201_6.3V6-K 1 PCIE_CTX_C_GRX_N1 PCIE_CTX_C_GRX_P1 15
N5 L2 2 PX@
GPU 15 PCIE_CRX_GTX_N1 P_GFX_RXN1 P_GFX_TXN1
CC8
PCIE_CTX_C_GRX_N1 15 GPU
PCIE_CRX_GTX_P2 N9 L4 PCIE_CTX_GRX_P2 0.22U_0201_6.3V6-K 1 2 PX@ CC9 PCIE_CTX_C_GRX_P2
15 PCIE_CRX_GTX_P2 PCIE_CRX_GTX_N2 P_GFX_RXP2 P_GFX_TXP2 PCIE_CTX_GRX_N2 0.22U_0201_6.3V6-K 1 PCIE_CTX_C_GRX_N2 PCIE_CTX_C_GRX_P2 15
N8 L3 2 PX@ CC10
15 PCIE_CRX_GTX_N2 P_GFX_RXN2 P_GFX_TXN2 PCIE_CTX_C_GRX_N2 15
PCIE_CRX_GTX_P3 L7 J1 PCIE_CTX_GRX_P3 0.22U_0201_6.3V6-K 1 2 PX@ CC11 PCIE_CTX_C_GRX_P3
15 PCIE_CRX_GTX_P3 PCIE_CRX_GTX_N3 P_GFX_RXP3 P_GFX_TXP3 PCIE_CTX_GRX_N3 0.22U_0201_6.3V6-K 1 PCIE_CTX_C_GRX_N3 PCIE_CTX_C_GRX_P3 15
L6 J2 2 PX@ CC12
15 PCIE_CRX_GTX_N3 P_GFX_RXN3 P_GFX_TXN3 PCIE_CTX_C_GRX_N3 15
PCIE_CRX_GTX_P4 L10 J4 PCIE_CTX_GRX_P4 0.22U_0201_6.3V6-K 1 2 PX@ CC18 PCIE_CTX_C_GRX_P4
15 PCIE_CRX_GTX_P4 PCIE_CRX_GTX_N4 P_GFX_RXP4 P_GFX_TXP4 PCIE_CTX_GRX_N4 0.22U_0201_6.3V6-K 1 PCIE_CTX_C_GRX_N4 PCIE_CTX_C_GRX_P4 15
L9 J3 2 PX@ CC30
15 PCIE_CRX_GTX_N4 P_GFX_RXN4 P_GFX_TXN4 PCIE_CTX_C_GRX_N4 15
PCIE_CRX_GTX_P5 K6 H2 PCIE_CTX_GRX_P5 0.22U_0201_6.3V6-K 1 2 PX@ CC31 PCIE_CTX_C_GRX_P5
15 PCIE_CRX_GTX_P5 PCIE_CRX_GTX_N5 P_GFX_RXP5 P_GFX_TXP5 PCIE_CTX_GRX_N5 0.22U_0201_6.3V6-K 1 PCIE_CTX_C_GRX_N5 PCIE_CTX_C_GRX_P5 15
K5 H1 2 PX@ CC33
15 PCIE_CRX_GTX_N5 P_GFX_RXN5 P_GFX_TXN5 PCIE_CTX_C_GRX_N5 15
PCIE_CRX_GTX_P6 K9 G1 PCIE_CTX_GRX_P6 0.22U_0201_6.3V6-K 1 2 PX@ CC32 PCIE_CTX_C_GRX_P6
15 PCIE_CRX_GTX_P6 PCIE_CRX_GTX_N6 P_GFX_RXP6 P_GFX_TXP6 PCIE_CTX_GRX_N6 0.22U_0201_6.3V6-K 1 PCIE_CTX_C_GRX_N6 PCIE_CTX_C_GRX_P6 15
K8 G2 2 PX@ CC34
15 PCIE_CRX_GTX_N6 P_GFX_RXN6 P_GFX_TXN6 PCIE_CTX_C_GRX_N6 15
PCIE_CRX_GTX_P7 J7 G4 PCIE_CTX_GRX_P7 0.22U_0201_6.3V6-K 1 2 PX@ CC35 PCIE_CTX_C_GRX_P7
B 15 PCIE_CRX_GTX_P7 PCIE_CRX_GTX_N7 P_GFX_RXP7 P_GFX_TXP7 PCIE_CTX_GRX_N7 0.22U_0201_6.3V6-K 1 PCIE_CTX_C_GRX_N7 PCIE_CTX_C_GRX_P7 15 B
J6 G3 2 PX@ CC36
15 PCIE_CRX_GTX_N7 P_GFX_RXN7 P_GFX_TXN7 PCIE_CTX_C_GRX_N7 15

FP4 REV 0.93

@ AMD-CARRIZO_FP4-BGA968

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP4 (PCIE I/F)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
320ABR 0.1

Date: Thursday, January 12, 2017 Sheet 4 of 50

5 4 3 2 1
 5 4 3 2 1

DDRB_DQS[0..7]
DDRA_DQS[0..7] 13 DDRB_DQS[0..7]
12 DDRA_DQS[0..7] DDRB_DQS#[0..7]
DDRA_DQS#[0..7] 13 DDRB_DQS#[0..7]
12 DDRA_DQS#[0..7]

DQ bit swapping is allowed in a byte lane.

UC2I
UC2A
MEMORY B
13 DDRB_MA[13..0] DDRB_MA0 DDRB_DQ0 DDRB_DQ[63..0] 13
MEMORY A AG31 A25
12 DDRA_MA[13..0] DDRA_MA0 DDRA_DQ0 DDRA_DQ[63..0] 12 DDRB_MA1 MB_ADD0 MB_DATA0 DDRB_DQ1
AE28 H17 AC30 C25
DDRA_MA1 Y27 MA_ADD0 MA_DATA0 J17 DDRA_DQ1 DDRB_MA2 AC31 MB_ADD1 MB_DATA1 C27 DDRB_DQ2
DDRA_MA2 Y29 MA_ADD1 MA_DATA1 F20 DDRA_DQ2 DDRB_MA3 AB32 MB_ADD2 MB_DATA2 D27 DDRB_DQ3
DDRA_MA3 Y26 MA_ADD2 MA_DATA2 H20 DDRA_DQ3 DDRB_MA4 AA32 MB_ADD3 MB_DATA3 B24 DDRB_DQ4
D
DDRA_MA4
DDRA_MA5
W28 MA_ADD3
MA_ADD4
MA_DATA3
MA_DATA4
E17 DDRA_DQ4
DDRA_DQ5
DDRB_MA5
DDRB_MA6
AA33 MB_ADD4
MB_ADD5
MB_DATA4
MB_DATA5
B25 DDRB_DQ5
DDRB_DQ6
APU SO-DIMM DRAM D

W29 F17 AA31 B27 DA0 DQ2 UD1.0

DDRA_MA6
DDRA_MA7
W26 MA_ADD5
MA_ADD6
MA_DATA5
MA_DATA6
K18 DDRA_DQ6
DDRA_DQ7
APU SO-DIMM DRAM DDRB_MA7
DDRB_MA8
Y33 MB_ADD6
MB_ADD7
MB_DATA6
MB_DATA7
A27 DDRB_DQ7
U29 E20 DA32 DQ39 UD3.1 AA30 DA1 DQ7 UD1.3
DDRA_MA8 W25 MA_ADD7 MA_DATA7 DDRB_MA9 W32 MB_ADD8 A29 DDRB_DQ8
DDRA_MA9 U26 MA_ADD8 A21 DDRA_DQ8 DDRB_MA10 AG32 MB_ADD9 MB_DATA8 C29 DDRB_DQ9
DDRA_MA10 MA_ADD9 MA_DATA8 DDRA_DQ9
DA33 DQ36 UD3.6 DDRB_MA11 MB_ADD10 MB_DATA9 DDRB_DQ10
DA2 DQ6 UD1.4
AG29 C21 Y32 B32
DDRA_MA11 U27 MA_ADD10 MA_DATA9 C23 DDRA_DQ10 DDRB_MA12 W33 MB_ADD11 MB_DATA10 D32 DDRB_DQ11
DDRA_MA12 MA_ADD11 MA_DATA10 DDRA_DQ11
DA34 DQ35 UD3.2 DDRB_MA13 MB_ADD12 MB_DATA11 DDRB_DQ12
DA3 DQ0 UD1.5
T28 D23 AL31 B28
DDRA_MA13 AK26 MA_ADD12 MA_DATA11 B20 DDRA_DQ12 1 DDRB_BG1 W30 MB_ADD13 MB_DATA12 B29 DDRB_DQ13
DDRA_BG1 MA_ADD13 MA_DATA12 DDRA_DQ13
DA35 DQ34 UD3.7 @ TC77
DDRB_ACT# MB_ADD14/MB_BG1 MB_DATA13 DDRB_DQ14
DA4 DQ1 UD1.2
T26 B21 V32 A31
12 DDRA_BG1 DDRA_ACT# MA_ADD14/MA_BG1 MA_DATA13 DDRA_DQ14 13 DDRB_ACT# MB_ADD15/MB_ACT_L MB_DATA14 DDRB_DQ15
T25 B23 DA36 DQ37 UD3.5 C31 DA5 DQ5 UD1.7
12 DDRA_ACT# MA_ADD15/MA_ACT_L MA_DATA14 DDRA_DQ15 MB_DATA15
A23
MA_DATA15 E30 DDRB_DQ16
DDRA_DQ16
DA37 DQ32 UD3.3 DDRB_BA0 MB_DATA16 DDRB_DQ17
DA6 DQ4 UD1.1
G22 AH32 E31
DDRA_BA0 MA_DATA16 DDRA_DQ17 13 DDRB_BA0 DDRB_BA1 MB_BANK0 MB_DATA17 DDRB_DQ18
AG26 H22 DA38 DQ38 UD3.4 AG33 G33 DA7 DQ3 UD1.6
12 DDRA_BA0 DDRA_BA1 MA_BANK0 MA_DATA17 DDRA_DQ18 13 DDRB_BA1 DDRB_BG0 MB_BANK1 MB_DATA18 DDRB_DQ19
AG27 E25 W31 G32
12 DDRA_BA1 DDRA_BG0 MA_BANK1 MA_DATA18 DDRA_DQ19 13 DDRB_BG0 MB_BANK2/MB_BG0 MB_DATA19 DDRB_DQ20
T29 G25 DA39 DQ33 UD3.0 C33 DA8 DQ12 UD1.11
12 DDRA_BG0 MA_BANK2/MA_BG0 MA_DATA19 DDRA_DQ20 13 DDRB_DM[7..0] DDRB_DM0 MB_DATA20 DDRB_DQ21
J20 D25 D33
12 DDRA_DM[7..0] DDRA_DM0 MA_DATA20 DDRA_DQ21 DDRB_DM1 MB_DM0 MB_DATA21 DDRB_DQ22
E19 E22 DA40 DQ45 UD3.15 D29 G30 DA9 DQ13 UD1.9
DDRA_DM1 D21 MA_DM0 MA_DATA21 H23 DDRA_DQ22 DDRB_DM2 E33 MB_DM1 MB_DATA22 G31 DDRB_DQ23
DDRA_DM2 K21 MA_DM1 MA_DATA22 J23 DDRA_DQ23 DDRB_DM3 J33 MB_DM2 MB_DATA23
DDRA_DM3 MA_DM2 MA_DATA23
DA41 DQ44 UD3.9 DDRB_DM4 MB_DM3 DDRB_DQ24
DA10 DQ11 UD1.12
F29 AR30 J30
DDRA_DM4 AP28 MA_DM3 F26 DDRA_DQ24 DDRB_DM5 AW30 MB_DM4 MB_DATA24 J31 DDRB_DQ25
DDRA_DM5 MA_DM4 MA_DATA24 DDRA_DQ25
DA42 DQ47 UD3.14 DDRB_DM6 MB_DM5 MB_DATA25 DDRB_DQ26
DA11 DQ10 UD1.14
AV26 E27 BC30 L33
DDRA_DM6 AR22 MA_DM5 MA_DATA25 J26 DDRA_DQ26 DDRB_DM7 BC26 MB_DM6 MB_DATA26 L32 DDRB_DQ27
DDRA_DM7 MA_DM6 MA_DATA26 DDRA_DQ27
DA43 DQ46 UD3.8 MB_DM7 MB_DATA27 DDRB_DQ28
DA12 DQ9 UD1.13
BC22 J27 N33 H32
K29 MA_DM7 MA_DATA27 H25 DDRA_DQ28 MB_DM8 MB_DATA28 H33 DDRB_DQ29
MA_DM8 MA_DATA28 DDRA_DQ29
DA44 DQ40 UD3.13 DDRB_DQS0 MB_DATA29 DDRB_DQ30
DA13 DQ8 UD1.15
E26 B26 L30
DDRA_DQS0 H19 MA_DATA29 G28 DDRA_DQ30 DDRB_DQS#0 A26 MB_DQS_H0 MB_DATA30 L31 DDRB_DQ31
DDRA_DQS#0 MA_DQS_H0 MA_DATA30 DDRA_DQ31
DA45 DQ41 UD3.11 DDRB_DQS1 MB_DQS_L0 MB_DATA31
DA14 DQ15 UD1.8
G19 G29 B30
DDRA_DQS1 B22 MA_DQS_L0 MA_DATA31 DDRB_DQS#1 A30 MB_DQS_H1 AN31 DDRB_DQ32
DDRA_DQS#1 MA_DQS_H1 DDRA_DQ32
DA46 DQ43 UD3.12 DDRB_DQS2 MB_DQS_L1 MB_DATA32 DDRB_DQ33
DA15 DQ14 UD1.10
A22 AN26 F32 AP32
DDRA_DQS2 F23 MA_DQS_L1 MA_DATA32 AP29 DDRA_DQ33 DDRB_DQS#2 E32 MB_DQS_H2 MB_DATA33 AT32 DDRB_DQ34
C DDRA_DQS#2 MA_DQS_H2 MA_DATA33 DDRA_DQ34
DA47 DQ42 UD3.10 DDRB_DQS3 MB_DQS_L2 MB_DATA34 DDRB_DQ35
DA16 DQ20 UD2.7 C
E23 AR26 K32 AU32
DDRA_DQS3 G27 MA_DQS_L2 MA_DATA34 AP24 DDRA_DQ35 DDRB_DQS#3 J32 MB_DQS_H3 MB_DATA35 AN33 DDRB_DQ36
DDRA_DQS#3 MA_DQS_H3 MA_DATA35 DDRA_DQ36
DA48 DQ55 UD4.0 DDRB_DQS4 MB_DQS_L3 MB_DATA36 DDRB_DQ37
DA17 DQ16 UD2.3
F27 AN29 AR32 AN32
DDRA_DQS4 AP25 MA_DQS_L3 MA_DATA36 AN27 DDRA_DQ37 DDRB_DQS#4 AR33 MB_DQS_H4 MB_DATA37 AR31 DDRB_DQ38
DDRA_DQS#4 MA_DQS_H4 MA_DATA37 DDRA_DQ38
DA49 DQ49 UD4.3 DDRB_DQS5 MB_DQS_L4 MB_DATA38 DDRB_DQ39
DA18 DQ19 UD2.4
AP26 AR29 AW32 AT33
DDRA_DQS5 AW27 MA_DQS_L4 MA_DATA38 AR27 DDRA_DQ39 DDRB_DQS#5 AW33 MB_DQS_H5 MB_DATA39
DDRA_DQS#5 MA_DQS_H5 MA_DATA39 DA50 DQ54 UD4.2 DDRB_DQS6 MB_DQS_L5 DDRB_DQ40
DA19 DQ18 UD2.1
AV27 BA29 AU30
DDRA_DQS6 AV22 MA_DQS_L5 AU26 DDRA_DQ40 DDRB_DQS#6 AY29 MB_DQS_H6 MB_DATA40 AV32 DDRB_DQ41
DDRA_DQS#6 MA_DQS_H6 MA_DATA40 DDRA_DQ41
DA51 DQ48 UD4.7 DDRB_DQS7 MB_DQS_L6 MB_DATA41 DDRB_DQ42
DA20 DQ17 UD2.0
AU22 AV29 BA25 BA33
DDRA_DQS7 BA21 MA_DQS_L6 MA_DATA41 AU25 DDRA_DQ42 DDRB_DQS#7 AY25 MB_DQS_H7 MB_DATA42 AY32 DDRB_DQ43
DDRA_DQS#7 MA_DQS_H7 MA_DATA42 DDRA_DQ43
DA52 DQ53 UD4.5 MB_DQS_L7 MB_DATA43 DDRB_DQ44
DA21 DQ21 UD2.2
AY21 AW25 P32 AU33
L27 MA_DQS_L7 MA_DATA43 AU29 DDRA_DQ44 N32 MB_DQS_H8 MB_DATA44 AU31 DDRB_DQ45
MA_DQS_H8 MA_DATA44 DDRA_DQ45
DA53 DQ52 UD4.1 MB_DQS_L8 MB_DATA45 DDRB_DQ46
DA22 DQ22 UD2.6
L26 AU28 AW31
MA_DQS_L8 MA_DATA45 AW26 DDRA_DQ46 DDRB_CLK0 AE33 MB_DATA46 AY33 DDRB_DQ47
DDRA_CLK0 MA_DATA46 DDRA_DQ47
DA54 DQ50 UD4.6 13 DDRB_CLK0 DDRB_CLK0# MB_CLK_H0 MB_DATA47
DA23 DQ23 UD2.5
AE25 AT25 AE32
12 DDRA_CLK0 DDRA_CLK0# MA_CLK_H0 MA_DATA47 13 DDRB_CLK0# MB_CLK_L0 DDRB_DQ48
AE26 DA55 DQ51 UD4.4 AE30 BC31 DA24 DQ24 UD2.9
12 DDRA_CLK0# DDRA_CLK1 MA_CLK_L0 DDRA_DQ48 MB_CLK_H1 MB_DATA48 DDRB_DQ49
AD26 AV23 AE31 BB30
12 DDRA_CLK1 DDRA_CLK1# MA_CLK_H1 MA_DATA48 DDRA_DQ49 MB_CLK_L1 MB_DATA49 DDRB_DQ50
AD27 AW23 DA56 DQ61 UD4.14 AD32 BB28 DA25 DQ28 UD2.11
12 DDRA_CLK1# MA_CLK_L1 MA_DATA49 DDRA_DQ50 MB_CLK_H2 MB_DATA50 DDRB_DQ51
AB28 AV20 AD33 AY27
AB29 MA_CLK_H2 MA_DATA50 AW20 DDRA_DQ51 AC33 MB_CLK_L2 MB_DATA51 BB32 DDRB_DQ52
MA_CLK_L2 MA_DATA51 DDRA_DQ52
DA57 DQ56 UD4.10 MB_CLK_H3 MB_DATA52 DDRB_DQ53
DA26 DQ30 UD2.12
AB25 AR23 AC32 BA31
AB26 MA_CLK_H3 MA_DATA52 AT23 DDRA_DQ53 MB_CLK_L3 MB_DATA53 BC29 DDRB_DQ54
MA_CLK_L3 MA_DATA53 DDRA_DQ54
DA58 DQ63 UD4.11 MEM_MB_RST#_R T33 MB_DATA54 DDRB_DQ55
DA27 DQ26 UD2.8
AR20 RC240 1 2 10_0402_5% BB29
MEM_MA_RST#_R N29 MA_DATA54 DDRA_DQ55 13 MEM_MB_RST# MEM_MB_EVENT#AG30 MB_RESET_L MB_DATA55
RC283 1 2 10_0402_5% AT20 DA59 DQ58 UD4.12 DA28 DQ25 UD2.13
12 MEM_MA_RST# MEM_MA_EVENT# AE29 MA_RESET_L MA_DATA55 MB_EVENT_L DDRB_DQ56
BB27
12 MEM_MA_EVENT# MA_EVENT_L DDRA_DQ56 DDRB_CKE0 MB_DATA56 DDRB_DQ57
BB23 DA60 DQ60 UD4.13 U32 BB26 DA29 DQ29 UD2.15
DDRA_CKE0 MA_DATA56 DDRA_DQ57 13 DDRB_CKE0 MB_CKE0 MB_DATA57 DDRB_DQ58
P27 BB22 U33 BB24
12 DDRA_CKE0 DDRA_CKE1 MA_CKE0 MA_DATA57 DDRA_DQ58 MB_CKE1 MB_DATA58 DDRB_DQ59
P29 BB20 DA61 DQ57 UD4.9 AY23 DA30 DQ27 UD2.14
12 DDRA_CKE1 MA_CKE1 MA_DATA58 DDRA_DQ59 MB_DATA59 DDRB_DQ60
AY19 BA27
MA_DATA59 BA23 DDRA_DQ60 MB_DATA60 BC27 DDRB_DQ61
MA_DATA60 DDRA_DQ61
DA62 DQ59 UD4.15 DDRB_ODT0 MB_DATA61 DDRB_DQ62
DA31 DQ31 UD2.10
BC23 AL30 BC25
DDRA_ODT0 MA_DATA61 DDRA_DQ62 13 DDRB_ODT0 MB0_ODT0 MB_DATA62 DDRB_DQ63
AK27 BC21 DA63 DQ62 UD4.8 AM32 BB25
12 DDRA_ODT0 DDRA_ODT1 MA0_ODT0 MA_DATA62 DDRA_DQ63 MB0_ODT1 MB_DATA63
AL26 BB21 AJ32
12 DDRA_ODT1 MA0_ODT1 MA_DATA63 MB1_ODT0
AH25 AM33 N30
B AL25 MA1_ODT0 K26 MB1_ODT1 MB_CHECK0 N31 B
MA1_ODT1 MA_CHECK0 K28 DDRB_CS0# AJ33 MB_CHECK1 R33
DDRA_CS0# MA_CHECK1 13 DDRB_CS0# MB0_CS_L0 MB_CHECK2
AH26 N26 AL32 R32
12 DDRA_CS0# DDRA_CS1# MA0_CS_L0 MA_CHECK2 MB0_CS_L1 MB_CHECK3
AL29 N28 AJ30 M32
12 DDRA_CS1# MA0_CS_L1 MA_CHECK3 MB1_CS_L0 MB_CHECK4
AH29 J29 AL33 M33
AL28 MA1_CS_L0 MA_CHECK4 K25 MB1_CS_L1 MB_CHECK5 R30
MA1_CS_L1 MA_CHECK5 L29 MB_CHECK6 R31
MA_CHECK6 N25 DDRB_MA16_RAS# AH33 MB_CHECK7
DDRA_MA16_RAS# AG24 MA_CHECK7 13 DDRB_MA16_RAS# DDRB_MA15_CAS# AK32 MB_RAS_L/MB_RAS_L_ADD16 +1.2V
12 DDRA_MA16_RAS# DDRA_MA15_CAS# AK29 MA_RAS_L/MA_RAS_L_ADD16 13 DDRB_MA15_CAS# DDRB_MA14_W E# AJ31 MB_CAS_L/MB_CAS_L_ADD15
+1.2V
12 DDRA_MA15_CAS# DDRA_MA14_W E# AH28 MA_CAS_L/MA_CAS_L_ADD15 13 DDRB_MA14_W E# MB_WE_L/MB_WE_L_ADD14
12 DDRA_MA14_W E# MA_WE_L/MA_WE_L_ADD14
@ TC70 1 APU_MB_VREFDQ A19 AF32 MB_ZVDDIO RC10 1 2 39.2_0402_1%
@ TC76 1 APU_MA_VREFDQ B19 AD29 MA_ZVDDIO RC33 1 2 39.2_0402_1% MB_VREFDQ MB_ZVDDIO_MEM_S
+MEM_VREF T32 MA_VREFDQ MA_ZVDDIO_MEM_S
M_VREF FP4 REV 0.93
FP4 REV 0.93
@ AMD-CARRIZO_FP4-BGA968
@ AMD-CARRIZO_FP4-BGA968 +1.2V

Memory down
+1.2V

1 2 1K_0402_5% MEM_MB_EVENT#

SO-DIMM
RC9
+1.2V
RC284 1 2 1K_0402_5% MEM_MA_EVENT#
1

RC4
1K_0402_1%
2

@ +MEM_VREF

A A
1000P_0201_50V7-K
.047U_0201_6.3V6K

0.1U_0201_6.3V6-K
1

1 1 1
RC5
CC13

CC14

CC15

1K_0402_1%

2 2 2
2

@ @ @
@

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP4 (MEM)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
320ABR 0.1

Date: Thursday, January 12, 2017 Sheet 5 of 50

5 4 3 2 1
 5 4 3 2 1

+3VS_APU
UC2C RPC18
APU_DDC_CLK 1 4
APU_DDC_DATA 2 3
DISPLAY/SVI2/JTAG/T EST

2.2K_0404_4P2R_5%
B6 A9 DP_2K_ZVSS RC55 1 2 2K_0402_1%
A6 DP2_TXP0 DP_ZVSS B9 DP_150_ZVSS RC12 1 2 150_0402_1%
+1.8VS DP2_TXN0 DP_AUX_ZVSS G5 DP_ENBKL APU_EDP_HPD RC35 1 2 100K_0402_5%
D7 DP_BLON G6 DP_ENVDD
DP2_TXP1 DP_DIGON DP_EDP_PWM
Hot Plug Detect pins is I-IO18-S,but 3.3V tolerant.
C7 F11
DP2_TXN1 DP_VARY_BL
1

RC18 A7 +1.8VS
B7 DP2_TXP2 H9 RPC11
D
300_0402_5% D
DP2_TXN2 DP2_AUXP G9 ALERT# 3 2
D9 DP2_AUXN E9 DP to VGA APU_PROCHOT#_R 4 1
APU_RST# DP2_TXP3 DP2_HPD
2

C9
DP2_TXN3 F7 APU_DDC_CLK 1K_0404_4P2R_5%
APU_HDMI_TX2+ A2 DP1_AUXP E7 APU_DDC_DATA APU_DDC_CLK 24
PLACE CC16 CAPS CLOSE TO APU,CRB reserve 27pf 24 APU_HDMI_TX2+ APU_HDMI_TX2- DP1_TXP0 DP1_AUXN APU_HDMI_HPD APU_DDC_DATA 24 HDMI
1 A3 F5
24 APU_HDMI_TX2- DP1_TXN0 DP1_HPD APU_HDMI_HPD 24
CC16 APU_SVT APU_HDMI_TX1+ B4 F8 APU_EDP_AUX
220P_0201_25V7-K 24 APU_HDMI_TX1+ APU_HDMI_TX1- A4 DP1_TXP1 DP0_AUXP E8 APU_EDP_AUX# APU_EDP_AUX 23
2 @ 1
24 APU_HDMI_TX1- DP1_TXN1 DP0_AUXN G8 APU_EDP_HPD APU_EDP_AUX# 23 eDP
APU_HDMI_TX0+ D5 DP0_HPD APU_EDP_HPD 23 +3VALW_APU
CC214
1000P_0201_50V7-K
HDMI 24 APU_HDMI_TX0+ APU_HDMI_TX0- C5 DP1_TXP2 K24 Core_type RC239 1 @ 2 100K_0402_5%
24 APU_HDMI_TX0- DP1_TXN2 RSVD_1 E15
2 APU_HDMI_CLK+ A5 TEMPIN0 E14
+1.8VS @ 24 APU_HDMI_CLK+ APU_HDMI_CLK- B5 DP1_TXP3 TEMPIN1 E12
To EDP panel +3VS_APU
24 APU_HDMI_CLK- DP1_TXN3 TEMPIN2 F14
APU_GFX_SVT APU_EDP_TX0+ E2 TEMPINRETURN AK24 TEST410 1 @ TC16
23 APU_EDP_TX0+ APU_EDP_TX0- DP0_TXP0 TEST410
1

1
1 E1 AL24 TEST411 1 @ TC17
23 APU_EDP_TX0- DP0_TXN0 TEST411 P24 TEST4 1 +3VALW_APU
RC19 CC215 @ TC13 RC70
APU_EDP_TX1+ E3 TEST4 N24 TEST5 1
300_0402_5% 1000P_0201_50V7-K
eDP 23 APU_EDP_TX1+ APU_EDP_TX1- E4 DP0_TXP1 TEST5 AN24
@ TC14 4.7K_0402_5%
2 23 APU_EDP_TX1- DP0_TXN1 TEST6

2
AB8
@ TEST9
2

2
D1 Y9 RC71
APU_PWROK D2 DP0_TXP2 TEST10 B10 APU_TEST14_BP0 RC21 1 @ 2 1K_0402_5% 10K_0402_5%
DP0_TXN2 TEST14 D11 APU_TEST15_BP1 1 @ TC18 PCH_EDP_PWM 23
C1 TEST15 A10 APU_TEST16_BP2 RC23 1 2 1K_0402_5%
PLACE CC17 CAPS CLOSE TO APU,CRB reserve 27pf DP0_TXP3 TEST16 APU_TEST17_BP3
@

1
1 B1 C11 RC24 1 @ 2 1K_0402_5%
DP0_TXN3 TEST17 APU_TEST11_BP4

3
B11 RC1891 @ 2 1K_0402_5% D
CC17 RC279 1 2 0_0402_5% APU_SVT_RA C15 TEST11 A14 APU_TEST18_PLLTEST1 4 1 +3VS_APU 5 QC8B
220P_0201_25V7-K 49 APU_SVT 1 2 0_0402_5% APU_SVC_RA D17 SVT0 TEST18 B14 APU_TEST19_PLLTEST0 3 2 G
RC213 DMN5L06DWK-7 2N SOT363-6
2 49 APU_SVC 1 2 0_0402_5% APU_SVD_RA D19 SVC0 TEST19
@ RC215 1K_0404_4P2R_5%
49 APU_SVD SVD0 +1.8VS S
RPC14
APU_GFX_SVT_RA APU_TEST28_H_PLLCHARZ

4
6
RC280 1 2 0_0402_5% B15 A13 1 @ TC21 D
C 50 APU_GFX_SVT 1 2 0_0402_5% APU_GFX_SVC_RA B16 SVT1 TEST28_H B13 APU_TEST28_L_PLLCHARZ 1 @ DP_EDP_PWM C
RC217 TC23 RC2591 @ 2 1K_0402_5% 2 QC8A
50 APU_GFX_SVC 1 2 0_0402_5% APU_GFX_SVD_RA A18 SVC1 TEST28_L P26 APU_TEST31_MEM_TEST 1 @
RC219 TC25 RC28 1 2 1K_0402_5% G DMN5L06DWK-7 2N SOT363-6
+1.8VS +1.8VS 50 APU_GFX_SVD SVD1 TEST31 E11 APU_TEST36_STEREOSYNC RC27 1 @ 2 1K_0402_5%
APU_SIC DP_STEREOSYNC/TEST36 APU_TEST37

1
B18 A17 RC29 1 @ 2 1K_0402_5% S
APU_SID SIC TEST37

1
C17 RC30 1 @ 2 1K_0402_5% RC11
SID 100K_0402_5%
APU_RST# D15
APU_PWROK RESET_L
4
3

C19 Test36 pull high for APU read EDID by HDMI DDC signal
49,50 APU_PWROK PWROK

2
RPC10 RC2051 @ 2 0_0402_5%
APU_PROCHOT#_R
5

1K_0404_4P2R_5% RC31 1 @ 2 0_0402_5% A15

G

35,46 H_PROCHOT# ALERT# B17 PROCHOT_L

ALERT_L H11 APU_VDDGFX_SEN_H
APU_TDI VDDCR_GFX_SENSE APU_VDDNB_SEN_H APU_VDDGFX_SEN_H 50
1
2

H15 J12 +3VS_APU

APU_SIC 4 3 APU_TDO H14 TDI VDDCR_NB_SENSE G12 APU_VDDCORE_SEN_H APU_VDDNB_SEN_H 49
S

EC_SMB_CK3 16,30,35 APU_TCK D13 TDO VDDCR_CPU_SENSE AY18 VDD_095_FB_H 1 APU_VDDCORE_SEN_H 49

D

APU_TMS G15 TCK VDDP_SENSE TC26 @

QC6B APU_TRST# TMS APU_VSS_SEN_L
2

1
J14 H12 RC2361 @ 2 0_0402_5%
G

DMN5L06DWK-7 2N SOT363-6 APU_DBRDY C13 TRST_L VSS_SENSE APU_VDD_SEN_L 49 +3VALW_APU RC74

APU_DBREQ# A11 DBRDY RC2371 @ 2 0_0402_5% 4.7K_0402_5%
DBREQ_L APU_VDDGFX_SEN_L 50
@
APU_SID

2
1 6
S

EC_SMB_DA3 16,30,35

2
RC73
D

APU_SVD PCH_ENVDD 23
FP4 REV 0.93 10K_0402_5%
QC6A APU_SVC @ @
DMN5L06DWK-7 2N SOT363-6 AMD-CARRIZO_FP4-BGA968
1

3
1 CC1283 D
CC1281 1000P_0201_50V7-K 5 QC9B
1000P_0201_50V7-K G DMN5L06DWK-7 2N SOT363-6
2 APU_VDDNB_SEN_H 1 @ TC27
2 @ @
S
@ APU_VDDCORE_SEN_H

4
6
1 @ TC28 D
APU_GFX_SVD DP_ENVDD 2 QC9A
APU_GFX_SVC APU_VDD_SEN_L 1 @ TC29 G
1 DMN5L06DWK-7 2N SOT363-6
B
1 CC1284 @
B
APU_VDDGFX_SEN_H

1
CC1282 1000P_0201_50V7-K 1 @ TC30 S

1
1000P_0201_50V7-K RC13
2 APU_VDDGFX_SEN_L 1 @ TC31 100K_0402_5%
2 @
@
@

2
RC206 1 @ 2 0_0402_5%
With HDT+ Header LCD Power IC can change for PCH_ENVDD for cost down
+1.8VS +1.8VS
+3VS_APU
+1.8VS JHDT1 @ RPC5 +1.8VS +1.8VS
1 2 APU_TCK 8 1
1 2

2
7 2
3 4 APU_TMS 6 3 RC77
3 4 1
2

1
5 4 +3VALW_APU 2.2K_0402_5%
RC7 5 6 APU_TDI CC25 RC32 RC36
5 6 1K_0804_8P4R_5% 0.1U_0201_6.3V6-K 300_0402_5% 300_0402_5%
1K_0402_5% APU_TDO

1
2

2
7 8 HDT@
7 8 RC75
APU_TRST# 2 33_0402_5% APU_TRST#_R APU_PWROK_BUF PCH_ENBKL 23
1

2
RC76 1 HDT@ 9 10 UC6 10K_0402_5%
9 10 APU_PWROK 3 4 APU_PWROK_BUF
11 12 APU_RST#_BUF 2A 2Y
2 11 12

3
2 5 D
CC84 13 14 APU_DBRDY GND VCC 5 QC10B
13 14 APU_RST# 1 6 APU_RST#_BUF G
0.01U_0201_10V6K 1A 1Y DMN5L06DWK-7 2N SOT363-6
1 15 16 RC273 1 HDT@ 2 33_0402_5% APU_DBREQ#
15 16 HDT@ SN74LVC2G07YZPR_WCSP6 S
APU_TEST19_PLLTEST0

4
8
7
6
5

6
17 18 D
RPC17 17 18 DP_ENBKL 2 QC10A
19 20 APU_TEST18_PLLTEST1 G
10K_0804_8P4R_5% 19 20 DMN5L06DWK-7 2N SOT363-6
HDT@

1
S
1
2
3
4

1
A RC14 A
SAMTE_ASP-136446-07-B APU_DBREQ# APU_TDI 100K_0402_5%

2 2

2
RC2071 2 0_0402_5%
CC213 CC212
0.01U_0201_10V6K 0.01U_0201_10V6K @
1 HDT@ 1 @
Security Classification LC Future Center Secret Data Title
Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP4 (DISPLAY/CLK/MISC)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
320ABR 0.1

Date: Thursday, January 12, 2017 Sheet 6 of 50

5 4 3 2 1
 5 4 3 2 1

+3VALW_APU
RC46 1 2 33_0402_5% LPC_RST#_R
30,35 APU_LPC_RST#
BOARD_ID3 BOARD_ID4
1 DRAM APIO15 AGPIO13
CC20
Config.

2
150P_0402_50V8-J
Hynix 0 0 RC39 RC40 RC41 RC257 RC265 RC263 RC268
2
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 2K_0402_5%
Micron 0 1 BD17@ UMA@ NOKBL@ @ @ TS@ @
BOARD_ID0

1
PCIE_RST#_R 1 0 BOARD_ID1
RC38 1 2 33_0402_5%
15,28,31 PLT_RST# BOARD_ID2
Samsung 1 1 BOARD_ID3
BOARD_ID4

1
1 BOARD_ID5 ID2--5 internal pull up 40K
RC43
@ 100K_0402_5% CC19 BOARD_ID6 ID6 internal pull low 40K
D D
100P_0201_25V8J
2 2

2
RC47 RC269 RC49 RC258 RC264 RC266 RC267
10K_0402_5% 10K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 10K_0402_5%
PX@ KBL@ @ @ NOTS@ @
BD15@

1
+1.8VALW

RC243 2 1 0_0402_5%

1
Connected to 10-ms RC-delay circuit on VDD_18_S5 power rail.
RC53
10K_0402_5%
(CRB PWR Dealy: 22K/0.1uF) UC2D
ACPI/SD/AZ/GPIO/RTC/I2C/UART/MI SC
DC1 LPC_RST#_R BB12 BB2 @1 TC61
LPC_RST_L SD0_WP/EGPIO101

2
1 2 RSMRST#_R PCIE_RST#_R AN7 BB5 @1
35 EC_RSMRST# TC44
PCIE_RST_L/EGPIO26 SD0_PWR_CTRL/AGPIO102 BC2 @1
SD0_CD/AGPIO25 TC71
RB751V-40_SOD323-2 @ RSMRST#_R AE4 BB4 @1
1 RSMRST_L SD0_CLK/EGPIO95 TC45
EC set RSMRST OD output CC21 AY5 @1
PBTN_OUT# RC191 PWRBTN#_R SD0_CMD/EGPIO96 TC59
0.1U_0402_25V6 1 @ 2 0_0402_5% AE1
35 PBTN_OUT# SYS_PWRGD_R PWR_BTN_L/AGPIO0
BC9
2 SYS_RESET# AF2 PWR_GOOD
11 SYS_RESET# PCIE_WAKE#_RA AG2 SYS_RESET_L/AGPIO1 BC3 @1 TC62
WAKE_L/AGPIO2 SD0_DATA0/EGPIO97 BA3 @1 TC63
PM_SLP_S3# RC193 1 @ 2 0_0402_5% PM_SLP_S3#_R AK7 SD0_DATA1/EGPIO98 BC5 @1 TC64
35 PM_SLP_S3# PM_SLP_S5# RC194 PM_SLP_S5#_R SLP_S3_L SD0_DATA2/EGPIO99
1 @ 2 0_0402_5% AH5 BA5 @1 TC65
35 PM_SLP_S5# SLP_S5_L SD0_DATA3/EGPIO100 BB6 @1 TC72
BOARD_ID1 AE8 SD0_LED/EGPIO93
APU_S5_MUX_CTRL AH8 S0A3_GPIO/AGPIO10 BA15 APU_SMB_CLK
9 APU_S5_MUX_CTRL S5_MUX_CTRL/EGPIO42 SCL0/I2C2_SCL/EGPIO113 APU_SMB_DATA APU_SMB_CLK 12,31
AY17
TEST0 AH6 SDA0/I2C2_SDA/EGPIO114
RPC2
APU_SMB_DATA 12,31 DIMM1, DIMM2, Mini CARD
TEST1 AK8 TEST0 AG5 SCL1 1 4 +1.8VS
TEST2 AE3 TEST1/TMS SCL1/I2C3_SCL/AGPIO19 AG4 SDA1 2 3
+3VS_APU TEST2 SDA1/I2C3_SDA/AGPIO20 @
C KBRST# AY15 10K_0404_4P2R_5% RPC21 C
35 KBRST# ESPI_RESET_L/KBRST_L/AGPIO129 TP_I2C0_SCL_R
BC19 3 2
35 GATEA20 GA20IN/AGPIO126 TP_I2C0_SDA_R
1

AD7 AL5 4 1
35 EC_SCI# BB13 LPC_PME_L/AGPIO22 AGPIO3 AL6 AGPIO3 11
RC72
10K_0402_5% LPC_SMI_L/AGPIO86 AGPIO4 AJ1 AGPIO5 2.2K_0404_4P2R_5%
@ AC_PRESENT AG3 AGPIO5 AJ3 LDT_RST_L @1 TC67 +3VS_APU
35 AC_PRESENT BOARD_ID4 AC_PRES/USB_OC4_L/IR_RX0/AGPIO23 AGPIO6/LDT_RST_L LDT_PWROK
AD5 AH1 @1 TC68
BOARD_ID5 IR_TX0/USB_OC5_L/AGPIO13 AGPIO7/LDT_PWROK BOARD_ID0
2

AL8 AJ4 RPC9

RC95 1 @ 2 0_0402_5% SYS_PWRGD_R BOARD_ID3 AN8 IR_TX1/USB_OC6_L/AGPIO14 AGPIO8 AK5 BOARD_ID6 APU_SMB_CLK 3 2
35 EC_SYS_PWRGD IR_RX1/AGPIO15 AGPIO9 VDDGFX_PD APU_SMB_DATA
1 AGPIO12 AE2 AD8 4 1
PCH_WLAN_OFF# IR_LED_L/LLB_L/AGPIO12 VDDGFX_PD/AGPIO39 VDDGFX_PD 35
BC15 AG8 AGPIO40
31 PCH_WLAN_OFF# WLAN_CLKREQ# CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/AGPIO92 AGPIO40
CC22 BB17 AW15 AGPIO64 RC278 1 @ 2 0_0402_5% 2.2K_0404_4P2R_5%
0.1U_0201_6.3V6-K 31 WLAN_CLKREQ# LAN_CLKREQ# CLK_REQ1_L/AGPIO115 AGPIO64 VR_GFX_PWRGD 35,50
BC17 AU15 RPC6
2 28 LAN_CLKREQ# PCH_BT_OFF# BB18 CLK_REQ2_L/AGPIO116 AGPIO65 PCH_PWRBT# 35 8 1
KBRST#
31 PCH_BT_OFF# GPU_CLKREQ# CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/EGPIO131 APU_SHUTDOWN# WLAN_CLKREQ#
BB16 AT15 7 2
16 GPU_CLKREQ# BOARD_ID2 CLK_REQG_L/OSCIN/EGPIO132 AGPIO66/SHUTDOWN_L APU_SHUTDOWN# 16 PCH_BT_OFF#
AH9 AU12 6 3
USB_OC1# AG1 USB_OC0_L/TRST_L/AGPIO16 AGPIO68/SGPIO_CLK AT14 PCH_TP_INT# PCH_WLAN_OFF# 5 4
25 USB_OC1# USB_OC2# AH2 USB_OC1_L/TDI/AGPIO17 AGPIO69/SGPIO_LOAD AR14 PCH_TP_INT# 36
AL9 USB_OC2_L/TCK/AGPIO18 AGPIO71/SGPIO_DATAOUT BC13 10K_0804_8P4R_5%
USB_OC3_L/TDO/AGPIO24 AGPIO72/SGPIO_DATAIN
HDA_BITCLK AU6 BA17
AZ_BITCLK/I2S_BCLK_MIC SPKR/AGPIO91 PCH_BEEP 32
RC201 1 2 0_0402_5% HDA_SDIN0_R AR8
32 HDA_SDIN0 HDA_SDIN1 AP6 AZ_SDIN0/I2S_DATA_MIC0 AN5 BLINK
HDA_SDIN2 AR5 AZ_SDIN1/I2S_LR_PLAYBACK BLINK/USB_OC7_L/AGPIO11
HDA_RST# AU9 AZ_SDIN2/I2S_DATA_MIC1 BB14 HVB_EN
HDA_SYNC AZ_RST_L/I2S_LR_MIC GENINT1_L/AGPIO89 VR_VGA_PWRGD HVB_EN 11,35 LAN_CLKREQ#
AT9 BA19 RC67 1 2 10K_0402_5%
HDA_SDOUT AZ_SYNC/I2S_BCLK_PLAYBACK GENINT2_L/AGPIO90 VR_VGA_PWRGD 15,48
AR7 GATEA20 RC78 1 2 10K_0402_5%
AZ_SDOUT/I2S_DATA_PLAYBACK BC18 PXS_PWREN_R RC109 1 @ 2 0_0402_5% GPU_CLKREQ# RC64 1 UMA@2 10K_0402_5%
TP_I2C0_SCL_R FANIN0/AGPIO84 PXS_PWREN 19,47,48APU_SHUTDOWN#
BB10 BB19 RC96 1 @ 2 2K_0402_5%
PCIE_WAKE#_RA RC88 2 36 TP_I2C0_SCL_R TP_I2C0_SDA_R I2C0_SCL/EGPIO145 FANOUT0/AGPIO85 PCH_TP_INT#
1 BB9 1 2
0_0402_5% 1
RPC3
4
Touch pad 36 TP_I2C0_SDA_R
I2C1SCL BB7 I2C0_SDA/EGPIO146 AY9
RC1655 10K_0402_5%

2 3 I2C1SDA BC7 I2C1_SCL/EGPIO147 UART0_CTS_L/EGPIO135 AW8

AGPIO5 RC92 2 1 I2C1_SDA/EGPIO148 UART0_RXD/EGPIO136 AV5 +3VALW_APU
PCIE_WAKE# 28,31,35 UART0_RTS_L/EGPIO137
0_0402_5% 10K_0404_4P2R_5% AG7 AV8
11,31 SUSCLK RTCCLK UART0_TXD/EGPIO138 AW9
2 1 DC3 UART0_INTR/AGPIO139 RPC15
32K_X1 AT1 AV11 PBTN_OUT# 1 8
SDM10U45LP-7_DFN1006-2-2 X32K_X1 UART1_CTS_L/BT_I2S_BCLK/EGPIO140 AU7 AC_PRESENT 2 7
B UART1_RXD/BT_I2S_SDI/EGPIO141 B
@ DC4 AT11 PCIE_WAKE#_RA 3 6
SYS_RESET# 1 2 SYS_PWRGD_R UART1_RTS_L/EGPIO142 AR11 AGPIO5 4 5
+3VALW_APU RC102 32K_X2 AT2 UART1_TXD/BT_I2S_SDO/EGPIO143 AP9
RB751V-40_SOD323-2 1 2 X32K_X2 UART1_INTR/BT_I2S_LRCLK/AGPIO144 10K_0804_8P4R_5%
FP4 REV 0.93
1 @ 20M_0402_5% RPC16
YC1 @ USB_OC1# 1 4
AMD-CARRIZO_FP4-BGA968 USB_OC2#
2

CC38 1 2 2 3
RC84 RC85 RC20 0.1U_0201_6.3V6-K Max ESR < 65K ohm !!
2 32.768KHZ_12.5PF_202740-PG14 10K_0404_4P2R_5%
2.2K_0402_5% 1K_0402_5% 2.2K_0402_5%
AGPIO12 RC141 1 2 10K_0402_5%
20P_0402_50V8

20P_0402_50V8

@ @ @ PM_SLP_S3# 1 2 2.2K_0402_5%
1 1
change YC1 PN to ESPON S CRYSTAL 32.768KHZ X1A000141000300, footprint no change RC203 @
1

TEST0 PM_SLP_S5# RC208 1 @ 2 2.2K_0402_5%

CC23

CC210

TEST1
TEST2 BLINK RC158 1 @ 2 10K_0402_5%
2 2 VDDGFX_PD RC247 1 @ 2 10K_0402_5%
2

RC195 RC196 RC197

15K_0402_5% 15K_0402_5% 15K_0402_5% BLINK isn't strap pin, don't need pull high
2/22: change to 50K ohm for Crystal vendor suggest
1

RPC4 AGPIO40 RC93 1 2 10K_0402_5%

1 8 HDA_RST# PCH_TP_INT# RC248 1 @ 2 10K_0402_5%

32 HDA_RST_AUDIO# HDA_SYNC
2 7
32 HDA_SYNC_AUDIO 3 6 HDA_BITCLK
32 HDA_BITCLK_AUDIO HDA_SDOUT
4 5
32 HDA_SDOUT_AUDIO
33_0804_8P4R_5%

+3VS_APU VDDGFX_PD RC250 1 @ 2 10K_0402_5%

2

2
1K_0402_5%

1K_0402_5%

1K_0402_5%
GPU_CLKREQ# RC65 1 PX@ 2 2K_0402_5%
RC260

RC261

RC262
RC98 1 PX@ 2 10K_0402_5% PXS_PWREN_R
RC101 1 @ 2 100K_0402_5% HDA_BITCLK RC90 1 2 1K_0402_5%
HDA_SDIN0_R RC91 1 @ 2 10K_0402_5%
APU_SHUTDOWN#
1

1
RC256 1 @ 2 2K_0402_5%
A A
RSMRST#_R RC87 1 2 100K_0402_5%
USB_OC2# RC1654 1 2 0_0402_5% SYS_PWRGD_R RC89 1 2 100K_0402_5%
+3VS_APU TYPE_C_OCP# 26
HDA_SDIN2 RC241 1 2 10K_0402_5%
HDA_SDIN1 RC242 1 2 10K_0402_5%
RC100 1 @ 2 10K_0402_5% VR_VGA_PWRGD
RC104 1 UMA@2 2K_0402_5%

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP4 (GEVENT/GPIO/SD/AZ)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
PXS_PWREN_R/PXS_RST#_R/VR_VGA_PWRGD internal pull up 40k DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
320ABR 0.1

Date: Thursday, January 12, 2017 Sheet 7 of 50

5 4 3 2 1
 5 4 3 2 1

UC2E
CLK/SATA/USB/SPI/LPC
SATA_PTX_DRX_P0 AU3 AP8 CLK_USB48M 1 @ TC69
34 SATA_PTX_DRX_P0 SATA_PTX_DRX_N0 SATA_TX0P USBCLK/25M_48M_OSC
AU4
34 SATA_PTX_DRX_N0 SATA_TX0N USB_RCOMP
HDD AP5 RC112 1 2 11.8K_0402_1%
SATA_PRX_DTX_N0 AV1 USB_ZVSS
34 SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 SATA_RX0N USB20_P0
AV2 AR2
34 SATA_PRX_DTX_P0 SATA_RX0P USB_HSD0P USB20_N0 USB20_P0 31
AR1 Blue Tooth
SATA_PTX_DRX_P1 USB_HSD0N USB20_N0 31
AY2
34 SATA_PTX_DRX_P1 SATA_PTX_DRX_N1 SATA_TX1P USB20_P1
AY1 AR3
34 SATA_PTX_DRX_N1 SATA_TX1N USB_HSD1P USB20_N1 USB20_P1 23
ODD AR4 Camera
SATA_PRX_DTX_N1 USB_HSD1N USB20_N1 23
AW4
D 34 SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 SATA_RX1N USB20_P2 D
AW3 AN2
34 SATA_PRX_DTX_P1 SATA_RX1P USB_HSD2P USB20_N2 USB20_P2 23
AN1 Touch screen
+1.05VS SATA_CALRN USB_HSD2N USB20_N2 23
RC113 1 2 1K_0402_1% AW1
RC114 1 2 1K_0402_1% SATA_CALRP AW2 SATA_ZVSS AN3 USB20_P3
SATA_ZVDDP USB_HSD3P USB20_N3 USB20_P3 36
RC270 1 2 10K_0402_5% EGPIO67 AT17 AN4 Finger print
DEVSLP0/EGPIO67 USB_HSD3N USB20_N3 36
RC271 1 2 10K_0402_5% EGPIO70 AT12
RC143 1 2 10K_0402_5% AGPIO130 BB15 DEVSLP1/EGPIO70 AM1 USB20_P4
SATA_ACT_L/AGPIO130 USB_HSD4P USB20_N4 USB20_P4 32
AM2 Card Reader
USB_HSD4N USB20_N4 32
AU2
SATA_X1 AL2 USB20_P5
USB_HSD5P USB20_N5 USB20_P5 25
AL1 LEFT USB (3.0) upper
USB_HSD5N USB20_N5 25
AU1 AL3 USB20_P6
SATA_X2 USB_HSD6P USB20_N6 USB20_P6 25
AL4 LEFT USB (3.0) lower
USB_HSD6N USB20_N6 25
CLK_PCIE_GPU RC117 1 2 0_0402_5% CLK_PCIE_GPU_R U4 AK2 USB20_P7
15 CLK_PCIE_GPU CLK_PCIE_GPU# GFX_CLKP USB_HSD7P USB20_P7 26
RC118 1 2 0_0402_5% CLK_PCIE_GPU#_R U3 AJ2 USB20_N7 Type C
15 CLK_PCIE_GPU# GFX_CLKN USB_HSD7N USB20_N7 26
U1
U2 GPP_CLK0P
GPP_CLK0N
CLK_PCIE_W LAN RC119 1 2 0_0402_5% CLK_PCIE_W LAN_R W4
31 CLK_PCIE_W LAN CLK_PCIE_W LAN# GPP_CLK1P
RC120 1 2 0_0402_5% CLK_PCIE_W LAN#_R W3
31 CLK_PCIE_W LAN# GPP_CLK1N USB3.0 port0 must map to USB2.0 port4,
28 CLK_PCIE_LAN
CLK_PCIE_LAN
CLK_PCIE_LAN#
RC121 1 2 0_0402_5% CLK_PCIE_LAN_R W1
GPP_CLK2P
USB3.0 port1 must map to USB2.0 port5,
RC122 1 2 0_0402_5% CLK_PCIE_LAN#_R W2
28 CLK_PCIE_LAN# GPP_CLK2N USB3.0 port2 must map to USB2.0 port6,
Y2
Y1 GPP_CLK3P USB3.0 port4 must map to USB2.0 port7
GPP_CLK3N
C C
TC53 @ 1 X14M_25M_48M_OSC BC10
X25M_48M_OSC AD2 USBSS_CALRN RC123 1 2 1K_0402_1% +1.05VALW
USB_SS_ZVSS AD1 USBSS_CALRP RC124 1 2 1K_0402_1%
48M_X1 T2 USB_SS_ZVDDP
X48M_X1 AA3
USB_SS_0TXP AA4
USB_SS_0TXN
48M_X2 T1 W9
X48M_X2 USB_SS_0RXP W8
RC125 1 TPM@ 2 22_0402_5% USB_SS_0RXN
30 TPM_CLK USB30_TX_P1
RC126 1 2 3.3_0402_1% LPCCLK0 AW14 AA2
11,35 CLK_PCI_EC LPCCLK0/EGPIO74 USB_SS_1TXP USB30_TX_N1 USB30_TX_P1 25
RC127 1 @ 2 0_0402_5% LPCCLK1 AY13 AA1
11 LPC_CLK1 LPCCLK1/EGPIO75 USB_SS_1TXN USB30_TX_N1 25
LEFT USB (3.0) upper
+3VS_APU BB11 W5 USB30_RX_P1
30,35 LPC_AD0 LAD0 USB_SS_1RXP USB30_RX_N1 USB30_RX_P1 25
BA11 W6
30,35 LPC_AD1 LAD1 USB_SS_1RXN USB30_RX_N1 25
30,35 LPC_AD2 AY11
RC99 1 @ 2 10K_0402_5% PXS_RST# BA13 LAD2 AC1 USB30_TX_P2
30,35 LPC_AD3 LAD3 USB_SS_2TXP USB30_TX_P2 25
RC103 1 2 10K_0402_5% AV14 AC2 USB30_TX_N2
11,30,35 LPC_FRAME# LFRAME_L USB_SS_2TXN USB30_TX_N2 25
TC54 @ 1 BA1 LEFT USB (3.0) lower
BC14 ESPI_ALERT_L/LDRQ0_L Y6 USB30_RX_P2
30,35 SERIRQ SERIRQ/AGPIO87 USB_SS_2RXP USB30_RX_P2 25
BC11 Y7 USB30_RX_N2
30 LPC_CLKRUN# LPC_CLKRUN_L/AGPIO88 USB_SS_2RXN USB30_RX_N2 25
1 2 10K_0402_5% AGPIO21 AE9
RC149 LPC_PD_L/AGPIO21 AC4 USB30_TX_P3
USB_SS_3TXP USB30_TX_N3 USB30_TX_P3 26
AC3
PCH_SPI_CLK SPI_CLK USB_SS_3TXN USB30_TX_N3 26
RC209 1 2 0_0402_5% BC6
PCH_SPI_CS0# RC202 1 2 0_0402_5% SPI_CS0# BB8 SPI_CLK/ESPI_CLK/EGPIO117 AB5 USB30_RX_P3
SPI_CS1_L/EGPIO118 USB_SS_3RXP USB30_RX_P3 26 Type C
RC144 1 2 10K_0402_5% EGPIO119 AW7 AB6 USB30_RX_N3
PCH_SPI_D1 SPI_D1 SPI_CS2_L/ESPI_CS_L/EGPIO119 USB_SS_3RXN USB30_RX_N3 26
RC199 1 2 0_0402_5% BA9
PCH_SPI_D0 RC198 1 2 0_0402_5% SPI_D0 AY7 SPI_DI/ESPI_DATA/EGPIO120
B PCH_SPI_D2 RC132 1 2 0_0402_5% SPI_D2 AW11 SPI_DO/EGPIO121 B
PCH_SPI_D3 1 2 SPI_D3 BA7 SPI_WP_L/EGPIO122
RC133 0_0402_5%
SPI_HOLD_L/EGPIO133
Connect the four USB 3.0 ports to onboard devices first
RC116 1 @ 2 0_0402_5% AW12 starting from the lower ports and then the remaining
15 PXS_RST# SPI_TPM_CS_L/AGPIO76
FP4 REV 0.93
ports can be used for routing to USB 3.0 connectors.
Less than four USB 3.0 ports can be utilized provided
@ AMD-CARRIZO_FP4-BGA968 the unused ports are higher-numbered consecutive
ports.
+1.8VS None of the four USB 3.0 ports can be configured
as USB 2.0 external ports.
48MHz/10pF Crystal 48M_X1
PCH_SPI_D2 RC254 1 2 10K_0402_5%
PCH_SPI_D3 RC255 1 2 10K_0402_5% 48M_X2
PCH_SPI_CS0# RC253 1 2 10K_0402_5% PCH_SPI_CLK

+1.8VS LPCCLK1 RC140 1 2 1M_0402_5%

UC3

2
LPCCLK0
PCH_SPI_CS0# 1 8 50mA
PCH_SPI_D1 /CS VCC PCH_SPI_D3 YC2
1

2 7 1 RC139 change YC2 PN to TXC 48MHZ 10PF X1E000021083400

PCH_SPI_D2 DO(IO1) /HOLDor/RESET(IO3) PCH_SPI_CLK
1

3 6 RC281 10_0402_5% footprint apply is on going

4 /WP(IO2) CLK 5 PCH_SPI_D0 CC204 RC282 0_0201_5% EMC_NS@ 1 4
GND DI(IO0) OSC1 NC2

1
0.1U_0201_6.3V6-K 0_0201_5% EMC_NS@
2 EMC_NS@ 2 3
NC1 OSC2
2

W 25Q64FW SSIQ_SO8 1
2

CC26 1 1
1 10P_0201_25V8G
CC218 EMC_NS@ CC28 48MHZ_10PF_7V48000017 CC29
8M ROM 1
CC219 22P_0201_25V8 2 10P_0402_50V8-J 12P_0402_50V8-J
22P_0201_25V8 EMC_NS@ 2 2
A
2 EMC A
EMC_NS@
2
EMC
EMC

Security Classification LC Future Center Secret Data Title

CC219 and CC218 should 27pf as EMC suggest
Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP4 (SATA/USB/LPC/SPI)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 320ABR
Date: Thursday, January 12, 2017 Sheet 8 of 50
5 4 3 2 1
 5 4 3 2 1

+1.2V UC2F +APU_CORE +APU_CORE

POWER
+1.2V P25 U8
3A P28 VDDIO_MEM_S3_1 VDDCR_CPU_1 W7

180P_0402_50V8-J
0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K
T24 VDDIO_MEM_S3_2 VDDCR_CPU_2 W12
T27 VDDIO_MEM_S3_3 VDDCR_CPU_3 W15

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K
VDDIO_MEM_S3_4 VDDCR_CPU_4 1 1 1 1 1 1 1 1 1
U25 W18

180P_0402_50V8-J

CC129

CC130

CC131

CC132

CC133

CC134

CC135

CC136

CC137
U28 VDDIO_MEM_S3_5 VDDCR_CPU_5 W21
1 1 1 1 1 1 1 VDDIO_MEM_S3_6 VDDCR_CPU_6
+1.2V V30 Y8

CC157

CC158

CC159

CC160

CC161

CC163

CC165
V33 VDDIO_MEM_S3_7 VDDCR_CPU_7 Y10 2 2 2 2 2 2 2 2 2
W24 VDDIO_MEM_S3_8 VDDCR_CPU_8 Y13
2 2 2 2 2 2 2 W27 VDDIO_MEM_S3_9 VDDCR_CPU_9 Y16
Y25 VDDIO_MEM_S3_10 VDDCR_CPU_10 Y19 SIT1CD@ SIT1CD@
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
Y28 VDDIO_MEM_S3_11 VDDCR_CPU_11 Y22
1 1 1 1 1 1 1 1 1 1 1
SIT1CD@ Y30 VDDIO_MEM_S3_12 VDDCR_CPU_12 AB7
OK
SIT1CD@
CC42

CC54

CC55

CC56

CC57

CC58

CC59

CC60

CC53

CC61

CC62
AB24 VDDIO_MEM_S3_13 VDDCR_CPU_13 AB9
OK AB27 VDDIO_MEM_S3_14 VDDCR_CPU_14 AB12
D D
@ 2 2 2 2 2 2 2 2 @ 2 @ 2 2 AB30 VDDIO_MEM_S3_15 VDDCR_CPU_15 AB15 +APU_GFX
AB33 VDDIO_MEM_S3_16 VDDCR_CPU_16 AB18
AD25 VDDIO_MEM_S3_17 VDDCR_CPU_17 AB21
AD28 VDDIO_MEM_S3_18 VDDCR_CPU_18 AD6

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K
SIT1CD@ SIT1CD@ SIT1CD@ VDDIO_MEM_S3_19 VDDCR_CPU_19
AD30 AD10

180P_0402_50V8-J
DVDD_IO +VDDIO_AZ_APU AE24 VDDIO_MEM_S3_20 VDDCR_CPU_20 AD13
VDDIO_MEM_S3_21 VDDCR_CPU_21 1 1 1 1 1 1 1 1 1 1
RC212 1 2 0_0402_5% AE27 AD16

CC147

CC148

CC149

CC150

CC151

CC152

CC153

CC154

CC156

CC155
AF30 VDDIO_MEM_S3_22 VDDCR_CPU_22 AD19
Wake-on-Ring not supported:

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
AF33 VDDIO_MEM_S3_23 VDDCR_CPU_23 AD22
+VDDIO_AZ_APU Connect to +1.5V S0 rail 1 1 1 VDDIO_MEM_S3_24 VDDCR_CPU_24
AG25 AE7 2 2 2 2 2 2 2 2 2 2

CC184

CC185

CC193
AG28 VDDIO_MEM_S3_25 VDDCR_CPU_25 AE12
AH24 VDDIO_MEM_S3_26 VDDCR_CPU_26 AK9
SIT1CD@ 2 2 2 AH27 VDDIO_MEM_S3_27 VDDCR_CPU_42 AG10 SIT1CD@ SIT1CD@
+1.05VS +1.05VS_GFX_APU AH30 VDDIO_MEM_S3_28 VDDCR_CPU_31 AK10
1 2 0_0805_5% AK25 VDDIO_MEM_S3_29 VDDCR_CPU_43 AG13
OK
RC210

0.22U_0201_6.3V6-K
AK28 VDDIO_MEM_S3_30 VDDCR_CPU_32 AK13

10U_0603_6.3V6M
AK30 VDDIO_MEM_S3_31 VDDCR_CPU_44 AG16

100_0402_5%
1 1 VDDIO_MEM_S3_32 VDDCR_CPU_33

1
AK33 AK16

CC180

CC181
AL27 VDDIO_MEM_S3_33 VDDCR_CPU_45 AG19 +1.2V

RC229
AM30 VDDIO_MEM_S3_34 VDDCR_CPU_34 AK19
2 2 VDDIO_MEM_S3_35 VDDCR_CPU_46 AG22
AR19 VDDCR_CPU_35 AK22
@ 0.2A

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K
VDDIO_AUDIO VDDCR_CPU_47

2
AH7

180P_0402_50V8-J

180P_0402_50V8-J
AE6 VDDCR_CPU_36 AE18
+3VS
1.5A AE5 VDDP_GFX_2 VDDCR_CPU_28 AE21
1 1 1 1 1 1

CC168

CC169

CC170

CC172

CC179

CC176
RC214 +3VS_APU VDDP_GFX_1 VDDCR_CPU_29 AH21
1 2 AP19 VDDCR_CPU_40 AG6
10U_0603_6.3V6M

0.2A AP21 VDD_33_1 VDDCR_CPU_30 AH12 2 2 2 2 2 2

1 VDD_33_2 VDDCR_CPU_37
0_0402_5% +1.8VS AN6
CC187

AP16 VDDCR_CPU_49 AH15

1.5A
0.22U_0201_6.3V6-K

AP18 VDD_18_1 VDDCR_CPU_38 AH18 SIT1CD@

10U_0603_6.3V6M

SIT1CD@
2 +1.8VALW VDD_18_2 VDDCR_CPU_39 AL7
1 1
AP10 VDDCR_CPU_48 AK6
DECOUPLING BETWEEN PROCESSOR AND DIMMs
0.5A
CC186

CC173

AR9 VDD_18_S5_1 VDDCR_CPU_41 AE15 ACROSS VDDIO AND VSS SPLIT

0.22U_0201_6.3V6-K
+3VALW_APU VDD_18_S5_2 VDDCR_CPU_27 +APU_GFX
10U_0603_6.3V6M

2 2 AP15
1 1 0.2A AR15 VDD_33_S5_1 L8
CC188

CC189

0.22U_0201_6.3V6-K
+1.05VALW VDD_33_S5_2 VDDCR_GFX_14 L13

10U_0603_6.3V6M
AN12 VDDCR_GFX_15 L16
0.8A Design Guide G FP4 CRB

0.22U_0201_6.3V6-K
1 1 VDDP_S5_1 VDDCR_GFX_16
2 2 AP12 L19

10U_0603_6.3V6M
CC190

CC191
C +VDDCR_FCH_S5 VDDP_S5_2 VDDCR_GFX_17 L22 9*22uf 0603 9*22uf 0805 13*22uf 0603 C
1 1 VDDCR_GFX_18
0.2A AP13 N7 VDDCR_CPU 8*0.22uf 0402 8*0.22uf 0402 8*0.22uf 0402

CC182

CC183
+1.05VS 2 2 AR12 VDDCR_FCH_S5_1 VDDCR_GFX_19 N12 1*180pf 0402 1*180pf 0402 1*180pf 0402
+1.05VS VDDCR_FCH_S5_2 VDDCR_GFX_20 N15 4*22uf 0603 4*22uf 0805 6*22uf 0603
2 2 AW19 VDDCR_GFX_21 N18 8*0.22uf 0402 8*0.22uf 0402 8*0.22uf 0402 split *5
7A VDDCR_NB
0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

AU17 VDDP_6 VDDCR_GFX_22 N21 1*180pf 0402 1*180pf 0402 1*180pf 0402
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

180P_0402_50V8-J

AU19 VDDP_1 VDDCR_GFX_23 P8 9*22uf 0603 10*22uf 0805 13*22uf 0603

1 1 1 1 1 1 1 1 1 1 1 1 VDDP_2 VDDCR_GFX_24
CC217 AV17 P13 VDDCR_GFX 9*0.22uf 0402 9*0.22uf 0402 9*0.22uf 0402
CC175

CC174

CC171

CC167

CC178

CC177

CC197

CC198

CC201

CC202

CC203

47P_0402_50V8J AV19 VDDP_3 VDDCR_GFX_25 P16 1*180pf 0402 1*180pf 0402 1*180pf 0402
RF_NS@ AW17 VDDP_4 VDDCR_GFX_26 P19 8*22uf 0603 8*22uf 0603 8*22uf 0603
2 2 2 2 2 2 2 2 2 2 2 2 +APU_CORE_NB VDDP_5 VDDCR_GFX_27 P22 6*0.22uf 0402 split*4 6*0.22uf 0402 split*4 8*0.22uf 0402 split*4
AL12 VDDCR_GFX_28 T7
VDDIO_MEM_S3
12A 1*180pf 0402 split*2 1*180pf 0402 split*2 1*180pf 0402 split*2
AL13 VDDCR_NB_1 VDDCR_GFX_29 F12 2*10uf 0402 2*10uf 0603 2*10uf 0603
SIT1CD@ SIT1CD@ AL15 VDDCR_NB_2 VDDCR_GFX_1 F15 1*0.22uf 0402 1*0.22uf 0402 1*0.22uf 0402
AL18 VDDCR_NB_3 VDDCR_GFX_2 G11
VDDCR_FCH_S5
OK AL21 VDDCR_NB_4 VDDCR_GFX_3 G14 4*10uf 0402 4*10uf 0603 4*10uf 0603
AN13 VDDCR_NB_5 VDDCR_GFX_4 J8 1*0.22uf 0402 1*0.22uf 0402 1*0.22uf 0402
AN16 VDDCR_NB_6 VDDCR_GFX_5 J9
VDDP
1*180pf 0402 1*180pf 0402 1*180pf 0402
+APU_CORE_NB AN19 VDDCR_NB_7 VDDCR_GFX_6 J11 1*10uf 0402 1*10uf 0603 1*10uf 0603
AN22 VDDCR_NB_8 VDDCR_GFX_7 K7 1*0.22uf 0402 1*0.22uf 0402 1*0.22uf 0402
VDDCR_NB_9 VDDCR_GFX_8 K12
VDDP_GFX
+RTCBATT +RTCBATT_APU VDDCR_GFX_9 K13 1*10uf 0402 1*10uf 0603 1*10uf 0603
180P_0402_50V8-J
0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

RC6 1 2 AR17 VDDCR_GFX_10 K15 1*0.22uf 0402 1*0.22uf 0402 1*0.22uf 0402
VDDBT_RTC_G VDDCR_GFX_11 K16
VDDP_S5
1 1 1 1 1 1 1 1 1 1 1 1 1 1K_0402_5%
VDDCR_GFX_12 T12 1*22uf 0603 1*22uf 0603 1*22uf 0603
CC138

CC139

CC140

CC141

CC142

CC143

CC144

CC146

CC145

CC195

CC196

CC199

CC200

0.22U_0201_6.3V6-K
VDDCR_GFX_30 T15 1*10uf 0402 1*10uf 0402 1*10uf 0603
VDDCR_GFX_31 T18
VDD_18
1 VDDCR_GFX_32
2 2 2 2 2 2 2 2 2 @ 2 @ 2 @ 2 @ 2 T21 1*10uf 0402 1*10uf 0603 1*10uf 0603

CC192
VDDCR_GFX_33 U13 1*0.22uf 0402 1*0.22uf 0402 1*0.22uf 0402
VDDCR_GFX_34 U16
VDD_18_S5
SIT1CD@ SIT1CD@ 2 VDDCR_GFX_35 U19
VDDCR_GFX_36 U22 1*10uf 0402 1*10uf 0603 1*10uf 0603
OK follow CRB reserve VDDCR_GFX_37 K19
VDD_33
VDDCR_GFX_13 1*10uf 0402 1*10uf 0403 1*10uf 0603
FP4 REV 0.93
VDD_33_S5 1*0.22uf 0402 1*0.22uf 0402 1*0.22uf 0402
UC5
VCCRTC @ AMD-CARRIZO_FP4-BGA968
RC231 1 2 10K_0402_5% 1 VDDIO_AUDIO 3*1uf 0402 3*1uf 0402 3*1uf 0402
Vin
3 +RTCBATT
Vout 1*0.22uf 0402 1*0.22uf 0402 1*0.22uf 0402
VDDBT_RTC_G
1U_0402_6.3V6K

1U_0402_6.3V6K

B 2 B
1 GND 1
1

JCMOS1 RC8 @
CC37

CC194

SHORT PADS 470_0603_5%

AP2138N-1.5TRG1_SOT23-3 @
2

2 2
12

D QC7
2 EC_RTCRST#_ON
G EC_RTCRST#_ON 35 QC1/QC2/QC3/QC4 Rds on should less possible, CRB is 11.8mohm,
there is no load swtich for 0.775V power, so it need mos
1

+1.05VS S 2N7002KW_SOT323-3 RC15

3

@ 100K_0402_5%
@ +VDDCR_FCH_S5
CC224 EMC_NS@

CC225 EMC_NS@
0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

1 1

4.7U_0402_6.3V6M

0.22U_0201_6.3V6-K
22U_0603_6.3V6-M

10U_0603_6.3V6M

10U_0603_6.3V6M
1 1 1 1 1
2 2

CC128

CC126

CC162

CC164

CC166
2 2 2 2 2
OK EMC
+3VALW_APU SIT1CD@
Decoupling cap
near APU ball
1

RC230
100K_0402_5%
S5_MUX_CTRL: Enable MUX(S0 to S3)-->LOW
@
Disable MUX(S3 to S0)-->HIGH
2

+APU_CORE_NB +VDDCR_FCH_S5
UC7
1 8 RC277 1 2 0_0603_5%
APU_S5_MUX_CTRL VIN1_1 VOUT_1

10U_0603_6.3V6M
7 APU_S5_MUX_CTRL 2 7
VIN1_2 VOUT_2

1
+0.775VALW

CC207
3 6 APU_S5_MUX_CTRL
VIN2 SEL
1

+5VALW

10U_0603_6.3V6M
A A

2
RC272 4 5
VCC EN

1
100K_0402_5%

CC208

1U_0402_6.3V6K
@ 1 9
@ GND

CC209
2

2
G5018RD1U_TDFN8_3X3
2
@
@

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP4 (POWER&DECOUPLING)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
320ABR 0.1

Date: Thursday, January 12, 2017 Sheet 9 of 50

5 4 3 2 1
 5 4 3 2 1

UC2G UC2H
GND GND
A8 L28 AE10 AV30
A12 VSS_1 VSS_63 M4 AE13 VSS_125 VSS_187 AV33
A16 VSS_2 VSS_64 M30 AE16 VSS_126 VSS_188 AW22
A20 VSS_3 VSS_65 N10 AE19 VSS_127 VSS_189 AY4
A24 VSS_4 VSS_66 N13 AE22 VSS_128 VSS_190 AY6
A28 VSS_5 VSS_67 N16 AF1 VSS_129 VSS_191 AY8
D D
A32 VSS_6 VSS_68 N19 AF4 VSS_130 VSS_192 AY10
B2 VSS_7 VSS_69 N22 AG9 VSS_131 VSS_193 AY12
B8 VSS_8 VSS_70 N27 AG12 VSS_132 VSS_194 AY14
B12 VSS_9 VSS_71 P1 AG15 VSS_133 VSS_195 AY16
B33 VSS_10 VSS_72 P2 AG18 VSS_134 VSS_196 AY20
C3 VSS_11 VSS_73 P4 AG21 VSS_135 VSS_197 AY22
D4 VSS_12 VSS_74 P5 AH4 VSS_136 VSS_198 AY24
D6 VSS_13 VSS_75 P12 AH10 VSS_137 VSS_199 AY26
D8 VSS_14 VSS_76 P15 AH13 VSS_138 VSS_200 AY28
D10 VSS_15 VSS_77 P18 AH16 VSS_139 VSS_201 AY30
D12 VSS_16 VSS_78 P21 AH19 VSS_140 VSS_202 BB1
D14 VSS_17 VSS_79 P30 AH22 VSS_141 VSS_203 BB33
D16 VSS_18 VSS_80 P33 AK1 VSS_142 VSS_204 BC4
D18 VSS_19 VSS_81 T4 AK4 VSS_143 VSS_205 BC8
D20 VSS_20 VSS_82 T10 AK12 VSS_144 VSS_206 BC12
D22 VSS_21 VSS_83 T13 AK15 VSS_145 VSS_207 BC16
D24 VSS_22 VSS_84 T16 AK18 VSS_146 VSS_208 BC20
D26 VSS_23 VSS_85 T19 AL16 VSS_147 VSS_209 BC24
D28 VSS_24 VSS_86 T22 AL19 VSS_148 VSS_210 BC28
D30 VSS_25 VSS_87 T30 AL22 VSS_149 VSS_211 BC32
F1 VSS_26 VSS_88 U5 AM4 VSS_150 VSS_212
F2 VSS_27 VSS_89 U12 AN9 VSS_151
F4 VSS_28 VSS_90 U15 AN10 VSS_152
F9 VSS_29 VSS_91 U18 AN15 VSS_153
C
F19 VSS_30 VSS_92 U21 AN18 VSS_154 C
F22 VSS_31 VSS_93 U24 AN21 VSS_155
F25 VSS_32 VSS_94 V1 AN25 VSS_156
F30 VSS_33 VSS_95 V2 AN28 VSS_157
F33 VSS_34 VSS_96 V4 AP1 VSS_158
G7 VSS_35 VSS_97 W10 AP2 VSS_159
G17 VSS_36 VSS_98 W13 AP4 VSS_160
G20 VSS_37 VSS_99 W16 AP7 VSS_161
G23 VSS_38 VSS_100 W19 AP22 VSS_162
G26 VSS_39 VSS_101 W22 AP27 VSS_163
H4 VSS_40 VSS_102 Y4 AP30 VSS_164
H30 VSS_41 VSS_103 Y5 AP33 VSS_165
VSS_42 VSS_104 VSS_166 UC2J
J5 Y12 AR6
J15 VSS_43 VSS_105 Y15 AR25 VSS_167
J19 VSS_44 VSS_106 Y18 AR28 VSS_168 @ TC4 1 U30
J22 VSS_45 VSS_107 Y21 AT4 VSS_169 @ TC6 1 U31 RSVD_2
J25 VSS_46 VSS_108 Y24 AT19 VSS_170 @ TC5 1 AN30 RSVD_3
J28 VSS_47 VSS_109 AB1 AT22 VSS_171 RSVD_4
K1 VSS_48 VSS_110 AB2 AT30 VSS_172
K2 VSS_49 VSS_111 AB4 AU5 VSS_173
K4 VSS_50 VSS_112 AB10 AU8 VSS_174
K10 VSS_51 VSS_113 AB13 AU11 VSS_175
K22 VSS_52 VSS_114 AB16 AU14 VSS_176
K27 VSS_53 VSS_115 AB19 AU20 VSS_177
K30 VSS_54 VSS_116 AB22 AU23 VSS_178 FP4 REV 0.93
B B
K33 VSS_55 VSS_117 AD4 AU27 VSS_179
L5 VSS_56 VSS_118 AD9 AV4 VSS_180 @
VSS_57 VSS_119 VSS_181 AMD-CARRIZO_FP4-BGA968
L12 AD12 AV7
L15 VSS_58 VSS_120 AD15 AV9 VSS_182
L18 VSS_59 VSS_121 AD18 AV12 VSS_183 L24
L21 VSS_60 VSS_122 AD21 AV15 VSS_184 VSS_213 AL10
L25 VSS_61 VSS_123 AD24 AV25 VSS_185 VSS_215 AK21
VSS_62 VSS_124 VSS_186 VSS_214
FP4 REV 0.93 FP4 REV 0.93
@ AMD-CARRIZO_FP4-BGA968 @ AMD-CARRIZO_FP4-BGA968

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP4 (VSS)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 320ABR
Date: Thursday, January 12, 2017 Sheet 10 of 50
5 4 3 2 1
 5 4 3 2 1

+3VS +3VS +3VS +3VALW_APU +3VALW_APU +3VALW_APU +3VS_APU

2
RC152 RC153 RC154 RC155 RC156 RC157 RC81
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
@ @
D D

1
8,30,35 LPC_FRAME#

8 LPC_CLK1

8,35 CLK_PCI_EC

7 AGPIO3

7 SYS_RESET#

7,31 SUSCLK

7,35 HVB_EN

1
RC79
C RC159 RC160 RC161 RC162 RC163 RC164 C
2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 0_0402_5%
@ @ @ @ @
@

2
STRAP PINS

LFRAME_L LPCCLK1 LPCCLK0 RTCCLK SYS_RESET_L AGPIO3 HVB_EN

Signal
Int pull-up Int pull-up Int pull-up

Type II II II I I I

SPI ROM Internal Boot Fail Timer RTC Coin Battery is Normal Power Up Enhanced reset floating
PULL CLK Gen Enabled implemented &Reset Timing logic (for quicker
HIGH S5 resume) Disable HVB
Default Default Default on FP4 platforms
Default Default
Default
B B
Boot Fail Timer Reserved traditional connected to VSS
PULL LPC ROM Reserved Disabled RTC Coin Battery is reset logic
LOW not implemented Enable HVB
Default on FP4 platforms

Type I straps become valid immediately after capture with the rising edge of RSMRST_L,they are captured only once when power is first applied to the processor
Type II straps become valid after PWR_GOOD is asserted,straps are captured every time the systems powers up from the S5 state. A transition from S3 to S0 does not trigger capture.
Type II straps should be pulled up to S0 power rail to prevent leakage when the signal is connected to a device in S0 power domain.
If the LPC bus is connected to devices that are on S0 power rail, then a pull-up resistor to VDD_33 is implemented.

All Strap pins must be configured with either external pull-up or pull-down resistors.
Platforms that are designed for AOAC complaint are recommended to use the Alternate Reset by strapping this pin to ‘ 1’ for C
Z
AGPIO3

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP4 (STRAPS)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 320ABR
Date: Thursday, January 12, 2017 Sheet 11 of 50
5 4 3 2 1
 5 4 3 2 1

DDRA_DQ[0..63]
DDRA_DQ[0..63] 5
DDRA_DQS[0..7]
DDRA_DQS[0..7] 5
DDRA_DQS#[0..7]
DDRA_DQS#[0..7] 5
DDRA_MA[0..13]
DDRA_MA[0..13] 5
+1.2V +1.2V DDRA_DM[0..7]
DDRA_DM[0..7] 5
JDDR1B
Swap Table
DDRA_MA3 131 132 DDRA_MA2
JDDR1A
DDRA_MA1 A3 A2 MEM_MA_EVENT#
Pin Name Net Name
133 134
A1 EVENT_n MEM_MA_EVENT# 5
135 136 DQ0 DDRB_DQ6
1 2 DDRA_CLK0 137 VDD_9 VDD_10 138 DDRA_CLK1
D
DDRA_DQ1 VSS_1 VSS_2 DDRA_DQ4 5 DDRA_CLK0 DDRA_CLK0# CK0_t CK1_t DDRA_CLK1# DDRA_CLK1 5 DQ1 DDRB_DQ5 D
3 4 139 140
5 DQ5 DQ4 6
5 DDRA_CLK0#
141 CK0_c CK1_c 142 DDRA_CLK1# 5 DQ2 DDRB_DQ3
DDRA_DQ6 7 VSS_3 VSS_4 8 DDRA_DQ5 RD259 1 2 0_0402_5% 143 VDD_11 VDD_12 144 DDRA_MA0 DQ3 DDRB_DQ7
9 DQ1 DQ0 10 Parity A0 DQ4 DDRB_DQ4
DDRA_DQS#0 11 VSS_5 VSS_6 12 DDRA_DM0 DQ5 DDRB_DQ0
DDRA_DQS0 13 DQS0_C DM0_n/DBIO_n/NC 14 DDRA_BA1 145 146 DDRA_MA10
DQS0_t VSS_7 DDRA_DQ0 5 DDRA_BA1 BA1 A10/AP DQ6 DDRB_DQ1
15 16 147 148 DQ7 DDRB_DQ2
DDRA_DQ3 17 VSS_8 DQ6 18 DDRA_CS0# 149 VDD_13 VDD_14 150 DDRA_BA0
19 DQ7 VSS_9 20 DDRA_DQ7 5 DDRA_CS0# DDRA_MA14_WE# 151 CS0_n BA0 152 DDRA_MA16_RAS# DDRA_BA0 5 DQS#0 DDRB_DQS#0
DDRA_DQ2 VSS_10 DQ2 5 DDRA_MA14_WE# WE_n/A14 RAS_n/A16 DDRA_MA16_RAS# 5 DQS0 DDRB_DQS0
21 22 153 154
23 DQ3 VSS_11 24 DDRA_DQ12 DDRA_ODT0 155 VDD_15 VDD_16 156 DDRA_MA15_CAS#
DDRA_DQ9 25 VSS_12 DQ12 26 5 DDRA_ODT0 DDRA_CS1# 157 ODT0 CAS_n/A15 158 DDRA_MA13 DDRA_MA15_CAS# 5
DQ13 VSS_13 DDRA_DQ8 5 DDRA_CS1# CS1_n A13
DQ8 DDRB_DQ8
27 28 159 160 DQ9 DDRB_DQ13
DDRA_DQ13 29 VSS_14 DQ8 30 DDRA_ODT1 161 VDD_17 VDD_18 162 +VREF_CA
31 DQ9 VSS_15 32 DDRA_DQS#1 5 DDRA_ODT1 163 ODT1 C0/CS2_n/NC 164
DQ10 DDRB_DQ11
DDRA_DM1 33 VSS_16 DQS1_c 34 DDRA_DQS1 165 VDD_19 VREFCA 166 DDRA0_SA2 DQ11 DDRB_DQ10
35 DM1_n/DBl1_n/NC DQS1_t 36 167 C1/CS3_n/NC SA2 168 DQ12 DDRB_DQ12
DDRA_DQ14 37 VSS_17 VSS_18 38 DDRA_DQ15 DDRA_DQ33 169 VSS_53 VSS_54 170 DDRA_DQ36 DQ13 DDRB_DQ9
39 DQ15 DQ14 40 171 DQ37 DQ36 172
DDRA_DQ11 VSS_19 VSS_20 DDRA_DQ10 DDRA_DQ32 VSS_55 VSS_56 DDRA_DQ37
DQ14 DDRB_DQ15
41 42 173 174 DQ15 DDRB_DQ14
43 DQ10 DQ11 44 175 DQ33 DQ32 176
DDRA_DQ21 45 VSS_21 VSS_22 46 DDRA_DQ16 DDRA_DQS#4 177 VSS_57 VSS_58 178 DDRA_DM4 DQS#1 DDRB_DQS#1
47 DQ21 DQ20 48 DDRA_DQS4 179 DQS4_c DM4_n/DBl4_n/NC 180 DQS1 DDRB_DQS1
DDRA_DQ20 49 VSS_23 VSS_24 50 DDRA_DQ17 181 DQS4_t VSS_59 182 DDRA_DQ39
51 DQ17 DQ16 52 DDRA_DQ35 183 VSS_60 DQ39 184
DDRA_DQS#2 VSS_25 VSS_26 DDRA_DM2 DQ38 VSS_61 DDRA_DQ38
DQ16 DDRB_DQ20
53 54 185 186 DQ17 DDRB_DQ16
DDRA_DQS2 55 DQS2_c DM2_n/DBl2_n/NC 56 DDRA_DQ34 187 VSS_62 DQ35 188
57 DQS2_t VSS_27 58 DDRA_DQ22 189 DQ34 VSS_63 190 DDRA_DQ40 DQ18 DDRB_DQ18
DDRA_DQ23 59 VSS_28 DQ22 60 DDRA_DQ41 191 VSS_64 DQ45 192 DQ19 DDRB_DQ19
61 DQ23 VSS_29 62 DDRA_DQ18 193 DQ44 VSS_65 194 DDRA_DQ44 DQ20 DDRB_DQ17
DDRA_DQ19 63 VSS_30 DQ18 64 DDRA_DQ45 195 VSS_66 DQ41 196 DQ21 DDRB_DQ21
65 DQ19 VSS_31 66 DDRA_DQ24 197 DQ40 VSS_67 198 DDRA_DQS#5
DDRA_DQ29 VSS_32 DQ28 DDRA_DM5 VSS_68 DQS5_c DDRA_DQS5
DQ22 DDRB_DQ22
67 68 199 200 DQ23 DDRB_DQ23
69 DQ29 VSS_33 70 DDRA_DQ28 201 DM5_n/DBl5_n/NC DQS5_t 202
DDRA_DQ25 71 VSS_34 DQ24 72 DDRA_DQ42 203 VSS_69 VSS_70 204 DDRA_DQ46 DQS#2 DDRB_DQS#2
73 DQ25 VSS_35 74 DDRA_DQS#3 205 DQ46 DQ47 206 DQS2 DDRB_DQS2
DDRA_DM3 75 VSS_36 DQS3_c 76 DDRA_DQS3 DDRA_DQ43 207 VSS_71 VSS_72 208 DDRA_DQ47
C DM3_n/DBl3_n/NC DQS3_t DQ42 DQ43 C
77 78 209 210 DQ24 DDRB_DQ28
DDRA_DQ31 79 VSS_37 VSS_38 80 DDRA_DQ26 DDRA_DQ53 211 VSS_73 VSS_74 212 DDRA_DQ52
DQ30 DQ31 DQ52 DQ53 DQ25 DDRB_DQ25
81 82 213 214
DDRA_DQ30 83 VSS_39 VSS_40 84 DDRA_DQ27 DDRA_DQ48 215 VSS_75 VSS_76 216 DDRA_DQ49 DQ26 DDRB_DQ31
85 DQ26 DQ27 86 217 DQ49 DQ48 218 DQ27 DDRB_DQ27
87 VSS_41 VSS_42 88 DDRA_DQS#6 219 VSS_77 VSS_78 220 DDRA_DM6 DQ28 DDRB_DQ24
89 CB5/NC CB4/NC 90 DDRA_DQS6 221 DQS6_c DM6_n/DBl6_n/NC 222 DQ29 DDRB_DQ29
+1.2V +1.2V 91 VSS_43 VSS_44 92 +1.2V 223 DQS6_t VSS_79 224 DDRA_DQ50
CB1/NC CB0/NC DDRA_DQ51 VSS_80 DQ54 DQ30 DDRB_DQ26
93 94 225 226 DQ31 DDRB_DQ30
RD273 1 @ 2 240_0402_1% 95 VSS_45 VSS_46 96 227 DQ55 VSS_81 228 DDRA_DQ54
RD274 1 @ 2 240_0402_1% 97 DQS8_c DM8_n/DBI8_n/NC 98 DDRA_DQ55 229 VSS_82 DQ50 230 DQS#3 DDRB_DQS#3
99 DQS8_t VSS_47 100 231 DQ51 VSS_83 232 DDRA_DQ56 DQS3 DDRB_DQS3
101 VSS_48 CB6/NC 102 DDRA_DQ60 233 VSS_84 DQ60 234
103 CB2/NC VSS_49 104 for MEM_MB_RST# overshoot issue 235 DQ61 VSS_85 236 DDRA_DQ61
DQ32 DDRB_DQ33
105 VSS_50 CB7/NC 106 DDRA_DQ57 237 VSS_86 DQ57 238
CB3/NC VSS_51 MEM_MA_RST# DQ56 VSS_87 DDRA_DQS#7 DQ33 DDRB_DQ37
107 108 239 240
DDRA_CKE0 109 VSS_52 RESET_n 110 DDRA_CKE1 MEM_MA_RST# 5 DDRA_DM7 241 VSS_88 DQS7_c 242 DDRA_DQS7 DQ34 DDRB_DQ34
5 DDRA_CKE0 CKE0 CKE1 DDRA_CKE1 5 DM7_n/DBl7_n/NC DQS7_t DQ35 DDRB_DQ38
111 112 243 244
5 DDRA_BG1
DDRA_BG1 113 VDD_1 VDD_2 114 DDRA_ACT#
DDRA_ACT# 5 1 0.1U_0201_6.3V6-K DDRA_DQ63 245 VSS_89 VSS_90 246 DDRA_DQ58 DQ36 DDRB_DQ36
DDRA_BG0 115 BG1 ACT_n 116 DDR4_ALERT 247 DQ62 DQ63 248 DQ37 DDRB_DQ32
CD120

5 DDRA_BG0 BG0 ALERT_n DDRA_DQ62 VSS_91 VSS_92 DDRA_DQ59

117 118 249 250 DQ38 DDRB_DQ35
DDRA_MA12 119 VDD_3 VDD_4 120 DDRA_MA11 251 DQ58 DQ59 252
DDRA_MA9 121 A12 A11 122 DDRA_MA7 2 +VDDSPD APU_SMB_CLK 253 VSS_93 VSS_94 254 APU_SMB_DATA DQ39 DDRB_DQ39
123 A9 A7 124 @
7,31 APU_SMB_CLK 255 SCL SDA 256 DDRA0_SA0 APU_SMB_DATA 7,31 DQS#4 DDRB_DQS#4
DDRA_MA8 125 VDD_5 VDD_6 126 DDRA_MA5 257 VDDSPD SA0 258 DQS4 DDRB_DQS4
DDRA_MA6 A8 A5 DDRA_MA4 +2.5V VPP_1 Vtt DDRA0_SA1 +0.6VS
127 128 1 1 259 260
129 A6 A4 130 VPP_2 SA1
VDD_7 VDD_8
CD28 CD29 1 DQ40 DDRB_DQ45
1U_0402_6.3V6K 0.1U_0201_6.3V6-K CD121 261 262 DQ41 DDRB_DQ44
22P_0402_50V8-J GND_1 GND_2
2 2 RF_NS@ ARGOS_D4AS0-26001-1P60
DQ42 DDRB_DQ46
RF 2 DQ43 DDRB_DQ42
ARGOS_D4AS0-26001-1P60 ME@
ME@
DQ44 DDRB_DQ41
DQ45 DDRB_DQ40
+3VS +VDDSPD
DQ46 DDRB_DQ47
1 2 0_0402_5%
DQ47 DDRB_DQ43
RD271
+2.5VS DQS#5 DDRB_DQS#5
B B
+1.2V DQS5 DDRB_DQS5
+1.2V RD272 1 @ 2 0_0402_5%
+2.5V +2.5VS DQ48 DDRB_DQ49
1

DQ49 DDRB_DQ48
1

RD10 3 1

D
RD258 +VREF_CA QD1
DQ50 DDRB_DQ54
1K_0402_1%
1K_0402_1% LP2301ALT1G_SOT23-3 DQ51 DDRB_DQ55
DQ52 DDRB_DQ53

G
15mil Layout Note: Place near JDDR1
2

2
@
DQ53 DDRB_DQ52
2

DQ54 DDRB_DQ50
0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

DDR4_ALERT
2

1000P_0201_50V7-K

24,37 SUSP DQ55 DDRB_DQ51

RD11 1 1 1
1K_0402_1% +0.6VS +1.2V DQS#6 DDRB_DQS#6
DQS6 DDRB_DQS6
CD262

CD116

CD117

follow CRB 1pcs 4.7uf + 1pcs 0.1uf follow CRB 6pcs 0.1uf
1

2 2 2 DQ56 DDRB_DQ60

180P_0402_50V8-J
0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

27P 25V J NPO 0201

0.1U_0201_6.3V6-K

27P 25V J NPO 0201

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K
DQ57 DDRB_DQ56
0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

4.7U_0402_6.3V6M

1 1 1 1 1 1 1 1 1 1 1 1 1 DQ58 DDRB_DQ63
1 1 1 1 CD16 CD17 CD18 CD20 CD21 CD22 CD23 CD58 CD59 CD60 CD61 CD62 CC211
CD249 CD251 CD250 CD248 @ EMC@ @ EMC@ @ @ DQ59 DDRB_DQ59
@ @ DQ60 DDRB_DQ61
2 2 2 2 2 2 2 2 2 2 2 2 2 DQ61 DDRB_DQ57
2 2 2 2
DQ62 DDRB_DQ58
DQ63 DDRB_DQ62
+3VS +3VS +3VS DQS#7 DDRB_DQS#7
DQS7 DDRB_DQS7
1

RD26 RD269 RD270 +2.5V +1.2V

10K_0402_5% 10K_0402_5% 10K_0402_5% follow CRB 1pcs 1uf + 2pcs 0.1uf + 1pcs 180pf
@ @ @
2

DDRA0_SA0 DDRA0_SA1 DDRA0_SA2

10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
1U_0402_6.3V6K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

180P_0402_50V8-J

1 1 1 1 1 1 1
1

RD268 1 1 1 1 CD261 CD63 CD66 CD67 CD19 CD260 CD12

A RD28 RD29 CD122 CD123 CD124 CC206 @ @ @ @ 22P_0402_50V8-J 22P_0402_50V8-J 22P_0402_50V8-J A
0_0402_5% RF@ RF@ RF@
0_0402_5% 0_0402_5%
@ @ 2 2 2 2 2 2 2
2 2 2 2
RF
2

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 DDRIII SO-DIMM A
SPD Address = A2H THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
320ABR 0.1

Date: Thursday, January 12, 2017 Sheet 12 of 50

5 4 3 2 1
 5 4 3 2 1

DDRB_DQ[0..63]
DDRB_DQ[0..63] 5
DDRB_DQS[0..7]
DDRB_DQS[0..7] 5
UD1 UD2 DDRB_DQS#[0..7]
DDRB_DQS#[0..7] 5
DDRB_MA0 DDRB_DQ3 DDRB_MA0 DDRB_DQ18 DDRB_MA[0..13]
P3 G2 P3 G2
DDRB_MA1 A0 DQ0 DDRB_DQ2 DDRB_MA1 A0 DQ0 DDRB_DQ19 DDRB_MA[0..13] 5
P7 F7 P7 F7 DDRB_DM[0..7]
DDRB_MA2 R3 A1 DQ1 H3 DDRB_DQ6 DDRB_MA2 R3 A1 DQ1 H3 DDRB_DQ23
DDRB_MA3 A2 DQ2 DDRB_DQ0 DDRB_MA3 A2 DQ2 DDRB_DQ17 DDRB_DM[0..7] 5
N7 H7 N7 H7
DDRB_MA4 N3 A3 DQ3 H2 DDRB_DQ1 DDRB_MA4 N3 A3 DQ3 H2 DDRB_DQ22
DDRB_MA5 P8 A4 DQ4 H8 DDRB_DQ5 DDRB_MA5 P8 A4 DQ4 H8 DDRB_DQ21
DDRB_MA6 P2 A5 DQ5 J3 DDRB_DQ7 DDRB_MA6 P2 A5 DQ5 J3 DDRB_DQ20
DDRB_MA7 R8 A6 DQ6 J7 DDRB_DQ4 DDRB_MA7 R8 A6 DQ6 J7 DDRB_DQ16
DDRB_MA8
DDRB_MA9
R2
R7
A7
A8
DQ7
DQ8
A3
B8
DDRB_DQ11
DDRB_DQ8
DDRB_MA8
DDRB_MA9
R2
R7
A7
A8
DQ7
DQ8
A3
B8
DDRB_DQ27
DDRB_DQ24 CD163 change from K to J +1.2V
DDRB_MA10 M3 A9 DQ9 C3 DDRB_DQ15 DDRB_MA10 M3 A9 DQ9 C3 DDRB_DQ31
DDRB_MA11 T2 A10/AP DQ10 C7 DDRB_DQ9 DDRB_MA11 T2 A10/AP DQ10 C7 DDRB_DQ25
DRAM@
DDRB_MA12 M7 A11 DQ11 C2 DDRB_DQ10 DDRB_MA12 M7 A11 DQ11 C2 DDRB_DQ26 DDRB_CLK0# 1 DRAM@ 2 1 2 0.01UF_0402_25V7-K
RD122 39_0402_5% CD163
DDRB_MA13 T8 A12/BC_N DQ12 C8 DDRB_DQ13 DDRB_MA13 T8 A12/BC_N DQ12 C8 DDRB_DQ28 DDRB_CLK0 1 DRAM@ 2
RD123 39_0402_5%
A13 DQ13 D3 DDRB_DQ14 A13 DQ13 D3 DDRB_DQ30
D D
DDRB_MA14_WE# L2 DQ14 D7 DDRB_DQ12 DDRB_MA14_WE# L2 DQ14 D7 DDRB_DQ29
5 DDRB_MA14_WE#
5 DDRB_MA15_CAS#
DDRB_MA15_CAS#
DDRB_MA16_RAS#
M8
L8
WE_N/A14
CAS_N/A15
DQ15
+1.2V
DDRB_MA15_CAS#
DDRB_MA16_RAS#
M8
L8
WE_N/A14
CAS_N/A15
DQ15
+1.2V 2/22: change to K back for materil stock risk, and this change +0.6VS

5 DDRB_MA16_RAS# RAS_N/A16 RAS_N/A16

5 DDRB_CLK0#
DDRB_CLK0#
DDRB_CLK0
K8
CK_C
VDD1
VDD2
D1
J1 DDRB_CLK0#
DDRB_CLK0
K8
CK_C
VDD1
VDD2
D1
J1 has conf i r mt o A MD DDRB_MA0
5 DDRB_CLK0 K7 L1 K7 L1 RD148 1 DRAM@ 2 39_0402_5%
CK_T VDD3 R1 CK_T VDD3 R1 DDRB_MA1 1 2
RD149 DRAM@ 39_0402_5%
DDRB_CKE0 K2 VDD4 B3 DDRB_CKE0 K2 VDD4 B3 DDRB_MA2 1 2
5 DDRB_CKE0 RD124 DRAM@ 39_0402_5%
CKE VDD5 G7 CKE VDD5 G7 DDRB_MA3 1 2
RD125 DRAM@ 39_0402_5%
DDRB_DQS#0 F3 VDD6 B9 DDRB_DQS#2 F3 VDD6 B9 DDRB_MA4 RD126 1 DRAM@ 2 39_0402_5%
DDRB_DQS0 G3 LDQS_C VDD7 J9 DDRB_DQS2 G3 LDQS_C VDD7 J9 DDRB_MA5 1 2
RD127 DRAM@ 39_0402_5%
DDRB_DQS#1 A7 LDQS_T VDD8 L9 DDRB_DQS#3 A7 LDQS_T VDD8 L9 DDRB_MA6 1 2
RD128 DRAM@ 39_0402_5%
DDRB_DQS1 B7 UDQS_C VDD9 T9 DDRB_DQS3 B7 UDQS_C VDD9 T9 DDRB_MA7 1 2
RD129 DRAM@ 39_0402_5%
UDQS_T VDD10 UDQS_T VDD10 DDRB_MA8 1 2
RD130 DRAM@ 39_0402_5%
DDRB_DM1 E2 A1 DDRB_DM3 E2 A1 DDRB_MA9 RD131 1 DRAM@ 2 39_0402_5%
DDRB_DM0 E7 NF/UDM_N/UDBI_N VDDQ1 C1 DDRB_DM2 E7 NF/UDM_N/UDBI_N VDDQ1 C1 DDRB_MA10 1 2
RD132 DRAM@ 39_0402_5%
NF/LDM_N/LDBI_N VDDQ2 G1 NF/LDM_N/LDBI_N VDDQ2 G1 DDRB_MA11 1 2
RD133 DRAM@ 39_0402_5%
DDRB_BA0 N2 VDDQ3 F2 DDRB_BA0 N2 VDDQ3 F2 DDRB_MA12 1 2
5 DDRB_BA0 RD134 DRAM@ 39_0402_5%
DDRB_BA1 N8 BA0 VDDQ4 J2 DDRB_BA1 N8 BA0 VDDQ4 J2 DDRB_MA13 1 2
RF 5 DDRB_BA1 BA1 VDDQ5 BA1 VDDQ5
RD135 DRAM@ 39_0402_5%
F8 F8
+1.2V DDRB_ACT# L3 VDDQ6 J8 +1.2V DDRB_ACT# L3 VDDQ6 J8 DDRB_MA14_WE# 1 DRAM@ 2
5 DDRB_ACT# RD138 39_0402_5%
DDRB_CS0# L7 ACT_N VDDQ7 A9 DDRB_CS0# L7 ACT_N VDDQ7 A9 DDRB_MA15_CAS# 1 DRAM@ 2
RD139 39_0402_5%
5 DDRB_CS0# CS_N VDDQ8 CS_N VDDQ8 DDRB_MA16_RAS#
1K_0402_1% 1 2 RD260 P9 D9 1K_0402_1% 1 DRAM@ 2 RD264 P9 D9 RD140 1 DRAM@ 2 39_0402_5%
DRAM@ ALERT_N VDDQ9 G9 ALERT_N VDDQ9 G9
DDRB_BG0 M2 VDDQ10 +2.5V DDRB_BG0 M2 VDDQ10 +2.5V DDRB_ACT# 1 DRAM@ 2
5 DDRB_BG0
DDRB_ODT0
BG0 B1
DDRB_ODT0
BG0 B1
DDRB_ODT0
RD144 39_0402_5%
Swap Table
K3 VPP1 R9 K3 VPP1 R9 RD147 1 DRAM@ 2 39_0402_5%
5 DDRB_ODT0 ODT VPP2 +VREF_CA ODT VPP2 +VREF_CA DDRB_CS0#
RD145 1 DRAM@ 2 39_0402_5% Pin Name Net Name
1 DRAM@ 2 RD261 T3 M1 1 DRAM@ 2 RD265 T3 M1 DDRB_CKE0 1 DRAM@ 2
0_0402_5% 0_0402_5% RD141 39_0402_5%
PAR VREFCA PAR VREFCA

1U_0402_6.3V6K

1U_0402_6.3V6K
0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K
1 1 1 1 DQ0 DDRB_DQ3
10K_0402_5%1 DRAM@ 2 RD251 TEN1 N9 E1 10K_0402_5% 1 DRAM@ 2 RD253 TEN2 N9 E1 DQ1 DDRB_DQ4

CD202

CD203

CD232

CD233
TEN VSS1 TEN VSS1

1000P_0201_50V7-K

1000P_0201_50V7-K
0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K
K1 1 1 K1 1 1 DQ2 DDRB_DQ1
MEM_MB_RST# P1 VSS2 N1 MEM_MB_RST# P1 VSS2 N1

CD189

CD188

CD230

CD231
5 MEM_MB_RST# RESET_N VSS3 T1 DRAM@ 2 2
DRAM@ RESET_N VSS3 T1 DRAM@2 2 DDRB_BA0
RD142 1 DRAM@ 2 39_0402_5%
DQ3 DDRB_DQ0
VSS4 VSS4 DDRB_BA1 DQ4 DDRB_DQ7
0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K
F1 B2 F1 B2 DRAM@ RD143 1 DRAM@ 2 39_0402_5%
H1 VSSQ1 VSS5 G8 DRAM@ 2 DRAM@2 H1 VSSQ1 VSS5 G8 2 2 DQ5 DDRB_DQ5
1 VSSQ2 VSS6 1 VSSQ2 VSS6
A2 E9 A2 E9 DRAM@ DRAM@ DQ6 DDRB_DQ2
CD132

CD160
D2 VSSQ3 VSS7 K9 D2 VSSQ3 VSS7 K9 DQ7 DDRB_DQ6
E3 VSSQ4 VSS8 M9 E3 VSSQ4 VSS8 M9 DDRB_BG0 1 DRAM@ 2
RD146 39_0402_5% DQS#0 DDRB_DQS#0
@ 2 A8 VSSQ5 VSS9 @ 2 A8 VSSQ5 VSS9
VSSQ6 VSSQ6 DQS0 DDRB_DQS0
D8 T7 D8 T7
E8 VSSQ7 NC E8 VSSQ7 NC UD1
C9 VSSQ8 C9 VSSQ8
VSSQ9 VSSQ9
DQ8 DDRB_DQ9
H9 H9 DQ9 DDRB_DQ11
C VSSQ10 VSSQ10 C
F9 F9
DQ10 DDRB_DQ12
ZQ ZQ DQ11 DDRB_DQ8
+1.2V DQ12 DDRB_DQ15
1

1
RD116 MT40A512M16HA083EA_FBGA96 RD117 MT40A512M16HA083EA_FBGA96 DQ13 DDRB_DQ13
240_0402_1% 240_0402_1% DQ14 DDRB_DQ14
@ DRAM@ @ DQ15 DDRB_DQ10
Layout Note: Place near DRAM DQS#1 DDRB_DQS#1
2

2
DRAM@ DQS1 DDRB_DQS1
CD266 1 CD267 1 CD268 1 CD269 1 CD270 1 CD271 1 CD272 1 CD273 1 CD274 1 CD275 1 CD276 1 CD277 1 3A@1.5V UD1

47P_0201_25V8-J

27P 25V J NPO 0201

27P 25V J NPO 0201

27P 25V J NPO 0201

27P 25V J NPO 0201

27P 25V J NPO 0201

27P 25V J NPO 0201

47P_0201_25V8-J

27P 25V J NPO 0201

47P_0201_25V8-J

47P_0201_25V8-J

27P 25V J NPO 0201

+1.2V

EMC_NS@

EMC@

EMC@

EMC@

EMC@

EMC@

EMC@

EMC_NS@

EMC@

EMC_NS@

EMC_NS@

EMC@
DQ16 DDRB_DQ7
2 2 2 2 2 2 2 2 2 2 2 2
DQ17 DDRB_DQ3
follow SCL 20pcs 0.22uf DQ18 DDRB_DQ0
DQ19 DDRB_DQ1
DQ20 DDRB_DQ6

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K
1 1 1 1 1 1 1 1 1 1
DQ21 DDRB_DQ5
CD154 CD155 CD142 CD127 CD141 CD152 CD150 CD158 CD143 CD137 DQ22 DDRB_DQ4
DQ23 DDRB_DQ2
2 2 2 2 2 2 2 2 2 2
DQS#2 DDRB_DQS#2
UD3 DQS2 DDRB_DQS2
DDRB_MA0 DDRB_DQ38
UD4 UD2
P3 G2 DQ24 DDRB_DQ9
DDRB_MA1 P7 A0 DQ0 F7 DDRB_DQ32 DDRB_MA0 P3 G2 DDRB_DQ51 DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@
DDRB_MA2 A1 DQ1 DDRB_DQ34 DDRB_MA1 A0 DQ0 DDRB_DQ48 DQ25 DDRB_DQ11
R3 H3 P7 F7 3A@1.5V DQ26 DDRB_DQ12
DDRB_MA3 N7 A2 DQ2 H7 DDRB_DQ37 DDRB_MA2 R3 A1 DQ1 H3 DDRB_DQ50
DDRB_MA4 N3 A3 DQ3 H2 DDRB_DQ35 DDRB_MA3 N7 A2 DQ2 H7 DDRB_DQ53 DQ27 DDRB_DQ8
DDRB_MA5 P8 A4 DQ4 H8 DDRB_DQ36 DDRB_MA4 N3 A3 DQ3 H2 DDRB_DQ55 +1.2V DQ28 DDRB_DQ13
DDRB_MA6 P2 A5 DQ5 J3 DDRB_DQ39 DDRB_MA5 P8 A4 DQ4 H8 DDRB_DQ52 DQ29 DDRB_DQ15
DDRB_MA7 R8 A6 DQ6 J7 DDRB_DQ33 DDRB_MA6 P2 A5 DQ5 J3 DDRB_DQ54 DQ30 DDRB_DQ14
DDRB_MA8 A7 DQ7 DDRB_DQ43 DDRB_MA7 A6 DQ6 DDRB_DQ49
DDRB_MA9
R2 A3
DDRB_DQ44 DDRB_MA8
R8 J7
DDRB_DQ59
DQ31 DDRB_DQ10
R7 A8 DQ8 B8 R2 A7 DQ7 A3
DDRB_MA10 A9 DQ9 DDRB_DQ40 DDRB_MA9 A8 DQ8 DDRB_DQ56 DQS#3 DDRB_DQS#3
M3 C3 R7 B8

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K
DDRB_MA11 A10/AP DQ10 DDRB_DQ41 DDRB_MA10 A9 DQ9 DDRB_DQ58 DQS3 DDRB_DQS3
T2 C7 M3 C3
DDRB_MA12
DDRB_MA13
M7 A11 DQ11 C2 DDRB_DQ46
DDRB_DQ45
DDRB_MA11
DDRB_MA12
T2 A10/AP DQ10 C7 DDRB_DQ61
DDRB_DQ63
CD174
1
CD173
1
CD169
1
CD165
1
CD167
1
CD172
1
CD171
1
CD175
1
CD168
1
CD166
1 UD2
T8 A12/BC_N DQ12 C8 M7 A11 DQ11 C2
A13 DQ13 DDRB_DQ42 DDRB_MA13 A12/BC_N DQ12 DDRB_DQ60 DQ32 DDRB_DQ1
D3 T8 C8 DQ33 DDRB_DQ7
DDRB_MA14_WE# L2 DQ14 D7 DDRB_DQ47 A13 DQ13 D3 DDRB_DQ62 2 2 2 2 2 2 2 2 2 2
DDRB_MA15_CAS# M8 WE_N/A14 DQ15 DDRB_MA14_WE# L2 DQ14 D7 DDRB_DQ57 DQ34 DDRB_DQ2
DDRB_MA16_RAS# L8 CAS_N/A15 +1.2V DDRB_MA15_CAS# M8 WE_N/A14 DQ15 DQ35 DDRB_DQ4
RAS_N/A16 D1 DDRB_MA16_RAS# L8 CAS_N/A15 +1.2V DQ36 DDRB_DQ5
DDRB_CLK0# K8 VDD1 J1 RAS_N/A16 D1 DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DQ37 DDRB_DQ3
DDRB_CLK0 K7 CK_C VDD2 L1 DDRB_CLK0# K8 VDD1 J1 DQ38 DDRB_DQ0
B B
CK_T VDD3 DDRB_CLK0 CK_C VDD2 +1.2V
DDRB_CKE0
R1 K7 L1 DQ39 DDRB_DQ6
K2 VDD4 B3 CK_T VDD3 R1 +1.2V
CKE VDD5 DDRB_CKE0 VDD4
DQS#4 DDRB_DQS#4
G7 K2 B3 DQS4 DDRB_DQS4
DDRB_DQS#4 F3 VDD6 B9 CKE VDD5 G7
DDRB_DQS4
DDRB_DQS#5
G3 LDQS_C VDD7 J9 DDRB_DQS#6
DDRB_DQS6
F3 VDD6 B9 UD3
A7 LDQS_T VDD8 L9 G3 LDQS_C VDD7 J9

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K
DDRB_DQS5 UDQS_C VDD9 DDRB_DQS#7 LDQS_T VDD8
DQ40 DDRB_DQ10
B7 T9 A7 L9 1 1 1 1 DQ41 DDRB_DQ11
UDQS_T VDD10 DDRB_DQS7 B7 UDQS_C VDD9 T9 CD215 CD218 CD212 CD211 1 1 DQ42 DDRB_DQ14
DDRB_DM5 E2 A1 UDQS_T VDD10 @ @ @ @ CD133 CD153
DDRB_DM4 E7 NF/UDM_N/UDBI_N VDDQ1 C1 DDRB_DM7 E2 A1 22P_0402_50V8-J 22P_0402_50V8-J
DQ43 DDRB_DQ8
NF/LDM_N/LDBI_N VDDQ2 G1 DDRB_DM6 E7 NF/UDM_N/UDBI_N VDDQ1 C1 2 2 2 2 RF_NS@ RF_NS@ DQ44 DDRB_DQ9
DDRB_BA0 N2 VDDQ3 F2 NF/LDM_N/LDBI_N VDDQ2 G1 2 2 DQ45 DDRB_DQ13
DDRB_BA1 N8 BA0 VDDQ4 J2 DDRB_BA0 N2 VDDQ3 F2 DQ46 DDRB_DQ12
BA1 VDDQ5 DDRB_BA1 BA0 VDDQ4
DDRB_ACT#
F8 N8 J2 DQ47 DDRB_DQ15
+1.2V L3 VDDQ6 J8 BA1 VDDQ5 F8
DDRB_CS0# ACT_N VDDQ7 +1.2V DDRB_ACT# VDDQ6
DQS#5 DDRB_DQS#5
L7 A9 L3 J8 DQS5 DDRB_DQS5
CS_N VDDQ8 DDRB_CS0# ACT_N VDDQ7
1K_0402_1% 1 DRAM@ 2 RD266 P9 D9 L7 A9
DDRB_BG0
ALERT_N VDDQ9 G9 1K_0402_1% 1 DRAM@ 2 RD262 P9 CS_N VDDQ8 D9 UD3
M2 VDDQ10 +2.5V ALERT_N VDDQ9 G9 +0.6VS
BG0 DDRB_BG0 VDDQ10 +2.5V
DQ48 DDRB_DQ1
B1 M2 DQ49 DDRB_DQ7
DDRB_ODT0 K3 VPP1 R9 BG0 B1
ODT VPP2 +VREF_CA DDRB_ODT0 K3 VPP1 R9 follow SCL 10pcs 0.22uf DQ50 DDRB_DQ2
0_0402_5% 1 DRAM@ 2 RD267 T3 M1 ODT VPP2 +VREF_CA DQ51 DDRB_DQ0
PAR VREFCA DQ52 DDRB_DQ5
1U_0402_6.3V6K
0.1U_0201_6.3V6-K

1 DRAM@ 2 RD263 T3 M1

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K
1 1 0_0402_5%
PAR VREFCA DQ53 DDRB_DQ3

1U_0402_6.3V6K
0.1U_0201_6.3V6-K
10K_0402_5%1 DRAM@ 2 RD255 TEN3 N9 E1 1 1 1 1 1 1 1 1 1 1 1 1
CD236

CD237

TEN VSS1
1000P_0201_50V7-K

DQ54 DDRB_DQ6
0.1U_0201_6.3V6-K

K1 1 1 10K_0402_5%1 DRAM@ 2 RD257 TEN4 N9 E1 CD146 CD148 CD139 CD138 CD201 CD245 CD246 CD244 CD243 CD242

CD240

CD241
MEM_MB_RST# VSS2 TEN VSS1

1000P_0201_50V7-K

0.1U_0201_6.3V6-K
P1 N1 K1 1 1 DQ55 DDRB_DQ4
CD234

CD235

RESET_N VSS3 T1 2 2 MEM_MB_RST# P1 VSS2 N1 DQS#6 DDRB_DQS#6

CD238

CD239
VSS4 DRAM@ RESET_N VSS3 2 DRAM@ 2 2 2 2 2 2 2 2 2 2 2
0.1U_0201_6.3V6-K

F1 B2 T1 DQS6 DDRB_DQS6
VSSQ1 VSS5 2 2 DRAM@ VSS4 DRAM@
0.1U_0201_6.3V6-K

H1 G8 F1 B2
1
A2 VSSQ2 VSS6 E9 1 H1 VSSQ1 VSS5 G8 2 2 UD4
CD161

D2 VSSQ3 VSS7 K9 DRAM@ DRAM@ A2 VSSQ2 VSS6 E9 DRAM@ DRAM@

DQ56 DDRB_DQ9
CD162

E3 VSSQ4 VSS8 M9 D2 VSSQ3 VSS7 K9 DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@
2 VSSQ5 VSS9 VSSQ4 VSS8 DQ57 DDRB_DQ15
@ A8 E3 M9
D8 VSSQ6 T7 @ 2 A8 VSSQ5 VSS9 DQ58 DDRB_DQ10
E8 VSSQ7 NC D8 VSSQ6 T7 +0.6VS +0.6VS DQ59 DDRB_DQ8
C9 VSSQ8 E8 VSSQ7 NC +2.5V DQ60 DDRB_DQ13
H9 VSSQ9 C9 VSSQ8 DQ61 DDRB_DQ11
VSSQ10 H9 VSSQ9 DQ62 DDRB_DQ14
F9 VSSQ10 DQ63 DDRB_DQ12
ZQ

180P_0402_50V8-J
F9

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K
ZQ 1 1 DQS#7 DDRB_DQS#7
1

1 1 1 1 CD265 DQS7 DDRB_DQS7

CC205
1

RD118 MT40A512M16HA083EA_FBGA96
240_0402_1% RD119 MT40A512M16HA083EA_FBGA96
CD259
@
CD252
@
CD263
22P_0402_50V8-J
CD264
22P_0402_50V8-J
22P_0402_50V8-J
RF_NS@ UD4
A DRAM@@ 240_0402_1% RF_NS@ RF_NS@ 2 2 A
@ 2 2 2 2
2

DRAM@
2

DRAM@

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 DDRIII SO-DIMM B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 320ABR
Dat e : Thursday, January 12, 2017 Sheet 13 of 50
5 4 3 2 1
 5 4 3 2 1

Power-Up/Down Sequence
"Topaz" has the following requirements with regards to power-supply sequencing to
avoid damaging the ASIC:
D D
All the ASIC supplies must reach their respective nominal voltages within 20 ms
of the start of the ramp-up sequence, though a shorter ramp-up duration is
preferred. The maximum slew rate on all rails is 50 mV/μ s. VRAM ID config
It is recommended that the 3.3-V rail ramp up first.
The 3.3-V, 1.8-V, and 0.95-V rails must reach their ready state at least 10 μ s VRAM ID PU resistor PD resistor
Memory Type
before VDDC, VDDCI, and VMEMIO start to ramp up. PS_3[3:1] RV63 RV70
The power rails that are shared with other components on the system should be
gated for the dGPU so that when the dGPU is powered down (for example Hynix
AMD PowerXpress idle state), all the power rails are removed from the dGPU. 100 4.53K 4.99K
H5GC4H24AJR-R0C 6.0Gbps@1.35V
The gate circuits must meet the slew rate requirement (such as ≤ 50 mV/μ s).
For power down, reversing the ramp-up sequence is recommended. 4Gb GDDR5 Micron
111 4.75K NC
EDW4032BABG-70-F 6.0Gbps@1.35V
256M x 16
Samsung
110 3.4K 10K
K4G41325FE-HC28 6.0Gbps@1.35V
0 ~ 20ms
Hynix
000 NC 4.75K
VDDR3(+3VGS) H5GC8H24MJR-R0C 6.0Gbps@1.35V
0 ~ 20ms
C C
8Gb GDDR5 Micron
010 4.53K 2K
VDD_CT(+1.8VGS) 512M x 16
MT51J256M32HF-70:A 6.0Gbps@1.35V

Samsung
001 8.45K 2K
PCIE_VDDC(+0.95VGS) K4G80325FB-HC28 6.0Gbps@1.35V

10us min.

VDDR1(+1.35VGS)

VDDC/VDDCI(+VGA_CORE) 100ms min.

PERSTb(GPU_RST#) 100us min.

REFCLK(CLK_PCIE_VGA)

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2016/08/16 Deciphered Date 2017/08/15 VGA Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 320ABR
Date: Thursday, January 12, 2017 Sheet 14 of 50
5 4 3 2 1
 5 4 3 2 1

PCIE_CTX_C_GRX_P[0..7] PCIE_CRX_GTX_P[0..7]
4 PCIE_CTX_C_GRX_P[0..7] PCIE_CRX_GTX_P[0..7] 4
UV1A
PCIE_CTX_C_GRX_N[0..7] PCIE_CRX_GTX_N[0..7]
4 PCIE_CTX_C_GRX_N[0..7] PCIE_CRX_GTX_N[0..7] 4

PCIE_CTX_C_GRX_P0 AF30 AH30 PCIE_CRX_C_GTX_P0 0.22U_0201_6.3V6-K 1 2 PX@ CV1 PCIE_CRX_GTX_P0

PCIE_CTX_C_GRX_N0 AE31 PCIE_RX0P PCIE_TX0P AG31 PCIE_CRX_C_GTX_N0 0.22U_0201_6.3V6-K 1 2 PX@ CV2 PCIE_CRX_GTX_N0
PCIE_RX0N PCIE_TX0N
D D
PCIE_CTX_C_GRX_P1 AE29 AG29 PCIE_CRX_C_GTX_P1 0.22U_0201_6.3V6-K 1 2 PX@ CV3 PCIE_CRX_GTX_P1
PCIE_CTX_C_GRX_N1 AD28 PCIE_RX1P PCIE_TX1P AF28 PCIE_CRX_C_GTX_N1 0.22U_0201_6.3V6-K 1 2 PX@ CV4 PCIE_CRX_GTX_N1
PCIE_RX1N PCIE_TX1N

PCIE_CTX_C_GRX_P2 AD30 AF27 PCIE_CRX_C_GTX_P2 0.22U_0201_6.3V6-K 1 2 PX@ CV5 PCIE_CRX_GTX_P2

PCIE_CTX_C_GRX_N2 AC31 PCIE_RX2P PCIE_TX2P AF26 PCIE_CRX_C_GTX_N2 0.22U_0201_6.3V6-K 1 2 PX@ CV6 PCIE_CRX_GTX_N2
PCIE_RX2N PCIE_TX2N

PCIE_CTX_C_GRX_P3 AC29 AD27 PCIE_CRX_C_GTX_P3 0.22U_0201_6.3V6-K 1 2 PX@ CV7 PCIE_CRX_GTX_P3

PCIE_CTX_C_GRX_N3 AB28 PCIE_RX3P PCIE_TX3P AD26 PCIE_CRX_C_GTX_N3 0.22U_0201_6.3V6-K 1 2 PX@ CV8 PCIE_CRX_GTX_N3
PCIE_RX3N PCIE_TX3N

PCIE_CTX_C_GRX_P4 AB30 AC25 PCIE_CRX_C_GTX_P4 0.22U_0201_6.3V6-K 1 2 PX@ CV636 PCIE_CRX_GTX_P4

PCIE_CTX_C_GRX_N4 AA31 PCIE_RX4P PCIE_TX4P AB25 PCIE_CRX_C_GTX_N4 0.22U_0201_6.3V6-K 1 2 PX@ CV639 PCIE_CRX_GTX_N4
PCIE_RX4N PCIE_TX4N

PCIE_CTX_C_GRX_P5 AA29 Y23 PCIE_CRX_C_GTX_P5 0.22U_0201_6.3V6-K 1 2 PX@ CV633 PCIE_CRX_GTX_P5

PCIE_CTX_C_GRX_N5 Y28 PCIE_RX5P PCIE_TX5P Y24 PCIE_CRX_C_GTX_N5 0.22U_0201_6.3V6-K 1 2 PX@ CV638 PCIE_CRX_GTX_N5
PCIE_RX5N PCIE_TX5N

PCIE_CTX_C_GRX_P6 Y30 AB27 PCIE_CRX_C_GTX_P6 0.22U_0201_6.3V6-K 1 2 PX@ CV632 PCIE_CRX_GTX_P6

PCIE_CTX_C_GRX_N6 W31 PCIE_RX6P PCIE_TX6P AB26 PCIE_CRX_C_GTX_N6 0.22U_0201_6.3V6-K 1 2 PX@ CV634 PCIE_CRX_GTX_N6
PCIE_RX6N PCIE_TX6N

PCIE_CTX_C_GRX_P7 W29 Y27 PCIE_CRX_C_GTX_P7 0.22U_0201_6.3V6-K 1 2 PX@ CV635 PCIE_CRX_GTX_P7

PCIE_CTX_C_GRX_N7 V28 PCIE_RX7P PCIE_TX7P Y26 PCIE_CRX_C_GTX_N7 0.22U_0201_6.3V6-K 1 2 PX@ CV637 PCIE_CRX_GTX_N7
PCIE_RX7N PCIE_TX7N
C C

V30 W24
U31 NC#V30 NC#W24 W23
NC#U31 NC#W23

U29 V27
T28 NC#U29 NC#V27 U26
NC#T28 NC#U26

PCI EXPRESS INTERFACE

T30 U24
R31 NC#T30 NC#U24 U23
NC#R31 NC#U23

R29 T26
P28 NC#R29 NC#T26 T27
NC#P28 NC#T27

P30 T24
N31 NC#P30 NC#T24 T23
NC#N31 NC#T23

N29 P27
M28 NC#N29 NC#P27 P26
NC#M28 NC#P26

M30 P24
L31 NC#M30 NC#P24 P23
B NC#L31 NC#P23
with BOM strcture control, CV1--CV8 change to 0.22uf for CZ B

L29 M27
K30 NC#L29 NC#M27 N26
NC#K30 NC#N26

CLOCK
CLK_PCIE_GPU AK30
8 CLK_PCIE_GPU
8 CLK_PCIE_GPU#
CLK_PCIE_GPU# AK32 PCIE_REFCLKP
PCIE_REFCLKN
change the GPU PN to AMD(EXO-S3 PRO), symbol check ok
+1.05VGS
CALIBRATION
Y22 1 PX@ 2 1.69K_0402_1%
PCIE_CALR_TX
RV3
11/4 change to PC sample SA000074V10
1K_0402_1% 1 PX@ 2 RV4 N10 AA22 RV5 1 PX@ 2 1K_0402_1%
TEST_PG PCIE_CALR_RX

GPU_RST# DV3
AL27
16 GPU_RST# PERSTB GPU_RST# 2
1 VGA_PWROK
VR_VGA_PWRGD VGA_PWROK 48
1

@ 3
7,48 VR_VGA_PWRGD
RV7 1 @ 2 0_0402_5% RV6
100K_0402_5% LBAT54AWT1G SOT323
+3VGS PX@ PX@
2

A A
5

UV2
VCC

1
8 PXS_RST# IN1 GPU_RST#
4
2 OUT
Title
GND

7,28,31 PLT_RST# IN2 Security Classification LC Future Center Secret Data

1
CV640 MC74VHC1G08DFT2G_SC70-5 Issued Date 2016/08/16 Deciphered Date 2017/08/15 ATI_EXO-PRO_PCIE
3

0.1U_0201_6.3V6-K PX@
@ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Re v
2 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 320ABR
Date: Thursday, January 12, 2017 Sheet 15 of 50
5 4 3 2 1
 5 4 3 2 1
RECOMMENDED SETTINGS
CONFIGURATION STRAPS 0= DO NOT INSTALL RESISTOR
UV1B 1 = INSTALL 10K RESISTOR
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE X = DESIGN DEPENDANT
GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET NA = NOT APPLICABLE

AF2
NC#AF2 AF4
NC#AF4 MLPS Bit Strap Name Description RECOMMENDED
SETTINGS
N9 AG3 PS_0[1] ROM_CONFIG[0] Define the ROM type when STRAP_BIOS_ROM_EN = 1,
L9 DBG_DATA16 NC#AG3 AG5 PS_0[2] ROM_CONFIG[1] Define the primary memory-aperture size when STRAP_BIOS_ROM_EN = 0.
AE9 DBG_DATA15 NC#AG5 PS_0[3] ROM_CONFIG[2] X
DPA
Y11 DBG_DATA14 AH3 001 = 256MB
AE8 DBG_DATA13 NC#AH3 AH1
AD9 DBG_DATA12 NC#AH1 PS_0[4] N/A Reserved for internal use only. Must be 1 at reset. 1
AC10 DBG_DATA11 AK3
AD7 DBG_DATA10 NC#AK3 AK1 AUD_PORT_CONN_ The LSB (least significant bit) of the strap option that
AC8 DBG_DATA9 NC#AK1 PS_0[5] PINSTRAP[0] indicates the number of audio-capable display outputs. 1
DVO
AC7 DBG_DATA8 AK5
AB9 DBG_DATA7 NC#AK5 AM3 1 = PCIe GEN3 is supported.
AB8 DBG_DATA6 NC#AM3 PS_1[1] STRAP_BIF_GEN3_EN_A 0 = PCIe GEN3 is not supported. 1= GEN3 is supported X
AB7 DBG_DATA5 AK6
AB4 DBG_DATA4 NC#AK6 AM5 0 = The CLKREQB power management capability is disabled
AB2 DBG_DATA3 NC#AM5 PS_1[2] STRAP_BIF_CLK_PM_EN 1 = The CLKREQB power management capability is enabled 0
DPB
Y8 DBG_DATA2 AJ7
D
Y7 DBG_DATA1 NC#AJ7 AH6 PS_1[3] N/A Reserved for internal use only. Must be 0 at reset. 0
D

+3VGS DBG_DATA0 NC#AH6

AK8 STRAP_TX_CFG_DRV_ 0 = The transmitter half-swing is enabled
NC#AK8 AL7 PS_1[4] FULL_SWING 1 = The transmitter full-swing is enabled 1
10K_0402_5% 1 @ 2 RV8 GPU_GPIO5 NC#AL7
0 = Tx deemphasis disabled.
W6 PS_1[5] STRAP_TX_DEEMPH_EN 1 = Tx deemphasis enabled. 1= Enable X
V6 NC#W6
1 2 GPU_GPIO0 NC#V6 V4
10K_0402_5% @ RV9 PS_2[1] N/A Reserved. 0
10K_0402_5% 1 @ 2 RV12 GPU_GPIO8 AC6 NC#V4 U5
10K_0402_5% 1 @ 2 RV13 GPU_GPIO9 AC5 NC#AC6 NC#U5 PS_2[2] N/A Reserved. 0
10K_0402_5% 1 @ 2 RV14 GPU_GPIO10 NC#AC5 W3 VGA_VSSI_SEN 1 TV10 PAD @
10K_0402_5% 1 @ 2 RV25 GPU_GPIO11 AA5 NC#W3 V2 0 = Disable the external BIOS ROM device.
10K_0402_5% 1 @ 2 RV96 GPU_GPIO12 AA6 NC#AA5 NC#V2 1 = Enable the external BIOS ROM device.
DPC PS_2[3] STRAP_BIOS_ROM_EN 0= Disable X
10K_0402_5% 1 @ 2 RV34 GPU_GPIO13 +1.8VGS NC#AA6 Y4
10K_0402_5% 1 @ 2 RV81 GPU_GPIO22 NC#Y4 W5 0 = VGA controller capacity enabled.
1 2 GPU_VID1 NC#W5 1 = The device will not be recognized as the system’ s V GA
10K_0402_5% @ RV97 PS_2[4] STRAP_BIF_VGA_DIS 1
10K_0402_5% 1 @ 2 RV98 GPU_GPIO21 RV93 1 2 TOPAZ@ BP_0 U1 AA3 PLL_ANALOG_OUT RV94 1 @ 2 controller.
10K_0402_5% 1 @ 2 RV99 GPU_VID5 1 VGA_VDDCI_SEN W1 NC#U1 NC#AA3 Y2
10K_0402_5% TV11 16.2K_0402_1% PS_2[5] N/A Reserved 1
10K_0402_5% 1 @ 2 RV106 GPU_VID2 RV95 1 2 TOPAZ@ @ PAD BP_1 U3 NC#W1 NC#Y2
10K_0402_5% Y6 NC#U3 J8 Board configuration related strapping, such as for memory ID
Reserve for Topaz
10K_0402_5% 1 @ 2 RV1011 GPU_GPIO17 TV12 1 PLL_ANALOG_IN AA1 NC#Y6 NC#J8 PS_3[1] BOARD_CONFIG[0] 100 = Hynix 4Gb 000 = Hynix 8Gb X
@ PAD NC#AA1 PS_3[2] BOARD_CONFIG[1] 111 = Micron 4Gb 010 = Micron 8Gb
5.11K_0402_1% 1 @ 2 RV1039 TESTEN PS_3[3] BOARD_CONFIG[2] 110 = Samsung 4Gb 001 = Samsung 8Gb

Determines the maximum number of digital display audio endpoints

Reserve I2C that will be presented to the OS and user.(Combine with PS_0[5])
111 = No usable endpoints.
R1 AUD_PORT_CONN_ 110 = One usable endpoint.
R3 SCL PS_3[4] PINSTRAP[1] 101 = Two usable endpoints. 111= No usable endpoints.
SDA 100 = Three usable endpoints. 11
AM26 DIECRACKMON RV120 1 2 TOPAZ@ PS_3[5] AUD_PORT_CONN_ 011 = Four usable endpoints.
+VGA_CORE NC_R AK26 10K_0402_5% PINSTRAP[2] 010 = Five usable endpoints.
GPU_GPIO0 U6 GENERAL PURPOSE I/ONC_AVSSN#AK26 001 = Six usable endpoints.
U10 GPIO_0 AL25 000 = All endpoints are usable.
T10 NC_GPIO_1 NC_G AJ25
VGA_SMB_DATA U8 NC_GPIO_2 NC_AVSSN#AJ25
RB751V-40_SOD323-2 VGA_SMB_CLK U7 SMBDATA AH24
DV1 1 2 @ GPU_GPIO5 T9 SMBCLK NC_B AG25 +1.8VGS +1.8VGS
35 VGA_AC_DET GPU_VID5 T8 GPIO_5_AC_BATT NC_AVSSN#AG25
T7 GPIO_6 DAC1 AH26
GPU_VR_HOT# GPU_GPIO8 NC_GPIO_7 NC_HSYNC

1
RV104 1 2 PX@ P10 AJ27 RV22 1 2 4.7K_0402_5%
0_0402_5% GPU_GPIO9 P4 GPIO_8_ROMSO NC_VSYNC TOPAZ@ RV71 RV74
GPU_GPIO10 P2 GPIO_9_ROMSI 8.45K_0402_1% 8.45K_0402_1%
GPU_GPIO11 N6 GPIO_10_ROMSCK AD22 PX@ PX@
+VGA_CORE GPU_GPIO12 NC_GPIO_11 NC_RSET Pull down for none OBFF design
@ PAD TV3 1 N5
GPU_GPIO13 NC_GPIO_12 PS_0 PS_1

2
N3 AG24
Y9 NC_GPIO_13 NC_AVDD AE22
GPU_SVD GPU_VID3 NC_GPIO_14 NC_AVSSQ

1
0_0402_5% 1 EXO@ 2 RV103 N1 1 1
C +VGA_CORE 10K_0402_5% 1 @ 2 RV67 GPU_GPIO16 M4 GPIO_15_PWRCNTL_0 AE23 RV77 CV15 RV80 CV16 C
0_0402_5% 1 @ 2 RV107 GPU_GPIO17 R6 GPIO_16 NC_VDD1DI AD23 2K_0402_1% .01U_0402_16V7-K 2K_0402_1% .01U_0402_16V7-K
35,48 GPU_VR_HOT# GPIO_17_THERMAL_INT NC_VSS1DI
W10 PX@ @ PX@ @
10K_0402_5% 1 PX@ 2 RV68 GPIO_19_CTF M2 NC_GPIO_18 2 2
GPU_SVC GPU_VID4 GPIO_19_CTF FutureASIC/SEYMOUR/PARK CEC_1

2
0_0402_5% 1 EXO@ 2 RV105 P8 AM12 1 TV5
GPU_GPIO21 P7 GPIO_20_PWRCNTL_1 CEC_1 PAD @
GPU_GPIO22 N8 GPIO_21
GPU_VID2 AK10 GPIO_22_ROMCSB AK12 GPU_SVD_R RV110 1 TOPAZ@ 2 0_0402_5% +1.8VGS +1.8VGS
GPU_VR_HOT# 0_0402_5% 1 2 RV1012 GPU_VID1 AM10 GPIO_29 NC_SVI2#AK12 AL11 GPU_SVT_R GPU_SVD 48
@ RV109 1 TOPAZ@ 2 0_0402_5%
1 2 RV124 GPU_CLKREQ#_R N7 GPIO_30 NC_SVI2#AL11 AJ11 GPU_SVC_R GPU_SVT 48
0_0402_5% @ RV111 1 TOPAZ@ 2 0_0402_5%
7 GPU_CLKREQ# CLKREQB NC_SVI2#AJ11 GPU_SVC 48

1
JTAG_TRSTB L6 RV60 RV63
+3VGS JTAG_TDI L5 JTAG_TRSTB 10K_0402_5% 8.45K_0402_1%
JTAG_TCK L3 JTAG_TDI @ @
JTAG_TMS L1 JTAG_TCK AL13 GENLK_CLK 1
@ PAD TV1 PAD @
JTAG_TRSTB 1JTAG_TDO JTAG_TMS NC_GENLK_CLK GENLK_VSYNC 1 PS_2 PS_3

2
10K_0402_5% 1 @ 2 RV72 TV7 K4 AJ13 TV2 PAD @
10K_0402_5% 1 @ 2 RV75 JTAG_TDI RV64 1 PX@ 2 TESTEN K7 JTAG_TDO NC_GENLK_VSYNC
JTAG_TMS TESTEN

1
10K_0402_5% 1 @ 2 RV78 1K_0402_5% AF24 1 1
NC#AF24 AG13 RV69 CV18 RV70 CV19
10K_0402_5% 1 @ 2 RV40 JTAG_TCK NC_SWAPLOCKA AH12 4.75K_0402_1% .01U_0402_16V7-K 2K_0402_1% .01U_0402_16V7-K
AB13 NC_SWAPLOCKB PX@ @ @ @
+VGA_CORE NC_GENERICA 2 2
W8
GPU_CLKREQ# NC_GENERICB

2
470_0402_5% 1 @ 2 RV1040 W9
W7 NC_GENERICC AC19 PS_0
AD10 NC_GENERICD PS_0
2016/09/02: Pull-down GPU_CLKREQ# at GPU side NC_GENERICE_HPD4 PS_1
AJ9 AD19
AL9 NC#AJ9 PS_1
DBG_CNTL0 PS_2 Bit BOM
AE17 MLPS
AC14 PS_2
PX_EN NC_HPD1 PS_3 5 4 3 2 1 R_pu( ) R_pd( ) C(nF)
@ PAD TV6 1 AB16 AE20
PX_EN PS_3
PS_0[5:1] 1 1 0 0 1 RV71=8.45k RV77=2K CV15=NC
4.7K_0402_5% 1 @ 2 RV54
PX@ 2 1 CV25 XTALIN AE19 PS_1[5:1] 1 1 0 0 1 RV74=8.45K RV80=2K CV16=NC
@ PAD TV15 1 NC_DBG_VREFG AC16 TS_A
NC_DBG_VREFG
8P_0201_25V8-D PS_2[5:1] 1 1 0 0 0 RV60=NC RV69=4.75K CV18=NC
PS_3[5:1] 1 1 X X X RV63=X76 RV70=X76 CV19=NC
DDC/AUX
2

AE6
PLL/CLOCK NC_DDC1CLK AE5
YV1 with BOM strcture control, R_pu (Ω ) R_pd (Ω ) Bits [3:1]
27MHZ_10PF_7V27000050
GND1

OSC1

PX@ NC_DDC1DATA
RV63,RV70 change to different value to
1

AD2 +VGA_CORE NC 4750 000

RV46 NC_AUX1P AD4
1
adjust VRAM config
NC_AUX1N
1M_0402_5% RV24 with BOM strcture control, 8450 2000 001
AC11
GND2

PX@ 100_0402_5%
OSC2

NC_DDC2CLK when config PEG3

AC13 TOPAZ@ 4530 2000 010
NC_DDC2DATA RV74 change to 8.45K,
2

RV80 change to 2K
2

XTALIN AM28 AD13 6980 4990 011

XTALIN NC_AUX2P
3

XTALOUT AK28 AD11

XTALOUT NC_AUX2N 4530 4990 100
B XO_IN VGA_VSS_SEN_R Capacitor Value (nF) Bits [5:4] B
10K_0402_5% 1 PX@ 2 RV45 AC22 AD20 RV125 1 TOPAZ@ 2 0_0402_5%
1 XO_IN2 XO_IN NC#AD20 VGA_CORE_SEN_R VGA_VSS_SEN 48
10K_0402_5% PX@ 2 RV50 AB22 AC20 RV126 1 TOPAZ@ 2 0_0402_5% 680 00 3240 5620 101
XO_IN2 NC#AC20 VGA_CORE_SEN 48
PX@ 2 1 CV32 XTALOUT AE16 82 01 3400 10000 110
NC#AE16 AD16
8P_0201_25V8-D NC#AD16 10 10 4750 NC 111
1

SEYMOUR/FutureASIC AC1
@ PAD TV13 1 GPU_DPLUS T4 NC_DDCVGACLK AC3 RV23 NC 11
no symbol for 8pf cap, PLM has PN,change the PN GPU_DMINUS DPLUS THERMAL NC_DDCVGADATA Note: 0402 1% resistors are required.
@ PAD TV14 1 T2 100_0402_5%
DMINUS TOPAZ@
+3VGS +VDDIO_GPU
GPIO_28_FDO
2

+3VGS RV41 1 @ 2 R5
10K_0402_5% LV3 1 2 PX@ +TSVDD AD17 GPIO28_FDO RV234 1 2 EXO@
+1.8VGS TSVDD SVC SVD Output Voltage (V)
BLM15PD121SN1D_2P AC17 +1.8VGS 0_0402_5%
TSVSS +VGA_CORE 0 0 1.1
2

(1.8V@20mA TSVDD) RV203 1 2 TOPAZ@

RV42 1 0 1 1.0 0_0402_5%
10K_0402_5% CV21 @
EXO@ 1U_0402_6.3V6K For Topaz, RV23/RV24 stuff 100ohm 1 0 0.9
PX@ For EXO, RV23/RV24 stuff 0hm
2
1

2
1 1 0.8
RV205 RV204 RV209
10K_0402_5% 10K_0402_5% 10K_0402_5%
Connect GPIO_28 to 10K pull @ PX@ @
down to enable MLPS. GPU_SVD

1
GPU_SVC
GPU_SVT
RV242 2 @ 1 0_0402_5% WRST# 35

2
RV206 RV207 RV210
10K_0402_5% 10K_0402_5% 10K_0402_5%
RV243 2 @ 1 0_0402_5% APU_SHUTDOWN# 7 PX@ @ @

1
1

C QV13
GPU_RST# @ 1 2 DV2 RV128 1 @ 2 2 MMBT3904WH_SOT323-3 Internal VGA Thermal Sensor
15 GPU_RST#
2.2K_0402_5% B @
0.1U_0201_6.3V6-K

SDM10U45LP-7_DFN1006-2-2 @ E
3

+3VGS
1

1
RV131 +3VGS
GPIO_19_CTF 1 @ 2 RV132 100K_0402_5%
47K_0402_5% @
2
1

A A
CV215
2

RV43 RV44
2

47K_0402_5% 47K_0402_5%
G

PX@ PX@
2

VGA_SMB_CLK QV4A 1 6 PX@

S

EC_SMB_CK3 6,30,35
D

2N7002KDWH_SOT363-6
G

VGA_SMB_DATA QV4B 4 3 PX@

S

EC_SMB_DA3 6,30,35
D

2N7002KDWH_SOT363-6

Security Classification LC Future Center Secret Data Title

Issued Date 2016/08/16 Deciphered Date 2017/08/15 ATI_EXO-PRO_Main_MSIC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Re v
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 320ABR
Date: Thursday, January 12, 2017 Sheet 16 of 50
5 4 3 2 1
 5 4 3 2 1

UV1F
+VGA_CORE

D D
AB11
NC_VARY_BL AB12
NC_DIGON

AL15
NC_UPHYAB_TMDPA_TX0N AK14
NC_UPHYAB_TMDPA_TX0P
AH16
NC_UPHYAB_TMDPA_TX1N AJ15
NC_UPHYAB_TMDPA_TX1P
AL17
NC_UPHYAB_TMDPA_TX2N AK16
NC_UPHYAB_TMDPA_TX2P
AH18
NC_UPHYAB_TMDPA_TX3N AJ17
NC_UPHYAB_TMDPA_TX3P
AL19
NC_TXOUT_L3P AK18
NC_TXOUT_L3N
C C
TMDP

AH20
NC_UPHYAB_TMDPB_TX0N AJ19
NC_UPHYAB_TMDPB_TX0P
AL21
NC_UPHYAB_TMDPB_TX1N AK20
NC_UPHYAB_TMDPB_TX1P
AH22
NC_UPHYAB_TMDPB_TX2N AJ21
NC_UPHYAB_TMDPB_TX2P
AL23
NC_UPHYAB_TMDPB_TX3N AK22
NC_UPHYAB_TMDPB_TX3P
AK24
NC_TXOUT_U3P AJ23
NC_TXOUT_U3N

@
B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2016/08/16 Deciphered Date 2017/08/15 ATI_EXO-PRO_TMDP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 320ABR
Date: Thursday, January 12, 2017 Sheet 17 of 50
5 4 3 2 1
 5 4 3 2 1

+1.8VGS (1.8V@425mA DP_VDDR)

RV48 1 @ 2 0_0603_5% +DP_VDDR
UV1G UV1E

PX@

PX@
DP POWER NC/DP POWER

10U_0603_6.3V6M

1U_0402_6.3V6K
1 1
AG15 AE11 AA27 A3
AG16 NC_DP_VDDR#AG15 NC#AE11 AF11 AB24 GND_1 GND_65 A30
D D
AF16 NC_DP_VDDR#AG16 NC#AF11 AE13 AB32 GND_2 GND_66 AA13
2 2 AG17 NC_DP_VDDR#AF16 NC#AE13 AF13 AC24 GND_3 GND_67 AA16

CV39

CV40
AG18 NC_DP_VDDR#AG17 NC#AF13 AG8 AC26 GND_4 GND_68 AB10
AG19 NC_DP_VDDR#AG18 NC#AG8 AG10 AC27 GND_5 GND_69 AB15
AF14 NC_DP_VDDR#AG19 NC#AG10 AD25 GND_6 GND_70 AB6
DP_VDDR#AF14 AD32 GND_7 GND_71 AC9
AE27 GND_8 GND_72 AD6
+1.05VGS AF32 GND_9 GND_73 AD8
(0.95V@560mA DP_VDDC) GND_10 GND_74
AG27 AE7
RV47 1 @ 2 0_0603_5% +DP_VDDC AG20 AF6 AH32 GND_11 GND_75 AG12
AG21 NC_DP_VDDC#AG20 NC#AF6 AF7 K28 GND_12 GND_76 AH10
NC_DP_VDDC#AG21 NC#AF7 GND_13 GND_77

PX@

PX@
AF22 AF8 K32 AH28

0.1U_0201_6.3V6-K
AG22 NC_DP_VDDC#AF22 NC#AF8 AF9 L27 GND_14 GND_78 B10

1U_0402_6.3V6K
AD14 NC_DP_VDDC#AG22 NC#AF9 M32 GND_15 GND_79 B12
1 1 DP_VDDC#AD14 GND_16 GND_80
N25 B14
N27 GND_17 GND_81 B16
P25 GND_18 GND_82 B18
2 2 AG14 AE1 P32 GND_19 GND_83 B20

CV38

CV37
AH14 NC_DP_VSSR_1 NC#AE1 AE3 R27 GND_20 GND_84 B22
AM14 NC_DP_VSSR_2 NC#AE3 AG1 T25 GND_21 GND_85 B24
AM16 NC_DP_VSSR_3 NC#AG1 AG6 T32 GND_22 GND_86 B26
AM18 NC_DP_VSSR_4 NC#AG6 AH5 U25 GND_23 GND_87 B6
AF23 NC_DP_VSSR_5 NC#AH5 AF10 U27 GND_24 GND_88 B8
AG23 NC_DP_VSSR_6 NC#AF10 AG9 V32 GND_25 GND_89 C1
C
AM20 NC_DP_VSSR_7 NC#AG9 AH8 W25 GND_26 GND_90 C32 C
AM22 NC_DP_VSSR_8 NC#AH8 AM6 W26 GND_27 GND_91 E28
AM24 NC_DP_VSSR_9 NC#AM6 AM8 W27 GND_28 GND_92 F10
AF19 NC_DP_VSSR_10 NC#AM8 AG7 Y25 GND_29 GND_93 F12
AF20 NC_DP_VSSR_11 NC#AG7 AG11 Y32 GND_30 GND_94 F14
AE14 NC_DP_VSSR_12 NC#AG11 GND_31 GND_95 F16
DP_VSSR_13 GND_96 F18
GND_97 F2
GND_98 F20
RV49 1 @ 2 AF17 AE10 M6 GND_99 F22
150_0402_1% NC_UPHYAB_DP_CALR NC#AE10 N13 GND_32 GND_100 F24
N16 GND_33 GND_101 F26
N18 GND_34 GND_102 F6
@ N21 GND_35 GND
GND_103 F8
P6 GND_36 GND_104 G10
P9 GND_37 GND_105 G27
R12 GND_38 GND_106 G31
R15 GND_39 GND_107 G8
R17 GND_40 GND_108 H14
R20 GND_41 GND_109 H17
T13 GND_42 GND_110 H2
T16 GND_43 GND_111 H20
T18 GND_44 GND_112 H6
T21 GND_45 GND_113 J27
T6 GND_46 GND_114 J31
B B
U15 GND_47 GND_115 K11
U17 GND_48 GND_116 K2
U20 GND_49 GND_117 K22
U9 GND_50 GND_118 K6
V13 GND_51 GND_119
V16 GND_52
V18 GND_53
Y10 GND_54
Y15 GND_55
Y17 GND_56
Y20 GND_57
R11 GND_58 A32
T11 GND_59 VSS_MECH_1 AM1
AA11 GND_60 VSS_MECH_2 AM32
M12 GND_61 VSS_MECH_3
N11 GND_62
V11 GND_63
GND_64

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2016/08/16 Deciphered Date 2017/08/15 ATI_EXO-PRO_DP Power
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 320ABR
Date: Thursday, January 12, 2017 Sheet 18 of 50
5 4 3 2 1
 5 4 3 2 1

+1.35VGS
For DDR3/GDDR5, 1500mA@1.5V

CV48

CV51

CV52

CV53

CV54

CV55

CV56

CV217
10U_0603_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

0.01U_0201_10V6K
0.1U_0201_6.3V6-K
1 1 1 1 1 1 1 1 1 UV1D +1.8VGS
CV501 (1.8V@100mA PCIE_PVDD)
33P_0402_50V8J AM30
MEM I/O PCIE_PVDD

PCIE
RF_PXNS@

CV46

CV47
2 2 2 2 2 2 2 2 2 H13 AB23

10U_0603_6.3V6M
1U_0402_6.3V6K
H16 VDDR1_1 NC#AB23 AC23

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@
VDDR1_2 NC#AC23 1 1
RF H19 AD24
J10 VDDR1_3 NC#AD24 AE24
J23 VDDR1_4 NC#AE24 AE25
J24 VDDR1_5 NC#AE25 AE26 2 2
J9 VDDR1_6 NC#AE26 AF25

PX@

PX@
K10 VDDR1_7 NC#AF25 AG26
+1.8VGS +VDD_CT K23 VDDR1_8 NC#AG26 +1.05VGS
(1.8V@13mA VDD_CT) VDDR1_9
K24 (0.95V@2500mA PCIE_VDDC)
D LV7 1 @ 2 0_0402_5% K9 VDDR1_10 L23 D
L11 VDDR1_11 PCIE_VDDC_1 L24

CV144
L12 VDDR1_12 PCIE_VDDC_2 L25

CV64

CV65

CV66

CV67

CV68

CV69

CV71
1U_0402_6.3V6K
L13 VDDR1_13 PCIE_VDDC_3 L26

10U_0603_6.3V6M
1

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
L20 VDDR1_14 PCIE_VDDC_4 M22
VDDR1_15 PCIE_VDDC_5 1 1 1 1 1 1 1 1
L21 N22 CV502
L22 VDDR1_16 PCIE_VDDC_6 N23 33P_0402_50V8J
2 VDDR1_17 PCIE_VDDC_7 N24

PX@
RF_PX@
PCIE_VDDC_8 R22 2 2 2 2 2 2 2 2
PCIE_VDDC_9 T22

PX@

PX@

PX@

PX@

PX@

PX@

PX@
PCIE_VDDC_10 RF
LEVEL U22
TRANSLATION PCIE_VDDC_11 V22
AA20 PCIE_VDDC_12 +VGA_CORE
AA21 VDD_CT_1
AB20 VDD_CT_2 AA15
+3VGS AB21 VDD_CT_3 CORE VDDC_1 N15
(3.3V@25mA VDDR3) VDD_CT_4 VDDC_2 N17

CV73

CV74

CV75

CV76

CV77

CV84
CV141

CV143

CV146

CV148

CV150

CV152

CV159

CV133

CV137

CV151
2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M
LV8 1 @ 2 0_0402_5% +VDDR3 VDDC_3 R13
I/O VDDC_4 R16

CV149
VDDC_5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
change LV4 to SM01000MK00 (S SUPPRE_ BLM15AG221SN1 122) AA17 R18

1U_0402_6.3V6K
AA18 VDDR3_1 VDDC_6 Y21
as DFC suggest, footprint with 1
AB17 VDDR3_2 VDDC_7 T12
MURAT_BLM15PD121SN1D_2P AB18 VDDR3_3 VDDC_8 T15 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
VDDR3_4 VDDC_9 T17

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@
2 V12 VDDC_10 T20

PX@
Y12 NC_VDDR4_1 VDDC_11 U13
+1.8VGS U12 NC_VDDR4_2 VDDC_12 U16
NC_VDDR4_3 VDDC_13 U18
(1.8V@130mA MPLL_PVDD) VDDC_14 V21
LV4 1 2 PX@ +MPLL_PVDD VDDC_15 V15
BLM15AG221SN1 VDDC_16 V17

CV139

CV153

CV156

CV160

CV134

CV135
VDDC_17 V20
CV26

CV34

CV27

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
VDDC_18 Y13

POWER
CV24

10U_0603_6.3V6M

10U_0603_6.3V6M

1 1 1 1 1 1 1
1U_0402_6.3V6K
0.1U_0201_6.3V6-K

VDDC_19 Y16 CV503

1 1 1 VDDC_20
1 Y18 33P_0402_50V8J
VDDC_21 AA12 RF_PX@
VDDC_22 M11 2 2 2 2 2 2 2
2 2 2 VDDC_23 N12

PX@

PX@

PX@

PX@

PX@

PX@
2 VDDC_24 U11
PX@

PX@

PX@

VDDC_25
RF
@

For EMC
PLL
C +1.05VGS C
(0.95V@1400mA BIF_VDDC)
+1.8VGS R21
BIF_VDDC_1 U21
(1.8V@75mA SPLL_PVDD) BIF_VDDC_2
+SPLL_PVDD +MPLL_PVDD 1
LV5 1 2 PX@ L8 CV41
BLM15PD121SN1D_2P MPLL_PVDD +VGA_CORE 1U_0402_6.3V6K
PX@
CV29

CV30

ISOLATED
(GDDR3/DDR3 8.8A@1.12V VDDCI) 2
CV28

10U_0603_6.3V6M

1U_0402_6.3V6K

CORE I/O
0.1U_0201_6.3V6-K

1 1 M13
+SPLL_PVDD H7 VDDCI_1 M15
1 SPLL_PVDD VDDCI_2 M16

CV218

CV219

CV158

CV132

CV136

CV138

CV220
+1.05VGS VDDCI_3 M17

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K
2 2 VDDCI_4 M18
(0.95V@100mA SPLL_VDDC)

10U_0603_6.3V6M

10U_0603_6.3V6M
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
2 VDDCI_5 M20
+SPLL_VDDC VDDCI_6 1 1 1 1 1 1 1 1
LV6 1 2 PX@ H8 M21
PX@

PX@

CV504
@

BLM15PD121SN1D_2P SPLL_VDDC VDDCI_7 N20 33P_0402_50V8J

For EMC J7 VDDCI_8 RF_PX@
SPLL_PVSS 2 2 2 2 2 2 2 2
CV35

CV36
0.1U_0201_6.3V6-K

PX@

PX@

PX@

PX@

PX@

PX@

PX@
1U_0402_6.3V6K

1 1 1 RF
CV33 @
0.1U_0201_6.3V6-K
@
2 2 2
PX@

PX@

For EMC

MOS. AO3402 VGS MAX is 12V +1.8VALW TO +1.8VGS +1.05VALW to +1.05VGS

+1.8VALW QV2 +1.8VGS Can change to low cost and small Can change to low cost and +1.05VALW
AO3402_SOT-23-3 QV3 +1.05VGS
PX@
size MOS. AO3402 small size MOS.Rdson<22mohm AON6414AL_DFN8-5
+1.8VGS /0.5A Rdson<65mohm Reserve for GPU support +0.95VS /2A PX@
1 3
D S 1
CV518

CV519

CV241

CV243

CV242
0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

B 2 B
10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1
G

5 3

CV521
1 1 1 1 1

0.1U_0201_6.3V6-K

1
RV1001

CV240

CV238

CV239
2

+5VALW 470_0603_5% RV1002

10U_0603_6.3V6M

10U_0603_6.3V6M
1 1

1U_0402_6.3V6K
@ PXS_PW REN#_H 1 @ 2 RV245 CV520 470_0603_5%
1 1 1

4
1 PX@ 2 RV1015 2 2 2 2 2 15K_0402_5% 0.1U_0201_6.3V6-K @
2
PX@

PX@

V20B+ 20K_0402_5% @
@

2
2 2
@

PXS_PW REN#_H 2 2 2
1

1 @ 2 RV202 D QV20 130K_0402_5% 1 PX@ 2 RV1006

@
PXS_PW REN# V20B+

1
2

PX@

PX@

PX@
120K_0402_5% D QV21
G 120K_0402_5% 1 @ 2 RV1016 2 PXS_PW REN#
+5VALW
1

1
1 G
1

QV31 D RV123 1 S 2N7002KW_SOT323-3 RV1004 CV221

PXS_PW REN#
3

2 150K_0402_5% CV237 @ QV23 1 D 1M_0402_5% 0.1U_0201_25V6-K S 2N7002KW_SOT323-3

PXS_PW REN#

3
G @ 0.1U_0201_25V6-K 2 PX@ PX@ @
PX@ G 2
2

2
2N7002KW_SOT323-3 S 2
3

PX@ 2N7002KW_SOT323-3 S
3

PX@
RV127 is 1% , will change to 5%
change MOS from 7408 to 6414 for Rds on consider

+3VGS +3.3VS TO +3VGS +VGA_CORE +1.35VGS

+3VALW +3.3VGS /25mA
+3VS RV1014 1 PX@ 2 0_0603_5% LP2301ALT1G_SOT23-3
1

RV1013 1 @ 2 0_0603_5% QV6 3 1 PX@ RV166 RV1005

S

470_0603_5% 470_0603_5%
CV513

CV511
10U_0603_6.3V6M

@ @
1U_0402_6.3V6K

1 1
G
2

RV1007
470_0603_5%
+5VALW @
2 2
1

1
PX@

PX@

D D QV25
PXS_PW REN# PXS_PW REN# 2 PXS_PW REN#
2

RV1009 1 PX@ 2 RV1010 2 PX@ 1 QV19 2

20K_0402_5% 15K_0402_5% G 2N7002KW_SOT323-3 G
A @ A
1
1

CV517 D QV28 S S 2N7002KW_SOT323-3

PXS_PW REN#
3

3
1

QV27 D 0.1U_0201_6.3V6-K 2 @
PXS_PW REN 2 PX@ G
7,47,48 PXS_PW REN G 2
S 2N7002KW_SOT323-3
3

2N7002KW_SOT323-3 S @
3

PX@

Security Classification LC Future Center Secret Data Title

Issued Date 2016/08/16 Deciphered Date 2017/08/15 ATI_EXO-PRO_Power
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
320ABR 0.1

Date: Thursday, January 12, 2017 Sheet 19 of 50

5 4 3 2 1
 5 4 3 2 1

UV1C
DQA0_[31..0]
DQA0_[31..0] 21 GDDR5/DDR3 GDDR5/DDR3
DQA0_0 K27 K17 MAA0_0
DQA1_[31..0] DQA0_1 J29 DQA0_0 MAA0_0/MAA_0 J20 MAA0_1
DQA1_[31..0] 22 DQA0_2 DQA0_1 MAA0_1/MAA_1 MAA0_2
H30 H23
DQA0_3 H32 DQA0_2 MAA0_2/MAA_2 G23 MAA0_3
DQA0_4 G29 DQA0_3 MAA0_3/MAA_3 G24 MAA0_4
DQA0_5 F28 DQA0_4 MAA0_4/MAA_4 H24 MAA0_5
DQA0_6 F32 DQA0_5 MAA0_5/MAA_5 J19 MAA0_6
D DQA0_6 MAA0_6/MAA_6 D
DQA0_7 F30 K19 MAA0_7
DQA0_8 C30 DQA0_7 MAA0_7/MAA_7 G20 MAA0_8
MAA0_[8..0] DQA0_9 F27 DQA0_8 MAA0_8/MAA_13 L17
MAA0_[8..0] 21 DQA0_10 A28 DQA0_9 MAA0_9/MAA_15
DQA0_11 C28 DQA0_10 J14 MAA1_0
MAA1_[8..0] DQA0_12 E27 DQA0_11 MAA1_0/MAA_8 K14 MAA1_1
MAA1_[8..0] 22 DQA0_13 G26 DQA0_12 MAA1_1/MAA_9 J11 MAA1_2
DQA0_14 D26 DQA0_13 MAA1_2/MAA_10 J13 MAA1_3
DQA0_15 F25 DQA0_14 MAA1_3/MAA_11 H11 MAA1_4
DQA0_16 A25 DQA0_15 MAA1_4/MAA_12 G11 MAA1_5
DQA0_17 C25 DQA0_16 MAA1_5/MAA_BA2 J16 MAA1_6
DQA0_18 E25 DQA0_17 MAA1_6/MAA_BA0 L15 MAA1_7
DQA0_19 D24 DQA0_18 MAA1_7/MAA_BA1 G14 MAA1_8
DQA0_20 E23 DQA0_19 MAA1_8/MAA_14 L16

MEMORY INTERFACE
DQA0_21 F23 DQA0_20 MAA1_9/RSVD
DQA0_22 D22 DQA0_21 E32 WCKA0_0
DQA0_23 F21 DQA0_22 W CKA0_0/DQMA0_0 E30 WCKA0#_0 WCKA0_0 21
DQA0_24 DQA0_23 W CKA0B_0/DQMA0_1 WCKA0_1 WCKA0#_0 21
E21 A21
DQA0_25 D20 DQA0_24 W CKA0_1/DQMA0_2 C21 WCKA0#_1 WCKA0_1 21
DQA0_26 DQA0_25 W CKA0B_1/DQMA0_3 WCKA1_0 WCKA0#_1 21
F19 E13
DQA0_27 DQA0_26 W CKA1_0/DQMA1_0 WCKA1#_0 WCKA1_0 22
A19 D12
DQA0_28 D18 DQA0_27 W CKA1B_0/DQMA1_1 E3 WCKA1_1 WCKA1#_0 22
DQA0_29 F17 DQA0_28 W CKA1_1/DQMA1_2 F4 WCKA1#_1 WCKA1_1 22
DQA0_30 A17 DQA0_29 W CKA1B_1/DQMA1_3 WCKA1#_1 22
DQA0_31 C17 DQA0_30 H28 EDCA0_0
DQA1_0 E17 DQA0_31 EDCA0_0/QSA0_0 C27 EDCA0_1 EDCA0_0 21
DQA1_1 D16 DQA1_0 EDCA0_1/QSA0_1 A23 EDCA0_2 EDCA0_1 21
C DQA1_1 EDCA0_2/QSA0_2 EDCA0_2 21 C
+1.35VGS DQA1_2 F15 E19 EDCA0_3
DQA1_3 A15 DQA1_2 EDCA0_3/QSA0_3 E15 EDCA1_0 EDCA0_3 21
DQA1_4 D14 DQA1_3 EDCA1_0/QSA1_0 D10 EDCA1_1 EDCA1_0 22
DQA1_5 DQA1_4 EDCA1_1/QSA1_1 EDCA1_2 EDCA1_1 22
1

F13 D6
DQA1_6 A13 DQA1_5 EDCA1_2/QSA1_2 G5 EDCA1_3 EDCA1_2 22
RV61
DQA1_7 DQA1_6 EDCA1_3/QSA1_3 EDCA1_3 22
40.2_0402_1% C13
PX@ DQA1_8 E11 DQA1_7 H27 DDBIA0_0
DQA1_9 DQA1_8 DDBIA0_0/QSA0_0B DDBIA0_1 DDBIA0_0 21
A11 A27
DQA1_9 DDBIA0_1/QSA0_1B DDBIA0_1 21
2

MVREFD_A DQA1_10 C11 C23 DDBIA0_2

DQA1_11 F11 DQA1_10 DDBIA0_2/QSA0_2B C19 DDBIA0_3 DDBIA0_2 21
DQA1_12 DQA1_11 DDBIA0_3/QSA0_3B DDBIA1_0 DDBIA0_3 21
1

1 A9 C15
DQA1_13 C9 DQA1_12 DDBIA1_0/QSA1_0B E9 DDBIA1_1 DDBIA1_0 22
RV65 CV154
DQA1_14 F9 DQA1_13 DDBIA1_1/QSA1_1B C5 DDBIA1_2 DDBIA1_1 22
100_0402_1% 1U_0402_6.3V6K
DQA1_15 D8 DQA1_14 DDBIA1_2/QSA1_2B H4 DDBIA1_3 DDBIA1_2 22
PX@ PX@
2 DQA1_16 E7 DQA1_15 DDBIA1_3/QSA1_3B DDBIA1_3 22
DQA1_16
2

DQA1_17 A7 L18 ADBIA0

DQA1_18 C7 DQA1_17 ADBIA0/ODTA0 K16 ADBIA0 21
ADBIA1
DQA1_19 F7 DQA1_18 ADBIA1/ODTA1 ADBIA1 22
DQA1_20 A5 DQA1_19 H26 CLKA0
DQA1_21 E5 DQA1_20 CLKA0 H25 CLKA0 21
CLKA#0
DQA1_22 DQA1_21 CLKA0B CLKA#0 21
C3
DQA1_23 E1 DQA1_22 G9 CLKA1
DQA1_24 DQA1_23 CLKA1 CLKA1 22
G7 H9 CLKA#1
DQA1_25 DQA1_24 CLKA1B CLKA#1 22
+1.35VGS G6
DQA1_26 G1 DQA1_25 G22 RASA#0
DQA1_27 G3 DQA1_26 RASA0B G17 RASA#0 21
RASA#1
DQA1_28 DQA1_27 RASA1B RASA#1 22
1

B J6 B
RV62 DQA1_29 J1 DQA1_28 G19 CASA#0
DQA1_30 J3 DQA1_29 CASA0B G16 CASA#0 21
40.2_0402_1% CASA#1
DQA1_31 J5 DQA1_30 CASA1B CASA#1 22
PX@
DQA1_31 H22 CSA0#_0
CSA0B_0 CSA0#_0 21
2

MVREFS_A MVREFD_A K26 J22

MVREFS_A J26 MVREFDA CSA0B_1
MVREFSA CSA1#_0
1

1 G13
J25 CSA1B_0 K13 CSA1#_0 22
RV66 CV157
100_0402_1% 1U_0402_6.3V6K RV55 1 PX@ 2 MEM_CALRP0 K25 NC#J25 CSA1B_1
PX@ PX@ 120_0402_1% MEM_CALRP0 K20 CKEA0
2 CKEA0 CKEA0 21
J17 CKEA1
CKEA1 CKEA1 22
2

G25 WEA#0
W EA0B WEA#0 21
DRAMRST L10 H10 WEA#1
DRAM_RST W EA1B WEA#1 22
PAD @ TV8 1 CLKTESTA K8
PAD @ TV9 1 CLKTESTB L7 CLKTESTA
CLKTESTB

A DRAMRST RV56 1 PX@ 2 RV57 1 2 PX@ A

DRAM_RST 21,22
10_0402_5% 51.1_0402_1%
1

RV58 1
4.99K_0402_1% CV147
PX@ 120P_0402_50V8-J Title
PX@
Security Classification LC Future Center Secret Data
2

2
Issued Date 2016/08/16 Deciphered Date 2017/08/15 ATI_EXO-PRO_MEM IF
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
320ABR 0.1

Date: Thursday, January 12, 2017 Sheet 20 of 50

5 4 3 2 1
 5 4 3 2 1

Lower 32 bits
DQA0_[31..0] 20
MF=0 No Mirror MF=1 Mirror
MAA0_[8..0] 20
UV5 UV6

MF=0 MF=1 MF=1 MF=0 MF=0 MF=1 MF=1 MF=0

+1.35VGS A4 DQA0_30 A4 DQA0_7

EDCA0_3 C2 DQ24 DQ0 A2 DQA0_28 EDCA0_0 C2 DQ24 DQ0 A2 DQA0_5
20 EDCA0_3 EDC0 EDC3 DQ25 DQ1 DQA0_31 20 EDCA0_0 EDC0 EDC3 DQ25 DQ1 DQA0_6
C13 B4 C13 B4
EDCA0_1 R13 EDC1 EDC2 DQ26 DQ2 B2 DQA0_29 EDCA0_2 R13 EDC1 EDC2 DQ26 DQ2 B2 DQA0_4
D D
20 EDCA0_1 EDC2 EDC1 DQ27 DQ3 DQA0_27 20 EDCA0_2 EDC2 EDC1 DQ27 DQ3 DQA0_3
1

1 R2 E4 R2 E4
RV1018 CV522 EDC3 EDC0 DQ28 DQ4 E2 DQA0_26 EDC3 EDC0 DQ28 DQ4 E2 DQA0_2 +1.35VGS
2.37K_0402_1% 1U_0402_6.3V6K DQ29 DQ5 F4 DQA0_24 DQ29 DQ5 F4 DQA0_1
@ @ DDBIA0_3 D2 DQ30 DQ6 F2 DQA0_25 DDBIA0_0 D2 DQ30 DQ6 F2 DQA0_0
2 20 DDBIA0_3 DBI0# DBI3# DQ31 DQ7 20 DDBIA0_0 DBI0# DBI3# DQ31 DQ7
D13 A11 D13 A11
+1.35VGS DDBIA0_1 DBI1# DBI2# DQ16 DQ8 +1.35VGS DDBIA0_2 DBI1# DBI2# DQ16 DQ8
2

P13 A13 P13 A13 CLKA0 60.4_0402_1% 1 PX@ 2 RV1031

VREFD1_A0 20 DDBIA0_1 DBI2# DBI1# DQ17 DQ9 20 DDBIA0_2 DBI2# DBI1# DQ17 DQ9
+1.35VGS P2 B11 +1.35VGS P2 B11
DBI3# DBI0# DQ18 DQ10 B13 DBI3# DBI0# DQ18 DQ10 B13 CLKA#0 60.4_0402_1% 1 PX@ 2 RV1036
DQ19 DQ11 DQ19 DQ11
1

1 CLKA0 J12 E11 CLKA0 J12 E11

20 CLKA0 CK DQ20 DQ12 CK DQ20 DQ12
RV1019 CV361 CLKA#0 J11 E13 CLKA#0 J11 E13
20 CLKA#0 CK# DQ21 DQ13 CK# DQ21 DQ13
5.49K_0402_1% 1U_0402_6.3V6K CKEA0 J3 F11 CKEA0 J3 F11
20 CKEA0 CKE# DQ22 DQ14 CKE# DQ22 DQ14
@ @ F13 F13
2 DQ23 DQ15 U11 DQA0_14 DQ23 DQ15 U11 DQA0_16
DQ8 DQ16 DQ8 DQ16
2

MAA0_2 H11 U13 DQA0_12 MAA0_4 H11 U13 DQA0_18

MAA0_5 K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 DQA0_15 MAA0_3 K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 DQA0_17
MAA0_4 K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 DQA0_13 MAA0_2 K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 DQA0_19
MAA0_3 H10 BA2/A4 BA0/A2 DQ11 DQ19 N11 DQA0_10 MAA0_5 H10 BA2/A4 BA0/A2 DQ11 DQ19 N11 DQA0_22
BA3/A3 BA1/A5 DQ12 DQ20 N13 DQA0_9 BA3/A3 BA1/A5 DQ12 DQ20 N13 DQA0_20
DQ13 DQ21 M11 DQA0_8 DQ13 DQ21 M11 DQA0_23
MAA0_7 K4 DQ14 DQ22 M13 DQA0_11 MAA0_0 K4 DQ14 DQ22 M13 DQA0_21
MAA0_1 H5 A8/A7 A10/A0 DQ15 DQ23 U4 MAA0_6 H5 A8/A7 A10/A0 DQ15 DQ23 U4
+1.35VGS MAA0_0 H4 A9/A1 A11/A6 DQ0 DQ24 U2 MAA0_7 H4 A9/A1 A11/A6 DQ0 DQ24 U2
MAA0_6 K5 A10/A0 A8/A7 DQ1 DQ25 T4 MAA0_1 K5 A10/A0 A8/A7 DQ1 DQ25 T4
MAA0_8 J5 A11/A6 A9/A1 DQ2 DQ26 T2 MAA0_8 J5 A11/A6 A9/A1 DQ2 DQ26 T2
A12/RFU/NC DQ3 DQ27 N4 A12/RFU/NC DQ3 DQ27 N4
DQ4 DQ28 DQ4 DQ28
1

1 A5 N2 A5 N2
RV1020 CV524 U5 VPP/NC1 DQ5 DQ29 M4 U5 VPP/NC1 DQ5 DQ29 M4
2.37K_0402_1% 1U_0402_6.3V6K VPP/NC2 DQ6 DQ30 M2 VPP/NC2 DQ6 DQ30 M2
@ @ DQ7 DQ31 DQ7 DQ31
2 J1 +1.35VGS J1 +1.35VGS
MF +1.35VGS MF
2

J10 J10
VREFD2_A0 1 PX@ 2 RV1017 J13 SEN B1 1 PX@ 2 RV1024 J13 SEN B1
120_0402_1% ZQ VDDQ1 D1 120_0402_1% ZQ VDDQ1 D1
VDDQ2 VDDQ2
1

1 F1 F1
C
RV1021 CV523 ADBIA0 J4 VDDQ3 M1 ADBIA0 J4 VDDQ3 M1 C
20 ADBIA0 ABI# VDDQ4 ABI# VDDQ4
5.49K_0402_1% 1U_0402_6.3V6K RASA#0 G3 P1 CASA#0 G3 P1
20 RASA#0 CSA0#_0 RAS# CAS# VDDQ5 RAS# CAS# VDDQ5
@ @ G12 T1 WEA#0 G12 T1
2 20 CSA0#_0 CS# WE# VDDQ6 CS# WE# VDDQ6
CASA#0 L3 G2 RASA#0 L3 G2
20 CASA#0 CAS# RAS# VDDQ7 CAS# RAS# VDDQ7
2

WEA#0 L12 L2 CSA0#_0 L12 L2

20 WEA#0 WE# CS# VDDQ8 WE# CS# VDDQ8
B3 B3
VDDQ9 D3 VDDQ9 D3
VDDQ10 F3 VDDQ10 F3
WCKA0#_1 D5 VDDQ11 H3 WCKA0#_0 D5 VDDQ11 H3
20 WCKA0#_1 WCKA0_1 WCK01# WCK23# VDDQ12 WCKA0_0 WCK01# WCK23# VDDQ12
D4 K3 D4 K3
20 WCKA0_1 WCK01 WCK23 VDDQ13 WCK01 WCK23 VDDQ13
M3 M3 UV6 SIDE
WCKA0#_0 P5 VDDQ14 P3 WCKA0#_1 P5 VDDQ14 P3 +1.35VGS
+1.35VGS 20 WCKA0#_0 WCKA0_0 WCK23# WCK01# VDDQ15 WCKA0_1 WCK23# WCK01# VDDQ15
P4 T3 P4 T3
20 WCKA0_0 WCK23 WCK01 VDDQ16 WCK23 WCK01 VDDQ16
E5 E5
VDDQ17 N5 VDDQ17 N5
VREFD2_A0 A10 VDDQ18 VREFD1_A0 A10 VDDQ18

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K
PX@

PX@

PX@
E10 E10

CD@

CD@

CD@

CD@
VREFD1_A0 U10 VREFD1 VDDQ19 VREFD2_A0 U10 VREFD1 VDDQ19
1

1 N10 N10 1 1 1 1 1 1 1 1
RV1023 CV526 VREFC_A0 J14 VREFD2 VDDQ20 B12 VREFC_A0 J14 VREFD2 VDDQ20 B12 CV562
2.37K_0402_1% 1U_0402_6.3V6K VREFC VDDQ21 D12 VREFC VDDQ21 D12 33P_0402_50V8J
PX@ @ VDDQ22 F12 VDDQ22 F12 RF_PX@
2 VDDQ23 H12 VDDQ23 H12 2 2 2 2 2 2 2 2

CV561

CV553

CV566

CV555

CV567

CV554

CV629
DRAM_RST VDDQ24 DRAM_RST VDDQ24
2

J2 K12 J2 K12
VREFC_A0 20,22 DRAM_RST RESET# VDDQ25 RESET# VDDQ25
M12 M12
VDDQ26 P12 VDDQ26 P12
VDDQ27 VDDQ27
1

1 T12 T12
RV1022 CV525 VDDQ28 G13 VDDQ28 G13
5.49K_0402_1% 1U_0402_6.3V6K H1 VDDQ29 L13 H1 VDDQ29 L13 +1.35VGS
VSS1 VDDQ30 VSS1 VDDQ30 UV6 SIDE
PX@ PX@ K1 B14 K1 B14
2 B5 VSS2 VDDQ31 D14 B5 VSS2 VDDQ31 D14
VSS3 VDDQ32 VSS3 VDDQ32
2

G5 F14 G5 F14
VSS4 VDDQ33 VSS4 VDDQ33

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K
PX@
L5 M14 L5 M14

CD@

CD@

CD@

CD@

CD@

CD@

CD@
T5 VSS5 VDDQ34 P14 T5 VSS5 VDDQ34 P14
VSS6 VDDQ35 VSS6 VDDQ35 1 1 1 1 1 1 1 1
B10 T14 B10 T14
D10 VSS7 VDDQ36 D10 VSS7 VDDQ36
G10 VSS8 G10 VSS8
B B
L10 VSS9 A1 L10 VSS9 A1 2 2 2 2 2 2 2 2

CV565

CV556

CV559

CV558

CV560

CV557

CV563

CV564
P10 VSS10 VSSQ1 C1 P10 VSS10 VSSQ1 C1
+1.35VGS T10 VSS11 VSSQ2 E1 T10 VSS11 VSSQ2 E1
UV5 SIDE VSS12 VSSQ3 VSS12 VSSQ3
H14 N1 H14 N1
K14 VSS13 VSSQ4 R1 K14 VSS13 VSSQ4 R1
VSS14 VSSQ5 U1 VSS14 VSSQ5 U1
VSSQ6 VSSQ6
0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K
PX@

PX@

H2 H2
CD@

CD@

CD@

CD@

CD@

+1.35VGS G1 VSSQ7 K2 +1.35VGS G1 VSSQ7 K2

1 1 1 1 1 1 1 1 VDD1 VSSQ8 VDD1 VSSQ8 UV6 SIDE
CV505 L1 A3 L1 A3 +1.35VGS
33P_0402_50V8J G4 VDD2 VSSQ9 C3 G4 VDD2 VSSQ9 C3
RF_PX@ L4 VDD3 VSSQ10 E3 L4 VDD3 VSSQ10 E3
2 2 2 2 2 2 2 2 C5 VDD4 VSSQ11 N3 C5 VDD4 VSSQ11 N3
CV85

CV86

CV87

CV88
CV552

CV155

CV628

VDD5 VSSQ12 VDD5 VSSQ12

PX@

PX@

PX@

PX@
R5 R3 R5 R3

CD@

CD@

CD@

CD@
VDD6 VSSQ13 VDD6 VSSQ13

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
C10 U3 C10 U3 1 1 1 1 1 1 1 1
R10 VDD7 VSSQ14 C4 R10 VDD7 VSSQ14 C4
D11 VDD8 VSSQ15 R4 D11 VDD8 VSSQ15 R4
G11 VDD9 VSSQ16 F5 G11 VDD9 VSSQ16 F5
L11 VDD10 VSSQ17 M5 L11 VDD10 VSSQ17 M5 2 2 2 2 2 2 2 2

CV573

CV572

CV571

CV575

CV574

CV568

CV569

CV570
+1.35VGS P11 VDD11 VSSQ18 F10 P11 VDD11 VSSQ18 F10
UV5 SIDE VDD12 VSSQ19 VDD12 VSSQ19
G14 M10 G14 M10
L14 VDD13 VSSQ20 C11 L14 VDD13 VSSQ20 C11
VDD14 VSSQ21 R11 VDD14 VSSQ21 R11
VSSQ22 VSSQ22
0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K
PX@

PX@

A12 A12
CD@

CD@

CD@

CD@

CD@

CD@

VSSQ23 C12 VSSQ23 C12 +1.35VGS

1 1 1 1 1 1 1 1 VSSQ24 VSSQ24
E12 E12
VSSQ25 N12 VSSQ25 N12
VSSQ26 R12 VSSQ26 R12
2 2 2 2 2 2 2 2 VSSQ27 VSSQ27

PX@
170-BALL U12 170-BALL U12

CD@
CV551

CV533

CV537

CV535

CV538

CV534

CV549

CV550

VSSQ28 VSSQ28

10U_0603_6.3V6M

10U_0603_6.3V6M
H13 H13 1 1
SGRAM GDDR5 VSSQ29 K13 SGRAM GDDR5 VSSQ29 K13
VSSQ30 A14 VSSQ30 A14
VSSQ31 C14 VSSQ31 C14
VSSQ32 E14 VSSQ32 E14 2 2

CV577

CV576
VSSQ33 N14 VSSQ33 N14
A
+1.35VGS VSSQ34 R14 VSSQ34 R14 A
UV5 SIDE VSSQ35 VSSQ35
U14 U14
VSSQ36 VSSQ36
H5GQ1H24AFR-T2L_BGA170 H5GQ1H24AFR-T2L_BGA170
PX@

PX@

PX@

PX@

PX@

@ @
CD@

CD@

CD@

CD@

CD@
10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 Security Classification LC Future Center Secret Data Title

CV78

CV79

CV80

CV81

CV82

CV83
CV548

CV545

CV546

CV547

Issued Date 2016/08/16 Deciphered Date 2017/08/15 ATI_EXO-PRO_VRAM_A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 320ABR
Date: Thursday, January 12, 2017 Sheet 21 of 50
5 4 3 2 1
 5 4 3 2 1

Upper 32 bits
MF=1 Mirror MF=0 No Mirror
DQA1_[31..0] 20

MAA1_[8..0] 20
UV7 UV8

MF=0 MF=1 MF=1 MF=0 MF=0 MF=1 MF=1 MF=0

+1.35VGS A4 DQA1_19 A4 DQA1_7

EDCA1_2 C2 DQ24 DQ0 A2 DQA1_18 EDCA1_0 C2 DQ24 DQ0 A2 DQA1_4
20 EDCA1_2 EDC0 EDC3 DQ25 DQ1 DQA1_16 20 EDCA1_0 EDC0 EDC3 DQ25 DQ1 DQA1_6
C13 B4 C13 B4
EDCA1_1 R13 EDC1 EDC2 DQ26 DQ2 B2 DQA1_17 EDCA1_3 R13 EDC1 EDC2 DQ26 DQ2 B2 DQA1_5
D D
20 EDCA1_1 EDC2 EDC1 DQ27 DQ3 DQA1_23 20 EDCA1_3 EDC2 EDC1 DQ27 DQ3 DQA1_3
1

1 R2 E4 R2 E4
RV1025 CV528 EDC3 EDC0 DQ28 DQ4 E2 DQA1_21 EDC3 EDC0 DQ28 DQ4 E2 DQA1_2
2.37K_0402_1% 1U_0402_6.3V6K DQ29 DQ5 F4 DQA1_22 DQ29 DQ5 F4 DQA1_0 +1.35VGS
@ @ DDBIA1_2 D2 DQ30 DQ6 F2 DQA1_20 DDBIA1_0 D2 DQ30 DQ6 F2 DQA1_1
2 20 DDBIA1_2 DBI0# DBI3# DQ31 DQ7 20 DDBIA1_0 DBI0# DBI3# DQ31 DQ7
D13 A11 D13 A11
+1.35VGS DDBIA1_1 DBI1# DBI2# DQ16 DQ8 +1.35VGS DDBIA1_3 DBI1# DBI2# DQ16 DQ8
2

P13 A13 P13 A13

VREFD2_A1 20 DDBIA1_1 DBI2# DBI1# DQ17 DQ9 20 DDBIA1_3 DBI2# DBI1# DQ17 DQ9
+1.35VGS P2 B11 +1.35VGS P2 B11
DBI3# DBI0# DQ18 DQ10 B13 DBI3# DBI0# DQ18 DQ10 B13 CLKA1 60.4_0402_1% 1 PX@ 2 RV1037
DQ19 DQ11 DQ19 DQ11
1

1 CLKA1 J12 E11 CLKA1 J12 E11

20 CLKA1 CK DQ20 DQ12 CK DQ20 DQ12
RV1026 CV527 CLKA#1 J11 E13 CLKA#1 J11 E13 CLKA#1 60.4_0402_1% 1 PX@ 2 RV1038
20 CLKA#1 CK# DQ21 DQ13 CK# DQ21 DQ13
5.49K_0402_1% 1U_0402_6.3V6K CKEA1 J3 F11 CKEA1 J3 F11
20 CKEA1 CKE# DQ22 DQ14 CKE# DQ22 DQ14
@ @ F13 F13
2 DQ23 DQ15 U11 DQA1_11 DQ23 DQ15 U11 DQA1_30
DQ8 DQ16 DQ8 DQ16
2

MAA1_4 H11 U13 DQA1_13 MAA1_2 H11 U13 DQA1_28

MAA1_3 K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 DQA1_10 MAA1_5 K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 DQA1_29
MAA1_2 K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 DQA1_12 MAA1_4 K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 DQA1_31
MAA1_5 H10 BA2/A4 BA0/A2 DQ11 DQ19 N11 DQA1_9 MAA1_3 H10 BA2/A4 BA0/A2 DQ11 DQ19 N11 DQA1_26
BA3/A3 BA1/A5 DQ12 DQ20 N13 DQA1_15 BA3/A3 BA1/A5 DQ12 DQ20 N13 DQA1_27
DQ13 DQ21 M11 DQA1_8 DQ13 DQ21 M11 DQA1_24
MAA1_0 K4 DQ14 DQ22 M13 DQA1_14 MAA1_7 K4 DQ14 DQ22 M13 DQA1_25
MAA1_6 H5 A8/A7 A10/A0 DQ15 DQ23 U4 MAA1_1 H5 A8/A7 A10/A0 DQ15 DQ23 U4
+1.35VGS MAA1_7 H4 A9/A1 A11/A6 DQ0 DQ24 U2 MAA1_0 H4 A9/A1 A11/A6 DQ0 DQ24 U2
MAA1_1 K5 A10/A0 A8/A7 DQ1 DQ25 T4 MAA1_6 K5 A10/A0 A8/A7 DQ1 DQ25 T4
MAA1_8 J5 A11/A6 A9/A1 DQ2 DQ26 T2 MAA1_8 J5 A11/A6 A9/A1 DQ2 DQ26 T2
A12/RFU/NC DQ3 DQ27 N4 A12/RFU/NC DQ3 DQ27 N4
DQ4 DQ28 DQ4 DQ28
1

1 A5 N2 A5 N2
RV1028 CV530 U5 VPP/NC1 DQ5 DQ29 M4 U5 VPP/NC1 DQ5 DQ29 M4
2.37K_0402_1% 1U_0402_6.3V6K VPP/NC2 DQ6 DQ30 M2 VPP/NC2 DQ6 DQ30 M2
@ @ DQ7 DQ31 DQ7 DQ31
2 J1 +1.35VGS J1 +1.35VGS
+1.35VGS MF MF
2

J10 J10
VREFD1_A1 1 PX@ 2 RV1032 J13 SEN B1 1 PX@ 2 RV1035 J13 SEN B1
120_0402_1% ZQ VDDQ1 D1 120_0402_1% ZQ VDDQ1 D1
VDDQ2 VDDQ2
1

1 F1 F1
C
RV1027 CV529 ADBIA1 J4 VDDQ3 M1 ADBIA1 J4 VDDQ3 M1 C
20 ADBIA1 ABI# VDDQ4 ABI# VDDQ4
5.49K_0402_1% 1U_0402_6.3V6K CASA#1 G3 P1 RASA#1 G3 P1
20 CASA#1 RAS# CAS# VDDQ5 CSA1#_0 RAS# CAS# VDDQ5
@ @ WEA#1 G12 T1 G12 T1
2 20 WEA#1 CS# WE# VDDQ6 CS# WE# VDDQ6
RASA#1 L3 G2 CASA#1 L3 G2
20 RASA#1 CAS# RAS# VDDQ7 CAS# RAS# VDDQ7
2

CSA1#_0 L12 L2 WEA#1 L12 L2

20 CSA1#_0 WE# CS# VDDQ8 WE# CS# VDDQ8
B3 B3
VDDQ9 D3 VDDQ9 D3
VDDQ10 F3 VDDQ10 F3
WCKA1#_1 D5 VDDQ11 H3 WCKA1#_0 D5 VDDQ11 H3
20 WCKA1#_1 WCKA1_1 WCK01# WCK23# VDDQ12 WCKA1_0 WCK01# WCK23# VDDQ12
D4 K3 D4 K3
20 WCKA1_1 WCK01 WCK23 VDDQ13 WCK01 WCK23 VDDQ13
M3 M3
WCKA1#_0 P5 VDDQ14 P3 WCKA1#_1 P5 VDDQ14 P3
+1.35VGS 20 WCKA1#_0 WCKA1_0 WCK23# WCK01# VDDQ15 WCKA1_1 WCK23# WCK01# VDDQ15 UV8 SIDE
P4 T3 P4 T3 +1.35VGS
20 WCKA1_0 WCK23 WCK01 VDDQ16 WCK23 WCK01 VDDQ16
E5 E5
VDDQ17 N5 VDDQ17 N5
VREFD2_A1 A10 VDDQ18 E10 VREFD1_A1 A10 VDDQ18 E10
VREFD1_A1 U10 VREFD1 VDDQ19 VREFD2_A1 U10 VREFD1 VDDQ19

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K
1

PX@

PX@
N10 N10

CD@

CD@

CD@

CD@

CD@
1 VREFC_A1 J14 VREFD2 VDDQ20 VREFC_A1 J14 VREFD2 VDDQ20
RV1029 CV532 B12 B12 1 1 1 1 1 1 1 1
2.37K_0402_1% 1U_0402_6.3V6K VREFC VDDQ21 D12 VREFC VDDQ21 D12 CV613
PX@ @ VDDQ22 F12 VDDQ22 F12 33P_0402_50V8J
2 VDDQ23 H12 VDDQ23 H12 RF_PX@
DRAM_RST VDDQ24 DRAM_RST VDDQ24 2 2 2 2 2 2 2 2
2

J2 K12 J2 K12

CV611

CV603

CV617

CV605

CV616

CV604

CV631
VREFC_A1 20,21 DRAM_RST RESET# VDDQ25 RESET# VDDQ25
M12 M12
VDDQ26 P12 VDDQ26 P12
VDDQ27 VDDQ27
1

1 T12 T12
RV1030 CV531 VDDQ28 G13 VDDQ28 G13
5.49K_0402_1% 1U_0402_6.3V6K H1 VDDQ29 L13 H1 VDDQ29 L13
PX@ PX@ K1 VSS1 VDDQ30 B14 K1 VSS1 VDDQ30 B14 +1.35VGS
2 VSS2 VDDQ31 VSS2 VDDQ31 UV8 SIDE
B5 D14 B5 D14
VSS3 VDDQ32 VSS3 VDDQ32
2

G5 F14 G5 F14
L5 VSS4 VDDQ33 M14 L5 VSS4 VDDQ33 M14
VSS5 VDDQ34 VSS5 VDDQ34

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K
PX@

PX@
T5 P14 T5 P14

CD@

CD@

CD@

CD@

CD@

CD@
B10 VSS6 VDDQ35 T14 B10 VSS6 VDDQ35 T14
VSS7 VDDQ36 VSS7 VDDQ36 1 1 1 1 1 1 1 1
D10 D10
G10 VSS8 G10 VSS8
B B
L10 VSS9 A1 L10 VSS9 A1
P10 VSS10 VSSQ1 C1 P10 VSS10 VSSQ1 C1 2 2 2 2 2 2 2 2

CV614

CV606

CV610

CV608

CV609

CV607

CV612

CV615
+1.35VGS T10 VSS11 VSSQ2 E1 T10 VSS11 VSSQ2 E1
UV7 SIDE VSS12 VSSQ3 VSS12 VSSQ3
H14 N1 H14 N1
K14 VSS13 VSSQ4 R1 K14 VSS13 VSSQ4 R1
VSS14 VSSQ5 U1 VSS14 VSSQ5 U1
VSSQ6 VSSQ6
0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K
PX@

PX@

H2 H2
CD@

CD@

CD@

CD@

CD@

+1.35VGS G1 VSSQ7 K2 +1.35VGS G1 VSSQ7 K2

1 1 1 1 1 1 1 1 VDD1 VSSQ8 VDD1 VSSQ8
CV596 L1 A3 L1 A3
33P_0402_50V8J G4 VDD2 VSSQ9 C3 G4 VDD2 VSSQ9 C3 +1.35VGS
VDD3 VSSQ10 VDD3 VSSQ10 UV8 SIDE
RF_PX@ L4 E3 L4 E3
2 2 2 2 2 2 2 2 C5 VDD4 VSSQ11 N3 C5 VDD4 VSSQ11 N3
CV586

CV579

CV601

CV580

CV602

CV578

CV630

R5 VDD5 VSSQ12 R3 R5 VDD5 VSSQ12 R3

VDD6 VSSQ13 VDD6 VSSQ13

PX@

PX@

PX@

PX@
C10 U3 C10 U3

CD@

CD@

CD@

CD@
VDD7 VSSQ14 VDD7 VSSQ14

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
R10 C4 R10 C4 1 1 1 1 1 1 1 1
D11 VDD8 VSSQ15 R4 D11 VDD8 VSSQ15 R4
G11 VDD9 VSSQ16 F5 G11 VDD9 VSSQ16 F5
L11 VDD10 VSSQ17 M5 L11 VDD10 VSSQ17 M5
+1.35VGS P11 VDD11 VSSQ18 F10 P11 VDD11 VSSQ18 F10 2 2 2 2 2 2 2 2
UV7 SIDE

CV623

CV621

CV622

CV625

CV624

CV618

CV619

CV620
G14 VDD12 VSSQ19 M10 G14 VDD12 VSSQ19 M10
L14 VDD13 VSSQ20 C11 L14 VDD13 VSSQ20 C11
VDD14 VSSQ21 R11 VDD14 VSSQ21 R11
VSSQ22 VSSQ22
0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K
PX@

PX@

A12 A12
CD@

CD@

CD@

CD@

CD@

CD@

VSSQ23 C12 VSSQ23 C12

1 1 1 1 1 1 1 1 VSSQ24 VSSQ24
E12 E12 +1.35VGS
VSSQ25 N12 VSSQ25 N12
VSSQ26 R12 VSSQ26 R12
2 2 2 2 2 2 2 2 170-BALL VSSQ27 U12 170-BALL VSSQ27 U12
CV600

CV581

CV585

CV582

CV584

CV583

CV598

CV599

VSSQ28 VSSQ28

PX@
H13 H13

CD@

10U_0603_6.3V6M

10U_0603_6.3V6M
SGRAM GDDR5 VSSQ29 K13 SGRAM GDDR5 VSSQ29 K13
VSSQ30 VSSQ30 1 1
A14 A14
VSSQ31 C14 VSSQ31 C14
VSSQ32 E14 VSSQ32 E14
VSSQ33 N14 VSSQ33 N14 2 2

CV627

CV626
A
+1.35VGS VSSQ34 R14 VSSQ34 R14 A
UV7 SIDE VSSQ35 VSSQ35
U14 U14
VSSQ36 VSSQ36
H5GQ1H24AFR-T2L_BGA170 H5GQ1H24AFR-T2L_BGA170
PX@

PX@

PX@

PX@

PX@

@ @
CD@

CD@

CD@

CD@

CD@
10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 Security Classification LC Future Center Secret Data Title

CV597

CV595

CV591

CV592

CV590

CV593

CV594

CV587

CV588

CV589

Issued Date 2016/08/16 Deciphered Date 2017/08/15 ATI_EXO-PRO_VRAM_B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 320ABR
Date: Thursday, January 12, 2017 Sheet 22 of 50
5 4 3 2 1
 5 4 3 2 1

+3VS
Need Short

LCD POWER CIRCUIT 1

J1 @
2
W=40 mils B+ to +LEDVDD POWER
+LCDVDD_CON 1 2
+3VS JUMP_43X39
U9 +LEDVDD
5 1 W=60mils LP2301ALT1G_SOT23-3 +3VS_CMOS V20B+
IN OUT
2A 80 mil
2 Q7 3 1 2 R22 1
1U_0402_6.3V6K

RF_NS@

D
0.1U_0201_6.3V6-K
1 GND

4.7U_0805_25V6-K

0.1U_0201_25V6-K
33P_0402_50V8J
0_0805_5% C25
C1

.1U_0402_10V6-K

0.01U_0402_25V7K
4.7U_0402_6.3V6M
PCH_ENVDD 4 3

10U_0603_6.3V6M

0.1U_0201_6.3V6-K
1 @1 1 1 @ 1 1 1 C23
EN OCB

C1323

C1322
G
1 1

2
2 C1321 C3
D SY6288C20AAC_SOT23-5 @ C23 0.1u for G HSW panel blink issue D
2 2 2 2 @ 2 @ 2 2
2 2

C122

C123
C2
R5 1 @ 2 CMOS_ON#_R
PCH_ENVDD 35 CMOS_ON#
100K_0402_5%
6 PCH_ENVDD
1

1
R35 C10
100K_0402_5% For RF .1U_0402_10V6-K
@
2
2

JEDP1
1
+LEDVDD 1
2
3 2
APU output enable Voh min is 1.8V-0.45V=1.35V 3
4
APU_EDP_TX0+ C19 2 1 0.1U_0201_6.3V6-K EDP_TX0+ 5 4
6 APU_EDP_TX0+ APU_EDP_TX0- C16 2 1 0.1U_0201_6.3V6-K EDP_TX0- 6 5
6 APU_EDP_TX0- 7 6
APU_EDP_TX1+ C17 2 1 0.1U_0201_6.3V6-K EDP_TX1+ 8 7
6 APU_EDP_TX1+ APU_EDP_TX1- C18 2 1 0.1U_0201_6.3V6-K EDP_TX1- 9 8
6 APU_EDP_TX1- 10 9
APU_EDP_AUX C20 2 1 0.1U_0201_6.3V6-K EDP_AUX 11 10
6 APU_EDP_AUX APU_EDP_AUX# C21 2 1 0.1U_0201_6.3V6-K EDP_AUX# 12 11
6 APU_EDP_AUX# 13 12
DISPOFF# 14 13
15 14
1 2 0_0402_5% INVT_PWM AUX don't pull high and pull low for eDP panel INVT_PWM 16 15
R19
6 PCH_EDP_PWM 17 16
@
+3VS 18 17
18
1

19
1 2 6 APU_EDP_HPD 20 19
R20 R21 @
100K_0402_5% 0_0402_5% 21 20
1 +LCDVDD_CON 21
C 22 C
@ W=60mils 23 22
C22 470P_0201_50V7-K +3VS 23
2

@ 24
2 32 DMIC_DATA 24
32 DMIC_CLK 25
26 25
Need Short 26
27
R182 1 2 0_0402_5% USB20_P1_R 28 27

+3VS
CMOS Camera 8 USB20_P1
8 USB20_N1
R183 1 2 0_0402_5% USB20_N1_R 29
30
28
29
+3VS_CMOS 30
1 31
32 G1
C1320 W=40mils G2
2

.047U_0201_6.3V6K
R10 EMC_NS@ DRAPH_FC5AF301-3181H
4.7K_0402_5% L12 EMC_NS@ 2
USB20_N1 USB20_N1_R ME@
@ 1 2
1 2
1

R12 1 2 0_0402_5% DISPOFF# USB20_P1 4 3 USB20_P1_R

35 BKOFF# 4 3
@
EXC24CH900U_4P
R14 1 2 0_0402_5% ENBKL
6 PCH_ENBKL ENBKL 35
@
1

R16 DMIC_CLK DISPOFF# INVT_PWM

470P_0201_50V7-K

470P_0201_50V7-K
100K_0402_5%
100P_0201_25V8J

EMC_NS@

EMC_NS@
C11

C12

C13
1 1 1
2

EMC_NS@

2 2 2

B B

EMC
Touch Screen
Touch Screen

USB20_P2_CONN
+5VS +5VS_TS
L33 USB20_N2_CONN
USB20_N2 1 2 USB20_N2_CONN
1 2
3

+5VS_TS R4675 1 TS@ 2 0_0402_5%

1 JTS1 ME@
USB20_P2 4 3 USB20_P2_CONN C2079 1
4 3 1
1

D42 0.1u_0201_10V6K 2 7
EXC24CH900U_4P TS@ R4677 2 TS@ 1 0_0402_5% TS_RS 3 2 GND1
1

2 35 EC_TS_ON 4 3 8
EMC_NS@ USB20_N2_CONN 4 GND2
R4678 1 TS@ 2 0_0402_5% 5
8 USB20_N2 USB20_P2_CONN 5
D41 R4676 1 TS@ 2 0_0402_5% 6
8 USB20_P2 6
AZC199-02S.R7G_SOT23-3
2

EMC_NS@ CVILU_CI1806M2HR0-NH
For EMI AZ5725-01F.R7GR_DFN1006P2X2
2

EMC_NS@
1

For ESD

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 eDP/CMOS/TS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 320ABR
Date: Thursday, January 12, 2017 Sheet 23 of 50
5 4 3 2 1
 5 4 3 2 1

L2 EMC@
HDMI_CLK-_C 1 2 HDMI_CLK-_CON 1 2 EMC_NS@
1 2 C26 10P_0201_25V8G
HDMI_CLK+_C 4 3 HDMI_CLK+_CON 1 2 EMC_NS@ +3VS
4 3 C27 10P_0201_25V8G
EXC24CH900U_4P
D D
L3 EMC@
HDMI_TX0-_C 1 2 HDMI_TX0-_CON 1 2 EMC_NS@
1 2 D3

5
C28 10P_0201_25V8G

G
Q1B HDMI_DET 1 1 10 9 HDMI_DET
HDMI_TX0+_C 4 3 HDMI_TX0+_CON 1 2 EMC_NS@
4 3 HDMICLK_R 2 2 HDMICLK_R
C29 10P_0201_25V8G 9 8
EXC24CH900U_4P APU_DDC_CLK 4 3 HDMICLK_R

S
6 APU_DDC_CLK HDMIDAT_R HDMIDAT_R
4 4 7 7

D
L4 EMC@ 2N7002KDWH_SOT363-6
HDMI_TX1-_C HDMI_TX1-_CON +5VS_HDMI +5VS_HDMI

2
1 2 1 2 EMC_NS@ 5 5 6 6

G
1 2 C30 10P_0201_25V8G Q1A
3 3
HDMI_TX1+_C 4 3 HDMI_TX1+_CON 1 2 EMC_NS@
4 3 C31 10P_0201_25V8G APU_DDC_DATA 1 6 HDMIDAT_R 8

S
6 APU_DDC_DATA
EXC24CH900U_4P

D
2N7002KDWH_SOT363-6
L5 EMC@ AZ1045-04F_DFN2510P10E-10-9
HDMI_TX2-_C 1 2 HDMI_TX2-_CON 1 2 EMC_NS@
1 2 EMC_NS@
C32 10P_0201_25V8G
HDMI_TX2+_C 4 3 HDMI_TX2+_CON 1 2 EMC_NS@
EMC
4 3 C33 10P_0201_25V8G
EXC24CH900U_4P

EMC +5VS_HDMI

+5VS +5VS_HDMI_F +5VS_HDMI

2
D4 D5
+3VS 2 @ F1
C @ 1 1 2 C
3
BAT54S-7-F_SOT23-3 RB491D_SOT23-3 0.5A_6V_1206L050YRHF

1
HDMI_CLK-_C R29 1 2 499_0402_1%
HDMI_CLK+_C Follow Zx05 and beema

1
R30 1 2 499_0402_1% C LP2301ALT1G_SOT23-3 1 2
Q43 2 R202 1 2 150K_0402_5% C34 @
HDMI_TX0-_C R31 1 2 499_0402_1% B 1 3 Q22 0.1u_0201_10V6K CC1279

2
1
E MMBT3904WH_SOT323-3 10U_0402_6.3V6M
HDMI_TX0+_C 2 1

3
R32 1 2 499_0402_1% RP2
6 APU_HDMI_HPD

1
2.2K_0404_4P2R_5%

G
2
HDMI_TX1-_C

1
R33 1 2 499_0402_1% R257
R910 100K_0402_5%
12,37 SUSP

3
4
HDMI_TX1+_C R34 1 2 499_0402_1% 100K_0402_5%
HDMI_DET
HDMI_TX2-_C

2
R37 1 2 499_0402_1%

2
+5VS_HDMI
HDMI_TX2+_C R38 1 2 499_0402_1% JHDMI1 ME@

18 15 HDMICLK_R
+5V_Power SCL 16 HDMIDAT_R
SDA
1

D Q13
2 APU_HDMI_TX0+ C38 2 1 0.1U_0201_6.3V6-K HDMI_TX0+_C R46 2 @ 1 0_0402_5% HDMI_TX0+_CON 7
+3VS 6 APU_HDMI_TX0+ APU_HDMI_TX0- HDMI_TX0-_C HDMI_TX0-_CON TMDS_Data0+
G 2N7002KW_SOT323-3 C37 2 1 0.1U_0201_6.3V6-K R45 2 @ 1 0_0402_5% 9 13
6 APU_HDMI_TX0- APU_HDMI_TX1+ HDMI_TX1+_C HDMI_TX1+_CON TMDS_Data0- CEC
C40 2 1 0.1U_0201_6.3V6-K R48 2 @ 1 0_0402_5% 4 17
6 APU_HDMI_TX1+ APU_HDMI_TX1- HDMI_TX1-_C HDMI_TX1-_CON TMDS_Data1+ DDC/CEC_Ground HDMI_DET
S C39 2 1 0.1U_0201_6.3V6-K R47 2 @ 1 0_0402_5% 6 19
6 APU_HDMI_TX1- TMDS_Data1- Hot_Plug_Detect
3

APU_HDMI_TX2+ C42 2 1 0.1U_0201_6.3V6-K HDMI_TX2+_C R50 2 @ 1 0_0402_5% HDMI_TX2+_CON 1

6 APU_HDMI_TX2+ APU_HDMI_TX2- HDMI_TX2-_C HDMI_TX2-_CON TMDS_Data2+
R42 1 @ 2 C41 2 1 0.1U_0201_6.3V6-K R49 2 @ 1 0_0402_5% 3
6 APU_HDMI_TX2- TMDS_Data2-
100K_0402_5% 8 14
5 TMDS_Data0_Shield Utility
2 TMDS_Data1_Shield
B TMDS_Data2_Shield B
20
11 GND1 21
APU_HDMI_CLK+ C36 2 1 0.1U_0201_6.3V6-K HDMI_CLK+_C R44 2 @ 1 0_0402_5% HDMI_CLK+_CON 10 TMDS_Clock_Shield GND2 22
6 APU_HDMI_CLK+ APU_HDMI_CLK- C35 HDMI_CLK-_C HDMI_CLK-_CON TMDS_Clock+ GND3
2 1 0.1U_0201_6.3V6-K R43 2 @ 1 0_0402_5% 12 23
6 APU_HDMI_CLK- TMDS_Clock- GND4
D6 D7
HDMI_CLK+_CON 1 1 HDMI_CLK+_CON HDMI_TX1-_CON HDMI_TX1-_CON
10 9 1 1 10 9
ALLTO_C128S9-K1935-L
HDMI_CLK-_CON 2 2 9 8 HDMI_CLK-_CON HDMI_TX1+_CON 2 2 9 8 HDMI_TX1+_CON

HDMI_TX0+_CON 4 4 7 7 HDMI_TX0+_CON HDMI_TX2-_CON 4 4 7 7 HDMI_TX2-_CON

HDMI_TX0-_CON 5 5 6 6 HDMI_TX0-_CON HDMI_TX2+_CON 5 5 6 6 HDMI_TX2+_CON

3 3 3 3

8 8

AZ1045-04F_DFN2510P10E-10-9 AZ1045-04F_DFN2510P10E-10-9
EMC_NS@ EMC_NS@

EMC

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 HDMI_CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 320ABR
Date: Thursday, January 12, 2017 Sheet 24 of 50
5 4 3 2 1
 A B C D E

+USB_VCCA

C55 1 2

+
220U_6.3V_M

C1117 1 2
@ 47U_0805_6.3V6-M
LEFT SIDE USB3.0 PORT x2 C125 1 2
@ 1U_0402_10V6K
+5VALW +USB_VCCA C127 1 2
U2 @ 1U_0402_10V6K
5 1
1 IN OUT JUSB1 ME@
1
1
C128 2
1U_0402_6.3V6K GND USB30_TX_P1 C126 1 2 0.1u_0201_10V6K USB30_TX_C_P1 R95 1 @ 2 0_0402_5% USB30_TX_R_P1 9
4 3 USB_OC1# 8 USB30_TX_P1 1 StdA_SSTX+
2 35 USB_ON# ENB OCB USB_OC1# 7 USB30_TX_N1 USB30_TX_C_N1 USB30_TX_R_N1 VBUS
C124 1 2 0.1u_0201_10V6K R96 1 @ 2 0_0402_5% 8
8 USB30_TX_N1 USB20_P5 USB20_P5_R StdA_SSTX-
SY6288D20AAC_SOT23-5 1 R97 1 @ 2 0_0402_5% 3
8 USB20_P5 7 D+
C140
1000P_0201_50V7-K USB20_N5 R93 1 @ 2 0_0402_5% USB20_N5_R 2 GND_DRAIN 10
8 USB20_N5 USB30_RX_P1 1 2 0_0402_5% USB30_RX_R_P1 6 D- GND_2 11
Low Active 2A EMC_NS@ R94 @
2 8 USB30_RX_P1 StdA_SSRX+ GND_3
4 12
USB30_RX_N1 R98 1 @ 2 0_0402_5% USB30_RX_R_N1 5 GND_1 GND_4 13
8 USB30_RX_N1 StdA_SSRX- GND_5

ALLTO_C190AG-10939-L

L13 EMC@
USB30_RX_N1 1 2 USB30_RX_R_N1
1 2

USB30_RX_P1 4 3 USB30_RX_R_P1
4 3
EXC24CH900U_4P USB20_P5_R
+USB_VCCA
USB20_N5_R D12 EMC@
L16 EMC@ USB30_RX_R_N1 9 1USB30_RX_R_N1
10 1
USB30_TX_C_N1 1 2 USB30_TX_R_N1

AZ5725-01F.R7GR_DFN1006P2X2
1 2 USB30_RX_R_P1 8 2 USB30_RX_R_P1

2
D11 9 2
D13

1
USB30_TX_C_P1 4 3 USB30_TX_R_P1 AZC199-02S.R7G_SOT23-3 USB30_TX_R_N1 7 4USB30_TX_R_N1
7 4
4 3 EMC@
EXC24CH900U_4P USB30_TX_R_P1 6 5 USB30_TX_R_P1
6 5

2
3
2 EMC@ 2

2
L8 EMC@ 8
USB20_P5 1 2 USB20_P5_R
1 2 AZ1045-04F_DFN2510P10E-10-9
USB20_N5 USB20_N5_R

1
4 3
4 3
EXC24CH900U_4P
EMC
EMC

+USB_VCCA

C2060 1 2
@ 1U_0402_10V6K

C2059 1 2
@ 1U_0402_10V6K

L30 EMC@ JUSB3 ME@

USB30_RX_N2 1 2 USB30_RX_R_N2
1 2 USB30_TX_P2 C2058 1 2 0.1u_0201_10V6K USB30_TX_C_P2 R3119 1 @ 2 0_0402_5% USB30_TX_R_P2 9
8 USB30_TX_P2 1 StdA_SSTX+
USB30_RX_P2 4 3 USB30_RX_R_P2 USB30_TX_N2 C2057 1 2 0.1u_0201_10V6K USB30_TX_C_N2 R3116 1 @ 2 0_0402_5% USB30_TX_R_N2 8 VBUS
4 3 8 USB30_TX_N2 USB20_P6 USB20_P6_R StdA_SSTX-
R3103 1 @ 2 0_0402_5% 3
8 USB20_P6 7 D+
EXC24CH900U_4P
USB20_N6 R942 1 @ 2 0_0402_5% USB20_N6_R 2 GND_DRAIN 10
8 USB20_N6 USB30_RX_P2 USB30_RX_R_P2 D- GND_2
R3117 1 @ 2 0_0402_5% 6 11
8 USB30_RX_P2 StdA_SSRX+ GND_3
L29 EMC@ 4 12
3 USB30_TX_C_N2 1 2 USB30_TX_R_N2 USB30_RX_N2 R3114 1 @ 2 0_0402_5% USB30_RX_R_N2 5 GND_1 GND_4 13 3
1 2 8 USB30_RX_N2 StdA_SSRX- GND_5

USB30_TX_C_P2 4 3 USB30_TX_R_P2 ALLTO_C190AG-10939-L

4 3
EXC24CH900U_4P

L17 EMC@
USB20_P6 1 2 USB20_P6_R
1 2

USB20_N6 4 3 USB20_N6_R
4 3
EXC24CH900U_4P
FOR ESD Close to Connector
D45 EMC@
USB30_RX_R_N2 9 10 1USB30_RX_R_N2
1
USB20_P6_R +USB_VCCA
USB30_RX_R_P2 8 2 USB30_RX_R_P2
9 2
USB20_N6_R
USB30_TX_R_N2 7 4USB30_TX_R_N2
7 4
3

D43 USB30_TX_R_P2 6 5 USB30_TX_R_P2

6 5

AZ5725-01F.R7GR_DFN1006P2X2
AZC199-02S.R7G_SOT23-3

1
EMC@ 3 3
D34

1
8
EMC_NS@
AZ1045-04F_DFN2510P10E-10-9
2
2
1

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2016/08/16 Deciphered Date 2017/08/15 USB3.0 PORT (LEFT)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
320ABR 0.1

Date: Thursday, January 12, 2017 Sheet 25 of 50

A B C D E
 5 4 3 2 1

+3VS
+3VALW Equalizer control and program for channel A
REDRV@ 3.3V tolerant. Internally pulled down at ~150K
RW31 1 2 0_0402_5% [A_EQ1, A_EQ0] ==
USB_EQ1_A RW19 1 @ 2 4.7K_0402_5% LL: program EQ for channel loss up to 9.5dB(default)
+3VS LH: program EQ for channel loss up to 13dB
RW32 1 @ 2 0_0402_5% USB_EQ0_A RW20 1 @ 2 4.7K_0402_5% HL: program EQ for channel loss up to 4.5dB
HH: program EQ for channel loss up to 7.5dB
U3 +3VS
1 1
1 Programmable output de-emphasis level setting for channel A
CW32 CW33 13 VDD1
3.3V tolerant. Internally pulled down at ~150K
.1U_0402_10V6-K VDD2 USB_DE0_A RW21 1 @ 2 4.7K_0402_5%
.1U_0402_10V6-K [A_DE1, A_DE0] ==
2 2 LL: 3.5dB de-emphasis (default)
REDRV@ REDRV@ USB_EQ1_A 15 4 USB_EQ1_B USB_DE1_A RW22 1 @ 2 4.7K_0402_5% LH: No de-emphasis
USB_DE0_A 16 A_EQ1_SDA_CTL B_EQ1_I2C_ADDR1 3 USB_DE0_B HL: 2.7dB de-emphasis
USB_EQ0_A 17 A_DE0_SCL_CTL B_DE0_I2C_ADDR0 2 USB_EQ0_B HH: 5dB de-emphasis
USB_DE1_A 18 A_EQ0_NC B_EQ0_NC 6 USB_DE1_B
REDRV@ A_DE1_NC B_DE1_NC +3VS Equalizer control and program for channel B
CW30 1 2 0.1U_0201_6.3V6-K USB30_TX_P3_C 19 12 USB30_TX_P3_U 3.3V tolerant. Internally pulled down at ~150K
8 USB30_TX_P3 A_INp A_OUTp
CW31 1 2 0.1U_0201_6.3V6-K USB30_TX_N3_C 20 11 USB30_TX_N3_U [B_EQ1, B_EQ0] ==
8 USB30_TX_N3 A_INn A_OUTn USB_EQ1_B RW23 1
D REDRV@ @ 2 4.7K_0402_5% LL: program EQ for channel loss up to 9.5dB(default) D
REDRV@ LH: program EQ for channel loss up to 13dB
USB30_RX_P3_U 9 22 USB30_RX_P3_C CW34 1 2 0.1U_0201_6.3V6-K USB_EQ0_B RW24 1 REDRV@2 4.7K_0402_5% HL: program EQ for channel loss up to 4.5dB
USB30_RX_N3_U B_INp B_OUTp USB30_RX_N3_C USB30_RX_P3 8
8 23 CW35 1 2 0.1U_0201_6.3V6-K HH: program EQ for channel loss up to 7.5dB
B_INn B_OUTn USB30_RX_N3 8
REDRV@
+3VS
@ TP53 1 5 Programmable output de-emphasis level setting for channel B
REXT 7 PD# 10 3.3V tolerant. Internally pulled down at ~150K
TEST 14 REXT GND1 21 USB_DE0_B RW25 1 @ 2 4.7K_0402_5% [B_DE1, B_DE0] ==
24 TEST GND2 25 LL: 3.5dB de-emphasis (default)
I2C_EN GPAD USB_DE1_B

1
RW26 1 @ 2 4.7K_0402_5% LH: No de-emphasis
RW30 PS8713BTQFN24GTR2A_TQFN24_4X4 HL: 2.7dB de-emphasis
4.99K_0402_1% REDRV@ HH: 5dB de-emphasis
REDRV@ +3VS
LFPS swing adjust.
2

3.3V tolerant. Internally pulled down at ~150KΩ

8/31 Follow Vendor suggestion change from 3.9K to 4.99K wei TEST==
TEST RW27 1 @ 2 4.7K_0402_5% L: Normal LFPS swing(default)
H:Turn down LFPS swing

+3VALW
+3V_MUX +5VALW +5V_MUX U27 @
R133 1 2 0_0402_5% R173 1 2 0_0402_5% 6 1
+5VALW IN OUT VBUS_P0 VBUS_P0
3.3K_0402_1% 1 @ 2 R418 5 2
+3VS +5VS ISET GND
R134 1 @ 2 0_0402_5% R174 1 @ 2 0_0402_5% VBUS_EN 4 3 TYPE_C_OCP#
EN/ENB OCB 3A
Iset =6800/3.3k=2.06A SY6861B1ABC_SOT23-6
11/16 SIT Reserve Power switch for OPC# flip issue wei
U26

TYPE_C_OCP# 2 2
16

25
26
27
28
VBUS_EN 15 OCP_DET CC1271 CC1272 JP1 ME@
VBUS_EN 220P_0201_25V7-K 220P_0201_25V7-K
+5VALW 1.5A VBUS_P0

GND5
GND6
GND7
GND8
1 1
VMON 17 12 CC1 A5 1 24 1
C VMON CC1 14 CC2 Power_GND_B12 GND_A1 C
B5 1
CC2 + C1333 C_RX1_P_C 23 2 C_TX1_P_C
C213 150U_B2_6.3VM_R35M SSRXp1_B11 SSTXp1_A2
11 MUX_TX2_N C2076 1 2 0.1U_0201_6.3V6-K C_TX2_N B3 47U_0805_6.3V6-M @ C_RX1_N_C 22 3 C_TX1_N_C
C_TX2_1P/2N 10 MUX_TX2_P C2075 1 2 0.1U_0201_6.3V6-K C_TX2_P 2 2 SSRXn1_B10 SSTXn1_A3
B2
C_TX2_1N/2P 21 4
USB30_RX_N3_U C2068 1 USB30_RX_N3_M C_RX2_N U6 VBUS_B9 VBUS_A4
2 0.1U_0201_6.3V6-K 4 24 A10
USB30_RX_P3_U C2067 1 2 0.1U_0201_6.3V6-K USB30_RX_P3_M 5 SSRX_1P/2N C_RX2_1P/2N 1 C_RX2_P 20 5 CC1
A11
SSRX_1N/2P C_RX2_1N/2P A1 A3 SBU2_B8 CC1_A5
USB30_TX_N3_U USB30_TX_N3_M 10Gbps 2:1 MUX MUX_TX1_N C2073 1 C_TX1_N VIN1 VOUT1 C_DM C_DP
C2065 1 2 0.1U_0201_6.3V6-K 6 8 2 0.1U_0201_6.3V6-K A3 B1 B3 19 6
USB30_TX_P3_U C2066 1 2 0.1U_0201_6.3V6-K USB30_TX_P3_M 7 SSTX_1P/2N C_TX1_1P/2N 9 MUX_TX1_P C2074 1 2 0.1U_0201_6.3V6-K C_TX1_P C1 VIN2 VOUT2 C3 Dn2_B7 Dp1_A6
A2
SSTX_1N/2P C_TX1_1N/2P VIN3 VOUT3 C_DP 18 7 C_DM
C_RX1_N VBUS_EN TYPE_C_OCP# Dp2_B6 Dn1_A7

GND1
GND2
GND3
2 B10 D3 D1
C_RX1_1P/2N C_RX1_P ON OC_FLAGB TYPE_C_OCP# 7
3 B11 D2 CC2 17 8
C_RX1_1N/2P ISET CC2_B5 SBU1_A8
+5V_MUX

1
FPF2595UCX_WLCSP12 16 9
VBUS_B4 VBUS_A9

A2
B2
C2
13 R604
VCON_IN 523_0402_1% C_TX2_N_C 15 10 C_RX2_N_C
23 +3V_MUX SSTXn2_B3 SSRXn2_A10
NC Realtek C_TX2_P_C C_RX2_P_C

10U_0805_10V6K
M1 21 19 Rset 528 Min 1800mA Type 2000mA Max 2200mA 14 11

0.1u_0201_10V6K
RP_SEL_M1 5V_IN SSTXp2_B2 SSRXp2_A11

2
M0 22 RTS5449 2 2 Rset 469 Min 2025mA Type 2250mA Max 2475mA
RP_SEL_M0 20 13 12
C2063

C2077
LDO_3V3 GND_B1 GND_A12
0.1u_0201_10V6K

GND12
GND11
GND10
4.7U_0402_6.3V6M

GND9
18 25
1 2 1 1 VBUS_P0
C2064
CC1273

REXT E-PAD VBUS_P0

2

HIGHS_UB11246-15A0C-1H
2 1

32
31
30
29
R3150 RTS5449-GR_QFN24_4X4

1
6.2K_0402_1%
Close Pin13
R3155

AZ5725-01F.R7GR_DFN1006P2X2

4.7U_0805_25V6-K

0.47U_0402_25V6-K

0.47U_0402_25V6-K

0.47U_0402_25V6-K

0.47U_0402_25V6-K
1

200K_0402_1%

10U_0805_25V6K
1
D38
Close Pin19 1
09/02 Update Type-C Conn. DC021608291 wei

1
C918

C919

C922

C921

C920

C1334
1
VMON

EMC_NS@
@
2

2
2
+3V_MUX +3V_MUX
Rp configuration
R3149

2
10K_0402_1%

2
2

Rp:1.5A (now) 1
R3139 R3142
10K_0402_5% @ 10K_0402_5%
B
M1 M0 Note B

Rp:900mA 0 1 R3144/R3142 mount

1

M1 M0 R943 1 @ 2 0_0402_5% R3135 1 @ 2 0_0402_5% CC1 C_DP

Rp:1.5A 1 0 R3139/R3143 mount CC2 C_DM
2

L23 EMC@ L31 EMC@

Rp:3.0A 1 1 R3139/R3142 mount C_DP C_RX1_N C_RX1_N_C

2
R3144 R4674 1 2 4 3 D47 EMC_NS@ D48 EMC_NS@
8 USB20_P7 1 2 4 3
@ 10K_0402_5% 10K_0402_5%

4 3 C_DM C_RX1_P 1 2 C_RX1_P_C

8 USB20_N7 4 3 1 2
1

EXC24CH900U_4P EXC24CH900U_4P
R3137 1 @ 2 0_0402_5%
R91 1 @ 2 0_0402_5%

+3V_MUX R3136 1 @ 2 0_0402_5%

For C_VBUS @
R944 2 1 0_0402_5%
power switch enable pin L32 EMC@ AZC199-02S.R7G_SOT23-3 AZC199-02S.R7G_SOT23-3
C_TX1_P C_TX1_P_C

1
2

L24 EMC@ 4 3
R3146 C_TX2_N 3 4 C_TX2_N_C 4 3
@ 10K_0402_5% 3 4
1 2
C_TX2_P 2 1 C_TX2_P_C 1 2
Power switch enable pin Note 2 1
1

EXC24CH900U_4P
VBUS_EN EXC24CH900U_4P C_TX1_N R3138 1 @ 2 0_0402_5% C_TX1_N_C
Low Active R3146 mount
@
2

R3107 2 1 0_0402_5%
R3141 High Active R3141 mount
10K_0402_5%
R100 2 @ 1 0_0402_5%
1

L25 EMC@
C_RX2_P 3 4 C_RX2_P_C D36 EMC_NS@ D20 EMC_NS@
3 4 C_TX2_P_C 9 C_TX2_P_C C_TX1_P_C 9 C_TX1_P_C
10 1 1 10 1 1
C_RX2_N 2 1 C_RX2_N_C C_TX2_N_C 8 2 C_TX2_N_C C_TX1_N_C 8 2 C_TX1_N_C
2 1
9 2 9 2
+3V_MUX
For C_VBUS C_RX1_N_C 7 C_RX1_N_C C_RX2_N_C 7 C_RX2_N_C
EXC24CH900U_4P 7 4 4 7 4 4
power switch OCP pin
PH at CPU side 09/06 wei @ C_RX1_P_C 6 C_RX1_P_C C_RX2_P_C 6 C_RX2_P_C
2

R101 2 1 0_0402_5% 6 5 5 6 5 5
R3147
@ 10K_0402_5% 3 3 3 3

8 8
Power switch OCP pin Note
1

A TYPE_C_OCP# AZ1045-04F_DFN2510P10E-10-9 AZ1045-04F_DFN2510P10E-10-9 A

Low Active R3147 mount For ESD
High Active R3140 mount
2

R3140
@ 10K_0402_5%
1

Security Classification LC Future Center Secret Data Title

Issued Date 2016/08/16 Deciphered Date 2017/08/15 3D Camera

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 320ABR
Date: Thursday, January 12, 2017 Sheet 26 of 50
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2016/08/16 Deciphered Date 2017/08/15 Blank
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
B
320ABR 0.1

Date: Thursday, January 12, 2017 Sheet 27 of 50

5 4 3 2 1
 5 4 3 2 1

+3VALW TO +3VALW_LAN
+3VALW_LAN rising t i me ( 10 %~90 %):
+3VALW +3VALW_LAN
0.5ms＜s pec＜ 10 0m s +3VALW_LAN +LAN_VDDREG
Need short
@
JL1 1 2 @ width : 40 mils RL1 1 2 0_0603_5%
1 2
JUMP_43X79
D 1 1 D
+3VALW LP2301ALT1G_SOT23-3 CL1 CL2

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K
1 1 1 1 4.7U_0402_6.3V6M 0.1U_0201_6.3V6-K
Q14 3 1 @ CL4 CL5 CL6 CL7

D
2 2

0.01U_0201_10V6K
SIT1CD@ SIT1CD@
RL2 1 1
100K_0402_5% CL8 CL9 2 2 2 2

G
2
@ 0.1U_0201_6.3V6-K
@ @

2
2 2
SIT1CD@ SIT1CD@
RL3 1 @ 2
35 LAN_PWR_ON#
47K_0402_5%
Close to Pin11 Close to Pin32 Close to Pin11 Close to Pin32

+3VALW_LAN +3VS

2
+3VALW_LAN

2
RL4

G
10K_0402_5% QL1
2

@
RL5

1
10K_0402_5% UL1 LAN_CLKREQ#_R 1 3 @
LAN_CLKREQ# 7
@

S
2N7002KW_SOT323-3
1

RL7 1 @ 2 0_0402_5% PCIE_WAKE#_R

7,31,35 PCIE_WAKE#
C
31,35 LAN_WAKE# RL6 1 @ 2 0_0402_5% RL18 1 2 C
33
32 +3VALW_LAN GND 16 CLK_PCIE_LAN# 0_0402_5%
AVDD33_2 REFCLK_N CLK_PCIE_LAN CLK_PCIE_LAN# 8
RL8 1 2 31 RSET 15
+LAN_VDD10 RSET REFCLK_P PCIE_PTX_C_DRX_N2 CLK_PCIE_LAN 8
2.49K_0402_1% 30 14 APU CLKREQ all both 3VS power plane
29 LAN_XTALO AVDD10 HSIN 13 PCIE_PTX_C_DRX_P2 PCIE_PTX_C_DRX_N2 4
28 LAN_XTALI CKXTAL2 HSIP 12 LAN_CLKREQ#_R PCIE_PTX_C_DRX_P2 4
+3VS TL3 @ 1 27 CKXTAL1 CLKREQB 11 +3VALW_LAN
LAN_PWR_ON# RL121 @ 2 LAN_DISABLE# 26 LED0 AVDD33_1 10 LAN_MDI3-
LED1/GPIO MDIN3 LAN_MDI3+ LAN_MDI3- 29
0_0402_5% TL4 @ 1 25 9
+LAN_REGOUT LED2 MDIP3 +LAN_VDD10 LAN_MDI3+ 29
1

24 8
RL9 +LAN_VDDREG 23 REGOUT AVDD10_2 7 LAN_MDI2-
+LAN_VDD10 VDDREG MDIN2 LAN_MDI2+ LAN_MDI2- 29
1K_0402_1% 22 6
PCIE_WAKE#_R 21 DVDD10 MDIP2 5 LAN_MDI1- LAN_MDI2+ 29
20 LANW AKEB MDIN1 4 LAN_MDI1+ LAN_MDI1- 29
ISOLATE#
ISOLATEB MDIP1 LAN_MDI1+ 29
2

PLT_RST# 19 3 +LAN_VDD10
7,15,31 PLT_RST# PCIE_PRX_C_DTX_N2 PERSTB AVDD10_1 LAN_MDI0-
4 PCIE_PRX_DTX_N2 CL10 2 1 0.1U_0201_6.3V6-K 18 2
LAN_PWR_ON# HSON MDIN0 LAN_MDI0- 29
ISOLATE# RL10 1 @ 2 CL11 2 1 0.1U_0201_6.3V6-K PCIE_PRX_C_DTX_P2 17 1 LAN_MDI0+
4 PCIE_PRX_DTX_P2 HSOP MDIP0 LAN_MDI0+ 29
0_0402_5% CL10 close to Pin18
1

RL11 CL11 close to Pin17

15K_0402_5%
@
2

RTL8111GUL-CG_QFN32_4X4
8111GUL@

B B

For RTL8111GUL/ RTL8106EUL (SWR mode)

LAN_XTALI
For RTL8111H (LDO mode) RL19 stuf f
YL1 LAN_XTALO 8111H@ +LAN_VDD10
RL19 1 2 0_0805_5%
1 4
OSC1 GND2
2 3 +LAN_REGOUT LL1 1 2
GND1 OSC2 2.2UH_NLC252018T-2R2J-N_5%
1 1 8111GUL@ 1 1 1 1 1 1 1 1
Layout Note: LL1 must be CL15 CL16 CL17 CL18 CL19 CL20 CL22
CL12 25MHZ_10PF_7V25000014 CL13 4.7U_0603_6.3V6K 0.1U_0201_6.3V6-K 0.1U_0201_6.3V6-K 0.1U_0201_6.3V6-K 0.1U_0201_6.3V6-K 0.1U_0201_6.3V6-K CL21 0.1U_0201_6.3V6-K
10P_0402_50V8J 12P_0402_50V8-J within 200mil to Pin24, 1U_0402_6.3V6K @
2 2 CL15,CL16 must be within 2 2 2 2 2 2 2 @ 2
200mil to LL1
+LAN_REGOUT: Width =60mil
Close to Pin3, 8, 22, 30 Close to Pin22(Reserved)
follow G CarrizoL 10pf

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 LAN_RTL8111GUL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
320ABR 0.1

Date: Thursday, January 12, 2017 Sheet 28 of 50

5 4 3 2 1
 5 4 3 2 1

DL1/DL2
1'S PN:SC300003M00
D D
TL1
24 1 MCT
MCT1 TCT1
LAN_MDI0+ 23 2 LAN_MDO0+
28 LAN_MDI0+ MX1+ TD1+
DL1
LAN_MDI2+ 1 10 LAN_MDI2+ LAN_MDI0- 22 3 LAN_MDO0-
LINE1IN LINE1OUT 28 LAN_MDI0- MX1- TD1-

1
EMC@
LAN_MDI2- 2 9 LAN_MDI2- 21 4 MCT RL17
LINE2IN LINE2OUT MCT2 TCT2 20_0603_5%
LAN_MDI1+ LAN_MDO1+

1
3 8 20 5
GND1 GND2 28 LAN_MDI1+ MX2+ TD2+ DL3

1
2
LAN_MDI3+ 4 7 LAN_MDI3+ LAN_MDI1- 19 6 LAN_MDO1- PDT5061_DO-214AA
LINE3IN LINE3OUT 28 LAN_MDI1- MX2- TD2- EMC@
LAN_MDI3- 5 6 LAN_MDI3- 18 7

2
MCT EMC
LINE4IN LINE4OUT MCT3 TCT3

2
11 13 LAN_MDI2+ 17 8 LAN_MDO2+
GND3 GND5 28 LAN_MDI2+ MX3+ TD3+
12 LAN_MDI2- 16 9 LAN_MDO2-
GND4 28 LAN_MDI2- MX3- TD3-
AZ3133-08F.R7G_DFN3020P10E10 15 10 MCT
EMC_NS@ MCT4 TCT4
1 1
LAN_MDI3+ 14 11 LAN_MDO3+ CL32 CL25
28 LAN_MDI3+ MX4+ TD4+
C
0.022U_0603_50V7K 1000P_1206_2KV7-K C
LAN_MDI3- 13 12 LAN_MDO3- EMC@ EMC@
28 LAN_MDI3- MX4- TD4- 2 2
1 EMC
DL2 CL24
LAN_MDI1- 1 10 LAN_MDI1- 0.01U_0201_25V6-K BOTH_GST5009 LF
LINE1IN LINE1OUT EMC@
LAN_MDI1+ 2 9 LAN_MDI1+ 2
LINE2IN LINE2OUT
3 8 EMC
GND1 GND2
LAN_MDI0- 4 7 LAN_MDI0- CHASSIS1_GND
LINE3IN LINE3OUT
LAN_MDI0+ 5 6 LAN_MDI0+
LINE4IN LINE4OUT
11 13
GND3 GND5
12
GND4
AZ3133-08F.R7G_DFN3020P10E10 JRJ1 ME@
EMC_NS@ 12
GND_4
11
GND_3
Place Close to TL1
10
LAN_MDO0+ 1 GND_2
B EMC TX_DA+ B
9
LAN_MDO0- 2 GND_1
TX_DA-
LAN_MDO1+ 3
RX_DB+ CHASSIS1_GND
LAN_MDO2+ 4
BI_DC+
LAN_MDO2- 5
BI_DC-
LAN_MDO1- 6
RX_DB-
RL14 1 EMC@ 2 0_0603_5% LAN_MDO3+ 7
BI_DD+
RL15 1 EMC@ 2 0_0603_5% LAN_MDO3- 8
BI_DD-
RL16 1 EMC@ 2 0_0603_5%
ALLTO_C10235-10839-L
EMC

CHASSIS1_GND

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 LAN_Transformer
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
320ABR 0.1

Date: Thursday, January 12, 2017 Sheet 29 of 50

5 4 3 2 1
 5 4 3 2 1

R175 1 @ 2 0_0402_5% REMOTE1+

Close to U1 REMOTE+_R R176 1 @ 2 0_0402_5% REMOTE2+ REMOTE1+

Near GPU&VRAM REMOTE2+
Near CPU core
1
REMOTE+_R

1
C46 C
1

1
1 C45 C 100P_0201_25V8J 2 Q16
C44 REMOTE-_R R177 1 @ 2 0_0402_5% REMOTE2- 100P_0201_25V8J 2 Q15 @ B MMBT3904WH_SOT323-3
2200P_0402_25V7-K @ B MMBT3904WH_SOT323-3 2 E @

3
@ 2 E @ REMOTE2-

3
2 REMOTE-_R R178 1 @ 2 0_0402_5% REMOTE1- REMOTE1-

D D
+3VALW
REMOTE+/-_R, REMOTE1+/-, REMOTE2+/-: +3VALW
Trace width/space:10/10 mil Near CPU
Trace length:<8"

1
R17
13.7K_0402_1% R25
SMSC thermal sensor PX@ 13.7K_0402_1%

placed near DIMM

2
NTC_V1

2
NTC_V2

1
+3VS

1
U1 PH2
1 8 EC_SMB_CK3 100K_0402_1%_NCP15WF104F03RC PH3
VDD SCL EC_SMB_CK3 6,16,35
PX@ 100K_0402_1%_NCP15WF104F03RC
REMOTE+_R 2 7 EC_SMB_DA3
1 D+ SDA EC_SMB_DA3 6,16,35

2
C47

2
0.1U_0201_6.3V6-K REMOTE-_R 3 6
D- ALERT#

2
@
2

2
+3VS R51 2 @ 1 4 5 R184 R185
10K_0402_5% T_CRIT# GND @ R191 R192
0_0402_5% 0_0402_5%
NCT7718W_MSOP8 PX@ @ 0_0402_5% 0_0402_5%
Address 1001_101xb @

1
@

1
+5VLP +5VLP EC_AGND
C C
+5VLP EC_AGND

HW thermal sensor

2
1 R252 R253
C4 21.5K_0402_1% 21.5K_0402_1%
0.1U_0201_6.3V6-K @ @
@

1
2 @
U4
1 8 TMSNS1 R196 1 @ 2 0_0402_5% NTC_V1
VCC TMSNS1 NTC_V1 35
2 7 PHYST1 R6 1 @ 2 10K_0402_5%
GND RHYST1
3 6 TMSNS2 R197 1 @ 2 0_0402_5% NTC_V2
45 EC_ON_R OT1 TMSNS2 NTC_V2 35
4 5 PHYST2 R7 1 @ 2 10K_0402_5%
OT2 RHYST2
G718TM1U_SOT23-8 +3VALW

+3VS RTPM12 1 @ 2 0_0603_5%

over temperature threshold: +3VS_TPM
RSET=3*RTMH RTPM1 1 TPM@ 2 0_0603_5%
20mA
92+/-30C 1 1
CTPM3
Hysteresis temperature threshold. CTPM1
10U_0603_6.3V6M
0.1U_0201_6.3V6-K
TPM@
B
RHYST=(RSET*RTML)/(3*RTML-RSET) 2 @ 2 B

56+/-30C
TPM
+3VS_TPM
UTPM1 TPM@
1 24
2 NC_1 VDD3 10
3 NC_2 VDD1
FAN Conn RTPM13 1 @ 2 0_0402_5% 7 NC_3
PP LPCPD#
28 RTPM2 1 TPM@ 2 10K_0402_5%
+5VS 27 SERIRQ_TPM RTPM5 1 TPM@ 2 0_0402_5%
SERIRQ LPC_AD0_TPM SERIRQ 8,35
6 26 RTPM6 1 TPM@ 2 0_0402_5%
NC_4 LAD0 LPC_AD1_TPM LPC_AD0 8,35
JFAN1 9 23 RTPM7 1 TPM@ 2 0_0402_5%
+5VS_FAN NC_7 LAD1 LPC_FRAME#_TPM LPC_AD1 8,35
R4682 1 2 0_0603_5% 1 22 RTPM8 1 TPM@ 2 0_0402_5%
1 LFRAME# LPC_AD2_TPM LPC_FRAME# 8,11,35
35 EC_FAN_SPEED 2 4 20 RTPM9 1 TPM@ 2 0_0402_5%
2 GND_1 LAD2 LPC_AD3_TPM LPC_AD2 8,35
0.1u_0201_10V6K

@ 35 EC_FAN_PWM 3 11 17 RTPM10 1 TPM@ 2 0_0402_5%

3 GND_2 LAD3 LPC_AD3 8,35
1 1 2 4 18
C2080 CC1280 5 4 GND_3 25 +3VS_TPM
10U_0805_10V6K @ 10U_0402_6.3V6M 6 GND1 RTPM14 1 @ 2 0_0603_5% 5 GND_4 21
GND2 +3VALW NC_5 LCLK TPM_CLK 8
8 19
2 2 1 ACES_85205-04001 RTPM15 1 @ 2 0_0603_5% 12 NC_6 VDD2 15 RTPM11 1 TPM@ 2 0_0402_5%
C2081

+3VS NC_8 CLK_RUN#

ME@ 13 RTPM16 1 TPM@ 2 0_0402_5% LPC_CLKRUN# 8
14 NC_9 16
NC_10 LRESET# APU_LPC_RST# 7,35

A A
Z32H320TC_TSSOP28

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Thermal sensor/FAN CONN/TPM

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 320ABR
Date: Thursday, January 12, 2017 Sheet 30 of 50
5 4 3 2 1
 A B C D E

Mini-Express Card(WLAN/WiMAX)

1 1

+3VS_W LAN
+3VS Need short
J2 @
1 2 1
1 2 C53
JUMP_43X79 0.1U_0201_6.3V6-K
@ +3VS_W LAN
2

JW LAN1 ME@
1 2
3 GND1 3.3VAUX1 4
8 USB20_P0 USB_D+ 3.3VAUX2
5 6 1 @ T7
8 USB20_N0 USB_D- LED1#
7 8
9 GND2 PCM_CLK/I2S_SCK 10
11 SDIO_CLK PCM_SYNC/I2S_WS 12
13 SDIO_CMD PCM_IN/I2S_SD_IN 14
15 SDIO_DATA0 PCM_OUT/I2S_SD_OUT 16 1 @ T6
17 SDIO_DATA1 LED#2 18
19 SDIO_DATA2 GND11 20
21 SDIO_DATA3 UART_WAKE# 22
23 SDIO_WAKE# UART_RXD
2 SDIO_RESET# 2

KEY E
25 PIN24~PIN31 NC PIN 24
27 26
29 28
31 30

33 32
35 GND3 UART_TXD 34
4 PCIE_PTX_C_DRX_P1 PETP0 UART_CTS
37 36
4 PCIE_PTX_C_DRX_N1 PETN0 UART_RTS
39 38
41 GND4 VENDOR_DEFINED1 40
4 PCIE_PRX_DTX_P1 PERP0 VENDOR_DEFINED2
43 42
4 PCIE_PRX_DTX_N1 PERN0 VENDOR_DEFINED3
45 44 R88 1 2 0_0402_5%
GND5 COEX3 EC_RX 35
47 46 @
8 CLK_PCIE_W LAN REFCLKP0 COEX2
49 48
8 CLK_PCIE_W LAN# REFCLKN0 COEX1 SUSCLK_R
51 50 R55 1 2 0_0402_5%
W LAN_CLKREQ_Q# GND6 SUSCLK PLT_RST# SUSCLK 7,11
7 W LAN_CLKREQ# R61 1 2 0_0402_5% 53 52 @
PCIE_W AKE#_W LAN CLKREQ0# PERST0# BT_OFF# PLT_RST# 7,15,28
R262 1 @ 2 0_0402_5% 55 54 R53 1 2 1K_0402_5%
7,28,35 PCIE_W AKE# PEWAKE0# W_DISABLE2# W LAN_OFF# PCH_BT_OFF# 7
R57 1 @ 2 0_0402_5% 57 56 R56 1 2 0_0402_5%
28,35 LAN_W AKE# GND7 W_DISABLE1# PCH_W LAN_OFF# 7
@

59 58 APU_SMB_DATA_R R58 1 @ 2 0_0402_5%

RSRVD/PETP1 I2C_DATA APU_SMB_CLK_R APU_SMB_DATA 7,12
61 60 R59 1 @ 2 0_0402_5%
RSRVD/PETN1 I2C_CLK APU_SMB_CLK 7,12
63 62
65 GND8 ALERT# 64 EC_TX_R R89 1 2 0_0402_5%
RSRVD/PERP1 RSRVD EC_TX 35
67 66 @
69 RERVD/PERN1 UIM_SWP/PERST1# 68 +3VS_W LAN
GND9 UIM_POWER_SNK/CLKREQ1#

1
71 70
3 73 RSRVD/REFCLKP1 UIM_POWER_SRC/GPIO1/PEWAKE1# 72 R186 3
75 RSRVD/REFCLKN1 3.3VAUX3 74 100K_0402_5%
GND10 3.3VAUX4
77 76
GND15 GND14

2
ARGOS_NASE0-S6701-TS40

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 NGFF WLAN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 320ABR
Date: Thursday, January 12, 2017 Sheet 31 of 50
A B C D E
 5 4 3 2 1

DVDD_IO +1.8VS +1.8V_AUDIO

+3VALW
RA225 1 2 0_0402_5%
RA213 1 @ 2 0_0402_5% Digital power for HDA link
8/29 Add +1.8VS Circuit for Audio wei
+3VS
2
CA2
RA216 1 @ 2 0_0402_5% 0.1U_0201_6.3V6-K UA1
Close to1 Pin7 DMIC_DATA DMIC_DATA_R
+1.8VS RA19 1 2 0_0402_5% 1 30
23 DMIC_DATA DMIC_CLK DMIC_CLK_R HD-GPIO0/DMIC-DATA CR-GPIO SD_CD#
RA18 1 2 0_0402_5% 2 31
23 DMIC_CLK HDA_SDOUT_AUDIO HD-GPIO1/DMIC-CLK CR-SD-CD SD_WP SD_CD# 33
RA227 1 2 0_0402_5% 3 32
7 HDA_SDOUT_AUDIO HDA_BITCLK_AUDIO 4 HD-SDATA-OUT CR-SD-WP 33 SD_D1_R SD_WP 33
D 7 HDA_BITCLK_AUDIO HD-BCLK CR-SD-DAT[1] SD_D0_R SD_D1_R 33 D
CA1 1 2 5 34
Analog power for mixers, & IO ports Power supply for full-bridge left/Right channel HDA_SDIN0 RA16 1
2.2U_0402_6.3V6M
2 33_0402_5% SDATA_IN 6 HD-LDO3-CAP CR-SD-DAT[0] 35 SD_CLK_R SD_D0_R 33
+5VS +5VA +5VS +5VD 7 HDA_SDIN0 7 HD-SDATA-IN CR-SD-CLK 36 SD_CLK_R 33
+5VA
DVDD_IO HDA_SYNC_AUDIO HD-DVDD-IO HD-AVDD1 LDO1_CAP
EMC_NS@ 8 37 CA43 1 2 2.2U_0402_6.3V6M CA48 1 2 1U_0402_6.3V6K
7 HDA_SYNC_AUDIO 2 100K_0402_1%PC_BEEP HD-SYNC HD-LDO1-CAP
LA25 1 2 BLM15PD600SN1D_2P
+3VS RA205 1 9 38 CA44 1 2 1U_0402_6.3V6K
RA7 1 2 0_0603_5% PLUG_IN RA204 1 2 200K_0402_1%JSENSE 10 HD-PCBEEP HD-VREF 39 MICBIASB
RA10 1 EMC@ 2 0_0603_5% RING2_CONN 11 HD-JD1(HP/LINE1) HD-MIC2-VREFO 40 LINE1_VREF_L +1.8V_AUDIO
RING3_CONN 12 HD-MIC2-L(RING) HD-LINE1-VREFO-L 41 HPOUT_L
VDD_STB 13 HD-MIC2-R(SLEEVE) HD-HPOUT-L 42 HPOUT_R
0.1U_0201_6.3V6-K

1U_0402_6.3V6K

2 2 HD-3V5V-STB HD-HPOUT-R
1 RA38 2 2.2K_0402_5% CA41 1 2 14 43 CA47 1 2 1U_0402_6.3V6K +1.8V_AUDIO

CA178
10U_0805_10V6K

CA18 0.1U_0201_6.3V6-K

CA19 0.1U_0201_6.3V6-K
1 2 2 2.2U_0402_6.3V6M
CA42 CA20 LINE1_R 15 HD-MIC2-CAP HD-CPVEE 44
MICBIASB 1 RA37 2 2.2K_0402_5% LINE1_L 16 HD-LINE1-R HD-CBN 45 4.7U_0603_6.3V6K 2 1 CA4
1 1 17 HD-LINE1-L HD-CPVDD 46
2 1 1 18 HD-LINE2-R HD-CBP 47 HD_LDO2 CA185 1 2 10U_0402_6.3V6M @
SD_CMD_R 19 HD-LINE2-L HD-LDO2-CAP 48
33 SD_CMD_R SD_D3_R 20 CR-SD-CMD HD-AVDD2 49
33 SD_D3_R SD_D2_R 21 CR-SD-DAT[3] HD-PVDD1 50
+5VD
SPK_L+ Analog power for DACs, ADCs
33 SD_D2_R 1 2 22 CR-SD-DAT[2] HD-SPKOUT-LP 51 SPK_L-
CW 1 1U_0402_6.3V6K 2
23 CR-SDREG HD-SPKOUT-LN 52 SPK_R- +3VS
CW 2 1 2 1U_0402_6.3V6K 24 CR-TEST1 HD-SPKOUT-RN 53 SPK_R+ CC257
RW 11 1 2 6.2K_0402_1% RREF 25 CR-V18-CAP HD-SPKOUT-RP 54 +5VD
USB20_N4 USB20_N4_R CR-RREF HD-PVDD2 SPKR_MUTE# 10U_0402_6.3V6M
RW 12 1 2 0_0402_5% 26 55 1
+3VALW 8 USB20_N4 USB20_P4 RW 13 1 2 0_0402_5% USB20_P4_R 27 CR-DM HD-PDB 56 Digital power for digital I/O circuit
+3VS +3VS_CARD 8 USB20_P4 28 CR-DP HD-DVDD
+3VS_CARD CR-3V3-IN
29
CARD_3V3 CR-SD-3V3 57 2 2
GNDPAD
1 1
RA220 1 2 0_0402_5%

0.1U_0201_6.3V6-K

1U_0402_6.3V6K
CW 18 CW 19 RTS5199-CG_QFN56_7X7 CA180 CA179
4.7U_0402_6.3V6M 0.1u_0201_10V6K
1 1
2 2
RA219 1 @ 2 0_0402_5%
1U_0402_6.3V6K

1 ABR USB leakage issue, card reader power need 3VALW

C2062

C 2 C
DA4
EC_MUTE# 1 2 @ SPKR_MUTE#
35 EC_MUTE#
LINE1_L

1
LRB751V-40T1G_SOD323-2 CA45 1 2 1U_0402_6.3V6K
RA35 1 @ 2 0_0402_5% RA43
10K_0402_5% LINE1_VREF_L RA41 1 2 4.7K_0402_5%
Power for combo jack depop circuit at system HPOUT_L RA21 1 2 51_0402_1% A_HP_OUTL_R
shutdown mode

2
HPOUT_R RA20 1 2 51_0402_1% A_HP_OUTR_R
+3VL
DA1 LINE1_VREF_L RA42 1 2 4.7K_0402_5%
RA203 1 2 0_0402_5% VDD_STB 2
35 BEEP#
1 PC_BEEP1 1 @ 2 CA40 1 2 PC_BEEP LINE1_R CA46 1 2 1U_0402_6.3V6K
3 RA211 0_0402_5% 0.1U_0201_6.3V6-K
7 PCH_BEEP

1
To solve the background noise while combojack connecting to an
active speaker and system entry into S3/S4/S5 without analog power. LBAT54CWT1G_SOT323-3 RA14
10K_0402_5%

2
1
RA217 @ 2 0_0402_5% @1 TC203
7 HDA_RST_AUDIO#

JSPK1 ME@
RA223 1 CD@ 2 15_0402_5% SPK_R+ RA222 1 2 0_0402_5% SPK_R+_CONN 1
RA224 1 CD@ 2 15_0402_5% SPK_R- RA221 1 2 0_0402_5% SPK_R-_CONN 2 1
RA1 1 2 0_0402_5% RA32 1 CD@ 2 15_0402_5% SPK_L+ RA30 1 2 0_0402_5% SPK_L+_CONN 3 2
EMC_NS@ RA33 1 CD@ 2 15_0402_5% SPK_L- RA34 1 2 0_0402_5% SPK_L-_CONN 4 3
RA4 1 2 0_0402_5% 4
EMC_NS@ 5
6 GND1

470P_0201_50V7-K

470P_0201_50V7-K

470P_0201_50V7-K

470P_0201_50V7-K
LW2

CA183

CA184

CA29

CA30
220P_0201_25V7-K

220P_0201_25V7-K

220P_0201_25V7-K

220P_0201_25V7-K
USB20_N4 1 2 USB20_N4_R GND2

CA31

CA32

CA181

CA182
B 1 2 2 2 2 2 B
RA9 1 2 0_0402_5% 1 1 1 1 ACES_88231-04001

RA12 1 2 0_0402_5% USB20_P4 4 3 USB20_P4_R

4 3 1 1 1 1

EMC@

EMC@

EMC@

EMC@
EMC_NS@
EXC24CH900U_4P 2 2 2 2
EMC_NS@
FOR EMI CD@ CD@ CD@ CD@

GND GNDA
8/16 Update Audio Jack P/N SP011509163 wei

Audio Jack JHP1 ME@

RING2_CONN 3
R3124 1 @ 2 C232 1 2 A_HP_OUTL_R 1 G/M
0_0402_5% @ 470P_0201_50V7-K L
RING3_CONN PLUG_IN 5
RING2_CONN 5
A_HP_OUTL_R DMIC_CLK HDA_SYNC_AUDIO 6
A_HP_OUTR_R EMC_NS@ HDA_SDOUT_AUDIO 6
PLUG_IN DMIC_DATA RA27 1 2 27_0402_5%HDA_BITCLK_AUDIO R3123 1 @ 2 C184 1 2 A_HP_OUTR_R 2
HDA_SDIN0 0_0402_5% @ 470P_0201_50V7-K R
RING3_CONN 4
CA38

CA39
100P_0201_25V8J

100P_0201_25V8J

M/G
AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

CA23

CA24

CA25

CA26
EMC_NS@

EMC_NS@

1 1
7
22P_0201_258J

22P_0201_258J

33P_0201_50V8-J

33P_0201_50V8-J

MS
1

EMC_NS@

EMC_NS@

EMC_NS@
47P_0201_25V8-J

1 1 1 1
DA5 DA6 DA7 DA8 DA9 SINGA_2SJ3095-140111F
EMC_NS@

100P_0201_25V8J

100P_0201_25V8J
1
1

C185 2 2
1 1
EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@
2 2 2 2 C182 C183
A 2 EMC@ EMC@ A
2 2
2

For EMI
2

8/16 Update Audio Jack P/N DC021608101 wei

Security Classification LC Future Center Secret Data Title

Issued Date 2016/08/16 Deciphered Date 2017/08/15 Codec & CR_RTS5199

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
320ABR 0.1

Date: Thursday, January 12, 2017 Sheet 32 of 50

5 4 3 2 1
 5 4 3 2 1

D D

CARD_3V3

SD / MMC

0.1u_0201_10V6K
4.7U_0402_6.3V6M
1 1
SD_D0_R RW3 1 2 0_0402_5% SD_D0 CW9 CW17
32 SD_D0_R
CW5 1 2 5.6P_0402_50V8-D @
2 2
EMC@

JREAD1 ME@
SD_D1_R RW4 1 2 0_0402_5% SD_D1 SD_D3 1
32 SD_D1_R SD_CMD CD/DAT3
CW6 1 2 5.6P_0402_50V8-D 2
3 CMD
4 VSS1
EMC@
SD_CLK 5 VDD
6 CLK
SD_D2_R RW5 1 2 0_0402_5% SD_D2 SD_D0 7 VSS2
32 SD_D2_R Close to Connector SD_D1 DAT0
CW7 1 2 5.6P_0402_50V8-D 8
C SD_D2 9 DAT1 C
DAT2
EMC@
SD_CD# 10 12
SD_D3_R SD_D3 32 SD_CD# SD_WP CARDDETECT SH1
RW6 1 2 0_0402_5% 11 13
32 SD_D3_R 32 SD_WP W RITEPROTECT SH2
CW8 1 2 5.6P_0402_50V8-D 14
SH3 15
SH4
EMC@
T-SOL_5-251301001000-6_NR
SD_CMD_R SD_CMD
Close to Connector
RW7 1 2 0_0402_5%
32 SD_CMD_R
CW11 1 2 5.6P_0402_50V8-D

EMC@ CARD_3V3

8/16 Update Conn. P/N SP07000WG00 wei

SD_CLK_R SD_CLK

1
RW8 1 2 0_0402_5%
32 SD_CLK_R
CW12 1 2 5.6P_0402_50V8-D DW1

AZ5123-01F.R7GR_DFN1006P2X2
EMC_NS@
EMC@

2
2
B B

FOR ESD

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2016/08/16 Deciphered Date 2017/08/15 Cardreader

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 320ABR
Date: Thursday, January 12, 2017 Sheet 33 of 50
5 4 3 2 1
 A B C D E F G H

SATA HDD Conn.

FOR 14"
JHDD1

10
SATA ODD Conn.
SATA_PTX_DRX_P0 C66 1 2 0.01U_0201_10V6K SATA_PTX_C_DRX_P0 9 10
8 SATA_PTX_DRX_P0 SATA_PTX_DRX_N0 SATA_PTX_C_DRX_N0 9
8 SATA_PTX_DRX_N0 C67 1 2 0.01U_0201_10V6K 8
7 8 12
1 SATA_PRX_DTX_N0 C68 1 2 0.01U_0201_10V6K SATA_PRX_C_DTX_N0 6 7 GND2 1
8 SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 C69 1 2 0.01U_0201_10V6K SATA_PRX_C_DTX_P0 5 6 JODD1
8 SATA_PRX_DTX_P0 4 5 1
3 4 11 SATA_PTX_DRX_P1 14@ C70 1 2 0.01U_0201_10V6K SATA_PTX_C_DRX_P1_14 2 GND_1
3 GND1 8 SATA_PTX_DRX_P1 SATA_PTX_DRX_N1 SATA_PTX_C_DRX_N1_14 RX+
2 8 SATA_PTX_DRX_N1 14@ C71 1 2 0.01U_0201_10V6K 3
1 2 4 RX-
1 SATA_PRX_DTX_N1 14@ C72 1 2 0.01U_0201_10V6K SATA_PRX_C_DTX_N1_14 5 GND_2
ELCO_006809610010846 8 SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 14@ C73 1 2 0.01U_0201_10V6K SATA_PRX_C_DTX_P1_14 6 TX-
8 SATA_PRX_DTX_P1 7 TX+
Need short ME@ GND_3
+5VS_HDD
J3 @ 8
1 2 9 DP
+5VS 1 2 +5V_ODD +5V_1
10
JUMP_43X79 11 +5V_2 14
12 MD GND1 15
13 GND_4 GND2
GND_5
+5VS_HDD SUYIN_127382FB013S255ZL
ME@

1 1 1 1 1
C74 C75 C76 C77 C78
1000P_0201_50V7-K 0.1u_0201_10V6K 33P_0402_50V8J 10U_0805_10V6K 33P_0402_50V8J
EMC_NS@ RF@ RF@
2 2 2 2 2

FOR 15"
2 EMC 2

SATA ODD FFC Conn

SATA 15 ODD P/N pin assgin is different from G SKL

JODD2
1
+5VS to +5V_ODD SATA_PTX_DRX_N1 15@ C198 1 2 0.01U_0201_10V6K SATA_PTX_C_DRX_N1_15 2 1
ME@
SATA_PTX_DRX_P1 15@ C197 1 2 0.01U_0201_10V6K SATA_PTX_C_DRX_P1_15 3 2
4 3
SATA_PRX_DTX_P1 15@ C200 1 2 0.01U_0201_10V6K SATA_PRX_C_DTX_P1_15 5 4
SATA_PRX_DTX_N1 15@ C199 1 2 0.01U_0201_10V6K SATA_PRX_C_DTX_N1_15 6 5
+5VS Need short +5V_ODD 7 6
+5V_ODD 8 7
J4 @ 8
1 2 9
3 1 2 10 GND1 3

JUMP_43X79 GND2
1 1 1 HIGHS_FC5AF081-2931H
C85 C86 C1324
10U_0805_10V6K 0.1u_0201_10V6K 33P_0402_50V8J
RF@
2 2 2

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 HDD/ODD CONN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 320ABR
Date: Thursday, January 12, 2017 Sheet 34 of 50
A B C D E F G H
 5 4 3 2 1

RE1 1 2 0_0603_5%
+3VL

RE3 1 @ 2 0_0603_5%
Close EC +3VALW

+3VL_EC +3VL_EC +3VL_EC_R

CE3 1 2 VCOREVCC
LE1 1 @ 2 0_0603_5%
0.1u_0201_10V6K +3VL_EC All capacitors close to EC

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K
CD@
1 1
1 1 1 @1 1 @1 CE4 CE5
0.1u_0201_10V6K 1000P_0201_50V7-K
+3VS +3VL_EC_R
2 2
2 2 2 2 2 2 EC_AGND
Change RE6 to 0ohm jump 1 2 0_0603_5%

CE10

CE11
D LE2 @ D

CE6

CE7

CE8

CE9
RE6 1 @ 2 0_0402_5%
EC_AGND

minimum trace width 12 mil

114
121
127
12

11

26
50
92

74
3
UE1
+3VS

VCORE
VBAT

VSTBY1
VSTBY2
VSTBY3
VSTBY4
VSTBY5
VSTBY(PLL)
VCC

AVCC
EC_FAN_SPEED RE10 1 2 10K_0402_5%
EC_FAN_PWM RE11 1 @ 2 10K_0402_5%
ENBKL RE9 1 @ 2 100K_0402_5%
EC_GFX_PWRGD RE12 1 @ 2 10K_0402_5%
16 WRST# 4 24 SERIRQ 1 2
RE81 @ 10K_0402_5%
+3VL_EC 7 KBRST# 5 KBRST#/GPB6 PWM0/GPA0 25 PWR_LED# 36 EC_LID_OUT# 1 2
RE93 @ 10K_0402_5%
8,30 SERIRQ 6 SERIRQ/GPM6 PWM1/GPA1 28 BATT_CHG_LED# 36
8,11,30 LPC_FRAME# 7 LFRAME#/GPM5 PWM2/GPA2 29 VGA_AC_DET BATT_LOW_LED# 36 +5VALW
2 8,30 LPC_AD3 8 LAD3/GPM3 PWM3/GPA3 30 VGA_AC_DET 16
DE1 @1
8,30 LPC_AD2 LAD2/GPM2 PW M PWM4/GPA4 EC_FAN_PWM LED_KB_PWM 36
9 31
8,30 LPC_AD1 10 LAD1/GPM1 PWM5/GPA5 32 EC_FAN_PWM 30 USB_ON# RE15 1 2 10K_0402_5%
RB751V-40_SOD323-2 8,30 LPC_AD0 CLK_PCI_EC 13 LAD0/GPM0 PWM6/SSCK/GPA6 34 EC_APU_ALWEN BEEP# 32
8,11 CLK_PCI_EC LPCCLK/GPM4 LPC PWM7/RIG1#/GPA7 EC_APU_ALWEN 46
RE8 1 2 100K_0402_5% WRST# 14 120 RE277 1 @ 2 0_0402_5% +3VL_EC
15 WRST# TMRI0/GPC4 124 SUSP# HVB_EN 7,11
28 LAN_PWR_ON# EC_RX 16 ECSMI#/GPD4 TMRI1/GPC6 SUSP# 37,46
1 SUSP# RE18 1 @ 2 100K_0402_5%
31 EC_RX EC_TX 17 PWUREQ#/BBO/SMCLK2ALT/GPC7 66 LAN_WAKE# RE5 1 2 10K_0402_5%
CE12 31 EC_TX APU_LPC_RST# 22 LPCPD#/GPE6 ADC0/GPI0 67 NTC_V1 30 EC_ON RE72 1 2 10K_0402_5%
1U_0402_6.3V6K 7,30 APU_LPC_RST# 23 LPCRST#/GPD2 ADC1/GPI1 68 NTC_V2 30
2 7 EC_SCI# 126 ECSCI#/GPD3 ADC2/GPI2 69 ENBKL BATT_TEMP 43,44 +3VL
7 GATEA20 GA20/GPB5 ADC ADC3/GPI3 ENBKL 23
70 RE278 1 2 0_0402_5%
EC_SCI# in APU internal pull high to 3VALW IT8586E/AX ADC4/GPI4
ADC5/DCD1#/GPI5
71
72
ADP_I 44
RE276 1
@

@ 2 0_0402_5%
IDCHG 44
LID_SW# RE38 1 2 10K_0402_5%

+3VS
+3VL_EC
36 KSI[0..7]
KSI[0..7] KSI0 58
LQFP-128L ADC6/DSR1#/GPI6
ADC7/CTS1#/GPI7
73 RE71 1 2 0_0402_5%
PSYS 44
2_5VEN

KSI1 59 KSI0/STB# 78 2_5VEN RE279 1 2 100K_0402_5%

KSO[0..17] 60 KSI1/AFD# DAC2/TACH0B/GPJ2 79 MAINPWON1_EC VR_APU_PWRGD 49 EC_APU_ALWEN
KSI2 RE26 1 @ 2 1K_0402_5% RE66 1 2 100K_0402_5%
36 KSO[0..17] 61 KSI2/INIT# DAC3/TACH1B/GPJ3 80 H_PROCHOT#_EC MAINPWON 45
KSI3 DAC SUSP# RE19 1 2 100K_0402_5%
KSI4 62 KSI3/SLIN# DAC4/DCD0#/GPJ4 81 SYSON RE21 1 2 100K_0402_5%
C C
KSI4 DAC5/RIG0#/GPJ5 EC_RTCRST#_ON 9
2
1

2
1

KSI5 63 BKOFF# RE40 1 2 10K_0402_5%

RPE3 RPE2 KSI6 64 KSI5 85 EC_ON
KSI7 65 KSI6 PS2CLK0/TMB0/CEC/GPF0 86 EC_ON 45,46
2.2K_0404_4P2R_5% 2.2K_0404_4P2R_5% KSI7 PS2DAT0/TMB1/GPF1 PBTN_OUT# 7 GPU_EC_HOT#
KSO0 36 87 RE90 1 2 0_0402_5% GPU_VR_HOT# 16,48
KSO1 37 KSO0/PD0 GPF2 88 APUALW_PWRGD
EC_SMB_CK3 EC_SMB_CK1 KSO1/PD1 Int. K/B PS2 GPF3 APUALW_PWRGD 46
3
4

3
4

KSO2 38 89 PAD 1 @
EC_SMB_DA3 EC_SMB_DA1 KSO2/PD2 Matrix PS2CLK2/GPF4 EC_LID_OUT# IT12

1
KSO3 39 90 QE8 D 1
KSO4 40 KSO3/PD3 PS2DAT2/GPF5 EC_LID_OUT# 36 2 CE33
KSO4/PD4
AMD request SIC/SID（ EC_SMB3 ） pul l hig h 1K KSO5
KSO6
41
42 KSO5/PD5 EXTERNAL SERIAL FLASH GPH3/ID3
96
97 EC_VR_ON CAPS_LED# 36
G 47P_0201_25V8-J
@
43 KSO6/PD6 GPH4/ID4 98 EC_VR_ON 49 2
KSO7 PAD 1 @ 2N7002KW_SOT323-3 S
KSO7/PD7 GPH5/ID5 IT9

3
+3VL_EC +3VALW KSO8 44 99
KSO9 45 KSO8/ACK# GPH6/ID6 EC_SYS_PWRGD 7 @
46 KSO9/BUSY 101
SMBus1:Charger/Battery KSO10
KSO10/PE NC1
2

SMBus2:PMIC KSO11 51 102

KSO12 52 KSO11/ERR# NC2 103
RE74
0_0402_5%
RE73 SMBus3:APU/GPU/thermalsensor KSO12/SLCT SPI Flash ROM NC3
0_0402_5% KSO13 53 105
@ KSO14 54 KSO13 NC4
KSO15 55 KSO14
KSO15
1

KSO16 56 108 ACIN#

KSO17 57 KSO16/SMOSI/GPC3 AC_IN# 109 LID_SW#
KSO17/SMISO/GPC5 UART LID_SW# LID_SW# 36

EC_GFX_ON
2
1

36 ON/OFF ON/OFF 110 82 VDDGFX_PD=0 -> VDDCR_GFX VRM turned ON.

EC_ON RE104 1 2 0_0402_5% 111 PWRSW# EGAD/GPE1 83 EC_MUTE# 32
RPE5 @ SM Bus RE23 1 2 0_0402_5%
EC_SMB_CK1 115 XLP_OUT EGCS#/GPE2 84 EC_GFX_ON 50VDDGFX_PD=1 -> VDDCR_GFX VRM turned OFF
2.2K_0404_4P2R_5% 43,44 EC_SMB_CK1 EC_SMB_DA1 SMCLK1/GPC1 EGCLK/GPE3 CMOS_ON# 23

1
116 QE5 D
43,44 EC_SMB_DA1 EC_SMB_CK2 117 SMDAT1/GPC2 77 VDDGFX_PD 2 10K_0402_5% VDDGFX_PD_R
GPIO PM_SLP_S5# 7 RE16 1 @ 2
EC_SMB_CK2 46 EC_SMB_CK2 EC_SMB_DA2 SMCLK2/PECI/GPF6 GPJ1
3
4

118 100 GPG2 G

EC_SMB_DA2 46 EC_SMB_DA2 EC_SMB_CK3 94 SMDAT2/PECIRQT#/GPF7 SSCE0#/GPG2 106 EC_GFX_PWRGD 2 0_0402_5% VR_GFX_PWRGD
RE28 1
6,16,30 EC_SMB_CK3 EC_SMB_DA3 95 CRX1/SIN1/SMCLK3/GPH1/ID1 SSCE1#/GPG0 104 PAD 1 @ 1 @ S 2N7002KW_SOT323-3
6,16,30 EC_SMB_DA3 CTX1/SOUT1/GPH2/SMDAT3/ID2 DSR0#/GPG6 IT10

3
1
107 RE85 1 2 0_0402_5% SYSON
+3VL DTR1#/SBUSY/GPG1/ID7 119 BKOFF# RE7 CE15
CRX0/GPC0 123 BKOFF# 23
PAD 1 @ 100K_0402_5% 1000P_0201_50V7-K
CTX0/TMA0/GPB2 IT11 2
RE27 1 @ 2 0_0402_5% 112 18 PM_SLP_S3# 7 @
LAN_WAKE# 125 VSTBY0 RI1#/GPD0 21 VDDGFX_PD @
28,31 LAN_WAKE# GPE4 RI2#/GPD1 VDDGFX_PD 7

2
WAKE UP 76 NOVO# 36
TACH2/GPJ0 48
B TACH1A/TMA1/GPD7 47 EC_FAN_SPEED EC_TS_ON 23 B
USB_ON# 33 TACH0A/GPD6 19
EC_FAN_SPEED 30
RE92 1 @ 2 0_0402_5%
will cost down in future if EC internal logic verify ok
25 USB_ON# 35 GINT/CTS0#/GPD5 L80HLAT/BAO/GPE0 20 PCH_PWRBT# 7 QE3B
37 PCH_CMOSP EC_RSMRST# RTS1#/GPE5 GPIO L80LLAT/GPE7 NUM_LED# 36
93 2N7002KDW H_SOT363-6
7 EC_RSMRST# CLKRUN#/GPH0/ID0 EC_GFX_PWRGD 3 4

D
VR_GFX_PWRGD 7,50

S
2 @
7,28,31 PCIE_WAKE# 128 CK32KE/GPJ7
7 AC_PRESENT CK32K/GPJ6 Clock +3VS

G
5
RE13 1 @ 2 10K_0402_5%

6
1 2 RB751V-40_SOD323-2
DE4
H_PROCHOT#
AVSS

D
VSS1

VSS2
VSS3
VSS4
VSS5
VSS6

VDDGFX_PD 1
2 QE3A C48
RE34 1 2 0_0402_5% G 2N7002KDW H_SOT363-6 0.1U_0201_6.3V6-K
SYSON RE99 2 1 0_0402_5% IT8586E-AX_LQFP128_14X14 44,49,50 VR_HOT# @
1_2VEN 46 @
1

27
49
91
113
122

75

S 2
H_PROCHOT#_EC

1
RE82 1 2 0_0402_5% H_PROCHOT# 6,46
@

1
DE5 1 2 RB751V-40_SOD323-2 QE1 D 1
EC_AGND 2 CE14
Mirror Core strap +3VL_EC RE100 1 @ 2 1K_0402_5% 2_5VEN
G 47P_0201_25V8-J
@
2_5VEN 46 S 2
2N7002KW_SOT323-3

3
+3VL @
GPG2 RE98 2 @ 1 10K_0402_5%
RE97 2 1 10K_0402_5% CLK_PCI_EC RE103 1 2 10_0402_5% EMC_NS@ CE29 1 2 10P_0201_25V8G
EMC_NS@ +3VS
APU_LPC_RST#
1

EMC_NS@ CE27 1 2 220P_0201_25V7-K

for VR_APU_PWRGD undershoot issue RE102
when mirror, GPG2 pull high 100K_0402_5% SYSON EMC_NS@ CE31 1 2 0.1U_0201_6.3V6-K
when no mirror, GPG2 pull low APUALW_PWRGD VR_APU_PWRGD BATT_TEMP EMC_NS@ CE28 1 2 100P_0201_25V8J 2
2

ACIN# 2 RE101 1
1 ACIN# EMC_NS@ CE26 1 2 100P_0201_25V8J CE32
1 CE24 0_0402_5% 0.1U_0201_6.3V6-K
EC_SMB_CK1 1
1

A 1 A
PAD @ CE25 0.01U_0201_10V6K D QE7 @ ON/OFF EMC@ CE30 1 2 0.1U_0402_25V6 EMC_NS@
EC_SMB_DA1 1 IT1 2
PAD @ 0.1U_0402_25V6
1 IT2 2 G ACIN 44
PAD @ @
1 IT3 2
PAD @
1 IT4
PAD @ 2N7002KW_SOT323-3 S @
IT5
3

VR_GFX_PWRGD
EMC
KSI7 PAD 1 @ 1
IT6
KSI6 PAD 1 @ CE34
IT7
WRST# PAD 1 @ 0.01U_0201_10V6K Title
IT8 Security Classification LC Future Center Secret Data
2
Issued Date 2016/08/16 Deciphered Date 2017/08/15 Blank
Reserve Factory EC flash, need confirm with ITE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
320ABR 0.1

Date: Thursday, January 12, 2017 Sheet 35 of 50

5 4 3 2 1
 5 4 3 2 1

ON/OFF switch +3VL +3VALW

Novo button NOVO_BTN#

2
SW2

1
R82 R83 4 D24

1
100K_0402_5% 100K_0402_5% AZ5123-01F.R7GR_DFN1006P2X2
@ 5 EMC@
R261 1 2

1
0_0402_5%

2
NTC325-EKJ-A160T_3P

2
NOVO# D15 2
35 NOVO#
1 NOVO_BTN#
ON/OFFBTN#
ON/OFF R85 1 @ 2 0_0402_5% 3 @

AZ5123-01F.R7GR_DFN1006P2X2
BAT54CW_SOT323-3

1
D25

1
D D

+3VALW +3VL

LID switch

2
2

2
EMC@

2
R111 R114
100K_0402_5% 100K_0402_5%
@

1
ON/OFFBTN# R119 1 @ 2 0_0402_5% ON/OFF 1
ON/OFF 35
C1104
U14 100P_0201_25V8J
J5 1 2 @ 1
GND 2
1 LID_SW#
SHORT PADS C1105 3
0.01U_0201_10V6K OUTPUT LID_SW# 35
J6 1 2 @
R264 1 2 2 +VCC_LID 2
+3VL VCC
SHORT PADS 0_0402_5%
AH9247-W-7_SC59-3

K/B Connector KSI[0..7]

KSI[0..7] 35 KB Backlight Connector
KSO[0..17] JKB1
KSO[0..17] 35
+5VS
32 33
ON/OFFBTN# 31 32 GND1 34
PWR_LED# 31 GND2 +5VALW
EMC_NS@ R285 1 2 0_0402_5% 30 +VCC_KB_LED
PWR_CAPS_LED R279 1 15@ 2 0_0402_5% NUM_LED#_R 29 30
C133 1 2 100P_0201_25V8J 35 NUM_LED# KSO17_R 29 Q31
KSO17 R281 1 15@ 2 0_0402_5% 28

1
KSO16_R 28 R265 LP2301ALT1G_SOT23-3
KSO16 R280 1 15@ 2 0_0402_5% 27
10K_0402_5% KBL@
KSI1 26 27
KBL@ 3 1

D
KSI7 25 26
KSI6 24 25
KSO9 23 24 1 1

2
23 R266 C1106 C1107

G
KSI4 22

2
22 1 2 10U_0603_6.3V6M 0.1u_0201_10V6K
KSI5 21 KBL@ KBL@
KSO0 20 21
EMC@ 100K_0402_5% 2 2
CAPS_LED# KSI2 19 20 1
C117 1 2 100P_0201_25V8J 19 KBL@ C1108
KSI3 18 0.01U_0201_10V6K
NUM_LED#_R KSO5 17 18
C C118 1 2 100P_0201_25V8J 17 KBL@ C
KSO1 16 2
KSI0 15 16
EMC_15@ 15
KSO2 14
KSO4 13 14 To be confirm Pin define
KSO7 12 13

1
12 D
KSO8 11 LED_KB_PWM 2 Q32
CAPS_LED# NUM_LED#_R PWR_LED# KSO6 10 11 35 LED_KB_PWM
10 G 2N7002KW_SOT323-3 JKBL1 ME@
KSO3 9 +VCC_KB_LED 1
9 KBL@
KSO12 8 1

2
8 1 S 2
KSO13 7 2

3
7 C1109 R4685 3 6
KSO14 6 0.1u_0201_10V6K 10K_0402_5% 4 3 GND2 5
KSO11 5 6 4 GND1
1

5 KBL@ @ 1
D22 D23 D46 KSO10 4 2 C1110 CVILU_CF50041D0RN-10-NH
4
1

KSO15 3

1
AZ5123-01F.R7GR_DFN1006P2X2 AZ5123-01F.R7GR_DFN1006P2X2 AZ5123-01F.R7GR_DFN1006P2X2 R275 3 0.1u_0201_10V6K
EMC@ EMC_15@ EMC@ 1 2 0_0402_5% 2 @
35 CAPS_LED# 1 2 200_0402_1% PWR_CAPS_LED 1 2
+3VALW 2
1
R84
CVILU_CF32321D0RONH
2

ME@
2

For EMC

Finger Print Connector TP/B Connector

FP_PWR +3VS TP_PWR
To be confirm Pin define
R141 1 2
+3VS 0_0402_5%
JFP1

0.1u_0201_10V6K
R3120 1 2 1 1
USB20_N3 R3122 1 FP@ 2 0_0402_5% USB20_N3_CONN 2 1
0_0402_5%
8 USB20_N3 USB20_P3 R3121 1 FP@ 2 0_0402_5% USB20_P3_CONN 2
FP@ 3
8 USB20_P3 3
0.1u_0201_10V6K

1 4
5 4 2

C114
6 5
FP@ 7 6
2 8 7
C2061

USB20_N3_CONN 8
9 JTP1 ME@
10 GND1 R4684 1 2 0_0402_5% EC_LID_OUT#_R 1
USB20_P3_CONN GND2 TP_I2C0_SCL 35 EC_LID_OUT# TP_INT# 1
R4683 1 2 0_0402_5% 2 7
B TP_I2C0_SDA 7 PCH_TP_INT# 2 GND1 B
HIGHS_FC5AF081-2931H 3
TP_I2C0_SDA_R R4681 1 @ 2 0_0402_5% TP_I2C0_SDA 4 3 8
ME@ TP_I2C0_SCL_R TP_I2C0_SCL 4 GND2
3

2
R4680 1 @ 2 0_0402_5% 5
DT2 DT1 6 5
TP_PWR 6

100P_0201_25V8J

100P_0201_25V8J
EMC_NS@ EMC_NS@ ELCO_04-6809-606-110-846-+

EMC_NS@

EMC_NS@
1 1

2 2

C115

C116
AZC199-02S.R7G_SOT23-3 AZC199-02S.R7G_SOT23-3
1

1
For EMC

TP_PWR
BATT_LOW_LED# LED2 1 2 R143 1 2 470_0402_5% +1.8VS
35 BATT_LOW_LED# +3VALW
L-C192JFCT-LCFC_SUPER_AMBER
1

2
1
D18 RPC20
1

AZ5725-01F.R7GR_DFN1006P2X2 2.2K_0404_4P2R_5%
EMC_NS@

5
G

3
4
2

TP_I2C0_SDA_R TP_I2C0_SDA
2

4 3

S
7 TP_I2C0_SDA_R

D
BATT_CHG_LED# Q159B

2
LED3 1 2 R144 1 2 1.5K_0402_5%

G
35 BATT_CHG_LED# +5VALW DMN5L06DWK-7 2N SOT363-6
L-C192WDT-LCFC_WHITE
TP_I2C0_SCL_R TP_I2C0_SCL
1

1 6

S
7 TP_I2C0_SCL_R
D19

D
1

AZ5725-01F.R7GR_DFN1006P2X2
EMC_NS@ Q159A
DMN5L06DWK-7 2N SOT363-6
2
2

PWR_LED#
A A

PWR_LED#
35 PWR_LED# LED4 1 2 R4672 1 2 1.5K_0402_5%
+5VALW
1

L-C192WDT-LCFC D16
1

AZ5725-01F.R7GR_DFN1006P2X2
EMC_NS@
2

PWR_LED Change to M/B (310->320) 08/17

2

Security Classification LC Future Center Secret Data Title

Issued Date 2016/08/16 Deciphered Date 2017/08/15 KBD/PWR/IO/LED/TP Conn.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Re v
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 320ABR
Date: Thursday, January 12, 2017 Sheet 36 of 50
5 4 3 2 1
 A B C D E

+5VLP +5VALW
Load Switch modify load swt i c h fr o m APL3523 t o G5016KD1 U T DF N 14P
+5VALW To +5VS +3VS, C173 --> 5.78ms
+3VALW To +3VS +5VS, C176 --> 1.71ms

1
R156 R157 R4
VIN 5V and 3.3V (VBIAS=5V), IMAX(per channel)=6A, Rds=16mohm
1 2 +5VALW
100K_0402_5% 100K_0402_5% 3VSON Need Short +5VS
@ 0_0402_5%
U13 J12 @

2
1 1 14 +5VS_LS 1 2 1
SUSP 2 IN1_1 OUT1_2 13 1 2
12,24 SUSP IN1_2 OUT1_1
R2 1 JUMP_43X118 1
SUSP# 1 2 5VSON 5VSON 3 12 C176 1 2 1000P_0201_50V7-K C174
0_0402_5% C177 EN1 CT1 0.1U_0201_6.3V6-K
1U_0402_6.3V6K 4 11 @
2 +5VALW VBIAS GND 2

1
Q6 D
1 1 @
2 +3VALW 3VSON 5 10 C173 1 2 2200P_0402_25V7-K +3VS
35,46 SUSP# G EN2 CT2
C180 C179 J11 @
1U_0402_6.3V6K 1U_0402_6.3V6K 6 9 +3VS_LS 1 2
S 2N7002KW_SOT323-3 2 2 7 IN2_1 OUT2_2 8 1 2
IN2_2 OUT2_1

3
1 JUMP_43X118 1
15 C175
GPAD
C178
1U_0402_6.3V6K
Need Short 0.1U_0201_6.3V6-K
G5016KD1U_TDFN14_2X3 @
2 @ 2

+1.8VALW to +1.8VS AON6414AL

VDS=30V VGS=20V, ID=50A,
+1.05VALW to +1.05VS AON6414AL
+1.8VALW Q39 +1.8VS +/- 5% 1.5A Rds=8mohm @ VGS=10V
+/- 2% AON6414AL_DFN8-5
VGS(th)=2.5V Max VDS=30V VGS=20V, ID=50A,
+1.05VALW Q41 +1.05VS +/-5% 3.6A Rds=8mohm @ VGS=10V
1 +/- 1.5% AON6414AL_DFN8-5
VGS(th)=2.5V Max
2 1 1
2 1 5 3 C142 1 2
C141 C2082 1U_0402_6.3V6K 2 1 1
10U_0603_6.3V6M 10U_0603_6.3V6M 1 5 3 C147
2 2

1
@ 1 1 C146 C145 1U_0402_6.3V6K
4

2 C1325 C1326 0.01U_0201_10V6K R213 @ 10U_0603_6.3V6M 10U_0603_6.3V6M

2 2

1
0.1U_0201_6.3V6-K @ 470_0603_5% @ 1 1

4
@ 2 C1327 C1328 0.01U_0201_10V6K R188 @
2 2 0.1U_0201_6.3V6-K @ 470_0603_5%
V20B+

2
@
2 2 R206
V20B+

2
R211 R194 1 2 1.8VS_GATE
1.8VS_GATE_R 1 2 1 2 1.8VS_GATE 2 R214 1 0_0402_5%
0_0402_5% 0_0402_5% R193
330K_0402_5% 1.05VS_GATE_R 1 2 1 R190 21.05VS_GATE 2 R189 1
1

1
1 D Q45 Q46 @ D 0_0402_5% 0_0402_5% 470K_0402_5%
C143 R212 2 SUSP 2 @ @

1
0.01U_0201_25V6-K 1M_0402_5% G G
1 D Q37 Q40 @ D
C144 R187 2 SUSP 2
2 S 2N7002KW_SOT323-3 S 2N7002KW_SOT323-3 0.01U_0201_25V6-K 820K_0402_5% G G
2

3
@
2 S 2N7002KW_SOT323-3 S 2N7002KW_SOT323-3

3
@

20VSB will change to 6V in DC mode, careful the Res divide voltage

+3VALW to +3VALW_APU For DisCharge
+0.6VS +2.5V +3VS CS31 CS40 CS34
3 3
+3VALW +3VALW_APU 1 2 1 2 1 2
Need Short 1 +5VALW +3VALW +APU_CORE_NB +3VS +3VS +3VALW

1
J7 @ R159 R935 R940 0.1U_0201_6.3V6-K 0.1U_0201_6.3V6-K 0.1U_0201_6.3V6-K
1 2 47_0603_5% 47_0603_5% 47_0603_5%
1 2 @ @ @
JUMP_43X79
2

2
+3VS +5VS +3VS +5VS
Id=3.2A
1

1
D Q8 D Q156 D Q158 1 1 1 1
LP2301ALT1G_SOT23-3 2 SUSP 2 SUSP 2 SUSP CS28 CS24 CS27 CS25
@ G G G 0.1U_0402_25V6 0.1U_0402_25V6 0.1U_0402_25V6 0.1U_0402_25V6
Q29 3 1
S

2N7002KW_SOT323-3 S @ 2N7002KW_SOT323-3 S @ 2N7002KW_SOT323-3 S @ 2 2 2 2

0.01U_0201_10V6K

3
1 1
C129 C130
G
2

0.1U_0201_6.3V6-K
@ @
2 2

R158 1 @ 2 0_0402_5% +3VALW +3VS +5VS

35 PCH_CMOSP +1.05VALW +1.05VALW +1.05VALW +1.05VALW +APU_GFX
1

1 1 2 1
C131 1 1 1 1 CS43 1 CS26
R164 0.1U_0201_6.3V6-K C2083 C2084 C2085 C2086 0.1U_0402_25V6 CS42 CS22 0.1U_0402_25V6
100K_0402_5% @ 2200P_0402_25V7-K 2200P_0402_25V7-K 2200P_0402_25V7-K 2200P_0402_25V7-K 10U_0402_6.3V6M 0.1U_0201_6.3V6-K
@ 2 EMC_NS@ EMC_NS@ EMC_NS@ EMC_NS@ 2 1 2
2

2 2 2 2 2
4 4

reserve to cut off APU 3VALW when clear CMOS

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 DC V TO VS INTERFACE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 320ABR
Date: Thursday, January 12, 2017 Sheet 37 of 50
A B C D E
 5 4 3 2 1

CPU Thermal Holex3 GPU Thermal Holex2 PCB Fedical Mark PAD
Close to RJ45 Close to Audio jack
H1 H2 H3 H4 H5 H6 H7
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA FD1 FD2 FD3 FD4 FD5 FD6
D 1 D

1
pad_c6p0d4p0 pad_c6p0d4p0 pad_c6p0d4p0 pad_c7p0d3p3 pad_c7p0d3p3 CHASSIS1_GND
pad_ct7p0b8p0d3p0 pad_ct7p0b8p0d3p0

WLAN Standoff
H10 H11 H12 H13 H15 H16
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
1

1
C C

pad_ct5p5d2p5 pad_ct7p0b6p0d3p3 pad_ct7p0d3p0 pad_ct7p0d3p0 pad_ct5p0d2p5 pad_cb5p5d2p5

H17 H18 H19 H20

HOLEA HOLEA HOLEA HOLEA
1

1
pad_o2p6x2p9d2p6x2p9n PAD_CT7P0D3P0 PAD_CT7P0D3P0 pad_c3p3d3p3n

SH1 ME@ SH2 ME@ SH3 ME@

B B
SH7 ME@ SH8 ME@ SH14 ME@
1 1 1 SH12 ME@
1 1 1 1 1 1
1 1 1 1
1

SPRING_FINGER_6.2X1.64 SPRING_FINGER_6.2X1.64 SPRING_FINGER_6.2X1.64

SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P
SPRING_FINGER_6.2X1.64

SH4 ME@ SH5 ME@ SH6 ME@

1 1 1 SH13 ME@ SH9 ME@

1 1 1 SH10 ME@ SH11 ME@
1 1
1 1 1 1
1 1
SPRING_FINGER_6.2X1.64 SPRING_FINGER_6.2X1.64 SPRING_FINGER_6.2X1.64

SPRING_FINGER_6.2X1.64 SHIELDING_SUL-35A2M_9P2X3P3_1P
SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P
USB3.0 Shielding
DDR4 Shielding
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Hole
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
B
320ABR 0.1

Date: Thursday, January 12, 2017 Sheet 38 of 50

5 4 3 2 1
 5 4 3 2 1

UC2 UC2
UC2
UL1 8111H@ UV1 PX@ ZZZ3 HDMI@

BRISTOL AM970PADY44AB 2.5G PR 1.0 BRISTOL AM960PADY44AB 2.4G PR 1.0

BRISTOL FM980PADY44AB 2.7G PR 1.0 A129720P@ A109620P@
RTL8111H-CG R17M-M1-70 GPU HDMI PN FX9800P@ SA00008A900 SA00008AA00
SA000074W00
LAN Chip SA000086K00
GPU RO00000040J
HDMI Royalty
SA00007RC10 APU type

D D

ZZZ9 DRAM_S4G@ ZZZ2 DRAM_M4G@ ZZZ7 DRAM_H4G@ ZZZ4 S4GX4@ ZZZ6 H4GX4@ ZZZ10 M4GX4@ ZZZ5 S8GX4@ ZZZ8 H8GX4@ ZZZ12 M8GX4@

Samsung Micron Hynix Samsung Hynix Micron Samsung Hynix Micron

X7643U12002 X7643S12002 X7643R12002 X7643P12001 X7643Q12001 X7643T12001 X7643U12001 X7643R12001 X7643S12001
DRAM X76 BOM
VRAM X76 BOM

UD1 MD_S8Gb@ UD2 MD_S8Gb@ UD3 MD_S8Gb@ UD4 MD_S8Gb@ RC257 MD_S8Gb@ RC265 MD_S8Gb@ UV5 S4G_VR@ UV6 S4G_VR@ UV7 S4G_VR@ UV8 S4G_VR@ RV63 S4G_VR@ RV70 S4G_VR@

K4A8G165WB-BCRC K4A8G165WB-BCRC K4A8G165WB-BCRC K4A8G165WB-BCRC 10K_0402_5% 10K_0402_5% K4G41325FE-HC28 K4G41325FE-HC28 K4G41325FE-HC28 K4G41325FE-HC28 3.4K_0402_1% 10K_0402_1%
SA00007TQ00 SA00007TQ00 SA00007TQ00 SA00007TQ00 SD02810028J SD02810028J SA00007VQ10 SA00007VQ10 SA00007VQ10 SA00007VQ10 SD03434018J SD03410028J

DRAM_Samsung 4G VRAM_Samsung 4GX4

UD1 MD_H8Gb@ UD2 MD_H8Gb@ UD3 MD_H8Gb@ UD4 MD_H8Gb@ RC258 MD_H8Gb@ RC264 MD_H8Gb@ UV5 H4G_VR@ UV6 H4G_VR@ UV7 H4G_VR@ UV8 H4G_VR@ RV63 H4G_VR@ RV70 H4G_VR@
C C

H5AN8G6NAFR-UHC H5AN8G6NAFR-UHC H5AN8G6NAFR-UHC H5AN8G6NAFR-UHC 2K_0402_5% 2K_0402_5% H5GC4H24AJR-R0C H5GC4H24AJR-R0C H5GC4H24AJR-R0C H5GC4H24AJR-R0C 4.53K_0402_1% 4.99K_0402_1%
SA00007X200 SA00007X200 SA00007X200 SA00007X200 SD02820018J SD02820018J SA000081A00 SA000081A00 SA000081A00 SA000081A00 SD03445318J SD03449918J

DRAM_Hynix 4G VRAM_Hynix 4GX4

UD1 MD_M8Gb@ UD2 MD_M8Gb@ UD3 MD_M8Gb@ UD4 MD_M8Gb@ RC258 MD_M8Gb@ RC265 MD_M8Gb@ UV5 M4G_VR@ UV6 M4G_VR@ UV7 M4G_VR@ UV8 M4G_VR@ RV63 M4G_VR@

MT40A512M16JY-083E:B MT40A512M16JY-083E:B MT40A512M16JY-083E:B MT40A512M16JY-083E:B 2K_0402_5% 10K_0402_5% EDW4032BABG-70-F EDW4032BABG-70-F EDW4032BABG-70-F EDW4032BABG-70-F 4.75K_0402_1%
SA00007TS00 SA00007TS00 SA00007TS00 SA00007TS00 SD02820018J SD02810028J SA000081800 SA000081800 SA000081800 SA000081800 SD03447518J

DRAM_Micron 4G VRAM_Micron 4GX4

UV5 S8G_VR@ UV6 S8G_VR@ UV7 S8G_VR@ UV8 S8G_VR@ RV63 S8G_VR@ RV70 S8G_VR@
ZZZ1 ZZZ13

REDRV@ NOREDRV@

B K4G80325FB-HC28 K4G80325FB-HC28 K4G80325FB-HC28 K4G80325FB-HC28 8.45K_0402_1% 2K_0402_1% B

PCB PN PCB PN SA000081C00 SA000081C00 SA000081C00 SA000081C00 SD000011R00 SD03420018J
DA600013G00 DA600013F00
PCB_MB with redriver PCB_MB without redriver VRAM_Samsung 8GX4

UV5 H8G_VR@ UV6 H8G_VR@ UV7 H8G_VR@ UV8 H8G_VR@ RV70 H8G_VR@

H5GC8H24MJR-R0C H5GC8H24MJR-R0C H5GC8H24MJR-R0C H5GC8H24MJR-R0C 4.75K_0402_1%

SA000081600 SA000081600 SA000081600 SA000081600 SD03447518J

VRAM_Hynix 8GX4

UV5 M8G_VR@ UV6 M8G_VR@ UV7 M8G_VR@ UV8 M8G_VR@ RV63 M8G_VR@ RV70 M8G_VR@

MT51J256M32HF-70:A MT51J256M32HF-70:A MT51J256M32HF-70:A MT51J256M32HF-70:A 4.53K_0402_1% 2K_0402_1%

SA000081700 SA000081700 SA000081700 SA000081700 SD03445318J SD03420018J

VRAM_Micron 8GX4
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Virtual symbol
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
320ABR 0.1

Date: Thursday, January 12, 2017 Sheet 39 of 50

5 4 3 2 1
 5 4 3 2 1

8 PXS_PWREN
A2 ACIN# EC_RSMRST#

V
A1

V
AC +0.95VGS
MODE

V
VIN PU802
9 PBTN_OUT# VDDGFX_PD

V V

V
A3 B2 3VL VR_GFX_PWRGD
PU501

V V V
PM_SLP_S3#
BATT 10 +APU_GFX
D
BATT PM_SLP_S5# APU V D

V
MODE +0.95VGS

V
B1

V
15 EC_SYS_PWRGD QV3
+APU_CORE

V
PLT_RST# 16

V
EC_ON A4 +APU_CORE_NB +3VGS
EC

V
QV6

V
17
KBRST# V V V V V V

V
B4
VGA
V +1.8VGS

V
APU_S5_MUX_CTRL +VDDCR_FCH_S5
ALW_PWRGD QV2
V
V

PU602
5 V B3
Compare

V
+0.7755VALW +1.35VGS

V
V

V
ALW_PWRGD ON/OFF
V

PU601 ALW_PWRGD UC4 QC1/QC2/QC3/QC5 PU801

V V V
7
V
EN_PMIC
or

+VGA_CORE

V
APUALW_PWRGD +0.95VALW +0.95VS
+3VALW +5VALW PU901
12 SUSP# Q41

V
C C
6 EC_APU_ALWEN
V V +1.8VS VGA_PWRGD

V
+1.8VALW
Q39
12 SUSP# 12 SUSP#

V
U13 loadswitch
V

11 SYSON PMIC +1.2V

V
PU701
+3VS +5VS

+0.6VS
V V

V
12 SUSP#
+1.5VS(reserve)

V
+2.5VS

V
B PU1103 B

14
VR_APU_PWRGD

13 EC_VR_ON +APU_CORE
V
PU1001
+APU_CORE +APU_CORE_NB
+APU_CORE_NB

13 EC_GFX_ON
PU1101 +APU_GFX
V

+APU_GFX

14
VR_GFX_PWRGD

A VDDGFX_PD A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 Power sequence Block

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 320ABR
Date: Thursday, January 12, 2017 Sheet 40 of 50
5 4 3 2 1
 5 4 3 2 1

B+
+5VLP/ 100mA
Silergy
SY8288C +5VALW/8A
Adaptor Converter
EC_ON EN FOR SYSTEM PGOOD ALW_PWRGD

+3VLP/ 100mA
D
Silergy D

SY8286B
Converter +3VALW/6A

EC_ON EN FOR SYSTEM PGOOD ALW_PWRGD

LCFC +1.2V/6A
LCFC5075B
1.2VEN S5 PMIC +0.6VS/1A
SUSP# S3
TI FOR SYS PGOOD

BQ24780SRUYR +5VALW
Battery Charger +1.05VALW/6A
EC_APU_ALWEN EN
PGOOD APUALW_PWRGD
Switch Mode
+3VALW +1.8VALW/3A
C C

EC_APU_ALWEN EN PGOOD APUALW_PWRGD

SMBus +1.8VALW
+0.775VALW/0.5A
EC_APU_ALWEN EN

+3.3VALW

Battery 2.5VEN EN
+2.5V/0.5A

Li-ion
2S1P
MPS
NB685GQ-Z +1.35VGA /8A
Converter
FOR 1.35VGS
B B
PXS_PWREN EN PGOOD

Richtek
RT3662EBGQW
Switch Mode +VGA_CORE/28A
FOR VGA_CORE
PXS_PWREN EN PGOOD VR_VGA_PWRGD

02 APU_CORE/22A
RT3661AB
Switch Mode
APU_SVID VIDs
APU_CORE_NB/12A
EN FOR CPU CORE&NB PGOOD
EC_VR_ON VR_APU_PWRGD Security Classification LC Future Center Secret Data Title

A
Issued Date 2013/08/15 Deciphered Date 2013/08/15 Power Diagram A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev

02 DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
320ABR 0.1

RT3669EA APU_GFX/22A Date: Thursday, January 12, 2017 Sheet 41 of 50

Switch Mode
APU_GFX_SVID VIDs
EN FOR CPU GFX PGOOD APU_PWROK
EC_GFX_ON

5 4 3 2 1
 5 4 3 2 1

Cost down PL101,PL102 if EMC test pass

PL101 EMC_NS@
HCB2012KF-121T50_0805
1 2
EMC_NS@
PL102
HCB2012KF-121T50_0805
VIN
1 2

D PJ101 @ D
JDCIN1 PF101 JUMP_43X79
1 APDIN 1 2 APDIN1 1 2
1 2 1 2
GND1 3 7A_24VDC_429007.WRML
GND2 4
GND3 5

1000P_0402_50V7K

1000P_0402_50V7K
100P_0402_50V8J

100P_0402_50V8J
GND4 6

PC101 EMC@

PC102 EMC@

PC103 EMC@

PC104 EMC@
GND5

1
7
GND6

2
HIGHS_PJSS0026-8B01H
ME@

C C
VCCRTC
+3VL

2
RTC_VCC
1
JRTC1
3 2 1 1
PR104 2 1
2 2
BAT54CW_SOT323-3 1K_0603_5% 3
PC105 PD101 4 GND1
1U_0402_10V6K GND2
1 @
HIGHS_WS33020-S0351-HF
ME@

JRTC2 PRTC1
1
2 1
3 2
4 GND1
B GND2 B

BATT CR2032 3V 220MAH

HIGHS_WS33020-S0351-HF
RTC@
ME@
35mm cable

RTC Battery for GCM BOM

(2nd source and quoted price )

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 DCIN / RTC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 320ABR
Date: Thursday, January 12, 2017 Sheet 42 of 50
5 4 3 2 1
 5 4 3 2 1

D D

PL103 EMC@
VMB HCB2012KF-121T50_0805
1 2
SUYIN_125022HB008M202ZL Cost down BATT fuse
PL104 EMC@
BATT+
JBATT1
HCB2012KF-121T50_0805
1 1 2
1 2
9 2 3 EC_SMCA
10 GND1 3 4 EC_SMDA
GND2 4 5
5 6
6

1
7 PC106 PC107
7 8 1000P_0402_50V7K 0.01U_0402_25V7K
8
EMC@ EMC@

2
ME@

100_0402_1%
PR105
C C

100_0402_1%
PR106

2
2

1
PD103 EC_SMB_CK1 35,44
AZC199-02S.R7G_SOT23-3
EMC_NS@
EC_SMB_DA1 35,44

PR107 1 2 100K_0402_1%
+3VALW

BATT_TEMP_IN 1 2
BATT_TEMP 35,44 A/D
PR108
10K_0402_5%

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 BATTERY CONN/OTP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
B
320ABR 0.1

Date: Thursday, January 12, 2017 Sheet 43 of 50

5 4 3 2 1
 5 4 3 2 1

PQ201 P3 PJ201
AON6414AL_DFN8-5
PQ202
AON7408L_DFN8-5 JUMP_43X79 PR201 V20B+
P2 @ 0.01_1206_1%
VIN 1 1
S1
2 2 5 2 1 1 4
5 3 3 S2 D 2 1
S3 2 3

10U_0603_25V6-M

10U_0603_25V6-M
4

4
1

1
EMC_NS@

EMC_NS@
D D
1

1
PC202
PC201 PR202 0.022U_0402_25V7K

PC203

PC204
2

2
4.7_0603_5%
2

470P_0402_50V7K

5
2

1 2

PC205 780s_BATDRV 4

1
PC206 0.1U_0402_25V6

1
1U_0603_25V6K PC207 PQ203
0.1U_0402_25V6 AON6324_DFN8-5

1
VIN BATT+

3
2
1
1
PR203
499K_0402_1% PC208
0.01U_0402_25V7K

2
BAT54CW_SOT323-3

2
780s_ACDRV_R

PD201
2

3
V20B+

1780s_VCC_R 1
VIN

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
1

2
EMC_NS@

PC211
4.02K_0603_1%

4.02K_0603_1%

ACN
ACP
PR206

PR207

PC212
BQ24780S_VDD

PC209
2

1
1

5
PR209
2

1
PR208 PC213 10_1206_5% PQ205

D
7.15K_0402_1% 43K_0402_1% 1U_0603_25V6K AON7408L_DFN8-5

ACN
ACP
1 2
780s_VCC

2
C PR210 1 2 28 24 1 2 C
VCC REGN
2

2.2U_0603_10V6-K PC214 4
1 2 780s_ACDET 6 PC216 G
PC215 ACDET 0.047U_0603_16V7K

S3
S2
S1
0.01U_0402_25V7K 25 780s_BS
1 2780s_BS_R
2 1
780s_CMSRC BTST PR211 PR213
780s_ACDRV BATT+

3
2
1
2.2_0603_5% 0.01_1206_1%
3 26 780s_HG
@ CMSRC HIDRV
PL201
PR212 1 2 10K_0402_5% 1 2 1 4
4 4.7UH_PCMB053T-4R7MS_4A_20%
ACDRV 2 3
@ 780s_LX

1
PR214 1 2 100K_0402_5% 27
BQ24780S_VDD

10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6
PHASE

EMC_NS@
PR216

D
780s_ACOK

1
PR215 1 2 0_0402_5% 5 PQ206 4.7_0805_5%

PC221

PC217

PC218
35 ACIN ACOK
780s_SDA
PU201 AON7408L_DFN8-5 EMC_NS@
PR217 1 2 0_0402_5% 11
35,43 EC_SMB_DA1 SDA 780s_LG

2
23 4

780s_SN
LODRV G
PR218 1 2 0_0402_5% 780s_SCL 12 22

S3
S2
S1
35,43 EC_SMB_CK1 SCL GND

1
PC222
780s_IADP

3
2
1
PR219 1 2 0_0402_5% 7 29 1000P_0402_50V9-J
35 ADP_I

0.1U_0402_25V6

0.1U_0402_25V6
IADP PAD

2
780s_IDCHG 780s_BATDRV
EMC_NS@

1
PR220 1 2 0_0402_5% 8 18

PC223

PC224
35 IDCHG IDCHG BATDRV
PR221 1 2 0_0402_5% 780s_PMON 9
35 PSYS PMON 780s_BATSRC 780s_BATSRC_R

2
@ 17 1 2
100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

PR223 1 2 BATSRC PR222 10_0603_5%

+3VALW 780s_SRP 780s_SRP_R
10K_0402_1% 20 1 2
10 SRP PR224 10_0603_5%
35,49,50 VR_HOT# PROCHOT#

1
1

13 PC228
PR231 CMPIN
0.1U_0402_25V6

2
BATPRES#
1

14
TB_STAT#

20K_0402_1%
CMPOUT 19 780s_SRN 1 2 780s_SRN_R
780s_ILIM 21 SRN PR225 10_0603_5%
PC225

PC226

PC227

ILIM
2

B B
PR226
780s_TB# 16

15

0_0402_5% BQ24780SRUYR_QFN28_4X4
2

1 2 780s_ILIM_R 1 2
+3VALW BATT_TEMP 35,43
PR227 14.7K_0402_1%
316K_0402_1% PR228
1
1

PR230
PC229 100K_0402_1%
0.1U_0402_25V6
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 CHARGER

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
320ABR 0.1

Date: Thursday, January 12, 2017 Sheet 44 of 50

5 4 3 2 1
 5 4 3 2 1

+3VALW

1
PR601
V20B+ 100K_0402_5%
D
@ D
@ PU601

2
1.5A 2
PJ601
1 +3VALW_VIN 5 9 +3VALW_PG
2 1 4 IN1 PG 1 +3VALW_BS 1 2
3 IN2 BS PC602

PC601 EMC@
+3VALW

10U_0805_25V6K

10U_0805_25V6K
0.1U_0201_25V6-K
IN3

1
JUMP_43X79 2 0.1U_0603_25V7-M
IN4 6 @

PC603

PC604
LX1
7
GND1 LX2
19
+3VALW_LX
PL601
+3VALW_P
PJ602
5A

2
8 20 1 2 2 1
18 GND2 LX3 2.2UH_PCMB053T-2R2MS_5.5A_20% 2 1

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
GND3

1
21
GND4

1
PR602 JUMP_43X79
+3VALW_EN 12 14 +3VALW_P 4.7_0805_5%

PC605

PC606

PC607

PC608
+3VALW_VIN 11 EN1 OUT
EN2 +3VALW_FB
EMC_NS@

2
13
FF

2
10
Vout=3.3V± 5%
100mA+3VLP
16 NC1
NC2

+3VALW_SN
@ 15 17
Vset=3.37V± 1.5%

1M_0402_5%
0.1U_0201_25V6-K
NC3 LDO

PR603

4.7U_0603_6.3V6K
1
OCP=12A

PC610
SY8286BRAC_QFN20_3X3

1
PC611
OVP=(1.15~1.25)*Vout

1
PC612
1000P_0402_50V9-J UVP=(0.55~0.65)*Vout
EMC_NS@ Fsw=600Khz

2
PC613
PR604
PR605 PR611 1 2 +3VALW_FB_C 1 2
0_0402_5% 0_0402_5%
EC_ON 1 2 EC_ON_R 1 2 +3VALW_EN 1K_0402_1%
35,46 EC_ON +3VL 1000P_0201_25V7K
PR612 +3VLP @
PD601 @ 0_0402_5% PJ603
LRB751V-40T1G_SOD323-2 1 2 +5VALW_EN 2 1
1 2 2 1
C 35 MAINPWON C
JUMP_43X39

30 EC_ON_R

+3VALW

1
PR606
100K_0402_5%
V20B+ @

2
@ PU602
2.5A 2
PJ604
1 +5VALW_VIN 5 9
2 1 4 IN1 PG 1 +5VALW_BS 1 2 ALW_PWRGD 46
3 IN2 BS PC615 0.1U_0603_25V7-M @ +5VALW
PC614 EMC@

10U_0805_25V6K

10U_0805_25V6K
0.1U_0201_25V6-K

IN3
1

2
JUMP_43X79 PL602 PJ605
8A
PC616

PC617

IN4 6 +5VALW_LX 1 2 +5VALW_P 2 1

7 LX1 19 2.2UH_PCMB063T-2R2MS_8A_20% 2 1

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
GND1 LX2
2

8 20
GND2 LX3
1

1
18 JUMP_43X79
B
21 GND3 PR608 PR607
B

PC618

PC619

PC620

PC621
GND4 14 +5VALW_OUT 1 2 +5VALW_P 4.7_0805_5%
+5VALW_EN OUT

2
12 0_0402_5% EMC_NS@
+5VALW_VIN 11 EN1 13 +5VALW_FB
EN2 FF Vout=5V± 3%
2

15
100mA +5VLP
LDO Vset=5.1V± 1.5%
1+5VALW_SN

@ 10
0.1U_0201_25V6-K

NC1
4.7U_0603_6.3V6K

+5VALW_VCC
1

16 17
OCP=12A
1M_0402_5%

NC2 VCC
1
PC625

PC624
1U_0603_25V6M
1

OVP=(1.15~1.25)*Vout
PR609

PC626

SY8288CRAC_QFN20_3X3
PC627
UVP=(0.55~0.65)*Vout
2

1000P_0402_50V9-J
2

EMC_NS@ Fsw=600Khz
2

PC628
PR610
1 2 +5VALW_FB_C 1 2

1K_0402_1%
1000P_0201_25V7K

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 PWR_3VALW/5VALW

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
320ABR 0.1

Date: Thursday, January 12, 2017 Sheet 45 of 50

5 4 3 2 1
 5 4 3 2 1

+5VALW LV5075_VCC

@
PR1903 1 2 10_0603_5% PR1901 1 2 0_0402_5%
EC_ON 35,45
PR1902 1 2 0_0402_5% LV5075_VDDQ_EN +5VLP
35 1_2VEN

LV5075_VTT_EN @
PR1904 1 2 0_0402_5% PR1907 1 2 10_0603_5% PR1905 1 2 0_0402_5%
35,37 SUSP# ALW_PWRGD 45

PR1906 1 2 0_0402_5% LV5075_1P0VA_EN

0.1U_0402_10V7K
2.2U_0603_6.3V6K
35 EC_APU_ALWEN

PC1902

PC1903
D D
LV5075_1P8VA_EN

1
PR1908 1 2 0_0402_5%

+1.2V_B+
2 10K_0402_5% LV507_0.775ALW_EN

2
PR1910 1 @

LV5075_PMIC_EN
PR1909 1 2 10_0402_5%
LV5075_2.5V_EN

LV5075_VSYS
PR1911 1 2 0_0402_5%

1 0.1U_0402_10V7K

1 0.1U_0402_10V7K

1 0.1U_0402_10V7K

1 0.1U_0402_10V7K

1 0.1U_0402_10V7K

1 0.1U_0402_10V7K

0.1U_0402_25V6
35 2_5VEN

PC1901
2
Vout=1.05V± 5% for ABR platform

28

27

41
PU1901

9
@ @ @ @ @ @ Vout=0.95V± 5% for AST platform

VSYS

PMIC_EN

GND
VCC
LV507_0.775ALW_EN LV5075_EC_SMB_DA2 OCP=8~10A

PC19042

PC19052

PC19062

PC19072

PC19082

PC19092
29 25 PR1925 1 2 0_0201_5%
EN_LDO1 SDA EC_SMB_DA2 35
LV5075_2.5V_EN 1 26 LV5075_EC_SMB_CK2 PR1926 1 2 0_0201_5%
OVP=(1.15~1.25)*Vout
EN_LDO2 SCL EC_SMB_CK2 35
+3VALW
LV5075_1P0VA_EN LV5075_ALERT# UVP=(0.55~0.65)*Vout
11
EN_V1P0A T_ALERT_B
24 PR1912 1 2 0_0402_5%
H_PROCHOT# 6,35 ABR:1.05V
LV5075_1P8VA_EN 16 22 APUALW_PWRGD @
AST:0.95V Fsw=1.2MHZ
EN_V1P8A POK_V1P0A
LV5075_VDDQ_EN 31 21 APUALW_PWRGD 4pcs 22uf for +/-5% tolerance
+5VALW LV5075_VTT_EN
EN_VDDQ POK_V1P8A
LV5075_VDDQ_PGOOD1
6pcs 22uf for +/-3% tolerance
36 23
EN_VTT POK_VDDQ
PTC701 @ Need change reference for BOM and standard +1.05VALW
100K_0402_5%

PAD
1

1.5A @
12 LV5075_LX_1P0 @ 6A
PR1915

PJ1901 PL1901 PJ1902

LV5075_V1P0_VIN LX_V1P0A_12 +1.05VS_P2
1 2 7 13 1 2 1
Vout=1.8V± 90mV

LV5075AGQV_VQFN40_5X5
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
1 2 8 VIN_V1P0A_7 LX_V1P0A_13 14 0.47UH_CMMB062D-R47MS_15A_20% 2 1

0.1U_0402_25V6
VIN_V1P0A_8 LX_V1P0A_14

1
EMC_NS@
15
OCP=4.8~6A

PC1910

PC1911

PC1912

PC1913

PC1914

PC1915

PC1916

PC1917
JUMP_43X39 JUMP_43X79
LX_V1P0A_15
2

APUALW_PWRGD 35 +3VALW 10 +1.8VALW OVP=(1.15~1.25)*Vout

VO_V1P0A

2
1.5A PJ1903
@
17 LV5075_LX_1P8 PL1902
@ @
PJ1904
@ 3A UVP=(0.55~0.65)*Vout
LV5075_V1P8_VIN LX_V1P8A_17 +1.8VA_P
1
1 2
2 19
VIN_V1P8A_19 LX_V1P8A_18
18 1 2 2
2 1
1
Fsw=1.2MHZ

EMC_NS@
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
1UH_PH041H-1R0MS_3.8A_20%

0.1U_0402_25V6
C C

1
20
2pcs 22uf for +/-5% tolerance

PC1918

PC1919

PC1920

PC1921

PC1922

PC1923
JUMP_43X39 JUMP_43X79
VO_V1P8A_20

LV5075_UG_1.2V
3pcs 22uf for +/-3% tolerance

2
33
38 UGATE_VDDQ
+1.2V_PWM VIN_VTT LV5075_BST_1.2V
PR1916
LV5075_BST_1.2V_R @ @
PC1924 1 2 10U_0603_6.3V6M 32 1 2
BOOT_VDDQ
1A PJ1905
Vout=0.6V± 30mV +0.6VS
2
2 1
1 +0.6VSP 39
VTT 34 LV5075_LX_1.2V
0_0603_5% PC1925
1 2

LV5075_LX_1P0

LV5075_LX_1P8
@ PHASE_VDDQ

1
Current Limit :Min 1.44A JUMP_43X39 PC1926 40 35 LV5075_LG_1.2V 0.1U_0603_25V7-M
VSNS_VTT LGATE_VDDQ
22U_0603_6.3V6-M
+1.2V_PWM LDO1 Vout=0.775V

2
PR1917 @ 37
+1.8VALW 1 2 LV5075_CS 30 VSNS_VDDQ
Current Limit :Min 1.5A
33K_0402_1% CS_VDDQ +0.775VALW
@ UVP=(0.55~0.65)*Vout

2
1A 1
PR1923
2 LV5075_0.775VALW_VIN 5 6 +0.775VALW_P 1
PJ1907
2
1A

10U_0603_6.3V6M
PR1918 PR1919
VIN_LDO1 LDO1 1 2 4.7_0603_5% 4.7_0603_5%
1

1
EMC_NS@ EMC_NS@

PC1928
0_0603_5%
+3VALW PC1927 JUMP_43X39
LDO2 Vout=2.5V

1P0_SN 1

1P8_SN 1
10U_0603_6.3V6M
2

2
+2.5V_P +2.5V FB reference=0.75V
1A PR1924
LV5075_2.5V_VIN LDO2
3
1 2 4
VIN_LDO2 2
Current Limit :Min 1.5A
@
FB_LDO2 V20B+
1

1
0_0603_5%
1
PJ1910
2
1A UVP=(0.55~0.65)*Vout PC1930
680P_0402_50V7K
PC1931
680P_0402_50V7K

10U_0603_6.3V6M
24.9K_0402_1%
PC1934

+2.5V_FB
1 2

1
10U_0603_6.3V6M EMC_NS@ EMC_NS@

PR1920
2

2
FB=0.75V JUMP_43X39 @ 1A

PC1935
PJ1908
+1.2V_B+ 1 2
1 2

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
2

EMC_NS@
JUMP_43X39

1
PC1929

PC1932

PC1933
1

10.5K_0402_1%

2
PR1921
@

5
B PQ1901 B

D
2
AON7408L_DFN8-5

LV5075_UG_1.2V 4
G
+1.2V

S3
S2
S1
@ 6A

3
2
1
PL1903 PJ1911
LV5075_LX_1.2V 1 2 +1.2V_PWM 2 1
0.47UH_CMMB062D-R47MS_15A_20% 2 1
JUMP_43X79

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
5
PR1922

1
PC1937

PC1938

PC1939

PC1940

PC1941

PC1942
PQ1902 4.7_0805_5%
AON7506_DFN EMC_NS@

2
LV5075_LG_1.2V 4 @ @

1.2V_SN
3
2
1

1
PC1943
680P_0402_50V7K
Vout=1.2V± 60mV
EMC_NS@ OCP=9A

2
OVP=(1.15~1.25)*Vout
UVP=(0.55~0.65)*Vout
Fsw=1MHZ
4pcs 22uf for +/-5% tolerance
6pcs 22uf for +/-3% tolerance

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/02/20 Deciphered Date 2014/02/20 System PMIC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
A2
320ABR 0.1

Date: Thursday, January 12, 2017 Sheet 46 of 50

5 4 3 2 1
 A B C D

1 1

V20B+
@
2A 2
PJ1401
1 +1.35VGS_VIN
2 1

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
PU1401
+1.35VGS

1
JUMP_43X79 PX@ PR1401 PX@ PC1404 PX@

PC1401

PC1402

PC1403
0_0603_5% 0.1U_0603_25V7-M
1 10 +1.35V_BST
1 2+1.35V_BST_R 1 2 PL1401 PX@ @
2 VIN BST

2
PR1451 PX@
100K_0402_1% 9 +1.35V_LX
0.47UH_PCMB053T-R47MS_13A_20%
1 2 +1.35V_P 8A 2
PJ1402
1
@ PX@ PX@ 2 1+1.35VGS_S3 16 SW 2 1

NB685GQ-Z_QFN16_3X3
EN1

1
JUMP_43X79

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
EN_1.35VGS +1.35V_FB

1
15 13 @
EN2 FB

1
PR1402 PR1404 PC1405
2.2_0805_5% 1M_0402_5% 220P_0402_50V7K

PC1406

PC1407

PC1408

PC1409

PC1410
PR1405 PX@ 12 6 +1.35V_P EMC_NS@ @ @
PG VDDQ

2
4.7_0402_5%

+1.35V_SN

2
1 2 +1.35VGS_3V3 3
+3VALW 3V3 MPS_VTT

2
5
VTT +1.35V_COMP PX@ PX@ PX@ PX@ PX@

1
PC1411 4 PC1412 PR1407
1U_0402_6.3V6K AGND 8 1200P_0402_50V7-K 41.2K_0402_1%
VTTS

1
PX@ 2 EMC_NS@
2 PGND

1
7 MPS_VTTREF PR1406
VTTREF 499_0402_1%

22U_0603_6.3V6-M
+1.35V_Mode
14 11 @ @

1U_0402_6.3V6K
2
MODE OTW# 2

2
1

1
Vout=1.35V± 5%

PC1415

PC1413
1.35V_GND 2
Vset=1.35V± 2%

2
PR1410 PX@
0_0402_5% PX@
OCP=13A

1
PR1408 PX@
1

7,19,48 PXS_PW REN

200K_0402_1%
1 2 EN_1.35VGS
1.35V_GND PX@
PR1411
Vref=0.6V
1.35V_GND
PJ1404 @
32.4K_0402_1%
OVP=(1.25~1.35)*Vref
1M_0402_5%

.1U_0402_10V6-K

2
2

1 2
UVP=(0.7~0.8)*Vref
1
PR1412

PC1416

JUMPER
Fsw=700Khz(Rmode=0)
2

1.35V_GND 1.35V_GND
Fsw=500Khz(Rmode=150K)
1

PX@ PX@

3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 1.35VGS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
A3 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 320ABR
Date: Thursday, January 12, 2017 Sheet 47 of 50
A B C D
 5 4 3 2 1

+VGA_B+ PJ2401 @ V20B+

JUMP_43X79

2 1
5A
2 1

+5VALW +VDDIO_GPU
EMC_PX@ PX@ PX@

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
PR2402 PX@

1
PX@ VGA_VCC VGA_VDDIO
4.7_0402_5%
1 2 2 1

PC2402

PC2403
2

2
PX@

PC2401
PR2401

AON6380_DFN8-5
1 1
For 196K resistor shortage, 4.7_0603_5%
PC2404
PC2405 PX@
2.2U_0402_6.3V6-K
D D
change PR2408 to 100K,

PQ2401
2.2U_0402_6.3V6-K
change PR2410 to 95.3K for SDV SMT. 2 2 +VGA_B+ VGA_UGATE1 4
14 19
VCC VDDIO VGA_VIN 2 1
PX@ PX@ PX@ VGA_PVCC
PR2405 PR2406 1 2 PR2404 PX@

1
0_0402_5% 11.3K_0402_1% PX@ 4.7_0402_5% PX@ PL2401
2VGA_SET1_11

3
2
1
1 2 PR2403 1
27 1
PC2408
VGA_PHASE1
0.22UH_CMMS063T-R22MS2R107_26A_20%
1 2
21A
0_0603_5% PX@ 1U_0402_25V6-K
PVCC VIN +VGA_CORE

2
PC2407 PX@

1
EMC_PXNS@
PX@ 2
2.2U_0402_6.3V6-K

1
4.7_0805_5%
PR2408 PX@ PR2410 PR2433

330U_D2_2V_Y
21

PR2412

330U_2.0V_M
196K_0402_1% 0_0402_5% 0_0402_5%

AON6324_DFN8-5

AON6324_DFN8-5

330U_D2_2V_Y
VSEN 1 1 1
1 VGA_SET1_2 VGA_SET1 11

1
2 2 1 PX@
SET1 + + +
PX@

PC2413

PC2406

PC2410
100P_0402_50V8J 150P_0402_50V8-J PR2434

1VGA_ISEN1P_R2
PX@ PC2411 2 1 2 1 PC2412

PQ2403

PQ2402
PU2401 0_0402_5%
VGA_LGATE1

VGA_SN2
PR2409 PX@ PR2413 PX@ PH2401 PX@ RT3662EBGQW_WQFN32_4X4 PX@ 4 4 PX@ 2 2 2
69.8K_0402_1% 0_0402_5% 100K_0402_1%_TSM0B104F4251RZ PX@
1 VGA_TSEN_2 2 1 VGA_TSEN_1 VGA_COMP

2
2 2 1 3 2 PR2414 1 2 1 PX@ @ PX@
COMP
VGA_FB
30K_0402_1% PX@

2
4

680P_0402_50V7K
PR2415 PC2416 PX@ PX@ PX@
VGA_TSEN 10 FB

3
2
1

3
2
1

EMC_PXNS@
10K_0402_1% 100P_0201_25V8J
TSEN 2

PC2417
PR2417 PX@ PR2418 PX@ PR2419 PX@
RGND

1
1
0_0402_5% 32.4K_0402_1% 60.4K_0402_1% PR2407
2 VGA_TSEN_3 1

2
1 2 2 1 PC2419 1.43K_0402_1%
PX@ 0.1U_0402_25V6 PX@ PC2414 PX@

2
PR2411 @ 0.47U_0402_25V6K

0.1U_0402_25V6
2
22 2.2_0603_5% 2 1 2 1
VGA_VREF 13 NC 23 VGA_BOOT1 1 2
VREF_PINSET BOOT1 @

2
PR2416 PX@

PC2415
PC2418
VGA_UGATE1
1

24
PR2420 PH2402 PX@ PX@ PX@
UGATE1
VGA_PHASE1 1
0.1U_0402_25V6
Close to PU2401 VGA_ISEN1P
357_0402_1%
2 1
2VGA_BOOT1_R

1
3.9_0402_1% 100K_0402_1%_TSM0B104F4251RZ PR2422 PR2423 25
PHASE1
PX@ 12.1K_0402_1% 7.87K_0402_1% PX@
1 2VGA_IMON_2 1 2 2 1 VGA_IMON 12 26 VGA_LGATE1 PC2409 PX@ PX@
1VRFF_R_1

IMON LGATE1
2

C 0.22U_0603_25V7K PR2436 C
PR2425 PX@ 0_0201_5% VGA_ISEN1N
14.3K_0402_1% VGA_CORE_SEN_L 1 2
1 2 VGA_IMON_1 VGA_CORE_SEN 16
7 VGA_ISEN1P
PC2420 ISEN1P
8 VGA_ISEN1N
0.47U_0402_25V6K
ISEN1N PX@
2

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
PX@ PR2437
9 0_0402_5% @ @ @ @ PX@ PX@ PX@ PX@
16,35 GPU_VR_HOT# VRHOT_L VGA_VSS_SEN_L 1 2

1
15 VGA_VSS_SEN 16
15 VGA_PWROK PWROK
PX@

PC2423

PC2424
PR2438
1 2 VGA_PGOOD 20 31

PC2421

PC2422

PC2425

PC2426

PC2427

PC2428
PGOOD BOOT2

2
7,15 VR_VGA_PWRGD 0_0201_5%

30
PR2426 PX@ UGATE2
0_0402_5% +3VGS
1 2 VGA_SVC 16 29
16 GPU_SVC SVC PHASE2
PR2427 PX@ +VDDIO_GPU
0_0402_5% 28
1 2 VGA_SVD 17 LGATE2
16 GPU_SVD SVD
PR2428 PX@
1 2 VGA_SVT 18 VGA_CORE
16 GPU_SVT SVT
0_0402_5%

2
7,19,47 PXS_PWREN
2 1 VGA_EN 32
EN ISEN2P
5 VGA_VCC
PX@ PX@ PX@ Vboot=0.9V（CL K=1, DAT=0)
PR2429 PX@
PR2430
10K_0402_5%
PR2432
10K_0402_5%
PR2431
10K_0402_5% Loadline=1.0mohm
Ripple SEPC: DC=+-15mV AC=+50mV -30mV
2

200K_0402_1% PX@ 33
GND

VR_VGA_PWRGD1

1
6
PC2429 ISEN2N TDC :21A

GPU_VR_HOT#
1

1 2
EDC=42A

VGA_PWROK
.1U_0402_10V6-K
B B
PD2401 @ OCP :50A(TBD)
RB751V-40_SOD323-2
OVP:1.8V
UVP:VID-500mV
FSW:400KH
CHOKE DCR=2.1+-7% mohm

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2016/01/20 Deciphered Date 2016/01/20 PWR-XXXX
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Size Document Number
Custom 320ABR Rev
0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, January 12, 2017 Sheet 48 of 50
5 4 3 2 1
 5 4 3 2 1

V20B+
PR2269
4.7_0603_5%
1 2

1
PC2290
.1U_0402_10V6-K

+1.8VS

2
PR2225
2.2_0603_5%
1 2
1
+5VALW PC2289 Close to APU
1U_0402_10V6K
PR2226 2
4.7_0603_5% PR2253
APU_VREF_PINSET 1 2 Close to PU2201 100_0402_1%
1 2 +APU_CORE

1
PC2226
1U_0603_6.3V7-K PU2201 PR2290 PR2254
0_0402_5% 0_0402_5%
APU_CORE_VSEN

2
PC2239 1 2 47P_0402_50V8J PC2238 1 2 150P_0402_50V8-J 1 2 1 2 APU_VDDCORE_SEN_H 6
APU_VCC APU_VIN
PR2224 17 28

330P_0402_50V8J
0_0402_5% VCC VIN

316K_0402_1%
34.8K_0402_1%

69.8K_0402_1%
1

1
D 1 2 PR2250 1 2 63.4K_0402_1% PR2249 1 2 10K_0402_1% PR2256 D

PC2255
22 APU_VDDIO_R
100_0402_1%
PR2271

PR2272

PR2273 VDDIO

1
PC2227 1 2
APU_PVCC +APU_CORE

2
1U_0603_6.3V7-K 34
PVCC APU_CORE_VSEN_R
VSEN
8 @ PR2202 PR2255 FSW=400KHz
2

2
0_0402_5% 0_0402_5%
APU_CORE_RGND TDC=22A

1
PC2292 1 2 1 2
APU_VDD_SEN_L 6
APU_SET1 13
0.1U_0402_25V6
@
EDC=35A
SET1 APU_CORE_COMP
OCP:45A

2
PR2232 5
60.4K_0402_1% COMP
1 2 6 APU_CORE_FB OVP=1.85V
FB
APU_TSEN_CORE_R
1
PH2203
2 APU_TSEN_CORE
12 V20B+ UVP=VID-500mV
TSEN 4 APU_CORE_RGND_R APU_CORE_VIN PJ2202 @ Load Line=2.1mohm
RGND
100K_0402_1%_TSM0B104F4251RZ JUMP_43X79
2 1
4A Ripple:+/-20mv
2 1
PR2218 1 MAX AC: VID_APU_CORE +70mv

10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6
APU_CORE_BOOT1
2CORE_BOOT_R

EMC_NS@
60.4K_0402_1% 38 1 1 2 PQ2203

68U_25V_M
APU_TSEN_NB_R APU_TSEN_NB BOOT MIN AC: VID_APU_CORE -20mv

1
1 2 23 AON6982_DFN8-7 +
+APU_CORE

PC2229

PC2230

PC2232

PC2231
TSEN_NB PR2237 PC2233 AON6982_DFN8-7
APU_VREF_PINSET 1 2 PH2202 2.2_0603_5% 0.1U_0603_25V7-M PQ2204
Choke DCR=0.98+-5%mohm

2
2
1

2
100K_0402_1%_TSM0B104F4251RZ
15K_0402_1%

33K_0402_1%

24K_0402_1%

37 APU_CORE_UGATE1 1 1
PR2201
PR2270

PR2235

PR2219

0_0402_5% UGATE
APU_VREF_PINSET_R
1 2 15 PL2202
VREF_PINSET
APU_IMON_CORE_R APU_CORE_PHASE1 7APU_CORE_PHASE1 APU_CORE_PHASE1
0.22UH_PCME064T-R22MS0R985_28A_20%
22A
2

PR2275 1 2 14K_0402_1% 36 7 1 2
PR2287 PR2231 PHASE

1
3.9_0402_1% PH2205 7.15K_0402_1% 6 6 PR2284

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
APU_IMON_CORE_NTC APU_IMON_CORE
1 2 1 2 1 2 14 PR2283 0_0402_5% 1 1@ 1

330U_2.0V_M
330U_D2_2V_Y

330U_D2_2V_Y
IMON 35 APU_CORE_LGATE1 PR2268
PR2276 12.4K_0402_1%

PC2251
LGATE 4.7_0805_5% 0_0402_5%
2

1
100K_0402_1%_TSM0B104F4251RZ PR2242 PC2244 + + +

PC2249

PC2250

PC2253

PC2276

PC2277
PR2227 EMC_NS@ APU_CORE_ISEN+
1.24K_0402_1% 0.47U_0402_25V6K

3
4
5

3
4
5

2
1

5.6K_0402_1% 1 2 1 2
APU_IMON_NB_R APU_IMON_NB

2
PC2286 PR2277 1 2 13.3K_0402_1% 1 2 16 2 2 2
IMON_NB APU_CORE_ISEN1P

CORE_SN
0.47U_0402_25V6K 9 PR2243
ISEN1P
2

1.24K_0402_1%
1 2 APU_IMON_NB_NTC 1 2 APU_CORE_ISEN1P 1 2
PH2206
10 APU_CORE_ISEN1N
PR2278 13.3K_0402_1% 100K_0402_1%_TSM0B104F4251RZ
+3VS ISEN1N
Close to PU2201

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
APU_VR_HOT_L

1
1 2 11 PC2234
VRHOT_L APU_CORE_ISEN1N
1

35,44,50 VR_HOT# PR2222 0_0402_5% PC2237 680P_0402_50V7K

1
PR2233 PR2289

PC2278

PC2279

PC2280

PC2281

PC2282

PC2283

PC2284

PC2285
APU_PWROK_R 0.1U_0402_25V6 EMC_NS@

2
1.91K_0402_1% 1 2 18 0_0402_5%
6,50 APU_PWROK PWROK APU_NB_VSEN_R
PR2230 0_0402_5% 7 1 2
VSEN_NB

2
VR_APU_PGOOD_R
2

1
1 2 3
35 VR_APU_PWRGD PR2234 0_0402_5% PGOOD PC2291 PC2205 Close to APU
0.1U_0402_25V6 150P_0402_50V8-J

2
@ PC2206 1 2 47P_0402_50V8J 1 2 PR2204
100_0402_1%
APU_SVC_R APU_NB_COMP APU_NB_VSEN
1 2 19 27 PR2206 1 2 60.4K_0402_1% PR2205 1 2 10K_0402_1% 1 2 +APU_CORE_NB
6 APU_SVC SVC COMP_NB
PR2220 0_0402_5%
PR2208
APU_SVD_R APU_NB_FB
1 2 20 26 0_0402_5%
6 APU_SVD SVD FB_NB 1 2
PR2223 0_0402_5% APU_VDDNB_SEN_H 6
C 1 2 APU_SVT_R 21 C
PR2211 PC2211
6 APU_SVT SVT
PR2228 0_0402_5% 2.2_0603_5% 0.1U_0603_25V7-M
APU_NB_BOOT BOOT_NB_R
30 1 2 1 2
BOOT_NB +APU_CORE_NB
APU_CORE_NB_VIN V20B+ FSW=400KHz
@
35 EC_VR_ON
1 2 APU_EN_R 29
EN APU_NB_UGATE
PJ2201
2A TDC=12A
PR2229 0_0402_5%
UGATE_NB
31 2
2 1
1
EDC=17A

10U_0805_25V6K

10U_0805_25V6K
OCP:25A

EMC_NS@
JUMP_43X79

0.1U_0402_25V6
1

PC2209
PC2207

PC2208
OVP=1.85V
1M_0402_5%

1 PQ2201
+APU_CORE_NB
PR2288

NC1 APU_NB_PHASE
UVP=VID-500mA

2
32
PHASE_NB

2
1
2
NC2
Load Line=4mohm
2

0.36UH_PCMB063T-R36MS_20A_20%
Ripple:+/-20mv
39 33 APU_NB_LGATE
7 APU_NB_PHASE
PL2201
1 2
12A MAX AC: VID_APU_CORE_NB +70mv
NC3 LGATE_NB
MIN AC: VID_APU_CORE_NB -40mv

1
6
40 PR2214 PR2215
NC4 APU_NB_ISENP PR2212
25 0_0402_5% 0_0402_5%
ISENP_NB 4.7_0805_5%
PR2280 PC2287 1 1 Choke DCR=3.3(typ)~3.9(max)mohm

330U_2.0V_M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
330U_D2_2V_Y
AON6982_DFN8-7 EMC_NS@ 1K_0402_1% 0.47U_0402_25V6K @ @
APU_NB_ISENN APU_NB_ISEN+

3
4
5

1
41 24 1 2 1 2 + +

PC2214

PC2215
GND ISENN_NB

PC2270

PC2271

PC2272

PC2273

PC2274

PC2275
1NB_SN

2
2 2

1
RT3661ABGQW_WQFN40_5X5
PC2288
0.1U_0402_25V6 PC2222

2
680P_0402_50V7K
EMC_NS@

2
PR2281
430_0402_1%
1 2

+1.8VS
Close to SVID pull high net
PRE-PWROK METAL VID CODES +1.8VS

SVC SVD Boot Voltage +1.8VS

@ @ @
1

0 0 1.1V
1K_0402_1%

1K_0402_1%

1K_0402_1%
PR2262

PR2263

PR2264

0 1 1.0V
1 0 0.9V(Default)
2

@ @
1U_0402_6.3V6K
.1U_0402_10V6-K

B PR2285 B
1 1 0.8V
1

1.91K_0402_1%
PC2268

PC2269

APU_SVC_R

APU_SVD_R @
2

APU_SVT_R
APU_VR_HOT_L

@ @ @
1

1
220_0402_5%

220_0402_5%

220_0402_5%
PR2265

PR2266

PR2267
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 PWR_CPU Core
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
A1 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 320ABR
Date : Thursday, January 12, 2017 Sheet 49 of 50

5 4 3 2 1
 5 4 3 2 1

+5VALW V20B+
GFX_VIN V20B+

@
PR3901 PR3902

1
4.7_0603_5%
2 1
4.7_0603_5%
2 2
PJ3901
1
4A
PU3901 2 1

10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6
EMC_NS@
1
PC3903 JUMP_43X79

1
GFX_VREF_PINSET PC3902 .1U_0402_10V6-K

PC3904

PC3905

PC3906
GFX_VCC 13
1U_0603_6.3V7-K
VCC

2
PQ3901 PQ3902
GFX_VIN_IC

2
1 AON6982_DFN8-7 AON6982_DFN8-7
VIN

2
PR3903
0_0402_5%
GFX_PVCC
1 1 +APU_GFX
1 2 28
PVCC PR3906

34.8K_0402_1%

69.8K_0402_1%
1

1
PC3901 2.2_0603_5%
GFX_BOOT1 GFX_BOOT_R GFX_PHASE1
1U_0603_6.3V7-K 25 1 2 7 7
+APU_GFX

PR3904

PR3905
BOOT PL3901
FSW=400KHz

2
6 6
26 GFX_UGATE1
0.22UH_PCME064T-R22MS0R985_28A_20%
1 2
22A
TDC=22A

22U_0603_6.3V6-M
UGATE
2

2
1 1 1

330U_2.0V_M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
330U_D2_2V_Y

330U_D2_2V_Y
GFX_PHASE1

1
D 27 1 2
EDC=35A D

PC3908 @

PC3913 @
PC3909
PHASE

1
+ + +

PC3907

PC3910

PC3911
PR3907
OCP:45A

3
4
5

3
4
5
PC3912 PR3908 PR3909
GFX_SET1 4.7_0805_5%
10 0.1U_0603_25V7-M 0_0402_5%
SET1 0_0402_5%
OVP=1.85V

2
EMC_NS@ 2 2 2

2
PR3911
GFX_SN UVP=VID-500mA

2
60.4K_0402_1% PR3910 PC3915
Load Line=2.1mohm

1
1 2 PC3914 1.24K_0402_1% 0.47U_0402_25V6K
29 GFX_LGATE1 APU_GFX_ISEN+ 1 2 1 2
680P_0402_50V7K
Ripple:+/-20mv

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
APU_GFX_NTC_R APU_GFX_NTC LGATE
1 2 9

PC3916 @
TSEN EMC_NS@
MAX AC: VID_APU_CORE +70mv

1
PH3901 PR3912

PC3917

PC3918

PC3919

PC3920

PC3921

PC3922

PC3923
100K_0402_1%_TSM0B104F4251RZ
APU_GFX_ISEN1P
1.24K_0402_1% MIN AC: VID_APU_CORE -20mv
1

6 1 2
15K_0402_1%

33K_0402_1%

ISEN1P

2
PR3916 30
PR3913

PR3914

0_0402_5%
APU_GFX_EN_R
NC
ISEN1N
7 APU_GFX_ISEN1N
Choke DCR=0.98+-5%mohm
1 2
35 EC_GFX_ON

1
2

1
PC3924

1M_0402_5%
PR3945
0.1U_0402_25V6

2
32
EN
Close to PU3901 Close to APU

2
+1.8VS PR3917 PC3925 PC3926 PR3946 PR3918
2.2_0603_5% 47P_0402_50V8J 150P_0402_50V8-J 0_0402_5% 100_0402_1%
1 2 GFX_VDDIO_R 3 APU_GFX_COMP 1 2 1 2 1 2 APU_GFX_VSEN 1 2
COMP +APU_GFX

1
PR3919 PR3920 PR3921
PC3927 18 63.4K_0402_1% 10K_0402_1% 0_0402_5%
VDDIO 1 2 1 2 1 2
1U_0603_6.3V7-K APU_VDDGFX_SEN_H 6

2
APU_GFX_FB
PR3922 4
FB

1
0_0402_5%
APU_GFX_PWROK_R

1
1 2 14 PC3929 @ PC3928
6,49 APU_PWROK PWROK
+3VS 680P_0402_50V7K 330P_0402_50V8J

@
2
PR3924
APU_GFX_SVC_R APU_GFX_VSEN_R
PR3923 1 2 0_0402_5% 15 5 0_0402_5%
6 APU_GFX_SVC SVC VSEN 1 2
APU_GFX_SVD_R
1

PR3926 1 2 0_0402_5% 16 APU_VDDGFX_SEN_L 6

6 APU_GFX_SVD SVD
PR3925 PR3928
APU_GFX_SVT_R
1.91K_0402_1% PR3927 1 2 0_0402_5% 17 0_0402_5%
6 APU_GFX_SVT SVT APU_GFX_RGND_R APU_GFX_RGND
2 1 2 1 2
RGND
APU_GFX_PGOOD PR3929
2

PR3930 1 2 0_0402_5% 31 33 100_0402_1%

7,35 VR_GFX_PWRGD PGOOD GND

GFX_VR_HOT_L
PR3931 1 2 0_0402_5% 8
35,44,49 VR_HOT# VRHOT_L 24
GFX_VREF_PINSET
PR3932 LDO_VIN
14K_0402_1%
APU_GFX_IMON_R
1 2 PR3933
7.15K_0402_1%
1 2 APU_GFX_IMON 11 21
PR3934
12.4K_0402_1% PH3902 IMON LDO_OUT
1 2 APU_GFX_IMON_NTC 1 2

C 100K_0402_1%_TSM0B104F4251RZ C
22
FBA
GFX_VREF_PINSET

PR3935 23
0_0402_5% MUX_CTRL
1 2 GFX_VREF_PINSET_R 12
VREF_PINSET 20
S5_OUT
1

PR3936
3.9_0402_1% 19
VSEN_NB_IN
2

RT3669EAGQW_WQFN32_4X4
1

PC3930
0.47U_0402_25V6K
2

+1.8VS

+1.8VS
Close to SVID pull high net
PR3937 @

PR3938 @

PR3939 @
1

1
1K_0402_1%

1K_0402_1%

1K_0402_1%

PRE-PWROK METAL VID CODES

+1.8VS
2

SVC SVD Boot Voltage PR3940

1.91K_0402_1%
0 0 1.1V APU_GFX_SVC_R
PC3931 @

PC3932 @

@
1U_0402_6.3V6K
.1U_0402_10V6-K

0 1 1.0V APU_GFX_SVD_R
2
1

1 0 0.9V(Default) APU_GFX_SVT_R
GFX_VR_HOT_L
2

1 1 0.8V
PR3942 @

PR3943 @

PR3944 @
1

1
220_0402_5%

220_0402_5%

220_0402_5%
2

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 PWR_CPU Core
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
A1 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 320ABR
Date : Thursday, January 12, 2017 Sheet 50 of 50

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