5 4 3 2 1

D D

U1A

PCIE_REFCLKP PCIE_RXP0 AA38 Y33 PCIE_TXP0

(8) PCIE_REFCLKP PCIE_RX0P PCIE_TX0P
PCIE_REFCLKN PCIE_RXN0 Y37 Y32 PCIE_TXN0
(8) PCIE_REFCLKN PCIE_RX0N PCIE_TX0N

PCIE_RXP1 Y35 W33 PCIE_TXP1

PCIE_RXP[15..0] PCIE_RXN1 W36 PCIE_RX1P PCIE_TX1P W32 PCIE_TXN1
(8) PCIE_RXP[15..0] PCIE_RX1N PCIE_TX1N
PCIE_RXN[15..0]
(8) PCIE_RXN[15..0]
PCIE_RXP2 W38 U33 PCIE_TXP2
PCIE_TXP[15..0] PCIE_RXN2 V37 PCIE_RX2P PCIE_TX2P U32 PCIE_TXN2
(8) PCIE_TXP[15..0] PCIE_RX2N PCIE_TX2N
PCIE_TXN[15..0]
(8) PCIE_TXN[15..0]
C PCIE_RXP3 V35 U30 PCIE_TXP3 C
PCIE_RXN3 U36 PCIE_RX3P PCIE_TX3P U29 PCIE_TXN3
PCIE_RX3N PCIE_TX3N

PCIE_RXP4 U38 T33 PCIE_TXP4

PCIE_RXN4 T37 PCIE_RX4P PCIE_TX4P T32 PCIE_TXN4
PCIE_RX4N PCIE_TX4N

PCI EXPRESS INTERFACE

PCIE_RXP5 T35 T30 PCIE_TXP5
PCIE_RXN5 R36 PCIE_RX5P PCIE_TX5P T29 PCIE_TXN5
PCIE_RX5N PCIE_TX5N

PCIE_RXP6 R38 P33 PCIE_TXP6

PCIE_RXN6 P37 PCIE_RX6P PCIE_TX6P P32 PCIE_TXN6
PCIE_RX6N PCIE_TX6N

PCIE_RXP7 P35 P30 PCIE_TXP7

PCIE_RXN7 N36 PCIE_RX7P PCIE_TX7P P29 PCIE_TXN7
PCIE_RX7N PCIE_TX7N

PCIE_RXP8 N38 N33 PCIE_TXP8

PCIE_RXN8 M37 PCIE_RX8P PCIE_TX8P N32 PCIE_TXN8
PCIE_RX8N PCIE_TX8N

PCIE_RXP9 M35 N30 PCIE_TXP9

PCIE_RXN9 L36 PCIE_RX9P PCIE_TX9P N29 PCIE_TXN9
PCIE_RX9N PCIE_TX9N

PCIE_RXP10 L38 L33 PCIE_TXP10

PCIE_RXN10 K37 PCIE_RX10P PCIE_TX10P L32 PCIE_TXN10
PCIE_RX10N PCIE_TX10N

PCIE_RXP11 K35 L30 PCIE_TXP11

PCIE_RXN11 J36 PCIE_RX11P PCIE_TX11P L29 PCIE_TXN11
PCIE_RX11N PCIE_TX11N

PCIE_RXP12 J38 K33 PCIE_TXP12

PCIE_RXN12 H37 PCIE_RX12P PCIE_TX12P K32 PCIE_TXN12
B PCIE_RX12N PCIE_TX12N B

PCIE_RXP13 H35 J33 PCIE_TXP13

PCIE_RXN13 G36 PCIE_RX13P PCIE_TX13P J32 PCIE_TXN13
PCIE_RX13N PCIE_TX13N

PCIE_RXP14 G38 K30 PCIE_TXP14

PCIE_RXN14 F37 PCIE_RX14P PCIE_TX14P K29 PCIE_TXN14
PCIE_RX14N PCIE_TX14N

PCIE_RXP15 F35 H33 PCIE_TXP15

PCIE_RXN15 E37 PCIE_RX15P PCIE_TX15P H32 PCIE_TXN15
PCIE_RX15N PCIE_TX15N

CLOCK
+1.8V_REG PCIE_REFCLKP AB35
PCIE_REFCLKN AA36 PCIE_REFCLKP
PCIE_REFCLKN

R6218 CALIBRATION
10K AJ21 Y30 R1009
DNI AK21 NC#1 PCIE_CALRP 1.27K +1.0V_REG
AH16 NC#2 Y29 R1010
PWRGOOD PCIE_CALRN 2.0K

C1401 R7111 PCIE_RST# AA30

(8,10) PCIE_RST# PERSTB
10nF 1K
DNI

Broadway

A A

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

© 2007 Advanced Micro Devices Advanced Micro Devices Inc.
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement 1 Commerce Valley Drive East
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose Markham, Ontario
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,
Date: Friday, December 11, 2009 Rev
3
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting Sheet 1 of 17
from use of the information included herein.
Title Doc No.
MADISON GDDR3 MxM3.0 105-B985xx-00D
5 4 3 2 1
 5 4 3 2 1

U1B
U1G R6216 10K

R6217 10K
AU24 TXCAP_DPA3P (8)
TXCAP_DPA3P AV23 LVDS CONTROL AK27
TXCAM_DPA3N TXCAM_DPA3N (8) VARY_BL BLON_PWM (8)
AJ27
DIGON FPVCC (4,8)
AT25 TX0P_DPA2P (8)
MUTI GFX TX0P_DPA2P AR24
TX0M_DPA2N TX0M_DPA2N (8)
DPA
AU26 TX1P_DPA1P (8)
TX1P_DPA1P AV25 AK35
TX1M_DPA1N TX1M_DPA1N (8) TXCLK_UP_DPF3P TXCLK_U+ (8)
AL36
TXCLK_UN_DPF3N TXCLK_U- (8)
AR8 AT27 TX2P_DPA0P (8)
AU8 DVPCNTL_MVP_0 TX2P_DPA0P AR26 AJ38
DVPCNTL_MVP_1 TX2M_DPA0N TX2M_DPA0N (8) TXOUT_U0P_DPF2P TXOUT_U0+ (8)
AP8 AK37
DVPCNTL_0 TXOUT_U0N_DPF2N TXOUT_U0- (8)
AW8 AR30 TXCBP_DPB3P (8)
AR3 DVPCNTL_1 TXCBP_DPB3P AT29 AH35
D DVPCNTL_2 TXCBM_DPB3N TXCBM_DPB3N (8) TXOUT_U1P_DPF1P TXOUT_U1+ (8) D
AR1 AJ36
DVPCLK TXOUT_U1N_DPF1N TXOUT_U1- (8)
AU1 AV31 TX3P_DPB2P (8)
AU3 DVPDATA_0 TX3P_DPB2P AU30 AG38
DVPDATA_1 TX3M_DPB2N TX3M_DPB2N (8) TXOUT_U2P_DPF0P TXOUT_U2+ (8)
AW3 DPB AH37
DVPDATA_2 TXOUT_U2N_DPF0N TXOUT_U2- (8)
AP6 AR32 TX4P_DPB1P (8)
AW5 DVPDATA_3 TX4P_DPB1P AT31 AF35
DVPDATA_4 TX4M_DPB1N TX4M_DPB1N (8) TXOUT_U3P TXOUT_U3+ (8)
AU5 AG36
DVPDATA_5 TXOUT_U3N TXOUT_U3- (8)
AR6 AT33 TX5P_DPB0P (8)
AW6 DVPDATA_6 TX5P_DPB0P AU32
DVPDATA_7 TX5M_DPB0N TX5M_DPB0N (8)
AU6 LVTMDP
AT7 DVPDATA_8 AU14
AV7 DVPDATA_9 TXCCP_DPC3P AV13 AP34
DVPDATA_10 TXCCM_DPC3N TXCLK_LP_DPE3P TXCLK_L+ (8)
+1.8V_REG AN7 AR34
DVPDATA_11 TXCLK_LN_DPE3N TXCLK_L- (8)
AV9 AT15
AT9 DVPDATA_12 TX0P_DPC2P AR14 AW37
DVPDATA_13 TX0M_DPC2N TXOUT_L0P_DPE2P TXOUT_L0+ (8)
AR10 AU35
DVPDATA_14 TXOUT_L0N_DPE2N TXOUT_L0- (8)
AW10 DPC AU16
R6208 R6209 R6087 R6088 AU10 DVPDATA_15 TX1P_DPC1P AV15 AR37
DVPDATA_16 TX1M_DPC1N TXOUT_L1P_DPE1P TXOUT_L1+ (8)
10K 10K 10K 10K AP10 AU39
DVPDATA_17 TXOUT_L1N_DPE1N TXOUT_L1- (8)
AV11 AT17
AT11 DVPDATA_18 TX2P_DPC0P AR16 AP35
DVPDATA_19 TX2M_DPC0N TXOUT_L2P_DPE0P TXOUT_L2+ (8)
MEM_ID0 AR12 AR35
DVPDATA_20 TXOUT_L2N_DPE0N TXOUT_L2- (8)
MEM_ID1 AW12 AU20
MEM_ID2 AU12 DVPDATA_21 TXCDP_DPD3P AT19 AN36
DVPDATA_22 TXCDM_DPD3N TXOUT_L3P TXOUT_L3+ (8)
MEM_ID3 AP12 AP37
DVPDATA_23 TXOUT_L3N TXOUT_L3- (8)
AT21
DVPDATA[23:20] = 0x0 for Hynix H5RS1H23MFR-N0C +VDDR3 TX3P_DPD2P AR20
DVPDATA[23:20] = 0x1 for Samsung K4J10324KE-HC1A TX3M_DPD2N
DPD AU22
TX4P_DPD1P AV21
R54 R5624 TX4M_DPD1N Broadway
4.7K 4.7K I2C AT23
DNI DNI TX5P_DPD0P AR22
TP19 35mil AK26 TX5M_DPD0N
TP20 35mil AJ26 SCL
SDA
AD39
GENERAL PURPOSE I/O R AD37
C C
GPIO0 AH20 RB
(8,9) GPIO0 GPIO_0
GPIO1 AH18 AE36
(8,9) GPIO1 GPIO_1 G
GPIO2 AN16 AD35
(9) GPIO2 GPIO_2 GB
GPIO3_SMBDAT AH23
(8) GPIO3_SMBDATA GPIO_3_SMBDATA
GPIO4_SMBCLK AJ23 AF37
(8) GPIO4_SMBCLK GPIO_4_SMBCLK B
GPIO5_AC_BATT AH17 AE38
(8) GPIO5_AC_BATT GPIO_5_AC_BATT DAC1 BB
R6215 10K GPIO6 AJ17
(10) GPIO6 GPIO_6
GPIO7_BLON AK17 AC36 HSYNC_DAC1 (9)
(8) GPIO7_BLON GPIO_7_BLON HSYNC
GPIO8 RP1C 3 6 33R GPIO8_ROMSO AJ13 AC38 VSYNC_DAC1 (9)
(9) GPIO8 GPIO_8_ROMSO VSYNC
GPIO9 RP1A 1 8 33R GPIO9_ROMSI AH15
(8,9) GPIO9 GPIO_9_ROMSI
GPIO10 RP1B 2 7 33R GPIO10_ROMSCK AJ16
GPIO11 AK16 GPIO_10_ROMSCK AB34 R5623
(9) GPIO11 GPIO_11 RSET
GPIO12 AL16 499R
(9) GPIO12 GPIO_12
GPIO13 AM16 AD34
(9) GPIO13 GPIO_13 AVDD
GPIO14_HPD2 AM14 AE34
(8) GPIO14_HPD2 GPIO_14_HPD2 AVSSQ
GPIO15_PCNTL0 AM13
(10) GPIO15_PCNTL0 GPIO_15_PWRCNTL_0
GPIO_16_SSIN AK14 AC33 +1.8V_REG (A2VDDQ: 1.5mA @ 1.8V) A2VDDQ
(10) GPIO16_SSIN GPIO_16_SSIN VDD1DI
GPIO17_THERMAL_INT AG30 AC34 B10063
(8,9) GPIO17_THERMAL_INT GPIO_17_THERMAL_INT VSS1DI
GPIO18_HPD4 AN14 BLM15BD121SN1
(8) GPIO18_HPD3 GPIO_18_HPD3
GPIO19_CTF AM17
(10) GPIO19_CTF GPIO20_PCNTL1 AL13 GPIO_19_CTF AC30 C5707 C5627 C5628
(10) GPIO20_PCNTL1 GPIO_20_PWRCNTL_1 R2 VGA_RED (8)
GPIO21_BB_EN AJ14 AC31 NS13 4.7uF_6.3V 1uF_6.3V 100nF_6.3V
GPIO22 RP1D 4 5 33R (9,10) GPIO21_BB_EN GPIO22_ROMCSB AK13 GPIO_21_BB_EN R2B 1 2
(9) GPIO22 GPIO23_CLKREQB AN13 GPIO_22_ROMCSB AD30
(8) GPIO23_CLKREQB GPIO_23_CLKREQB G2 VGA_GRN (8)
TP13 35mil GPIO24_TRSTB AM23 AD31 NS_VIA A2VSSQ
TP14 35mil GPIO25_TDI AN23 JTAG_TRSTB G2B
JTAG DEBUG PORT TP15 35mil GPIO26_TCK AK23 JTAG_TDI AF30
JTAG_TCK B2 VGA_BLU (8)
TP16 35mil GPIO27_TMS AL24 AF31 (VDD2DI: 50mA @ 1.8V) VDD2DI
TP17 35mil GPIO28_TDO AM24 JTAG_TMS B2B B10064
R5631 0R DNI GENERICA AJ19 JTAG_TDO R6118 R6119 R6120 BLM15BD121SN1
(8) MB_GPIO0 GENERICA PLACE RGB
R5632 0R DNI GENERICB AK19 AC32 150R 150R 150R
(8) MB_GPIO1
TP18 35mil GENERICC AJ20 GENERICB C AD32
TERMINATION C5708 C5610 C36
R5633 0R DNI GENERICD AK20 GENERICC Y AF32 RESISTORS CLOSE 4.7uF_6.3V 1uF_6.3V 100nF_6.3V
(8) MB_GPIO2 GENERICD COMP
AJ24 TO ASIC
AH26 GENERICE_HPD4 DAC2
R5627 R5628 R5629 R6144 AH24 GENERICF AD29
GENERICG H2SYNC HSYNC_DAC2 (8,9)
10K 10K 10K 10K AC29 VSYNC_DAC2 (8,9)
B
DNI DNI DNI DNI V2SYNC B
AK24 VDD2DI +VDDR3 (A2VDD: 130mA @ 3.3V) A2VDD
(8) HPD1 HPD1 AG31 B10061
+VDDR3 +VDDR3 VDD2DI AG32 BLM15BD121SN1
VSS2DI
A2VDD C5706 C31 C33
AG33 4.7uF_6.3V 1uF_6.3V 100nF_6.3V
A2VDD A2VDDQ
+1.8V_REG AD33
R5675 499R VREFG AH13 A2VDDQ
PLACE VREFG VREFG
R586 249R AF33
DIVIDER AND CAP C5685 100nF_6.3V A2VSSQ
CLOSE TO ASIC
+1.8V_REG DPLL_PVDD AA29 R55 A2VSSQ
(DPLL_PVDD: 75mA @ 1.8V) R2SET
B10098 AM32 715R
BLM15BD121SN1 AN32 DPLL_PVDD
DPLL_PVSS
C5784 C5785 C5786 DPLL_PVSS DDC/AUX AM26
NS27 4.7uF_6.3V 1uF_6.3V 100nF_6.3V AN31 PLL/CLOCK DDC1CLK AN26
1 2 DPLL_VDDC DDC1DATA +VDDR3
AM27
AUX1P DDCCLK_AUX1P (8)
NS_VIA XTALIN AV33 AL27 DPA
XTALIN AUX1N DDCDATA_AUX1N (8)
DPLL_PVSS XTALOUT AU34 BIOS1
XTALOUT AM19
DDC2CLK AL19
+1.0V_REG DPLL_VDDC AW34 DDC2DATA R2191 C5613 BIOS
(DPLL_VDDC: 125mA @ 1.0V) XO_IN
B10099 R6092 1M AN20 0R 100nF_6.3V
AUX2P DDCCLK_AUX2P (8)
BLM15BD121SN1 AW35 AM20 DPB U5508
XO_IN2 AUX2N DDCDATA_AUX2N (8)
2 4 GPIO22 1 8 113-B985XX-XXX
C5787 C5788 C5789 1 3 AL30 GPIO8 2 CE# VCC 7 VIDEO BIOS
DDCCLK_AUX3P DDC3CLK (8) SO HOLD#
4.7uF_6.3V 1uF_6.3V 100nF_6.3V AM30 LVDS 3 6 GPIO10 FIRMWARE
DDCDATA_AUX3N DDC3DATA (8) WP# SCK
C5973 Y1 C5974 4 5 GPIO9
12pF_50V 27.000MHz_10PPM_30R 12pF_50V AL29 GND SI
AF29 DDCCLK_AUX4P AM29 PM25LV512A-100SCE
(9) GPU_DPLUS DPLUS THERMAL DDCDATA_AUX4N
DPLL_PVSS AG29 R2190
(9) GPU_DMINUS DMINUS AN21 0R
DDCCLK_AUX5P DDC5CLK (8)
AM21 VGA DNI
DDCDATA_AUX5N DDC5DATA (8)
A AK32 A
(9) TS_FDO TS_FDO AJ30
AL31
TS_A
DDC6CLK
DDC6DATA
AJ31
DDC6CLK (9)
DDC6DATA (9) External thermal sensor SERIAL EEPROM 512K/1M
+1.8V_REG TSVDD AK30
PN 2280007900G for 1Mbit (PM25LV010A-100SCE)
(TSVDD: 5mA @ 1.8V) DDCCLK_AUX7P
B10122 AJ32 AK29 R5625 R5626
BLM15BD121SN1 AJ33 TSVDD DDCDATA_AUX7N 4.7K 4.7K
TSVSS DNI DNI CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
C5923 C5924 © 2007 Advanced Micro Devices Advanced Micro Devices Inc.
NS43 4.7uF_6.3V 1uF_6.3V TSVSS Broadway This AMD Board schematic and design is the exclusive property of AMD,
1 2 +VDDR3 and is provided only to entities under a non-disclosure agreement 1 Commerce Valley Drive East
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose Markham, Ontario
NS_VIA other than evaluation requires a Board Technology License Agreement
TSVSS with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,
Date: Friday, December 11, 2009 Rev
3
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting Sheet 2 of 17
from use of the information included herein.
Title Doc No.
MADISON GDDR3 MxM3.0 105-B985xx-00D
5 4 3 2 1
 5 4 3 2 1

U1E U1F

MEM I/O
+MVDD (VDDR1: 1.7A (RMS) 2.6A (Peak) @ 1.8V) PCIE PCIE_VDDR (PCIE_VDDR: 400mA @ 1.8V) +1.8V_REG
AC7 AA31 L115 AB39 A3
AD11 VDDR1#1 PCIE_VDDR#1 AA32 470R_1000mA E39 PCIE_VSS#1 GND#1 A37
AF7 VDDR1#2 PCIE_VDDR#2 AA33 F34 PCIE_VSS#2 GND#2 AA16
C6064 C6065 C6066 C6067 C6068 C6069 C6070 C6071 C6072 C6073 AG10 VDDR1#3 PCIE_VDDR#3 AA34 C5935 C5936 C5928 C5929 C5800 C5802 MC5802 F39 PCIE_VSS#3 GND#3 AA18
1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V AJ7 VDDR1#4 PCIE_VDDR#4 V28 100nF_6.3V 100nF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 10uF_4V 4.7uF_6.3V G33 PCIE_VSS#4 GND#4 AA2
AK8 VDDR1#5 PCIE_VDDR#5 W29 G34 PCIE_VSS#5 GND#5 AA21
AL9 VDDR1#6 PCIE_VDDR#6 W30 H31 PCIE_VSS#6 GND#6 AA23
G11 VDDR1#7 PCIE_VDDR#7 Y31 Overlap H34 PCIE_VSS#7 GND#7 AA26
G14 VDDR1#8 PCIE_VDDR#8 H39 PCIE_VSS#8 GND#8 AA28
D
G17 VDDR1#9 PCIE_VDDC +1.0V_REG J31 PCIE_VSS#9 GND#9 AA6 D
VDDR1#10 (PCIE_VDDC: 1.1A @ 1.0V) PCIE_VSS#10 GND#10
C6074 C6075 C6076 C6077 C6078 C6079 C5586 C5969 C5967 C5968 G20 G30 J34 AB12
1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V G23 VDDR1#11 PCIE_VDDC#1 G31 K31 PCIE_VSS#11 GND#11 AB15
G26 VDDR1#12 PCIE_VDDC#2 H29 K34 PCIE_VSS#12 GND#12 AB17
G29 VDDR1#13 PCIE_VDDC#3 H30 C981 C982 C983 C972 C5927 C5930 C973 C1668 MC1668 K39 PCIE_VSS#13 GND#13 AB20
H10 VDDR1#14 PCIE_VDDC#4 J29 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 10uF_4V 4.7uF_6.3V L31 PCIE_VSS#14 GND#14 AB22
J7 VDDR1#15 PCIE_VDDC#5 J30 L34 PCIE_VSS#15 GND#15 AB24
J9 VDDR1#16 PCIE_VDDC#6 L28 M34 PCIE_VSS#16 GND#16 AB27
C5584 C5620 C5585 C5665 C5666 K11 VDDR1#17 PCIE_VDDC#7 M28 Overlap M39 PCIE_VSS#17 GND#17 AC11
10uF_6.3V 10uF_6.3V 10uF_6.3V 10uF_6.3V 10uF_6.3V K13 VDDR1#18 PCIE_VDDC#8 N28 N31 PCIE_VSS#18 GND#18 AC13
K8 VDDR1#19 PCIE_VDDC#9 R28 N34 PCIE_VSS#19 GND#19 AC16
L12 VDDR1#20 PCIE_VDDC#10 T28 P31 PCIE_VSS#20 GND#20 AC18
L16 VDDR1#21 PCIE_VDDC#11 U28 P34 PCIE_VSS#21 GND#21 AC2
L21 VDDR1#22 PCIE_VDDC#12 P39 PCIE_VSS#22 GND#22 AC21
L23 VDDR1#23 +VDDC R34 PCIE_VSS#23 GND#23 AC23
VDDR1#24 (VDDC: 19A (RMS) 29A (Peak) @ 1.0V) PCIE_VSS#24 GND#24
C7195 C7196 C7197 C7198 C7199 L26 AA15 T31 AC26
10uF_4V 10uF_4V 10uF_4V 10uF_4V 10uF_4V L7 VDDR1#25 CORE VDDC#1 AA17 T34 PCIE_VSS#25 GND#25 AC28
M11 VDDR1#26 VDDC#2 AA20 T39 PCIE_VSS#26 GND#26 AC6
N11 VDDR1#27 VDDC#3 AA22 C942 C251 C252 C253 C943 C255 C260 C261 C258 C259 U31 PCIE_VSS#27 GND#27 AD15
P7 VDDR1#28 VDDC#4 AA24 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V U34 PCIE_VSS#28 GND#28 AD17
R11 VDDR1#29 VDDC#5 AA27 V34 PCIE_VSS#29 GND#29 AD20
U11 VDDR1#30 VDDC#6 AB16 V39 PCIE_VSS#30 GND#30 AD22
U7 VDDR1#31 VDDC#7 AB18 W31 PCIE_VSS#31 GND#31 AD24
Y11 VDDR1#32 VDDC#8 AB21 W34 PCIE_VSS#32 GND#32 AD27
Y7 VDDR1#33 VDDC#9 AB23 Y34 PCIE_VSS#33 GND#33 AD9
VDDR1#34 VDDC#10 AB26 C161 C162 C163 C164 C165 C166 C167 C168 C169 C170 Y39 PCIE_VSS#34 GND#34 AE2
VDDC#11 AB28 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V PCIE_VSS#35 GND#35 AE6
VDDC#12 AC17 GND#36 AF10
VDDC#13 AC20 GND#37 AF16
LEVEL VDDC#14 AC22 GND#38 AF18
+1.8V_REG VDD_CT TRANSLATION VDDC#15 AC24 GND#39 AF21
(VDD_CT: 17mA @ 1.8V) VDDC#16
GND GND#40

POWER
B10100 AF26 AC27 AG17
BLM15BD121SN1 AF27 VDD_CT#1 VDDC#17 AD18 C171 C172 C173 C174 C175 C176 C177 C178 C179 C180 F15 GND#41 AG2
AG26 VDD_CT#2 VDDC#18 AD21 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V F17 GND#100 GND#42 AG20
C5824 C5821 C5826 AG27 VDD_CT#3 VDDC#19 AD23 F19 GND#101 GND#43 AG22
4.7uF_6.3V 1uF_6.3V 100nF_6.3V VDD_CT#4 VDDC#20 AD26 F21 GND#102 GND#44 AG6
VDDC#21 AF17 F23 GND#103 GND#45 AG9
+VDDR3 VDDR3 I/O VDDC#22 AF20 F25 GND#104 GND#46 AH21
C (VDDR3: 60mA @ 3.3V) VDDC#23 GND#105 GND#47
C
B27 AF23 AF22 F27 AJ10
BLM15BD121SN1 AF24 VDDR3#1 VDDC#24 AG16 C160 C184 C185 C190 C944 C945 C946 C947 C948 C949 F29 GND#106 GND#48 AJ11
AG23 VDDR3#2 VDDC#25 AG18 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V F31 GND#107 GND#49 AJ2
C5591 C5592 AG24 VDDR3#3 VDDC#26 AG21 F33 GND#108 GND#50 AJ28
4.7uF_6.3V 1uF_6.3V VDDR3#4 VDDC#27 AH22 F7 GND#109 GND#51 AJ6
VDDC#28 AH27 F9 GND#110 GND#52 AK11
AF13 VDDC#29 AH28 G2 GND#111 GND#53 AK31
AF15 VDDR4#4 VDDC#30 M26 G6 GND#112 GND#54 AK7
AG13 VDDR4#5 VDDC#31 N24 C262 C263 C264 H9 GND#113 GND#55 AL11
VDDR4 AG15 VDDR4#7 VDDC#32 N27 1uF_6.3V 1uF_6.3V 1uF_6.3V J2 GND#114 GND#56 AL14
(VDDR4: 170mA @ 1.8V) VDDR4#8 VDDC/BIF_VDDC#33 GND#115 GND#57
B10101 R18 J27 AL17
BLM15BD121SN1 VDDC#34 R21 J6 GND#116 GND#58 AL2
AD12 VDDC#35 R23 J8 GND#117 GND#59 AL20
C5932 C5829 AF11 VDDR4#1 VDDC#36 R26 K14 GND#118 GND#60 AL21
1uF_6.3V 100nF_6.3V AF12 VDDR4#2 VDDC#37 T17 K7 GND#119 GND/PX_EN#61 AL23
AG11 VDDR4#3 VDDC#38 T20 C181 C182 C183 C191 C192 C193 C194 L11 GND#120 GND#62 AL26
VDDR4#6 VDDC#39 T22 10uF_4V 10uF_4V 10uF_4V 10uF_4V 10uF_4V 10uF_4V 10uF_4V L17 GND#121 GND#63 AL32
VDDC#40 T24 L2 GND#122 GND#64 AL6
VDDC#41 T27 L22 GND#123 GND#65 AL8
VDDC/BIF_VDDC#42 U16 L24 GND#124 GND#66 AM11
M20 VDDC#43 U18 L6 GND#125 GND#67 AM31
M21 NC_VDDRHA VDDC#44 U21 M17 GND#126 GND#68 AM9
NC_VSSRHA VDDC#45 U23 MC181 MC182 MC183 MC191 MC192 MC193 MC194 M22 GND#127 GND#69 AN11
VDDC#46 U26 4.7uF_6.3V 4.7uF_6.3V 4.7uF_6.3V 4.7uF_6.3V 4.7uF_6.3V 4.7uF_6.3V 4.7uF_6.3V M24 GND#128 GND#70 AN2
V12 VDDC#47 V17 N16 GND#129 GND#71 AN30
U12 NC_VDDRHB VDDC#48 V20 N18 GND#130 GND#72 AN6
NC_VSSRHB VDDC#49 V22 Overlap N2 GND#131 GND#73 AN8
VDDC#50 V24 N21 GND#132 GND#74 AP11
VDDC#51 V27 N23 GND#133 GND#75 AP7
VDDC#52 Y16 N26 GND#134 GND#76 AP9
PCIE_PVDD PLL VDDC#53 Y18 N6 GND#135 GND#77 AR5
(PCIE_PVDD: 40mA @ 1.8V) VDDC#54 GND#136 GND#78
B10105 AB37 Y21 R15 B11
BLM15BD121SN1 MPV18 PCIE_PVDD VDDC#55 Y23 R17 GND#137 GND#79 B13
H7 VDDC#56 Y26 R2 GND#138 GND#80 B15
C5832 C5833 C5834 H8 MPV18#1 VDDC#57 Y28 R20 GND#139 GND#81 B17
4.7uF_6.3V 1uF_6.3V 100nF_6.3V MPV18#2 VDDC#58 R22 GND#140 GND#82 B19
SPV18 R24 GND#141 GND#83 B21
B
AM10 +VDDC R27 GND#142 GND#84 B23 B
SPV10 SPV18 (VDDCI : 3A (RMS) 4A (Peak) @ VDDC) GND#143 GND#85
AA13 R6 B25
AN9 VDDCI#1 AB13 T11 GND#144 GND#86 B27
SPV10 VDDCI#2 AC12 T13 GND#145 GND#87 B29
+1.8V_REG AN10 VDDCI#3 AC15 C5839 C5838 C5837 C5836 C5835 C5970 C5971 C5972 MC5972 T16 GND#146 GND#88 B31
(MPV18: 150mA @ 1.8V) SPVSS VDDCI#4 GND#147 GND#89
B10128 AD13 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 10uF_4V 4.7uF_6.3V T18 B33
BLM15BD121SN1 SPVSS VDDCI#5 AD16 T21 GND#148 GND#90 B7
VDDCI#6 M15 T23 GND#149 GND#91 B9
C7115 C5950 C5951 C5954 VDDCI#7 M16 Overlap T26 GND#150 GND#92 C1
4.7uF_6.3V 4.7uF_6.3V 1uF_6.3V 100nF_6.3V VOLTAGE VDDCI#8 M18 U15 GND#151 GND#93 C39
SENESE VDDCI#9 M23 U17 GND#153 GND#94 E35
VDDCI#10 N13 U2 GND#154 GND#95 E5
AF28 VDDCI#11 N15 U20 GND#155 GND#96 F11
(11) ASIC_FB_VDDC FB_VDDC VDDCI#12 GND#156 GND#97
N17 U22 F13
VDDCI#13 N20 U24 GND#157 GND#98
(SPV18: 50mA @ 1.8V) VDDCI#14 GND#158
B10127 AG28 N22 U27
BLM15BD121SN1 FB_VDDCI ISOLATED VDDCI#15 R12 U6 GND#159
CORE I/O VDDCI#16 R13 V11 GND#160
C5947 C5948 C5949 AH29 VDDCI#17 R16 V16 GND#161
4.7uF_6.3V 1uF_6.3V 100nF_6.3V FB_GND VDDCI#18 T12 V18 GND#163
VDDCI#19 T15 V21 GND#164
VDDCI#20 V15 V23 GND#165
VDDCI#21 Y13 V26 GND#166
SPVSS VDDCI#22 W2 GND#167
W6 GND#168
Broadway Y15 GND#169
+1.0V_REG Y17 GND#170
(SPV10: 100mA @ 1.0V) GND#171
B10124 Y20
BLM15BD121SN1 Y22 GND#172 A39
Y24 GND#173 VSS_MECH#1 AW1
C5694 C5614 C45 Y27 GND#174 VSS_MECH#2 AW39
NS21 4.7uF_6.3V 1uF_6.3V 100nF_6.3V U13 GND#175 VSS_MECH#3
1 2 V13 GND#152
GND#162
NS_VIA Broadway
SPVSS

A A

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

© 2007 Advanced Micro Devices Advanced Micro Devices Inc.
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement 1 Commerce Valley Drive East
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose Markham, Ontario
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,
Date: Friday, December 11, 2009 Rev
3
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting Sheet 3 of 17
from use of the information included herein.
Title Doc No.
MADISON GDDR3 MxM3.0 105-B985xx-00D
5 4 3 2 1
 5 4 3 2 1

D D

U1H

DP C/D POWER DP A/B POWER

DPAB_VDD18 +1.8V_REG
(DPAB_VDD18: 260mA @ 1.8V)
AP20 AN24 B10130
AP21 DPC_VDD18#1 DPA_VDD18#1 AP24 120R_450mA
DPC_VDD18#2 DPA_VDD18#2
C5956 C5957 C5955
100nF_6.3V 1uF_6.3V 4.7uF_6.3V
AP13 AP31
AT13 DPC_VDD10#1 DPA_VDD10#1 AP32
DPC_VDD10#2 DPA_VDD10#2

AN17 AN27
AP16 DPC_VSSR#1 DPA_VSSR#1 AP27 DPAB_VDD10 +1.0V_REG
DPC_VSSR#2 DPA_VSSR#2 (DPAB_VDD10: 220mA @ 1.0V)
AP17 AP28 B10108
AW14 DPC_VSSR#3 DPA_VSSR#3 AW24 120R_450mA
AW16 DPC_VSSR#4 DPA_VSSR#4 AW26
+5VRUN DPC_VSSR#5 DPA_VSSR#5 C5842 C5841 C5840
Q27 100nF_6.3V 1uF_6.3V 4.7uF_6.3V
+1.8V_REG NDS335N DPEF_VDD18 DPAB_VDD18
AP22 AP25
3 2 AP23 DPD_VDD18#1 DPB_VDD18#1 AP26
C27 DPD_VDD18#2 DPB_VDD18#2
100nF
5
1

U27 DPAB_VDD10

1
AP14 AN33
2 4 AP15 DPD_VDD10#1 DPB_VDD10#1 AP33
(2,8) FPVCC DPD_VDD10#2 DPB_VDD10#2
C C
74HCT1G126GW
3

AN19 AN29
AP18 DPD_VSSR#1 DPB_VSSR#1 AP29
AP19 DPD_VSSR#2 DPB_VSSR#2 AP30
AW20 DPD_VSSR#3 DPB_VSSR#3 AW30
AW22 DPD_VSSR#4 DPB_VSSR#4 AW32
DPD_VSSR#5 DPB_VSSR#5

R6078 150R AW18 AW28 R6079 150R

DNI DPCD_CALR DPAB_CALR

+1.8V_REG (DPEF_VDD18: 400mA @ 1.8V) DPEF_VDD18 DP E/F POWER DP PLL POWER DPAB_PVDD (DPAB_PVDD: 40mA @ 1.8V) +1.8V_REG
B10113 AH34 AU28 B10112
120R_450mA AJ34 DPE_VDD18#1 DPA_PVDD AV27 BLM15BD121SN1
DPE_VDD18#2 DPA_PVSS
C5855 C5856 C5857 C5852 C5853 C5854
4.7uF_6.3V 1uF_6.3V 100nF_6.3V DPEF_VDD10 DPAB_PVDD 100nF_6.3V 1uF_6.3V 4.7uF_6.3V NS34
AL33 AV29 2 1
AM33 DPE_VDD10#1 DPB_PVDD AR28
DPE_VDD10#2 DPB_PVSS NS_VIA
DPAB_PVSS DPAB_PVSS

+1.0V_REG (DPEF_VDD10: 240mA @ 1.0V) AN34 AU18

B10115 AP39 DPE_VSSR#1 DPC_PVDD AV17
120R_450mA AR39 DPE_VSSR#2 DPC_PVSS
AU37 DPE_VSSR#3
C5861 C5862 C5863 DPE_VSSR#4
4.7uF_6.3V 1uF_6.3V 100nF_6.3V AV19
DPD_PVDD AR18
DPEF_VDD18 DPD_PVSS
AF34
AG34 DPF_VDD18#1 DPEF_PVDD
DPF_VDD18#2 (DPEF_PVDD: 40mA @ 1.8V)
AM37 B10119
DPE_PVDD AN38 BLM15BD121SN1
DPEF_VDD10 DPE_PVSS
B B
AK33 C5873 C5874 C5875
AK34 DPF_VDD10#1 DPEF_PVDD 100nF_6.3V 1uF_6.3V 4.7uF_6.3V NS41
DPF_VDD10#2 AL38 2 1
DPF_PVDD AM35
DPF_PVSS NS_VIA
If DPEF ports are not used (i.e no LVDS): AF39 DPEF_PVSS DPEF_PVSS
DNI B10113, C5855, C5856, B10115, C5861, C5862, B10119, C5874, C5875 and R6080. AH39 DPF_VSSR#1
AK39 DPF_VSSR#2
DNI U27, Q27 and C27 AL34 DPF_VSSR#3
Install 0R resistors on C5857, C5863 and C5873. AM34 DPF_VSSR#4
DPF_VSSR#5

R6080 150R AM39

DPEF_CALR

Broadway

A A

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

© 2007 Advanced Micro Devices Advanced Micro Devices Inc.
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement 1 Commerce Valley Drive East
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose Markham, Ontario
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,
Date: Friday, December 11, 2009 Rev
3
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting Sheet 4 of 17
from use of the information included herein.
Title Doc No.
MADISON GDDR3 MxM3.0 105-B985xx-00D
5 4 3 2 1
 1 2 3 4 5 6 7 8

A A

U1C
DDR2 DDR2 U1D
GDDR3/GDDR5 GDDR5/GDDR3 DDR2 DDR2
DDR3 DDR3 GDDR3/GDDR5 GDDR5/GDDR3
MDA0 C37 G24 MAA0 DDR3 DDR3
MDA1 C35 DQA0_0/DQA_0 MAA0_0/MAA_0 J23 MAA1 MDB0 C5 P8 MAB0
MDA2 A35 DQA0_1/DQA_1 MAA0_1/MAA_1 H24 MAA2 MDB1 C3 DQB0_0/DQB_0 MAB0_0/MAB_0 T9 MAB1
RASA0# MDA3 E34 DQA0_2/DQA_2 MAA0_2/MAA_2 J24 MAA3 MDB2 E3 DQB0_1/DQB_1 MAB0_1/MAB_1 P9 MAB2

MEMORY INTERFACE A
(6) RASA0# RASA1# MDA4 G32 DQA0_3/DQA_3 MAA0_3/MAA_3 H26 MAA4 MDB3 E1 DQB0_2/DQB_2 MAB0_2/MAB_2 N7 MAB3
(6) RASA1# MDA5 D33 DQA0_4/DQA_4 MAA0_4/MAA_4 J26 MAA5 MDB4 F1 DQB0_3/DQB_3 MAB0_3/MAB_3 N8 MAB4

MEMORY INTERFACE B
CASA0# MDA6 F32 DQA0_5/DQA_5 MAA0_5/MAA_5 H21 MAA6 MDB5 F3 DQB0_4/DQB_4 MAB0_4/MAB_4 N9 MAB5
(6) CASA0# CASA1# MDA7 E32 DQA0_6/DQA_6 MAA0_6/MAA_6 G21 MAA7 MDB6 F5 DQB0_5/DQB_5 MAB0_5/MAB_5 U9 MAB6
(6) CASA1# MDA8 D31 DQA0_7/DQA_7 MAA0_7/MAA_7 H19 MAA8 MDB7 G4 DQB0_6/DQB_6 MAB0_6/MAB_6 U8 MAB7
WEA0# MDA9 F30 DQA0_8/DQA_8 MAA1_0/MAA_8 H20 MAA9 MDB8 H5 DQB0_7/DQB_7 MAB0_7/MAB_7 Y9 MAB8
(6) WEA0# WEA1# MDA10 C30 DQA0_9/DQA_9 MAA1_1/MAA_9 L13 MAA10 MDB9 H6 DQB0_8/DQB_8 MAB1_0/MAB_8 W9 MAB9
(6) WEA1# MDA11 A30 DQA0_10/DQA_10 MAA1_2/MAA_10 G16 MAA11 MDB10 J4 DQB0_9/DQB_9 MAB1_1/MAB_9 AC8 MAB10
CKEA0 MDA12 F28 DQA0_11/DQA_11 MAA1_3/MAA_11 J16 MAA12 MDB11 K6 DQB0_10/DQB_10 MAB1_2/MAB_10 AC9 MAB11 RASB0#
(6) CKEA0 DQA0_12/DQA_12 MAA1_4/MAA_12 DQB0_11/DQB_11 MAB1_3/MAB_11 (7) RASB0#
CKEA1 MDA13 C28 H16 A_BA2 MDB12 K5 AA7 MAB12 RASB1#
(6,14) CKEA1 DQA0_13/DQA_13 MAA1_5/MAA_13_BA2 DQB0_12/DQB_12 MAB1_4/MAB_12 (7) RASB1#
MDA14 A28 J17 A_BA0 MDB13 L4 AA8 B_BA2
CSA0#_0 MDA15 E28 DQA0_14/DQA_14 MAA1_6/MAA_14_BA0 H17 A_BA1 MDB14 M6 DQB0_13/DQB_13 MAB1_5/BA2 Y8 B_BA0 CASB0#
(6) CSA0#_0 DQA0_15/DQA_15 MAA1_7/MAA_A15_BA1 DQB0_14/DQB_14 MAB1_6/BA0 (7) CASB0#
CSA1#_0 MDA16 D27 MDB15 M1 AA9 B_BA1 CASB1#
(6) CSA1#_0 DQA0_16/DQA_16 DQB0_15/DQB_15 MAB1_7/BA1 (7) CASB1#
CSA0#_1 MDA17 F26 A32 DQMA#0 MDB16 M3
(6) CSA0#_1 CSA1#_1 MDA18 C26 DQA0_17/DQA_17 WCKA0_0/DQMA_0 C32 DQMA#1 MDB17 M5 DQB0_16/DQB_16 H3 DQMB#0 WEB0#
(6) CSA1#_1 DQA0_18/DQA_18 WCKA0B_0/DQMA_1 DQB0_17/DQB_17 WCKB0_0/DQMB_0 (7) WEB0#
MDA19 A26 D23 DQMA#2 MDB18 N4 H1 DQMB#1 WEB1#
DQA0_19/DQA_19 WCKA0_1/DQMA_2 DQB0_18/DQB_18 WCKB0B_0/DQMB_1 (7) WEB1#
MDA20 F24 E22 DQMA#3 MDB19 P6 T3 DQMB#2
MDA21 C24 DQA0_20/DQA_20 WCKA0B_1/DQMA_3 C14 DQMA#4 MDB20 P5 DQB0_19/DQB_19 WCKB0_1/DQMB_2 T5 DQMB#3 CSB0#_0
DQA0_21/DQA_21 WCKA1_0/DQMA_4 DQB0_20/DQB_20 WCKB0B_1/DQMB_3 (7) CSB0#_0
CLKA0 MDA22 A24 A14 DQMA#5 MDB21 R4 AE4 DQMB#4 CSB1#_0
(6,14) CLKA0 DQA0_22/DQA_22 WCKA1B_0/DQMA_5 DQB0_21/DQB_21 WCKB1_0/DQMB_4 (7) CSB1#_0
CLKA0# MDA23 E24 E10 DQMA#6 MDB22 T6 AF5 DQMB#5 CSB0#_1
(6) CLKA0# DQA0_23/DQA_23 WCKA1_1/DQMA_6 DQB0_22/DQB_22 WCKB1B_0/DQMB_5 (7) CSB0#_1
MDA24 C22 D9 DQMA#7 MDB23 T1 AK6 DQMB#6 CSB1#_1
DQA0_24/DQA_24 WCKA1B_1/DQMA_7 DQB0_23/DQB_23 WCKB1_1/DQMB_6 (7) CSB1#_1
CLKA1 MDA25 A22 MDB24 U4 AK5 DQMB#7
(6,14) CLKA1 CLKA1# MDA26 F22 DQA0_25/DQA_25 GDDR5/DDR2/GDDR3 C34 RDQSA0 MDB25 V6 DQB0_24/DQB_24 WCKB1B_1/DQMB_7
(6) CLKA1# MDA27 D21 DQA0_26/DQA_26 EDCA0_0/QSA_0/RDQSA_0 D29 RDQSA1 MDB26 V1 DQB0_25/DQB_25 GDDR5/DDR2/GDDR3 F6 RDQSB0 CKEB0
WDQSA[7..0] DQA0_27/DQA_27 EDCA0_1/QSA_1/RDQSA_1 DQB0_26/DQB_26 EDCB0_0/QSB_0/RDQSB_0 (7) CKEB0
B MDA28 A20 D25 RDQSA2 MDB27 V3 K3 RDQSB1 CKEB1 B
(6) WDQSA[7..0] DQA0_28/DQA_28 EDCA0_2/QSA_2/RDQSA_2 DQB0_27/DQB_27 EDCB0_1/QSB_1/RDQSB_1 (7,14) CKEB1
MDA29 F20 E20 RDQSA3 MDB28 Y6 P3 RDQSB2
RDQSA[7..0] MDA30 D19 DQA0_29/DQA_29 EDCA0_3/QSA_3/RDQSA_3 E16 RDQSA4 MDB29 Y1 DQB0_28/DQB_28 EDCB0_2/QSB_2/RDQSB_2 V5 RDQSB3 CLKB0
(6) RDQSA[7..0] DQA0_30/DQA_30 EDCA1_0/QSA_4/RDQSA_4 DQB0_29/DQB_29 EDCB0_3/QSB_3/RDQSB_3 (7,14) CLKB0
MDA31 E18 E12 RDQSA5 MDB30 Y3 AB5 RDQSB4 CLKB0#
DQMA#[7..0] DQA0_31/DQA_31 EDCA1_1/QSA_5/RDQSA_5 DQB0_30/DQB_30 EDCB1_0/QSB_4/RDQSB_4 (7,14) CLKB0#
MDA32 C18 J10 RDQSA6 MDB31 Y5 AH1 RDQSB5
(6) DQMA#[7..0] DQA1_0/DQA_32 EDCA1_2/QSA_6/RDQSA_6 DQB0_31/DQB_31 EDCB1_1/QSB_5/RDQSB_5
MDA33 A18 D7 RDQSA7 MDB32 AA4 AJ9 RDQSB6 CLKB1
MDA[63..0] DQA1_1/DQA_33 EDCA1_3/QSA_7/RDQSA_7 DQB1_0/DQB_32 EDCB1_2/QSB_6/RDQSB_6 (7,14) CLKB1
MDA34 F18 MDB33 AB6 AM5 RDQSB7 CLKB1#
(6) MDA[63..0] DQA1_2/DQA_34 DQB1_1/DQB_33 EDCB1_3/QSB_7/RDQSB_7 (7,14) CLKB1#
MDA35 D17 A34 WDQSA0 MDB34 AB1
MAA[12..0] MDA36 A16 DQA1_3/DQA_35 DDBIA0_0/QSA_0B/WDQSA_0 E30 WDQSA1 MDB35 AB3 DQB1_2/DQB_34 G7 WDQSB0
(6) MAA[12..0] DQA1_4/DQA_36 DDBIA0_1/QSA_1B/WDQSA_1 DQB1_3/DQB_35 DDBIB0_0/QSB_0B/WDQSB_0 WDQSB[7..0]
MDA37 F16 E26 WDQSA2 MDB36 AD6 K1 WDQSB1
MDA38 D15 DQA1_5/DQA_37 DDBIA0_2/QSA_2B/WDQSA_2 C20 WDQSA3 MDB37 AD1 DQB1_4/DQB_36 DDBIB0_1/QSB_1B/WDQSB_1 P1 WDQSB2 (7) WDQSB[7..0]
MDA39 E14 DQA1_6/DQA_38 DDBIA0_3/QSA_3B/WDQSA_3 C16 WDQSA4 MDB38 AD3 DQB1_5/DQB_37 DDBIB0_2/QSB_2B/WDQSB_2 W4 WDQSB3 RDQSB[7..0]
A_BA0 MDA40 F14 DQA1_7/DQA_39 DDBIA1_0/QSA_4B/WDQSA_4 C12 WDQSA5 MDB39 AD5 DQB1_6/DQB_38 DDBIB0_3/QSB_3B/WDQSB_3 AC4 WDQSB4 (7) RDQSB[7..0]
(6) A_BA0 DQA1_8/DQA_40 DDBIA1_1/QSA_5B/WDQSA_5 DQB1_7/DQB_39 DDBIB1_0/QSB_4B/WDQSB_4 DQMB#[7..0]
A_BA1 MDA41 D13 J11 WDQSA6 MDB40 AF1 AH3 WDQSB5
(6) A_BA1 DQA1_9/DQA_41 DDBIA1_2/QSA_6B/WDQSA_6 DQB1_8/DQB_40 DDBIB1_1/QSB_5B/WDQSB_5 (7) DQMB#[7..0]
A_BA2 MDA42 F12 F8 WDQSA7 MDB41 AF3 AJ8 WDQSB6
(6) A_BA2 DQA1_10/DQA_42 DDBIA1_3/QSA_7B/WDQSA_7 DQB1_9/DQB_41 DDBIB1_2/QSB_6B/WDQSB_6 MDB[63..0]
MDA43 A12 MDB42 AF6 AM3 WDQSB7
DQA1_11/DQA_43 DQB1_10/DQB_42 DDBIB1_3/QSB_7B/WDQSB_7 (7) MDB[63..0]
MDA44 D11 J21 MDB43 AG4
MDA45 F10 DQA1_12/DQA_44 ADBIA0/ODTA0 G19 MDB44 AH5 DQB1_11/DQB_43 T7 MAB[12..0]
DQA1_13/DQA_45 ADBIA1/ODTA1 DQB1_12/DQB_44 ADBIB0/ODTB0 (7) MAB[12..0]
MDA46 A10 MDB45 AH6 W7
MDA47 C10 DQA1_14/DQA_46 H27 CLKA0 MDB46 AJ4 DQB1_13/DQB_45 ADBIB1/ODTB1
MDA48 G13 DQA1_15/DQA_47 CLKA0 G27 CLKA0# MDB47 AK3 DQB1_14/DQB_46 L9 CLKB0
MDA49 H13 DQA1_16/DQA_48 CLKA0B MDB48 AF8 DQB1_15/DQB_47 CLKB0 L8 CLKB0# B_BA0
DQA1_17/DQA_49 DQB1_16/DQB_48 CLKB0B (7) B_BA0
MDA50 J13 J14 CLKA1 MDB49 AF9 B_BA1
DQA1_18/DQA_50 CLKA1 DQB1_17/DQB_49 (7) B_BA1
MDA51 H11 H14 CLKA1# MDB50 AG8 AD8 CLKB1 B_BA2
DQA1_19/DQA_51 CLKA1B DQB1_18/DQB_50 CLKB1 (7) B_BA2
MDA52 G10 MDB51 AG7 AD7 CLKB1#
MDA53 G8 DQA1_20/DQA_52 K23 RASA0# MDB52 AK9 DQB1_19/DQB_51 CLKB1B
MDA54 K9 DQA1_21/DQA_53 RASA0B K19 RASA1# MDB53 AL7 DQB1_20/DQB_52 T10 RASB0#
MDA55 K10 DQA1_22/DQA_54 RASA1B MDB54 AM8 DQB1_21/DQB_53 RASB0B Y10 RASB1#
MDA56 G9 DQA1_23/DQA_55 K20 CASA0# MDB55 AM7 DQB1_22/DQB_54 RASB1B
MDA57 A8 DQA1_24/DQA_56 CASA0B K17 CASA1# MDB56 AK1 DQB1_23/DQB_55 W10 CASB0#
+MVDD MDA58 C8 DQA1_25/DQA_57 CASA1B MDB57 AL4 DQB1_24/DQB_56 CASB0B AA10 CASB1#
MDA59 E8 DQA1_26/DQA_58 K24 CSA0#_0 MDB58 AM6 DQB1_25/DQB_57 CASB1B
MDA60 A6 DQA1_27/DQA_59 CSA0B_0 K27 CSA0#_1 +MVDD MDB59 AM1 DQB1_26/DQB_58 P10 CSB0#_0
MDA61 C6 DQA1_28/DQA_60 CSA0B_1 MDB60 AN4 DQB1_27/DQB_59 CSB0B_0 L10 CSB0#_1
R137 MDA62 E6 DQA1_29/DQA_61 M13 CSA1#_0 MDB61 AP3 DQB1_28/DQB_60 CSB0B_1
40.2R MDA63 A5 DQA1_30/DQA_62 CSA1B_0 K16 CSA1#_1 MDB62 AP1 DQB1_29/DQB_61 AD10 CSB1#_0
DQA1_31/DQA_63 CSA1B_1 R5693 MDB63 AP5 DQB1_30/DQB_62 CSB1B_0 AC10 CSB1#_1
MVREFDA L18 K21 CKEA0 40.2R DQB1_31/DQB_63 CSB1B_1
C
MVREFSA L20 MVREFDA CKEA0 J20 CKEA1 U10 CKEB0 C
+MVDD MVREFSA CKEA1 MVREFDB Y12 CKEB0 AA11 CKEB1
R138 C149 R6081 243R L27 K26 WEA0# MVREFSB AA12 MVREFDB CKEB1
100R 100nF_6.3V R6082 243R N12 MEM_CALRN0 WEA0B L15 WEA1# 35mil MVREFSB N10 WEB0#
+MVDD R6083 243R AG12 MEM_CALRN1 WEA1B R5694 C5670 WEB0B AB11 WEB1#
MEM_CALRN2 TP12 WEB1B
100R 100nF_6.3V +VDDR3
R6084 243R M12 H23 +MVDD R1171 10K DNI
R6085 243R M27 MEM_CALRP1 MAA0_8 J19 R43 10K TESTEN AD28 T8
GDDR5

R148 R6086 243R AH12 MEM_CALRP0 MAA1_8 TESTEN MAB0_8 W8

GDDR5
40.2R MEM_CALRP2 CLKTESTA AK10 MAB1_8
R5695 TP7 35mil CLKTESTB AL10 CLKTESTA AH11 R1000 10R R1001 49.9R
40.2R TP8 35mil CLKTESTB DRAM_RST MEM_RST (6,7)

R163 C1000
R149 C148 C7118 C7119 5.1K 120pF_50V
100R 100nF_6.3V 100nF_6.3V 100nF_6.3V
Broadway R5696 C5671 DNI DNI
100R 100nF_6.3V Broadway
R157 R156
51.1R 51.1R
DNI DNI

Route 50ohms
single-ended/100ohms
diff and keep short

D D

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

© 2007 Advanced Micro Devices Advanced Micro Devices Inc.
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement 1 Commerce Valley Drive East
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose Markham, Ontario
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,
Date: Friday, December 11, 2009 Rev
3
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting Sheet 5 of 17
from use of the information included herein.
Title Doc No.
MADISON GDDR3 MxM3.0 105-B985xx-00D
1 2 3 4 5 6 7 8
 5 4 3 2 1

GDDR3 32MX32 MEMORY

U50 +MVDD U51 +MVDD A_BA0

(5) A_BA0
MDA9 T3 A1 MDA61 T3 A1 A_BA1
DQ31 | DQ23 VDDQ DQ31 | DQ23 VDDQ (5) A_BA1
MDA10 T2 A12 MDA62 T2 A12 A_BA2
DQ30 | DQ22 VDDQ#A12 DQ30 | DQ22 VDDQ#A12 (5) A_BA2
MDA8 R3 C1 MDA60 R3 C1
MDA11 R2 DQ29 | DQ21 VDDQ#C1 C4 MDA63 R2 DQ29 | DQ21 VDDQ#C1 C4
MDA13 M3 DQ28 | DQ20 VDDQ#C4 C9 MDA58 M3 DQ28 | DQ20 VDDQ#C4 C9 MAA[12..0]
DQ27 | DQ19 VDDQ#C9 DQ27 | DQ19 VDDQ#C9 (5) MAA[12..0]
MDA15 N2 C12 MDA59 N2 C12
D
MDA12 L3 DQ26 | DQ18 VDDQ#C12 E1 MDA57 L3 DQ26 | DQ18 VDDQ#C12 E1 WDQSA[7..0] D
DQ25 | DQ17 VDDQ#E1 DQ25 | DQ17 VDDQ#E1 (5) WDQSA[7..0]
MDA14 M2 E4 MDA56 M2 E4
MDA3 T10 DQ24 | DQ16 VDDQ#E4 E9 MDA54 T10 DQ24 | DQ16 VDDQ#E4 E9 RDQSA[7..0]
DQ23 | DQ31 VDDQ#E9 DQ23 | DQ31 VDDQ#E9 (5) RDQSA[7..0]
MDA0 T11 E12 MDA53 T11 E12
MDA2 R10 DQ22 | DQ30 VDDQ#E12 J4 MDA55 R10 DQ22 | DQ30 VDDQ#E12 J4 DQMA#[7..0]
DQ21 | DQ29 VDDQ#J4 DQ21 | DQ29 VDDQ#J4 (5) DQMA#[7..0]
MDA1 R11 J9 MDA52 R11 J9
MDA4 M10 DQ20 | DQ28 VDDQ#J9 N1 MDA51 M10 DQ20 | DQ28 VDDQ#J9 N1 MDA[63..0]
DQ19 | DQ27 VDDQ#N1 DQ19 | DQ27 VDDQ#N1 (5) MDA[63..0]
MDA7 N11 N4 MDA50 N11 N4
MDA5 L10 DQ18 | DQ26 VDDQ#N4 N9 MDA49 L10 DQ18 | DQ26 VDDQ#N4 N9
MDA6 M11 DQ17 | DQ25 VDDQ#N9 N12 MDA48 M11 DQ17 | DQ25 VDDQ#N9 N12
MDA24 G10 DQ16 | DQ24 VDDQ#N12 R1 MDA47 G10 DQ16 | DQ24 VDDQ#N12 R1 MEM_RST
DQ15 | DQ7 VDDQ#R1 DQ15 | DQ7 VDDQ#R1 (5,7) MEM_RST
MDA27 F11 R4 MDA44 F11 R4
MDA26 F10 DQ14 | DQ6 VDDQ#R4 R9 MDA46 F10 DQ14 | DQ6 VDDQ#R4 R9
MDA25 E11 DQ13 | DQ5 VDDQ#R9 R12 MDA45 E11 DQ13 | DQ5 VDDQ#R9 R12
MDA30 C10 DQ12 | DQ4 VDDQ#R12 V1 MDA40 C10 DQ12 | DQ4 VDDQ#R12 V1
MDA28 C11 DQ11 | DQ3 VDDQ#V1 V12 MDA42 C11 DQ11 | DQ3 VDDQ#V1 V12
MDA29 B10 DQ10 | DQ2 VDDQ#V12 MDA43 B10 DQ10 | DQ2 VDDQ#V12
MDA31 B11 DQ9 | DQ1 A2 MDA41 B11 DQ9 | DQ1 A2
MDA17 G3 DQ8 | DQ0 VDD A11 MDA36 G3 DQ8 | DQ0 VDD A11 GDDR3 MEMORY CONTROL SIGNAL PULLUP RESISTOR VALUES MAY CHANGE.
MDA18 F2 DQ7 | DQ15 VDD#A11 F1 MDA37 F2 DQ7 | DQ15 VDD#A11 F1 SEE LAYOUT GUIDE FOR LATEST INFORMATION
MDA16 F3 DQ6 | DQ14 VDD#F1 F12 MDA39 F3 DQ6 | DQ14 VDD#F1 F12 +MVDD
MDA19 E2 DQ5 | DQ13 VDD#F12 M1 MDA38 E2 DQ5 | DQ13 VDD#F12 M1
MDA22 C3 DQ4 | DQ12 VDD#M1 M12 MDA34 C3 DQ4 | DQ12 VDD#M1 M12 RASA0# R5697 121R
DQ3 | DQ11 VDD#M12 DQ3 | DQ11 VDD#M12 (5) RASA0#
MDA23 C2 V2 MDA32 C2 V2 RASA1# R5698 121R
DQ2 | DQ10 VDD#V2 DQ2 | DQ10 VDD#V2 (5) RASA1#
MDA20 B3 V11 MDA35 B3 V11
MDA21 B2 DQ1 | DQ9 VDD#V11 MDA33 B2 DQ1 | DQ9 VDD#V11 CASA0# R5699 121R
DQ0 | DQ8 DQ0 | DQ8 (5) CASA0#
B1 B1 CASA1# R5700 121R
VSSQ VSSQ (5) CASA1#
B4 B4
RASA0# H10 VSSQ#B4 B9 A_BA2 H10 VSSQ#B4 B9 WEA0# R5701 121R
BA2 | RAS VSSQ#B9 BA2 | RAS VSSQ#B9 (5) WEA0#
A_BA0 G9 B12 A_BA1 G9 B12 WEA1# R5702 121R
BA1 | BA0 VSSQ#B12 BA1 | BA0 VSSQ#B12 (5) WEA1#
A_BA1 G4 D1 A_BA0 G4 D1
BA0 | BA1 VSSQ#D1 D4 BA0 | BA1 VSSQ#D1 D4
MAA7 L4 VSSQ#D4 D9 MAA11 L4 VSSQ#D4 D9
MAA8 K2 A11 | A7 VSSQ#D9 D12 MAA10 K2 A11 | A7 VSSQ#D9 D12
MAA3 M9 A10 | A8 VSSQ#D12 G2 MAA9 M9 A10 | A8 VSSQ#D12 G2 CSA0#_0 R5703 121R
A9 | A3 VSSQ#G2 A9 | A3 VSSQ#G2 (5) CSA0#_0
MAA10 K11 G11 MAA8 K11 G11 CSA1#_0 R5704 121R
A8/AP | A10 VSSQ#G11 A8/AP | A10 VSSQ#G11 (5) CSA1#_0
MAA11 L9 L2 MAA7 L9 L2 CSA0#_1 R5796 121R
MAA2 K10 A7 | A11 VSSQ#L2 L11 MAA6 K10 A7 | A11 VSSQ#L2 L11 (5) CSA0#_1 CSA1#_1 R5797 121R
C C
MAA1 H11 A6 | A2 VSSQ#L11 P1 MAA5 H11 A6 | A2 VSSQ#L11 P1 (5) CSA1#_1
MAA0 K9 A5 | A1 VSSQ#P1 P4 MAA4 K9 A5 | A1 VSSQ#P1 P4
MAA9 M4 A4 | A0 VSSQ#P4 P9 MAA3 M4 A4 | A0 VSSQ#P4 P9
MAA6 K3 A3 | A9 VSSQ#P9 P12 MAA2 K3 A3 | A9 VSSQ#P9 P12 CKEA0 R5706 121R
A2 | A6 VSSQ#P12 A2 | A6 VSSQ#P12 (5) CKEA0
MAA5 H2 T1 MAA1 H2 T1 CKEA1 R5705 121R
A1 | A5 VSSQ#T1 A1 | A5 VSSQ#T1 (5,14) CKEA1
MAA4 K4 T4 MAA0 K4 T4
A0 | A4 VSSQ#T4 T9 A0 | A4 VSSQ#T4 T9
CASA0# F9 VSSQ#T9 T12 CSA1#_0 F9 VSSQ#T9 T12 CLKA0 R5707 60.4R
CS | CAS VSSQ#T12 CS | CAS VSSQ#T12 (5,14) CLKA0
A3 A3 CLKA0# R5708 60.4R
VSS VSS (5) CLKA0#
CKEA0 H9 A10 WEA1# H9 A10
WE | CKE VSS#A10 G1 WE | CKE VSS#A10 G1
A_BA2 H3 VSS#G1 G12 RASA1# H3 VSS#G1 G12
RAS | BA2 VSS#G12 L1 RAS | BA2 VSS#G12 L1 CLKA1 R5709 60.4R
VSS#L1 VSS#L1 (5,14) CLKA1
DRAM Scan pins CSA0#_0 F4 L12 CASA1# F4 L12 CLKA1# R5710 60.4R
CAS | CS VSS#L12 CAS | CS VSS#L12 (5) CLKA1#
SSH [V9] - Scan shift V3 V3
SCK [F9] - Scan clock WEA0# H4 VSS#V3 V10 CKEA1 H4 VSS#V3 V10
SOUT [D2] - Scan output CKE | WE VSS#V10 CKE | WE VSS#V10
SEN [V4] - Scan enable CLKA0# J10 CLKA1# J10
CLKA0 J11 CK K1 B10075 BLM15BD121SN1 CLKA1 J11 CK K1 B10077 BLM15BD121SN1
SOE# [A9] - Scan output enable
CK VDDA K12 B10076 BLM15BD121SN1 CK VDDA K12 B10078 BLM15BD121SN1
RDQSA1 P3 VDDA#K12 RDQSA7 P3 VDDA#K12
RDQSA0 P10 RDQS3 | RDQS2 RDQSA6 P10 RDQS3 | RDQS2
RDQSA3 D10 RDQS2 | RDQS3 C5672 C5673 RDQSA5 D10 RDQS2 | RDQS3 C5674 C5675
RDQSA2 D3 RDQS1 | RDQS0 100nF_6.3V 100nF_6.3V RDQSA4 D3 RDQS1 | RDQS0 100nF_6.3V 100nF_6.3V
RDQS0 | RDQS1 RDQS0 | RDQS1
WDQSA1 P2 WDQSA7 P2
WDQSA0 P11 WDQS3 | WDQS2 J12 WDQSA6 P11 WDQS3 | WDQS2 J12
WDQSA3 D11 WDQS2 | WDQS3 VSSA#J12 J1 WDQSA5 D11 WDQS2 | WDQS3 VSSA#J12 J1
WDQSA2 D2 WDQS1 | WDQS0 VSSA WDQSA4 D2 WDQS1 | WDQS0 VSSA
WDQS0 | WDQS1 WDQS0 | WDQS1
DQMA#1 N3 J3 CSA0#_1 DQMA#7 N3 J3 CSA1#_1
DQMA#0 N10 DM3 | DM2 RFU2 DQMA#6 N10 DM3 | DM2 RFU2
DQMA#3 E10 DM2 | DM3 J2 MAA12 DQMA#5 E10 DM2 | DM3 J2 MAA12
+MVDD DQMA#2 E3 DM1 | DM0 RFU1 +MVDD +MVDD DQMA#4 E3 DM1 | DM0 RFU1 +MVDD
DM0 | DM1 V4 R5742 1K DNI DM0 | DM1 V4 R5744 1K DNI
MEM_RST V9 RFU0 R5741 1K MEM_RST V9 RFU0 R5743 1K
RESET RESET
B B
R50 R5711 243R A4 R51 R5712 243R A4
2.37K ZQ 2.37K ZQ

VREF = 0.7*VDDQ H1 +MVDD VREF = 0.7*VDDQ H1

VREF A9 R5751 1K VREF A9 R5752 1K
H12 MF H12 MF
R52 +MVDD VREF#H12 GND | VDD R53 +MVDD VREF#H12 GND | VDD
5.49K C5921 5.49K C42
100nF_6.3V 100nF_6.3V
R5713 R5714
2.37K K4J55323QG-BC14 2.37K K4J55323QG-BC14

VREF = 0.7*VDDQ VREF = 0.7*VDDQ

PLACE VREF DIVIDER COMPONENTS PLACE VREF DIVIDER COMPONENTS

R5715 AS CLOSE TO MEMORY AS POSSIBLE R5716 AS CLOSE TO MEMORY AS POSSIBLE
5.49K C5676 5.49K C5677
100nF_6.3V 100nF_6.3V

+MVDD +MVDD
C1246 100nF_6.3V

C1247 100nF_6.3V

C1248 100nF_6.3V

C1249 100nF_6.3V

C1250 100nF_6.3V

C1251 100nF_6.3V

C1252 100nF_6.3V

C1253 100nF_6.3V

C1254 100nF_6.3V

C1255 100nF_6.3V

C1257 1uF_6.3V

C1258 1uF_6.3V

C1259 1uF_6.3V

C1260 1uF_6.3V

C1261 1uF_6.3V

C1262 1uF_6.3V

C1267 100nF_6.3V

C1268 100nF_6.3V

C1269 100nF_6.3V

C1270 100nF_6.3V

C1271 100nF_6.3V

C1272 100nF_6.3V

C1273 100nF_6.3V

C1274 100nF_6.3V

C1275 100nF_6.3V

C1276 100nF_6.3V

C1278 1uF_6.3V

C1279 1uF_6.3V

C1280 1uF_6.3V

C1281 1uF_6.3V

C1282 1uF_6.3V

C1283 1uF_6.3V
A A

+MVDD +MVDD

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

C1325 C1334 C1335 C1361 C1339 C1340 © 2007 Advanced Micro Devices Advanced Micro Devices Inc.
10uF_4V 10uF_4V 10uF_4V 10uF_4V 10uF_4V 10uF_4V This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement 1 Commerce Valley Drive East
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose Markham, Ontario
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,
Date: Friday, December 11, 2009 Rev
3
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting Sheet 6 of 17
from use of the information included herein.
Title Doc No.
MADISON GDDR3 MxM3.0 105-B985xx-00D
5 4 3 2 1
 5 4 3 2 1

GDDR3 32MX32 MEMORY

U52 +MVDD U53 +MVDD
MDB10 T3 A1 MDB61 T3 A1
MDB11 T2 DQ31 | DQ23 VDDQ A12 MDB62 T2 DQ31 | DQ23 VDDQ A12
MDB9 R3 DQ30 | DQ22 VDDQ#A12 C1 MDB60 R3 DQ30 | DQ22 VDDQ#A12 C1
MDB8 R2 DQ29 | DQ21 VDDQ#C1 C4 MDB63 R2 DQ29 | DQ21 VDDQ#C1 C4
MDB13 M3 DQ28 | DQ20 VDDQ#C4 C9 MDB58 M3 DQ28 | DQ20 VDDQ#C4 C9
MDB15 N2 DQ27 | DQ19 VDDQ#C9 C12 MDB59 N2 DQ27 | DQ19 VDDQ#C9 C12 WDQSB[7..0]
DQ26 | DQ18 VDDQ#C12 DQ26 | DQ18 VDDQ#C12 (5) WDQSB[7..0]
MDB12 L3 E1 MDB57 L3 E1
MDB14 M2 DQ25 | DQ17 VDDQ#E1 E4 MDB56 M2 DQ25 | DQ17 VDDQ#E1 E4 RDQSB[7..0]
DQ24 | DQ16 VDDQ#E4 DQ24 | DQ16 VDDQ#E4 (5) RDQSB[7..0]
MDB2 T10 E9 MDB55 T10 E9
D
MDB0 T11 DQ23 | DQ31 VDDQ#E9 E12 MDB53 T11 DQ23 | DQ31 VDDQ#E9 E12 DQMB#[7..0] D
DQ22 | DQ30 VDDQ#E12 DQ22 | DQ30 VDDQ#E12 (5) DQMB#[7..0]
MDB3 R10 J4 MDB54 R10 J4
MDB1 R11 DQ21 | DQ29 VDDQ#J4 J9 MDB52 R11 DQ21 | DQ29 VDDQ#J4 J9 MDB[63..0]
DQ20 | DQ28 VDDQ#J9 DQ20 | DQ28 VDDQ#J9 (5) MDB[63..0]
MDB6 M10 N1 MDB48 M10 N1
MDB7 N11 DQ19 | DQ27 VDDQ#N1 N4 MDB50 N11 DQ19 | DQ27 VDDQ#N1 N4 MAB[12..0]
DQ18 | DQ26 VDDQ#N4 DQ18 | DQ26 VDDQ#N4 (5) MAB[12..0]
MDB4 L10 N9 MDB49 L10 N9
MDB5 M11 DQ17 | DQ25 VDDQ#N9 N12 MDB51 M11 DQ17 | DQ25 VDDQ#N9 N12 B_BA0
DQ16 | DQ24 VDDQ#N12 DQ16 | DQ24 VDDQ#N12 (5) B_BA0
MDB24 G10 R1 MDB46 G10 R1 B_BA1
DQ15 | DQ7 VDDQ#R1 DQ15 | DQ7 VDDQ#R1 (5) B_BA1
MDB27 F11 R4 MDB45 F11 R4 B_BA2
DQ14 | DQ6 VDDQ#R4 DQ14 | DQ6 VDDQ#R4 (5) B_BA2
MDB25 F10 R9 MDB47 F10 R9
MDB26 E11 DQ13 | DQ5 VDDQ#R9 R12 MDB44 E11 DQ13 | DQ5 VDDQ#R9 R12
MDB28 C10 DQ12 | DQ4 VDDQ#R12 V1 MDB40 C10 DQ12 | DQ4 VDDQ#R12 V1
MDB29 C11 DQ11 | DQ3 VDDQ#V1 V12 MDB43 C11 DQ11 | DQ3 VDDQ#V1 V12 MEM_RST
DQ10 | DQ2 VDDQ#V12 DQ10 | DQ2 VDDQ#V12 (5,6) MEM_RST
MDB31 B10 MDB41 B10
MDB30 B11 DQ9 | DQ1 A2 MDB42 B11 DQ9 | DQ1 A2
MDB19 G3 DQ8 | DQ0 VDD A11 MDB39 G3 DQ8 | DQ0 VDD A11
MDB17 F2 DQ7 | DQ15 VDD#A11 F1 MDB38 F2 DQ7 | DQ15 VDD#A11 F1
MDB18 F3 DQ6 | DQ14 VDD#F1 F12 MDB37 F3 DQ6 | DQ14 VDD#F1 F12
MDB20 E2 DQ5 | DQ13 VDD#F12 M1 MDB32 E2 DQ5 | DQ13 VDD#F12 M1 GDDR3 MEMORY CONTROL SIGNAL PULLUP RESISTOR VALUES MAY CHANGE.
MDB21 C3 DQ4 | DQ12 VDD#M1 M12 MDB36 C3 DQ4 | DQ12 VDD#M1 M12 SEE LAYOUT GUIDE FOR LATEST INFORMATION
MDB22 C2 DQ3 | DQ11 VDD#M12 V2 MDB34 C2 DQ3 | DQ11 VDD#M12 V2
MDB23 B3 DQ2 | DQ10 VDD#V2 V11 MDB33 B3 DQ2 | DQ10 VDD#V2 V11 +MVDD
MDB16 B2 DQ1 | DQ9 VDD#V11 MDB35 B2 DQ1 | DQ9 VDD#V11
DQ0 | DQ8 B1 DQ0 | DQ8 B1 RASB0# R5718 121R
VSSQ VSSQ (5) RASB0#
B4 B4 RASB1# R5717 121R
VSSQ#B4 VSSQ#B4 (5) RASB1#
RASB0# H10 B9 B_BA2 H10 B9
B_BA0 G9 BA2 | RAS VSSQ#B9 B12 B_BA1 G9 BA2 | RAS VSSQ#B9 B12 CASB0# R5719 121R
BA1 | BA0 VSSQ#B12 BA1 | BA0 VSSQ#B12 (5) CASB0#
B_BA1 G4 D1 B_BA0 G4 D1 CASB1# R5720 121R
BA0 | BA1 VSSQ#D1 BA0 | BA1 VSSQ#D1 (5) CASB1#
D4 D4
MAB7 L4 VSSQ#D4 D9 MAB11 L4 VSSQ#D4 D9 WEB0# R5722 121R
A11 | A7 VSSQ#D9 A11 | A7 VSSQ#D9 (5) WEB0#
MAB8 K2 D12 MAB10 K2 D12 WEB1# R5721 121R
A10 | A8 VSSQ#D12 A10 | A8 VSSQ#D12 (5) WEB1#
MAB3 M9 G2 MAB9 M9 G2
MAB10 K11 A9 | A3 VSSQ#G2 G11 MAB8 K11 A9 | A3 VSSQ#G2 G11 CSB0#_0 R5723 121R
A8/AP | A10 VSSQ#G11 A8/AP | A10 VSSQ#G11 (5) CSB0#_0
MAB11 L9 L2 MAB7 L9 L2 CSB1#_0 R5724 121R
A7 | A11 VSSQ#L2 A7 | A11 VSSQ#L2 (5) CSB1#_0
MAB2 K10 L11 MAB6 K10 L11 CSB0#_1 R5799 121R
A6 | A2 VSSQ#L11 A6 | A2 VSSQ#L11 (5) CSB0#_1
MAB1 H11 P1 MAB5 H11 P1 CSB1#_1 R5798 121R
A5 | A1 VSSQ#P1 A5 | A1 VSSQ#P1 (5) CSB1#_1
MAB0 K9 P4 MAB4 K9 P4
MAB9 M4 A4 | A0 VSSQ#P4 P9 MAB3 M4 A4 | A0 VSSQ#P4 P9
C C
MAB6 K3 A3 | A9 VSSQ#P9 P12 MAB2 K3 A3 | A9 VSSQ#P9 P12
MAB5 H2 A2 | A6 VSSQ#P12 T1 MAB1 H2 A2 | A6 VSSQ#P12 T1 CKEB0 R5725 121R
A1 | A5 VSSQ#T1 A1 | A5 VSSQ#T1 (5) CKEB0
MAB4 K4 T4 MAB0 K4 T4 CKEB1 R5726 121R
A0 | A4 VSSQ#T4 A0 | A4 VSSQ#T4 (5,14) CKEB1
T9 T9
CASB0# F9 VSSQ#T9 T12 CSB1#_0 F9 VSSQ#T9 T12
CS | CAS VSSQ#T12 A3 CS | CAS VSSQ#T12 A3
CKEB0 H9 VSS A10 WEB1# H9 VSS A10 CLKB0 R5727 60.4R
WE | CKE VSS#A10 WE | CKE VSS#A10 (5,14) CLKB0
G1 G1 CLKB0# R5728 60.4R
VSS#G1 VSS#G1 (5,14) CLKB0#
B_BA2 H3 G12 RASB1# H3 G12
RAS | BA2 VSS#G12 L1 RAS | BA2 VSS#G12 L1
CSB0#_0 F4 VSS#L1 L12 CASB1# F4 VSS#L1 L12
CAS | CS VSS#L12 V3 CAS | CS VSS#L12 V3 CLKB1 R5729 60.4R
VSS#V3 VSS#V3 (5,14) CLKB1
WEB0# H4 V10 CKEB1 H4 V10 CLKB1# R5730 60.4R
CKE | WE VSS#V10 CKE | WE VSS#V10 (5,14) CLKB1#
CLKB0# J10 CLKB1# J10
CLKB0 J11 CK K1 B10079 BLM15BD121SN1 CLKB1 J11 CK K1 B10082 BLM15BD121SN1
CK VDDA K12 B10080 BLM15BD121SN1 CK VDDA K12 B10081 BLM15BD121SN1
RDQSB1 P3 VDDA#K12 RDQSB7 P3 VDDA#K12
DRAM Scan pins RDQSB0 P10 RDQS3 | RDQS2 RDQSB6 P10 RDQS3 | RDQS2
SSH [V9] - Scan shift RDQSB3 D10 RDQS2 | RDQS3 C5678 C5679 RDQSB5 D10 RDQS2 | RDQS3 C5680 C5681
SCK [F9] - Scan clock RDQSB2 D3 RDQS1 | RDQS0 100nF_6.3V 100nF_6.3V RDQSB4 D3 RDQS1 | RDQS0 100nF_6.3V 100nF_6.3V
SOUT [D2] - Scan output RDQS0 | RDQS1 RDQS0 | RDQS1
SEN [V4] - Scan enable WDQSB1 P2 WDQSB7 P2
WDQSB0 P11 WDQS3 | WDQS2 J12 WDQSB6 P11 WDQS3 | WDQS2 J12
SOE# [A9] - Scan output enable
WDQSB3 D11 WDQS2 | WDQS3 VSSA#J12 J1 WDQSB5 D11 WDQS2 | WDQS3 VSSA#J12 J1
WDQSB2 D2 WDQS1 | WDQS0 VSSA WDQSB4 D2 WDQS1 | WDQS0 VSSA
WDQS0 | WDQS1 WDQS0 | WDQS1
DQMB#1 N3 J3 CSB0#_1 DQMB#7 N3 J3 CSB1#_1
DQMB#0 N10 DM3 | DM2 RFU2 DQMB#6 N10 DM3 | DM2 RFU2
DQMB#3 E10 DM2 | DM3 J2 MAB12 DQMB#5 E10 DM2 | DM3 J2 MAB12
DQMB#2 E3 DM1 | DM0 RFU1 +MVDD +MVDD DQMB#4 E3 DM1 | DM0 RFU1 +MVDD
+MVDD DM0 | DM1 V4 R5746 1K DNI DM0 | DM1 V4 R5748 1K DNI
MEM_RST V9 RFU0 R5745 1K MEM_RST V9 RFU0 R5747 1K
RESET RESET
R152 R5731 243R A4 R153 R5732 243R A4
2.37K ZQ 2.37K ZQ

B B
VREF = 0.7*VDDQ H1 +MVDD VREF = 0.7*VDDQ H1
VREF A9 R5753 1K VREF A9 R5754 1K
+MVDD H12 MF +MVDD H12 MF
R65 VREF#H12 GND | VDD R154 VREF#H12 GND | VDD
5.49K C65 5.49K C64
100nF_6.3V R5733 100nF_6.3V R5734
2.37K 2.37K
K4J55323QG-BC14 K4J55323QG-BC14
VREF = 0.7*VDDQ VREF = 0.7*VDDQ

R5735 C5682 PLACE VREF DIVIDER COMPONENTS R5736 PLACE VREF DIVIDER COMPONENTS
5.49K 100nF_6.3V AS CLOSE TO MEMORY AS POSSIBLE 5.49K C5683 AS CLOSE TO MEMORY AS POSSIBLE
100nF_6.3V

+MVDD
+MVDD
C1288 100nF_6.3V

C1289 100nF_6.3V

C1290 100nF_6.3V

C1291 100nF_6.3V

C1292 100nF_6.3V

C1293 100nF_6.3V

C1294 100nF_6.3V

C1295 100nF_6.3V

C1296 100nF_6.3V

C1297 100nF_6.3V

C1299 1uF_6.3V

C1300 1uF_6.3V

C1301 1uF_6.3V

C1302 1uF_6.3V

C1303 1uF_6.3V

C1304 1uF_6.3V

C1225 100nF_6.3V

C1226 100nF_6.3V

C1227 100nF_6.3V

C1228 100nF_6.3V

C1229 100nF_6.3V

C1230 100nF_6.3V

C1231 100nF_6.3V

C1232 100nF_6.3V

C1233 100nF_6.3V

C1234 100nF_6.3V

C1236 1uF_6.3V

C1237 1uF_6.3V

C1238 1uF_6.3V

C1239 1uF_6.3V

C1240 1uF_6.3V

C1241 1uF_6.3V
+MVDD +MVDD
A A

C1352 C1359 C1353 C1320 C1321 C1322

10uF_4V 10uF_4V 10uF_4V 10uF_4V 10uF_4V 10uF_4V

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

© 2007 Advanced Micro Devices Advanced Micro Devices Inc.
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement 1 Commerce Valley Drive East
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose Markham, Ontario
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,
Date: Friday, December 11, 2009 Rev
3
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting Sheet 7 of 17
from use of the information included herein.
Title Doc No.
MADISON GDDR3 MxM3.0 105-B985xx-00D
5 4 3 2 1
 5 4 3 2 1

+3VRUN +3VRUN +3VRUN

PLACE CAPS ON THIS PAGE AS CLOSE TO CONNECTOR AS POSSIBLE J1A
+PWR_SRC E1 E2 C5978
E3 PWR_SRC_E1 PWR_SRC_E2 E4 R6097
GND_E3 GND_E4 100nF_6.3V
C5976 C5977 C5979 Part 1 of 4 R6095 100K

5
100nF_50V 100nF_50V 1nF 1 2 R6096 0R 100K
3 5V_1 PRSNT_R#_2 4 1
5V_3 WAKE#_4 (10) CTFb
5 6 4 RUNPWROK
5V_5 PWR_GOOD_6 PWRGOOD (9) RUNPWROK (9)
+VDDR3 +VDDR3 7 8 R6098 0R 2
9 5V_7 PWR_EN_8 10 U5511
+5VRUN 5V_9 RSVD_10
11 12 NC7SZ08P5X_NL

3
R6227 R6228 C5980 C5981 13 GND_11 RSVD_12 14
100K 100K 100nF_6.3V 15 GND_13 RSVD_14 16
1uF_6.3V
DNI 17 GND_15 RSVD_16 18 PWR_LEVEL R6089 0R R6090 0R
(2,9) GPIO0 GND_17 PWR_LEVEL_18 GPIO5_AC_BATT (2) CTFb (10)
R6099 0R PEX_STD_SW# 19 20 TH_OVERT#
(2,9) GPIO1 PEX_STD_SW#_19 TH_OVERT#_20 MB_THERMB (9)
R6101 0R DNI VGA_DISABLE# 21 22 TH_ALERT# R6100 0R DNI
VGA_DISABLE#_21 TH_ALERT#_22 GPIO17_THERMAL_INT (2,9)
6

3
FPVCC_MB 23 24 TH_PWM
PNL_PWR_EN_23 TH_PWM_24 TH_PWM (9)
Q5536A Q5536B BL_ENA 25 26 MB_GPIO0
D PNL_BL_EN_25 GPIO0_26 MB_GPIO0 (2) D
BL_BRIGHT_MB 27 28 MB_GPIO1
PNL_PWM_27 GPIO1_28 MB_GPIO1 (2)
2 5 29 30 MB_GPIO2 R1130 R6123 R6125 R6126
HDMI_CEC_29 GPIO2_30 MB_GPIO2 (2)
2N7002 2N7002 DVI_HPD 31 32 SMB_DAT 100K 2.61K 100K 100K
33 DVI_HPD_31 SMB_DAT_32 34 SMB_CLK DNI DNI
(2) DDC3DATA
1

4
35 LVDS_DDC_DAT_33 SMB_CLK_34 36
(2) DDC3CLK LVDS_DDC_CLK_35 GND_36
37 38
39 GND_37 OEM_38 40 +VDDR3 +VDDR3 +VDDR3 +VDDR3
R6225 R6226 41 OEM_39 OEM_40 42
4.7K 4.7K 43 OEM_41 OEM_42 44
45 OEM_43 OEM_44 46
47 OEM_45 GND_46 48 PCIE_RXN15
PCIE_TXN15 49 GND_47 PEX_TX15#_48 50 PCIE_RXP15
+VDDR3 PCIE_TXP15 51 PEX_RX15#_49 PEX_TX15_50 52
53 PEX_RX15_51 GND_52 54 PCIE_RXN14
PCIE_TXN14 55 GND_53 PEX_TX14#_54 56 PCIE_RXP14
PCIE_TXP14 57 PEX_RX14#_55 PEX_TX14_56 58
R6207 10K 59 PEX_RX14_57 GND_58 60 PCIE_RXN13
(2,9) GPIO9 GND_59 PEX_TX13#_60
DNI PCIE_TXN13 61 62 PCIE_RXP13
PEX_RX13#_61 PEX_TX13_62
3

PCIE_TXP13 63 64
Q5537 65 PEX_RX13_63 GND_64 66 PCIE_RXN12
2N7002E PCIE_TXN12 67 GND_65 PEX_TX12#_66 68 PCIE_RXP12 R6103 0R
DNI 1 PCIE_TXP12 69 PEX_RX12#_67 PEX_TX12_68 70
71 PEX_RX12_69 GND_70 72 PCIE_RXN11 BL_ENA DNI R6104 0R
GND_71 PEX_TX11#_72 BLON_PWM (2)
PCIE_TXN11 73 74 PCIE_RXP11
2

PCIE_TXP11 75 PEX_RX11#_73 PEX_TX11_74 76 R6105 0R

PEX_RX11_75 GND_76 GPIO7_BLON (2)
77 78 PCIE_RXN10
PCIE_TXN10 79 GND_77 PEX_TX10#_78 80 PCIE_RXP10
STRAP OPTIONS FROM MOTEHRBOARD PCIE_TXP10 81 PEX_RX10#_79 PEX_TX10_80 82
PEX_RX10_81 GND_82 The circuit is an option to prevent the leakage from LCD
83 84 PCIE_RXN9
PCIE_TXN9 85 GND_83 PEX_TX9#_84 86 PCIE_RXP9 U5512
PCIE_TXP9 87 PEX_RX9#_85 PEX_TX9_86 88 BL_BRIGHT_MB 6 2 BL_BRIGHT
89 PEX_RX9_87 GND_88 90 PCIE_RXN8 FPVCC_MB 3 1Y 1A 5 FPVCC
PCIE_TXN8 91 GND_89 PEX_TX8#_90 92 PCIE_RXP8 2Y 2A
PCIE_TXP8 93 PEX_RX8#_91 PEX_TX8_92 94 +3VRUN 8 1 R6106 0R
PEX_RX8_93 GND_94 PWRGOOD (9)
95 96 PCIE_RXN7 R6107 4 VCC 1OE 7
PCIE_TXN7 97 GND_95 PEX_TX7#_96 98 PCIE_RXP7 10K GND 2OE
PCIE_TXP7 99 PEX_RX7#_97 PEX_TX7_98 100 C5990 C5991
PEX_RX7_99 GND_100 74LVC2G126
C 101 102 PCIE_RXN6 100nF_6.3V 100nF_6.3V C
PCIE_TXN6 103 GND_101 PEX_TX6#_102 104 PCIE_RXP6
PCIE_TXP6 105 PEX_RX6#_103 PEX_TX6_104 106
107 PEX_RX6_105 GND_106 108 PCIE_RXN5
PCIE_REFCLKP PCIE_TXN5 109 GND_107 PEX_TX5#_108 110 PCIE_RXP5
(1) PCIE_REFCLKP PEX_RX5#_109 PEX_TX5_110
PCIE_REFCLKN PCIE_TXP5 111 112
(1) PCIE_REFCLKN PEX_RX5_111 GND_112
113 114 PCIE_RXN4 BL_BRIGHT_MB R6108 0R DNI BL_BRIGHT
PCIE_TXN4 115 GND_113 PEX_TX4#_114 116 PCIE_RXP4
PCIE_RXP[15..0] PCIE_TXP4 117 PEX_RX4#_115 PEX_TX4_116 118 FPVCC_MB R6109 0R DNI FPVCC
(1) PCIE_RXP[15..0] PEX_RX4_117 GND_118
119 120 PCIE_RXN3
PCIE_RXN[15..0] PCIE_TXN3 121 GND_119 PEX_TX3#_120 122 PCIE_RXP3
(1) PCIE_RXN[15..0] PEX_RX3#_121 PEX_TX3_122
PCIE_TXP3 123 124
PCIE_TXP[15..0] 125 PEX_RX3_123 GND_124
(1) PCIE_TXP[15..0] GND_125
PCIE_TXN[15..0] 133
Mechanical Key 134
(1) PCIE_TXN[15..0] GND_133 GND_134
PCIE_TXN2 135 136 PCIE_RXN2
PCIE_TXP2 137 PEX_RX2#_135 PEX_TX2#_136 138 PCIE_RXP2
139 PEX_RX2_137 PEX_TX2_138 140
PCIE_TXN1 141 GND_139 GND_140 142 PCIE_RXN1 +VDDR3
PCIE_TXP1 143 PEX_RX1#_141 PEX_TX1#_142 144 PCIE_RXP1
145 PEX_RX1_143 PEX_TX1_144 146
PCIE_TXN0 147 GND_145 GND_146 148 PCIE_RXN0 R6114
PCIE_TXP0 149 PEX_RX0#_147 PEX_TX0#_148 150 PCIE_RXP0 10K
151 PEX_RX0_149 PEX_TX0_150 152 DNI
PCIE_REFCLKN 153 GND_151 GND_152 154 R6113 0R DNI
PCIE_REFCLKP 155 PEX_REFCLK#_153 CLK_REQ#_154 156 GPIO23_CLKREQB (2)
PEX_REFCLK_155 PEX_RST#_156 PCIE_RST# (1,10)
TXOUT_L0- 157 158
(2) TXOUT_L0- GND_157 VGA_DDC_DAT_158
TXOUT_L0+ 159 160 R6115
(2) TXOUT_L0+ RSVD_159 VGA_DDC_CLK_160
TXOUT_L1- 161 162 10K
(2) TXOUT_L1- RSVD_161 VGA_VSYC_162 VSYNC_DAC2 (2,9)
TXOUT_L1+ 163 164
(2) TXOUT_L1+ RSVD_163 VGA_HSYC_164 HSYNC_DAC2 (2,9)
TXOUT_L2- 165 166
(2) TXOUT_L2- RSVD_165 GND_166
TXOUT_L2+ 167 168 VGA_RED
(2) TXOUT_L2+ RSVD_167 VGA_RED_168 VGA_RED (2) DDC5DATA (2)
TXOUT_L3- TXCLK_U- 169 170 VGA_GRN
(2) TXOUT_L3- LVDS_UCLK#_169 VGA_GREEN_170 VGA_GRN (2) DDC5CLK (2)
TXOUT_L3+ TXCLK_U+ 171 172 VGA_BLU
(2) TXOUT_L3+ LVDS_UCLK_171 VGA_BLUE_172 VGA_BLU (2)
TXCLK_L- 173 174
(2) TXCLK_L- GND_173 GND_174
TXCLK_L+ TXOUT_U3- 175 176 TXCLK_L- R6121 R6122
(2) TXCLK_L+ LVDS_UTX3#_175 LVDS_LCLK#_176
TXOUT_U3+ 177 178 TXCLK_L+ 4.7K 4.7K
TXOUT_U0- 179 LVDS_UTX3_177 LVDS_LCLK_178 180
B (2) TXOUT_U0- GND_179 GND_180 B
TXOUT_U0+ TXOUT_U2- 181 182 TXOUT_L3-
(2) TXOUT_U0+ LVDS_UTX2#_181 LVDS_LTX3#_182
TXOUT_U1- TXOUT_U2+ 183 184 TXOUT_L3+
(2) TXOUT_U1- LVDS_UTX2_183 LVDS_LTX3_184 +VDDR3
TXOUT_U1+ 185 186
(2) TXOUT_U1+ GND_185 GND_186
TXOUT_U2- TXOUT_U1- 187 188 TXOUT_L2-
(2) TXOUT_U2- LVDS_UTX1#_187 LVDS_LTX2#_188
TXOUT_U2+ TXOUT_U1+ 189 190 TXOUT_L2+
(2) TXOUT_U2+ LVDS_UTX1_189 LVDS_LTX2_190
TXOUT_U3- 191 192
(2) TXOUT_U3- GND_191 GND_192
TXOUT_U3+ TXOUT_U0- 193 194 TXOUT_L1-
(2) TXOUT_U3+ LVDS_UTX0#_193 LVDS_LTX1#_194
TXCLK_U- TXOUT_U0+ 195 196 TXOUT_L1+
(2) TXCLK_U- LVDS_UTX0_195 LVDS_LTX1_196
TXCLK_U+ 197 198
(2) TXCLK_U+ GND_197 GND_198
199 200 TXOUT_L0- +VDDR3 +VDDR3
(2) TX5M_DPB0N DP_C_L0#_199 LVDS_LTX0#_200
201 202 TXOUT_L0+
(2) TX5P_DPB0P DP_C_L0_201 LVDS_LTX0_202
203 204
FPVCC 205 GND_203 GND_204 206 R526 R6127
(2,4) FPVCC (2) TX4M_DPB1N DP_C_L1#_205 DP_D_L0#_206

1
207 208 100K DNI 10K
(2) TX4P_DPB1P DP_C_L1_207 DP_D_L0_208
209 210 Q62 DNI
211 GND_209 GND_210 212 SMB_CLK 3 2 R6222 0R
(2) TX3M_DPB2N DP_C_L2#_211 DP_D_L1#_212 GPIO4_SMBCLK (2)
213 214 DNI
(2) TX3P_DPB2P DP_C_L2_213 DP_D_L1_214
215 216 BSH111
217 GND_215 GND_216 218
(2) TXCBM_DPB3N DP_C_L3#_217 DP_D_L2#_218
219 220 R7122 0R DNI
(2) TXCBP_DPB3P DP_C_L3_219 DP_D_L2_220
221 222
223 GND_221 GND_222 224 R128 0R
(2) DDCDATA_AUX2N DP_C_AUX#_223 DP_D_L3#_224 SMBCLK (9)
225 226
(2) DDCCLK_AUX2P DP_C_AUX_225 DP_D_L3_226
227 228
229 RSVD_227 GND_228 230 +VDDR3 +VDDR3
231 RSVD_229 DP_D_AUX#_230 232
233 RSVD_231 DP_D_AUX_232 234 DP_C_HPD J1C J1D
DP_A_HPD 235 RSVD_233 DP_C_HPD_234 236 R651 R6128
(2) HPD1 RSVD_235 DP_D_HPD_236 Part 3 of 4 Part 4 of 4

1
237 238 100K DNI 10K
239 RSVD_237 RSVD_238 240 Q63 DNI
R6124 241 RSVD_239 RSVD_240 242 SMB_DAT 3 2 R6224 0R
RSVD_241 RSVD_242 GPIO3_SMBDATA (2)
100K 243 244 BSH111 DNI
RSVD_243 GND_244

G10
245 246

G1
G2
G3
G4
G5

G6
G7
G8
G9
247 RSVD_245 DP_B_L0#_246 248
249 RSVD_247 DP_B_L0_248 250 R7123 0R DNI

G1
G2
G3
G4
G5

G6
G7
G8
G9
G10
251 RSVD_249 GND_250 252
DP_C_HPD 253 GND_251 DP_B_L1#_252 254 R129 0R
(2) GPIO14_HPD2 (2) TX2M_DPA0N DP_A_L0#_253 DP_B_L1_254 SMBDATA (9)
A 255 256 A
(2) TX2P_DPA0P DP_A_L0_255 GND_256
257 258
R6116 259 GND_257 DP_B_L2#_258 260
(2) TX1M_DPA1N DP_A_L1#_259 DP_B_L2_260
100K 261 262
(2) TX1P_DPA1P DP_A_L1_261 GND_262
263 264
265 GND_263 DP_B_L3#_264 266
(2) TX0M_DPA2N DP_A_L2#_265 DP_B_L3_266 J1B
267 268
(2) TX0P_DPA2P DP_A_L2_267 GND_268
269 270 Part 2 of 4 CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
DVI_HPD 271 GND_269 DP_B_AUX#_270 272 MTG1 © 2007 Advanced Micro Devices Advanced Micro Devices Inc.
(2) GPIO18_HPD3 (2) TXCAM_DPA3N DP_A_L3#_271 DP_B_AUX_272 MTG1 This AMD Board schematic and design is the exclusive property of AMD,
273 274 MTG2
(2) TXCAP_DPA3P DP_A_L3_273 DP_B_HPD_274 +3VRUN MTG2 and is provided only to entities under a non-disclosure agreement 1 Commerce Valley Drive East
275 276 DP_A_HPD MTG3 with AMD for evaluation purposes. Further distribution or disclosure
R6102 277 GND_275 DP_A_HPD_276 278 MTG4 MTG3
(2) DDCDATA_AUX1N is strictly prohibited. Use of this schematic and design for any purpose Markham, Ontario
100K 279 DP_A_AUX#_277 3V3_278 280 MTG4 other than evaluation requires a Board Technology License Agreement
(2) DDCCLK_AUX1P DP_A_AUX_279 3V3_280 with AMD. AMD makes no representations or warranties of any kind
R6133 0R 281 C6016 C6017 C6018 Date: Friday, December 11, 2009 Rev
PRSNT_L#_281 10uF_.095 1uF_6.3V 1uF_6.3V
regarding this schematic and design, including, not limited to, 3
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting Sheet 8 of 17
from use of the information included herein.
Title Doc No.
MADISON GDDR3 MxM3.0 105-B985xx-00D
5 4 3 2 1
 5 4 3 2 1

CONFIGURATION STRAPS
PIN STRAPS
External Thermal Sensor ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
+VDDR3
THEY MUST NOT CONFLICT DURING RESET
(2,8) GPIO0 GPIO0 R6134 10K

+3VRUN GPIO1 R6135 10K STRAPS PIN DESCRIPTION OF DEFAULT SETTINGS Default Setting
(2,8) GPIO1
I2C option
(2) GPIO2 GPIO2 R6136 10K
R125 0R DNI C326 100nF_6.3V TX_PWRS_ENB GPIO0 Transmitter Power Savings Enable GPIO0 and GPIO1
(2) DDC6CLK 0: 50% Tx output swing pulls ups need to be 1
R126 0R DNI GPIO9 R6138 10K DNI 1: Full Tx output swing stuffed with Q5536 if
(2) DDC6DATA (2,8) GPIO9
U14 system board is
8 1 C329 2.2nF_50V TX_DEEMPH_EN GPIO1 PCIE Transmitter De-emphasis Enable controlling the PCIE 1
SCLK VDD GPIO11 R6139 10K 0: Tx de-emphasis disabled
(8) SMBCLK (2) GPIO11 swing.
D 1: Tx de-emphasis enabled D
7 2
SDATA D+ GPU_DPLUS (2)
(2) GPIO12 GPIO12 R6140 10K DNI
(8) SMBDATA
6 3 BIF_GEN2_EN_A GPIO2 PCIE Gen2 Enable 1
ALERT D- GPU_DMINUS (2) 0: Advertises the PCIE device as 2.5GT/s capable at power-on
(2) GPIO13 GPIO13 R6141 10K
5 4 1: Advertises the PCIE device as 5.0GT/s capable at power-on
GND THERM R220 0R DNI GPIO22 R6147 10K
MB_THERMB (8) (2) GPIO22
EMC1402-1-ACZL R221 0R DNI BIF_VGA DIS GPIO9 VGA Control GPIO9 pull up needs 0
R130 0R 0: VGA controller capacity enabled to be stuffed with
R131 0R DNI V1SYNC R6142 10K DNI 1: VGA controller capacity disabled (for multi-GPU) Q5537 if system
GPIO17_THERMAL_INT (2,8) (2) VSYNC_DAC1
board is controlling
R132 0R DNI H1SYNC R6143 10K the VGA capacity
TH_PWM (8) (2) HSYNC_DAC1
R133 0R DNI
(2) TS_FDO
V2SYNC R6145 10K ROMIDCFG[2:0] GPIO[13:11] Serial ROM type or Memory Aperture Size Select 101
(2,8) VSYNC_DAC2 If GPIO22 = 0, defines memory aperture size
If GPIO22 = 1, defines ROM type
H2SYNC R6146 10K DNI 100 - 512Kbit M25P05A (ST)
(2,8) HSYNC_DAC2 101 - 1Mbit M25P10A (ST)
101 - 2Mbit M25P20 (ST)
(2,10) GPIO21_BB_EN GPIO21_BBEN R6148 10K DNI 101 - 4Mbit M25P40 (ST)
101 - 8Mbit M25P80 (ST)
(2) GPIO8 GPIO8 R6137 10K DNI 100 - 512Kbit Pm25LV512 (Chingis)
101 - 1Mbit Pm25LV010 (Chingis)
BIOS_ROM_EN GPIO22 Enable external BIOS ROM device 1
0: Disabled
1: Enabled

AUD[1] HSYNC 00 - No audio function 10

AUD[0] VSYNC 01 - Audio for DP only
10 - Audio for DP and HDMI if dongle is detected
LDO Vin = +1.8V +/-5% Vout = +1.0V +/- 2% Iout = 1.7A RMS MAX 11 - Audio for both DP and HDMI
HDMI must only be enabled on systems that are legally entitled. It is the
responsibility of the system designer to ensure that the system is entitled to
PCB: 50 to 70mm sq. copper area for cooling support this feature.

VIP_DEVICE_STRAP_DIS V2SYNC VIP Device Strap Enable 1

0: Slave VIP host port devices present
1: No slave VIP host port devices reporting presence
C C

SMS_EN_HARD H2SYNC Reserved 0

+1.8V_REG GPIO21_BBEN GPIO21_BBEN Reserved
MR858 1R_1210 +5VRUN BIF_CLK_PM_EN GPIO8 Reserved
R858 0.50R
+1.0V_REG
MR859 1R_1210 +1.0V_REG
R859 0.50R
R853
Overlap 10K
TP850
footprints R1 R855 C852 C851 C854
Use 0.5R U851 2.67K C855 10uF_X6S 10uF_X6S 100nF_6.3V
PWRGOOD 1 8 33pF_50V
1/2W <=5% (8) PWRGOOD LDO_EN 2 POK GND#8 7 LDO_FB
LDO_VIN 3 EN FB 6
LDO_CNTL 4 VIN VOUT 5 R856 0R
CNTL REFIN
GND#9
9 DNI R2
C856 R854
10uF_X6S C858 uP7706U8 10.2K
1uF_6.3V

VOUT = Vref x (1 + R1/R2)

Vref = 0.8V

Power Up Sequence
B B

+PWR_SRC

10K VDDC_EN (11)

3

R848
R849 5.1K 1 Q845
MMBT3904
2
3

R847 5.1K 1 Q844

(8) RUNPWROK MMBT3904
2

C843
1uF_6.3V
DNI
+PWR_SRC

R6194 0R DNI
+MVDD R515
10K PWRGOOD (8)

3
DNI IF +1.8V_REG IS SHARED WITH +MVDD +VDDR3
+3VRUN Q5531 1 Q511
+PWR_SRC 2 3 R514 MMBT3904
1.8V_REG_EN (13)
1K

2
3

3
Si2301BDS C509
+VDDC R844 5.1K1 Q841 MVDDUP 1 Q509 100nF
1

R843 MMBT3904 MMBT3904 DNI

10K
2

2
R841 R6196 100K C508
A 1K 1uF_6.3V A
3

MVDD_EN (12) +MVDD

1 Q840 R6198 15K DNI DNI IF +1.8V_REG IS SHARED WITH +MVDD
3

MMBT3904
3

R846 5.1K1 Q842 Q5534

2

C842 MMBT3904 1 R6199 5.1K

MMBT3904 RUNPWROK (8)
1uF_6.3V CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
2

DNI © 2007 Advanced Micro Devices Advanced Micro Devices Inc.

2

C6053 This AMD Board schematic and design is the exclusive property of AMD,
1uF_6.3V
and is provided only to entities under a non-disclosure agreement 1 Commerce Valley Drive East
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose Markham, Ontario
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,
Date: Friday, December 11, 2009 Rev
3
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting Sheet 9 of 17
from use of the information included herein.
Title Doc No.
MADISON GDDR3 MxM3.0 105-B985xx-00D
5 4 3 2 1
 5 4 3 2 1

CRITICAL TEMPERATURE FAULT

+PWR_SRC +3VRUN

R4056 3.9R

3
R4055
20K 2N7002E
Q4014 C4013 C4014
1 1uF_6.3V 1uF_6.3V

2
R4054 1K 1 Q4013 1 Q4008 R4050

2
(1,8) PCIE_RST# MMBT3904 CTF_SET2 MMBT3906 0R
DNI

3
D D
R4061

3
20K R4043
DNI 1 R4060 5.1K 470K

Q4016 R4045

2
MMBT3904 10K

CTFb (8)

3
CTF_VCNTL R4051 1K 1 Q4010
MMBT3904

3
+3VRUN C4015

2
CTF_GATED2 R4044 1K CTF_SET3 1 Q4009 R4047 1uF_6.3V R4053
MMBT3904 100K DNI 100K
DNI

2
R4040
3 5.1K

3
R4038 2.2K CTF_TRIP 1 Q4006 Q4007 1 CTF_FB_CNTL R4046 5.1K
(2) GPIO19_CTF MMBT3904 MMBT3904
1%
2

2
CTF SHOULD BE R4039
ACTIVE HI. 1K
1%

R4052 0R DNI

CTF Bypass

C
POWER PLAY C

+VDDR3 For VDDC Controller

GPIO15 GPIO6 VDDC R1671 R1672 R1673 R1674 R1675

10K 10K 10K 10K 10K
DNI DNI DNI
0 0 1.05V VID0_VDDC
VID1_VDDC
(2) GPIO6
VID2_VDDC
(2) GPIO15_PCNTL0
0 1 1.00V VID3_VDDC
(2) GPIO20_PCNTL1
VID4_VDDC
(2) GPIO16_SSIN
1 0 0.95V VID_VREF
R1677 R1678 R1679 R1680 R1676
10K 10K 10K 10K 10K U1604
1 1 0.90V DNI DNI 1 8
+5VRUN 2 VID2 VID3 7
3 VID1 VID4 6
4 VDA GND 5
VDD VIDO
RT9401BPV8
VDDC_REFIN R639 0R R1689 1.78K C1620
(11) VDDC_REFIN 100nF
External Reference is used C1621
C616 R1690 33nF_16V
6.8nF_25V 20K
VDDC_FB (11) R636, R639
share pad

R2
VDDC Lower Resistor R636 1K DNI
VCC (11)
R610
15K R650 must be populated only if VID is Internal Reference is used when
B 402 REFIN is pull-up to > 4.5V VDDC Vref Mode Selection B
1% not used. This will set VDDC to a fixed
DNI value Vref Mode R636, R610 R639, C616 Vref (V)
Vout = Vref * (1+Rt/R2) R1689 & R1690 must be Internal Populate NC 2.5*R2/(R1+R2)
- Vref = 0.6V selected to limit MAX ref voltage External NC Populate set by VID IC (U1604)
- Rt = 10k to MAX VDDC.

MVDD & 1.8V_REG Share

+MVDD

0R
0R
0R
0R

0R
0R
0R
0R
GPIO21 MVDD MVDDC_FB (12) 1.8V_REG_FB (13)

1
2
3
4

1
2
3
4
- 1.8V

8
RP1206A 7
RP1206B 6
RP1206C 5

8
RP1207A 7
RP1207B 6
RP1207C 5
RP1206D

RP1207D
- - Rf1 R2
R2 R810
R1249 R710 7.87K
12K4 7.87K 402 Vout = Vref * (1+Rt/R2)
DNI 1%
- Vref = 0.8V
3

A - Rt = 10k A
Q1244
+1.8V_REG
DNI
1
(2,9) GPIO21_BB_EN
BSS138
DNI Vout = Vref * (1+Rt/Rb) DNI IF +1.8V_REG IS SHARED WITH +MVDD
2

- Vref = 0.8V CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

- Rt = 10k © 2007 Advanced Micro Devices Advanced Micro Devices Inc.
This AMD Board schematic and design is the exclusive property of AMD,
- Rb = R2 // Rf1 and is provided only to entities under a non-disclosure agreement 1 Commerce Valley Drive East
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose Markham, Ontario
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,
Date: Friday, December 11, 2009 Rev
3
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting Sheet 10 of 17
from use of the information included herein.
Title Doc No.
MADISON GDDR3 MxM3.0 105-B985xx-00D
5 4 3 2 1
 8 7 6 5 4 3 2 1

INPUT CAP

+PWR_SRC +PWR_SRC +PWR_SRC +PWR_SRC

C657 C669 C638 C665

2.2uF_16V 2.2uF_16V 2.2uF_16V 2.2uF_16V
X7R, 1206 X7R, 1206 X7R, 1206 X7R, 1206
1.3mm Hi 1.3mm Hi 1.3mm Hi 1.3mm Hi

D D

Top Side Hmax=1.5mm

+PWR_SRC +PWR_SRC +PWR_SRC +PWR_SRC +PWR_SRC +PWR_SRC +PWR_SRC +PWR_SRC

C683 C684 C671 C670 C685 C636 C696 C697

1uF_16V 1uF_16V 1uF_16V 1uF_16V 1uF_16V 1uF_16V 1nF 1nF
X7R, 1206 X7R, 1206 X7R, 1206 X7R, 1206 X7R, 1206 X7R, 1206
0.95mm Hi 0.95mm Hi 0.95mm Hi 0.95mm Hi 0.95mm Hi 0.95mm Hi

Bottom Side Hmax=1.2mm Place close to Q601

+PWR_SRC
Share pad

MR621 R623 BOOT R619 0R

10K 10K 0402
DNI
Q601A
10
11
12
13
14
15
16
17
18
19
20

OUTPUT CAP
4

8
9

5
R2J20602NP
C602
VLDRV

VIN9
VIN10
VIN11
VIN12
VIN13
VIN14
VIN15
VIN16
VIN17
VIN18
VIN19
VIN20
VCIN

VIN

BOOT

100nF +VDDC
C 0603 C

+VDDC +VDDC
55
REG5V DISBL# 21 PHASE L601 Sunken Inductor
VSWH 40 0.56UH 10x10mm C639 C640 C648
C666 VSWH40 41 330uF 330uF 330uF C646
1uF_6.3V 54 VSWH41 42 220UF_2V
Reg5V VSWH42 43
VSWH43 44 SP/POSCAP, SP/POSCAP, SP/POSCAP, SP/POSCAP,
VSWH44 45 SMT 7343 SMT 7343 SMT 7343 SMT 7343
PWM 56 VSWH45 46 Max 1.5mm_H Max 1.5mm_H Max 1.5mm_H Max 1.2mm_H
PWM VSWH46 47 R698
VSWH47 ASIC_FB_VDDC (3)
48 300R Top Side Hmax=1.5mm Bottom Side Hmax=1.2mm
VSWH48 49 805
VSWH49 50 LOW PROFILE POSCAP
2 VSWH50
53 NC C618
NC53

1
1UF_16V NS601
603 +VDDC NS_VIA
CGND51
PGND23
PGND24
PGND25
PGND26
PGND27
PGND28
PGND29
PGND30
PGND31
PGND32
PGND33
PGND34
PGND35
PGND36
PGND37
PGND38
PGND39

Sense Point +VDDC

CGND6
CGND
PGND

2
GH
GL

Place across R600 Place Sense Point on the load side

Q601 100R and routed with separate 20mil trace
7
52

22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39

1
6
51

DNI to PWM IC. C643 C647 C642 C645

RC snubber values shown 10uF_.095 10uF_.095 15nF 100nF
are for reference only, X7R, 0805
X7R, 0805 402 402
tuning is required
FB_TRACE

R616 Reserve for

Q601B 0R Loop Measurement LOW PROFILE MLCC
R2J20602NP 603

57
58 CGND57
B CGND58 VDD_SV B
59
60 CGND59 C613
CGND60 3.9nF
76 RFB1 402
+PWR_SRC VSWH76 75 R611
VSWH75 74
VSWH74 10K
61 THERMAL PADS 73 402
62 VIN61 VSWH73 72 1% R613
63 VIN62 VSWH72 71 3.65K
64 VIN63 VSWH71 70 402
65 VIN64 VSWH70 69 FB
66 VIN65 VSWH69 68 (10) VDDC_FB
VIN66 VSWH68 67 Place close to PWM IC
VSWH67

U601
COMPENSATION CIRCUIT FILTERED SMPS VCC PHASE 42.2K R602 1 8 R604 1K
ISEN RT/SYN
COMP 2 7
COMP/EN REFIN VDDC_REFIN (10)
(9) VDDC_EN FB 3 6 VCC
COMP FB VCC VCC (10)
share pad 4 5 PWM
C611 GND PWM
6.8nF_25V REG5V R607 2.2R uP6113AMT8
402 603
C612 TSOT23-8
150PF +5VRUN
A R612 402 MR607 2.2R VCC A
8.06K 603
402

R614 0R FB 603 C607

X7R 100nF
5%
R609 CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
0R © 2007 Advanced Micro Devices Advanced Micro Devices Inc.
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement 1 Commerce Valley Drive East
with AMD for evaluation purposes. Further distribution or disclosure
Place close to U601 Place close to U601 is strictly prohibited. Use of this schematic and design for any purpose Markham, Ontario
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,
Date: Friday, December 11, 2009 Rev
3
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting Sheet 11 of 17
from use of the information included herein.
Title Doc No.
MADISON GDDR3 MxM3.0 105-B985xx-00D
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

D INPUT CAP D

+5VRUN +5VRUN +5VRUN +5VRUN BOOST

+PW_MVDDC_M
C721 C732 C726 C727 C705
2.2uF_16V 2.2uF_16V 2.2uF_16V 2.2uF_16V 100nF
X7R, 1206 X7R, 1206 X7R, 1206 X7R, 1206
1.3mm Hi 1.3mm Hi 1.3mm Hi 1.3mm Hi

R718
0R
Top Side Hmax=1.5mm

16

15

14

13
+5VRUN +5VRUN +5VRUN U701

PHASE

IMAX

CSP
BOOT
MVDD_EN (9)
+PW_MVDDC_HGD 1 12
C730 C733 C796 UG CSN
1uF_16V 1uF_16V 1nF 2 11
X7R, 1206 X7R, 1206 VCC DROOP
0.95mm Hi 0.95mm Hi +PW_MVDDC_LGD 3 10
LG SS
R734 4 9 MVDDC_COMP
42.2K POK COMP
Bottom Side Hmax=1.2mm Place close to Q701 17 18 C711
TH1 TH2

RT/EN

REFIN
VREF
6.8nF_25V

FB
C712 Type III
150PF Compensation +MVDD

8
402 R712
+PWR_SRC 8.06K

1
R707 2.2R +MVDD_VCC R714 R709 0R NS_VIA
C 0R NS701 C
C707 Sense Point

2
100nF R711 10K
603 402 RFB1

MVDDC_SV
MVDDC_FB 1% R701 0R MVDDC_FB_TRACE
603
R713 C713
3.65K 6.8nF_25V Reserve for
402 402 Loop Measurement
(10) MVDDC_FB

+5VRUN
9
5
6
7
8

Q701
BSC120N03LSG

SM
NL701 1.5uH_10A
4
3
2
1

+PW_MVDDC_HGD ML701 1.5uH_11A

+MVDD

+PW_MVDDC_M L701 2.2uH_8A

Overlap

C741
C738 C737 15nF
R719 330uF 330uF 402
Rs 2.2R
B 1210 SP/POSCAP, SP/POSCAP, B
1% SMT 7343 SMT 7343
9
5
6
7
8

Max 1.5mm_H Max 1.5mm_H

Q702 C708
BSC030N03LS G Cs 10nF_25V
402 Top Side Hmax=1.5mm
X7R
25V LOW PROFILE POSCAP

Place Rs and
4
3
2
1

Cs across QL
+PW_MVDDC_LGD
RC snubber values shown
are for reference only,
tuning is required

A A

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

© 2007 Advanced Micro Devices Advanced Micro Devices Inc.
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement 1 Commerce Valley Drive East
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose Markham, Ontario
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,
Date: Friday, December 11, 2009 Rev
3
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting Sheet 12 of 17
from use of the information included herein.
Title Doc No.
MADISON GDDR3 MxM3.0 105-B985xx-00D
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

D D

BOOST

+PW_1.8V_REG_M
C805
100nF

R818
0R

16

15

14

13
U801
INPUT CAP

PHASE

IMAX

CSP
BOOT
+PW_1.8V_REG_HGD 1 12 1.8V_REG_EN (9)
UG CSN
2 11
+PWR_SRC +PWR_SRC VCC DROOP
+PW_1.8V_REG_LGD 3 10
LG SS
R834 4 9 1.8V_REG_COMP
C822 C896 42.2K POK COMP
2.2uF_16V 1nF 17 18 C811
TH1 TH2

RT/EN

REFIN
VREF
6.8nF_25V
X7R, 1206

FB
1.3mm Hi C812 Type III
2480087600G 150PF Compensation +1.8V_REG

8
C 402 R812 C
Place close to Q801 8.06K

2
+PWR_SRC
Top Side R814 R809 0R NS801
Hmax=1.5mm R807 2.2R 1.8V_REG_VCC 0R NS_VIA
603 Sense Point

1
C807 R811 10K
100nF 402 RFB1

1.8V_REG_SV
603 1V8_REG_FB 1% R801 0R 1.8V_REG_FB_TRACE
603
R813 C813
3.65K 6.8nF_25V Reserve for
402 402 Loop Measurement
(10) 1.8V_REG_FB
+PWR_SRC

SSO8 Dual-FET (FT1)

SM
QH
7
8
9

NL801 3.3uH_7A
Q801A

+PW_1.8V_REG_HGD 2 ML801 1.5uH_11A

BSC150N03LD_G
+1.8V_REG
1

+PW_1.8V_REG_M L801 3.3uH_6A

10
5
6

Overlap
Q801B
C838 C841
+PW_1.8V_REG_LGD 4 330uF C839 15nF
BSC150N03LD_G 10uF_.095 402
R819 2.5V, X7R, 0805
QL
3

2.2R SP/POSCAP,
B 805 SMT 7343 B
1.5MM H
Top Side H<1.5mm C808
10nF_25V
402 Top Side Hmax=1.5mm Bottom Side Hmax=1.2mm
X7R MLCC
25V LOW PROFILE POSCAP

Place Rs and Cs across QL

RC snubber values shown
are for reference only,
tuning is required

A A

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

© 2007 Advanced Micro Devices Advanced Micro Devices Inc.
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement 1 Commerce Valley Drive East
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose Markham, Ontario
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,
Date: Friday, December 11, 2009 Rev
3
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting Sheet 13 of 17
from use of the information included herein.
Title Doc No.
MADISON GDDR3 MxM3.0 105-B985xx-00D
8 7 6 5 4 3 2 1
 5 4 3 2 1

TP_BP1 TP_BP2 TP_BP3 TP_BP4 TP_BP5 TP_BP6 TP_BP7 TP_BP8

620NOPN039 620NOPN039 620NOPN039 620NOPN039 620NOPN039 620NOPN039 620NOPN039 620NOPN039

CLKB1# CLKB1 CKEB1 CLKB0 CLKB0# CLKA1 CKEA1 CLKA0

D D

(5,7) CLKB1# (5,7) CLKB1 (5,7) CKEB1 (5,7) CLKB0 (5,7) CLKB0# (5,6) CLKA1 (5,6) CKEA1 (5,6) CLKA0

C C

B B

A A

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

© 2007 Advanced Micro Devices Advanced Micro Devices Inc.
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement 1 Commerce Valley Drive East
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose Markham, Ontario
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,
Date: Friday, December 11, 2009 Rev
3
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting Sheet 14 of 17
from use of the information included herein.
Title Doc No.
MADISON GDDR3 MxM3.0 105-B985xx-00D
5 4 3 2 1
 5 4 3 2 1

POWER UP SEQUENCE (not to scale)

D D

+PWR_SRC

+5VRUN

+3VRUN

> 1ms

PWR_EN

VDDR3, A2VDD
+VDDR3
+VDDR3 should ramp before or simultaneously with +VDDC.
For LVDS, DPx_VDD10 should ramp-up before DPx_VDD18 and PCIe Reference clock should begin before DPx_VDD18.
The external pull-ups on the DDC/AUX signals (if applicable) should ramp-up before or after both +VDDC and +1.8V_REG have ramped up.
+VDDC and +1.8V_REG should not ramp-up simultaneously.
C VDDC, VDDCI +VDDC should ramp before +1.8V_REG and +1.0V_REG. C

+VDDC

VDDR1, MVDDQ/C
+MVDD

VDDR4, VDD_CT, TSVDD, PCIE_VDDR, PCIE_PVDD, DPLL_PVDD, DPx_PVDD,

+1.8V_REG DPx_VDD18, MPV18, SPV18, AVDD, VDD1DI, A2VDDQ, VDD2DI

PCIE_VDDC, DPLL_VDDC, DPx_VDD10, SPV10

+1.0V_REG

< 20ms

PWR_GODD

< 90ms

B B

A A

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

© 2007 Advanced Micro Devices Advanced Micro Devices Inc.
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement 1 Commerce Valley Drive East
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose Markham, Ontario
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,
Date: Friday, December 11, 2009 Rev
3
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting Sheet 15 of 17
from use of the information included herein.
Title Doc No.
MADISON GDDR3 MxM3.0 105-B985xx-00D
5 4 3 2 1
 5 4 3 2 1

MEMORY CHANNEL A & B

GDDR3 4pcs 32Mx32

D D

CH A&B
LVTMDP
DL LVDS LVDS
LVDS_LTXx/LTXx#
DPE/F LVDS_UTXx/UTXx#
POWER REGULATORS
DDC3 LVDS_DDC_CLK/DAT

From +PWR_SRC HPD3 DVI_HPD

+VDDC, +1.8V_REG

From +5VRUN TMDPAB

+MVDD DP_A
DPA DP_A_Lx/Lx#
From +3VRUN
+VDDR3, A2VDD DDCAUX1 DP_A_AUX/AUX#

C Straps
GPIO HPD1 DP_A_HPD C
From +VDDC
VDDC, VDDCI
DP_C
From +MVDD BIOS DPB DP_C_Lx/Lx#
ROM
VDDR1, MVDDQ/C DDCAUX2 DP_C_AUX/AUX#

From +1.8V_REG HPD2 DP_C_HPD

VDDR4, VDD_CT, TSVDD,

PCIE_VDDR, PCIE_PVDD,
DPLL_PVDD, DPx_PVDD, XTALIN/OUT
DPx_VDD18, MPV18, SPV18, XTAL
AVDD, VDD1DI, A2VDDQ,
DAC2
VDD2DI, +1.0V_REG CRT DAC2 VGA
VGA_RED/GREEN/BLUE

From +1.0V_REG DDC5

VGA_DDC_CLK/DAT
PCIE_VDDC, DPLL_VDDC, Dynamic MVDD GPIO21 V/H2Sync
VGA_VSYNC/HSYNC
DPx_VDD10, SPV10 Dynamic VDDC GPIO20/16/15/6

POWER DELIVERY
MxM3.0 Source
Thermal
+3VRUN +5VRUN +PWR_SRC GPIO3, GPIO4
B B
DDC6 I2C
External SMB_CLK/DAT
D+/D- Temp. Sensing
Madison Temperature TH_ALERT#
GPIO17 Interrupt
Sensor TH_OVERT#

3V3 delayed circuit GPIO19_CTF

Temperature Critical
GPIO19_CTF

PCIE
SMPS Enable
Circuit

3VRUN
5VRUN MxM3.0 Connector MxM3.0 Madison GDDR3 512MB
PWR_SRC
DP DP DL-LVDS VGA

A A

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© 2007 Advanced Micro Devices Advanced Micro Devices Inc.
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement 1 Commerce Valley Drive East
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose Markham, Ontario
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,
Date: Friday, December 11, 2009 Rev
3
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting Sheet 16 of 17
from use of the information included herein.
Title Doc No.
MADISON GDDR3 MxM3.0 105-B985xx-00D
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Title Schematic No. Date:

MADISON GDDR3 MxM3.0 105-B985xx-00D Friday, December 11, 2009
NOTE: This schematic represents the PCB, it does not represent any specific SKU.
Rev
REVISION HISTORY For Stuffing options (component values, DNI’s, …) please consult the product specific BOM.

D
Please contact AMD representative to obtain latest BOM closest to the application desired.
3 D
Sch PCB Date REVISION DESCRIPTION
Rev Rev
0 00A 09/06/02 Initial design for Madison GDDR3 MxM3.0 based on M96 B803

1 00B 09/08/27 Add U27, Q27, C27 - Gating circuit to delay DPEF_VDD18
Add R1677, R1678, R1679, R1680 - Pull downs for VID circuit
Add R600 for debug
Increase TP coverage

2 00C 09/10/30 Add C696, C697, C796, C896 (0402 input caps for power supplies)
Add R1001 (DRAM_RST topology change)
Change J1 symbol (inlcudes non-plated tooling holes)
Move JTAG TPs out of the back plate area

C C
3 00D 09/12/11 Pull back power planes

B B

A A

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