5 4 3 2 1

U1A

PCIE_RXP0 AA38 Y33 PCIE_TXP0

PCIE_RXN0 Y37 PCIE_RX0P PCIE_TX0P Y32 PCIE_TXN0
PCIE_RX0N PCIE_TX0N
D D
PCIE_RXP1 Y35 W33 PCIE_TXP1
PCIE_RXN1 W36 PCIE_RX1P PCIE_TX1P W32 PCIE_TXN1
PCIE_RX1N PCIE_TX1N

PCIE_RXP2 W38 U33 PCIE_TXP2

PCIE_RXN2 V37 PCIE_RX2P PCIE_TX2P U32 PCIE_TXN2
PCIE_RX2N PCIE_TX2N
PCIE_RST#
8 PCIE_RST#
PCIE_RXP3 V35 U30 PCIE_TXP3
PCIE_RXN3 U36 PCIE_RX3P PCIE_TX3P U29 PCIE_TXN3
PCIE_RX3N PCIE_TX3N
PCIE_REFCLKP
8 PCIE_REFCLKP
PCIE_RXP4 U38 T33 PCIE_TXP4 PCIE_REFCLKN
PCIE_RX4P PCIE_TX4P 8 PCIE_REFCLKN
PCIE_RXN4 T37 T32 PCIE_TXN4
PCIE_RX4N PCIE_TX4N

PCI EXPRESS INTERFACE

PCIE_RXP5 T35 T30 PCIE_TXP5 PCIE_RXP[15..0]
PCIE_RX5P PCIE_TX5P 8 PCIE_RXP[15..0]
PCIE_RXN5 R36 T29 PCIE_TXN5
PCIE_RX5N PCIE_TX5N PCIE_RXN[15..0]
8 PCIE_RXN[15..0]
PCIE_RXP6 R38 P33 PCIE_TXP6 PCIE_TXP[15..0]
PCIE_RX6P PCIE_TX6P 8 PCIE_TXP[15..0]
PCIE_RXN6 P37 P32 PCIE_TXN6
PCIE_RX6N PCIE_TX6N PCIE_TXN[15..0]
C 8 PCIE_TXN[15..0] C

PCIE_RXP7 P35 P30 PCIE_TXP7

PCIE_RXN7 N36 PCIE_RX7P PCIE_TX7P P29 PCIE_TXN7
PCIE_RX7N PCIE_TX7N

PCIE_RXP8 N38 N33 PCIE_TXP8

PCIE_RXN8 M37 PCIE_RX8P PCIE_TX8P N32 PCIE_TXN8
PCIE_RX8N PCIE_TX8N

PCIE_RXP9 M35 N30 PCIE_TXP9

PCIE_RXN9 L36 PCIE_RX9P PCIE_TX9P N29 PCIE_TXN9
PCIE_RX9N PCIE_TX9N

PCIE_RXP10 L38 L33 PCIE_TXP10

PCIE_RXN10 K37 PCIE_RX10P PCIE_TX10P L32 PCIE_TXN10
PCIE_RX10N PCIE_TX10N

PCIE_RXP11 K35 L30 PCIE_TXP11

PCIE_RXN11 J36 PCIE_RX11P PCIE_TX11P L29 PCIE_TXN11
PCIE_RX11N PCIE_TX11N

PCIE_RXP12 J38 K33 PCIE_TXP12

PCIE_RXN12 H37 PCIE_RX12P PCIE_TX12P K32 PCIE_TXN12
PCIE_RX12N PCIE_TX12N
B B

PCIE_RXP13 H35 J33 PCIE_TXP13

PCIE_RXN13 G36 PCIE_RX13P PCIE_TX13P J32 PCIE_TXN13
PCIE_RX13N PCIE_TX13N

PCIE_RXP14 G38 K30 PCIE_TXP14

PCIE_RXN14 F37 PCIE_RX14P PCIE_TX14P K29 PCIE_TXN14
PCIE_RX14N PCIE_TX14N

PCIE_RXP15 F35 H33 PCIE_TXP15

PCIE_RXN15 E37 PCIE_RX15P PCIE_TX15P H32 PCIE_TXN15
PCIE_RX15N PCIE_TX15N

CLOCK
PCIE_REFCLKP AB35
PCIE_REFCLKN AA36 PCIE_REFCLKP
PCIE_REFCLKN

CALIBRATION 1.0V_REG
AJ21 Y30 R11
AK21 NC#1 PCIE_CALRP 1.27K
AH16 NC#2 Y29 R12 CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
A PWRGOOD PCIE_CALRN 2.0K © 2007 Advanced Micro Devices Advanced Micro Devices Inc. A
This AMD Board schematic and design is the exclusive property of AMD,
PCIE_RST# AA30 and is provided only to entities under a non-disclosure agreement 1 Commerce Valley Drive East
PERSTB with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose Markham, Ontario
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind Date: Monday, September 13, 2010 Rev
Broadway regarding this schematic and design, including, not limited to, 1
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting Sheet 1 of 12
from use of the information included herein.
Title Doc No.
Whisler MXM3.0 G5 105-C29247-00B
5 4 3 2 1
 5 4 3 2 1

U1B R425 10K

U1G
R426 10K

AU24
TXCAP_DPA3P TXCAP_DPA3P 8
AV23 LVDS CONTROL AK27
TXCAM_DPA3N TXCAM_DPA3N 8 VARY_BL BLON_PWM 8
AJ27
DIGON FPVCC 8
AT25
TX0P_DPA2P TX0P_DPA2P 8
MUTI GFX AR24
TX0M_DPA2N TX0M_DPA2N 8
DPA
AU26
CON1 TX1P_DPA1P TX1P_DPA1P 8
AV25 AK35
TX1M_DPA1N TX1M_DPA1N 8 TXCLK_UP_DPF3P TXCLK_U+ 8
20 CLK_A AL36
20 TXCLK_UN_DPF3N TXCLK_U- 8
19 AR8 AT27
19 DVPCNTL_MVP_0 TX2P_DPA0P TX2P_DPA0P 8
18 GENERICD CLK_A AU8 AR26 AJ38
18 DVPCNTL_MVP_1 TX2M_DPA0N TX2M_DPA0N 8 TXOUT_U0P_DPF2P TXOUT_U0+ 8
17 GPIO2 AP8 AK37
17 DVPCNTL_0 TXOUT_U0N_DPF2N TXOUT_U0- 8
16 AW8 AR30
16 DVPCNTL_1 TXCBP_DPB3P TXCBP_DPB3P 8
15 D11 DE_B AR3 AT29 AH35
15 DVPCNTL_2 TXCBM_DPB3N TXCBM_DPB3N 8 TXOUT_U1P_DPF1P TXOUT_U1+ 8
14 D10 CLK_B AR1 AJ36
14 DVPCLK TXOUT_U1N_DPF1N TXOUT_U1- 8
13 D9 D0 AU1 AV31
13 DVPDATA_0 TX3P_DPB2P TX3P_DPB2P 8
12 D8 D1 AU3 AU30 AG38
12 DVPDATA_1 DPB TX3M_DPB2N TX3M_DPB2N 8 TXOUT_U2P_DPF0P TXOUT_U2+ 8
11 D7 D2 AW3 AH37
11 DVPDATA_2 TXOUT_U2N_DPF0N TXOUT_U2- 8
10 D6 D3 AP6 AR32
10 DVPDATA_3 TX4P_DPB1P TX4P_DPB1P 8
9 D4 AW5 AT31 AF35
D 9 DVPDATA_4 TX4M_DPB1N TX4M_DPB1N 8 TXOUT_U3P TXOUT_U3+ 8 D
8 D5 D5 AU5 AG36
8 DVPDATA_5 TXOUT_U3N TXOUT_U3- 8
7 D4 D6 AR6 AT33
7 DVPDATA_6 TX5P_DPB0P TX5P_DPB0P 8
6 D3 D7 AW6 AU32
6 DVPDATA_7 TX5M_DPB0N TX5M_DPB0N 8
5 D2 D8 AU6 LVTMDP
5 4 D1 D9 AT7 DVPDATA_8 AU14
4 DVPDATA_9 TXCCP_DPC3P TXCCP_DPC3P 8
3 D0 D10 AV7 AV13 AP34
3 DVPDATA_10 TXCCM_DPC3N TXCCM_DPC3N 8 TXCLK_LP_DPE3P TXCLK_L+ 8
37 2 DE_B D11 AN7 AR34
TAB1 2 DVPDATA_11 TXCLK_LN_DPE3N TXCLK_L- 8
36 1 CLK_B AV9 AT15
TAB2 1 DVPDATA_12 TX0P_DPC2P TX0P_DPC2P 8
AT9 AR14 AW37
DVPDATA_13 TX0M_DPC2N TX0M_DPC2N 8 TXOUT_L0P_DPE2P TXOUT_L0+ 8
AR10 AU35
CABLINE_V_RECPT_20P DVPDATA_14 TXOUT_L0N_DPE2N TXOUT_L0- 8
AW10 DPC AU16
AU10 DVPDATA_15 TX1P_DPC1P AV15 TX1P_DPC1P 8 AR37
DVPDATA_16 TX1M_DPC1N TX1M_DPC1N 8 TXOUT_L1P_DPE1P TXOUT_L1+ 8
AP10 AU39
DVPDATA_17 TXOUT_L1N_DPE1N TXOUT_L1- 8
AV11 AT17
DVPDATA_18 TX2P_DPC0P TX2P_DPC0P 8
AT11 AR16 AP35
DVPDATA_19 TX2M_DPC0N TX2M_DPC0N 8 TXOUT_L2P_DPE0P TXOUT_L2+ 8
AR12 AR35
AW12 DVPDATA_20 AU20 TXOUT_L2N_DPE0N TXOUT_L2- 8
DVPDATA_21 TXCDP_DPD3P TXCDP_DPD3P 8
AU12 AT19 AN36
DVPDATA_22 TXCDM_DPD3N TXCDM_DPD3N 8 TXOUT_L3P TXOUT_L3+ 8
AP12 AP37
DVPDATA_23 TXOUT_L3N TXOUT_L3- 8
AT21
TX3P_DPD2P TX3P_DPD2P 8
AR20
TX3M_DPD2N TX3M_DPD2N 8
DPD AU22
TX4P_DPD1P TX4P_DPD1P 8
AV21
TX4M_DPD1N TX4M_DPD1N 8
Broadway
I2C AT23
TX5P_DPD0P TX5P_DPD0P 8
AR22
TX5M_DPD0N TX5M_DPD0N 8
I2C_CLK AK26
9 I2C_CLK SCL
I2C_DAT AJ26
9 I2C_DAT SDA
AD39
R VGA_RED 8
GENERAL PURPOSE I/O AD37 1.8V_REG
GPIO0 AH20 RB B1 120R_1.3A AVDD
8,9,10 GPIO0 GPIO_0
GPIO1 AH18 AE36 (1.8V@65mA A2VDD)
8,9 GPIO1 GPIO_1 G VGA_GRN 8
GPIO2 AN16 AD35
9 GPIO2 GPIO_2 GB
GPIO3 AH23 C39 C41 C40
8 GPU_SMBDAT GPIO_3_SMBDATA
GPIO4 AJ23 AF37
8 GPU_SMBCLK GPIO_4_SMBCLK B VGA_BLU 8
GPIO5 AH17 AE38 NS1 10uF_2.5V 1uF_6.3V 100nF
8 GPIO5 GPIO_5_AC_BATT BB
AJ17 DAC1 1 2
AK17 GPIO_6 AC36
8 GPIO7_BLON GPIO_7_BLON HSYNC HSYNC 8,9
9 GPIO8 GPIO8 RP1A 1 8 33R AJ13 AC38 NS_VIA AVSSQ
GPIO_8_ROMSO VSYNC VSYNC 8,9
GPIO9 RP1B 2 733R AH15
8,9 GPIO9 GPIO_9_ROMSI
GPIO10 RP1C 3 633R AJ16 B2 120R_1.3A (1.8V@100mA VDD2DI) VDD1DI
GPIO11 AK16 GPIO_10_ROMSCK AB34 R25
9,10 GPIO11 GPIO_11 RSET
GPIO12 AL16 499R AVDD
9,10 GPIO12 GPIO_12
GPIO13 AM16 AD34 C42 C43 C44
9,10 GPIO13 GPIO_13 AVDD
HPD2 AM14 AE34
8 HPD2 GPIO_14_HPD2 AVSSQ
AM13 VDD1DI AVSSQ NS30 10uF_2.5V 1uF_6.3V 100nF
10 GPIO15 GPIO_15_PWRCNTL_0
DPLL_VDDC GPIO16 AK14 AC33 1 2
10 GPIO16 GPIO_16_SSIN VDD1DI
C 1.0V_REG AG30 AC34 C
8,9 MB_ALERTB GPIO_17_THERMAL_INT VSS1DI
B7 120R_3A (1.1V@300mA DPLL_VDDC) AN14 NS_VIA VSS1DI
8 HPD3 AM17 GPIO_18_HPD3 VSS1DI
8 GPIO19_CTF AL13 GPIO_19_CTF AC30
C58 C59 C60 10 GPIO20 AJ14 GPIO_20_PWRCNTL_1 R2 AC31
GPIO22 4 11
RP1D GPIO21
533R AK13 GPIO_21_BB_EN R2B
10uF_2.5V 1uF_6.3V 9
100nF GPIO22 CLKREQB AN13 GPIO_22_ROMCSB AD30
8 CLKREQB AM23 GPIO_23_CLKREQB G2 AD31
GPIO24_TRSTB
GPIO25_TDI AN23 JTAG_TRSTB G2B
GPIO26_TCK AK23 JTAG_TDI AF30
DPLL_PVSS GPIO27_TMS AL24 JTAG_TCK B2 AF31
GPIO28_TDO AM24 JTAG_TMS B2B
GEN_A AJ19 JTAG_TDO
8 GENERICA GENERICA
AK19 AC32
8 GENERICB GENERICB C
AJ20 AD32
9 GENERICC GENERICC Y
1.8V_REG TSVDD GENERICD AK20 AF32
AJ24 GENERICD COMP
(1.8V@15mA TSVDD) 8 HPD4 GENERICE_HPD4
B8 AH26 DAC2
8 HPD5 GENERICF
BLM15BD121SN1 AH24 AD29
8 HPD6 GENERICG H2SYNC H2SYNC 9
C62 C63 C64 AC29
V2SYNC V2SYNC 9
NS5 10uF_2.5V 1uF_6.3V 100nF AK24
8 HPD1 HPD1
1 2 AG31
1.8V_REG VDD2DI AG32
NS_VIA VSS2DI
TSVSS
PLACE VREFG DIVIDER AND CAP AG33
R31 A2VDD
CLOSE TO ASIC AD33
499R
AH13 A2VDDQ
VREFG AF33
1.8V_REG R32 C54 A2VSSQ
B6 120R_3A (1.8V@150mA DPLL_PVDD) DPLL_PVDD 249R
100nF AA29
AM32 R2SET
C55 C56 C57 AN32 DPLL_PVDD
DPLL_PVDD DPLL_VDDC DPLL_PVSS 51K
NS3 10uF_2.5V 1uF_6.3V 100nF DDC/AUX AM26 R8445
1 2 AN31 PLL/CLOCK DDC1CLK AN26 R8446 51K
DPLL_VDDC DDC1DATA GPIO8
NS_VIA AM27 U56
AUX1P DDCCLK_AUX1P 8
DPLL_PVSS XTALIN AV33 AL27 GPIO9 5 2
AU34 XTALIN AUX1N DDCDATA_AUX1N 8 D Q
51K
XTALOUT AM19 R8447 GPIO10 6
DDC2CLK AL19 R8448 51K C
XO_IN AW34 DDC2DATA GPIO22 1
XO_IN AN20 +3VRUN S
AW35 AUX2P AM20 DDCCLK_AUX2P 8 7
X0_IN2
SS_IN AUX2N DDCDATA_AUX2N 8 HOLD
AL30 3
B DDCCLK_AUX3P DDCCLK_AUX3P 8 +3VRUN W B
AM30
DDCDATA_AUX3N DDCDATA_AUX3N 8
R36 0R 8 4
AL29 R39 0R VCC VSS
DDCCLK_AUX4P DDCCLK_AUX4P 8
AF29 AM29 C61 M25P05-VMN6T
9 GPU_DPLUS DPLUS DDCDATA_AUX4N DDCDATA_AUX4N 8
AG29 THERMAL 100nF
9 GPU_DMINUS DMINUS AN21 A 256MB MEMORY APERTURE SIZE
DDCCLK_AUX5P DDCCLK_AUX5P 8
AM21 ALTERNATIVE PART :M25P05(512Kbit)
AK32 DDCDATA_AUX5N DDCDATA_AUX5N 8 CAN BE DEFINED USING A SEPARATE
TS_FDO AJ30 ROM OR STRAPPING
DDC6CLK DDC6CLK 8
AL31 AJ31
TS_A DDC6DATA DDC6DATA 8
TSVDD NC7SZ08P5X_NL
AK30 +3VRUN
AJ32
TSVDD
DDCCLK_AUX7P
DDCDATA_AUX7N
AK29 DDCCLK_AUX7P 8
DDCDATA_AUX7N 8
+3VRUN SERIAL EEPROM 512K/1M
AJ33
R451 TSVSS R619 A 256MB MEMORY APERTURE SIZE
1M C829
2 4 TSVSS
CAN BE DEFINED USING A SEPARATE
3K 100nF
5

1 3 Broadway ROM OR STRAPPING

1
Y1 4 TS_FDO 8
+3VRUN C681 27.000MHz_10PPM_30R C682 2
18pF_50V 18pF_50V U58
3

B49
BLM15BD121SN1
B50
BLM15BD121SN1

C836 C837 U60

100nF 100nF 1 10
XTALIN XTALOUT
R631 R630 4
10K 10K 8 VDD_100M 5 R629 0R X0_IN2
VDD_27M 100M_OUT
7
3 SS_SEL0
SS_SEL1 9 27M_OUT R634 75R XO_IN
6 27M_OUT
R635 R636 2 GND_100M
10K 10K 11 GND_27M
GND_PAD R8455 182R DNI XTALIN
SL16010DCT
+3VRUN
R8456
221R
R627
JTAG1
10K GPIO26_TCK 1 2 TESTEN
TESTEN 5
A GPIO27_TMS 3 4 A

GPIO25_TDI 5 6 GPIO24_TRSTB R561 +3VRUN

10K
GPIO28_TDO 7 8
+3VRUN R615

JTAG_SOCKET_8 10K

Advanced Micro Devices Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
Whisler MXM3.0 G5
Size Document Number Rev
Custom 105-C29247-00B 0
Date: Monday, September 13, 2010 Sheet 2 of 12
5 4 3 2 1
 5 4 3 2 1

U1E

+1.5V_REG MEM I/O 1.8V_REG

PCIE PCIE_VDDR (1.8V@504mA PCIE_VDDR) B51 120R_3A
AC7 AA31
AD11 VDDR1#1 PCIE_VDDR#1 AA32
C73 C88 C74 C89 C90 C91 C92 C93 C120 C121 AF7 VDDR1#2 PCIE_VDDR#2 AA33 C95 C776 C100 C101
AG10 VDDR1#3 PCIE_VDDR#3 AA34
1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V AJ7 VDDR1#4 PCIE_VDDR#4 V28 100nF 1uF_6.3V 2.2UF_2.5V 10uF_2.5V
AK8 VDDR1#5 PCIE_VDDR#5 W29
AL9 VDDR1#6 PCIE_VDDR#6 W30
G11 VDDR1#7 PCIE_VDDR#7 Y31
G14 VDDR1#8 PCIE_VDDR#8
C122 C123 C124 C125 C126 C127 G17 VDDR1#9 1.0V_REG
VDDR1#10
(1.1V@1920mA PCIE_VDDC) For M96/M92 PCIE_VDDC = 1.1V
G20 G30
G23 VDDR1#11 PCIE_VDDC#1 G31
For M97/RV8xx PCIE_VDDC = 1.0V
10uF_2.5V 10uF_2.5V 10uF_2.5V 10uF_2.5V 10uF_2.5V 10uF_2.5V
D
G26 VDDR1#12 PCIE_VDDC#2 H29 C111 C112 C113 C114 C117
D
G29 VDDR1#13 PCIE_VDDC#3 H30
H10 VDDR1#14 PCIE_VDDC#4 J29 100nF 1uF_6.3V 1uF_6.3V 2.2UF_2.5V 10uF_2.5V
J7 VDDR1#15 PCIE_VDDC#5 J30
J9 VDDR1#16 PCIE_VDDC#6 L28
K11 VDDR1#17 PCIE_VDDC#7 M28
K13 VDDR1#18 PCIE_VDDC#8 N28
K8 VDDR1#19 PCIE_VDDC#9 R28
L12 VDDR1#20 PCIE_VDDC#10 T28
L16 VDDR1#21 PCIE_VDDC#11 U28
L21 VDDR1#22 PCIE_VDDC#12
L23 VDDR1#23 VDDC
L26 VDDR1#24 AA15
L7 VDDR1#25 CORE VDDC#1 AA17
M11 VDDR1#26 VDDC#2 AA20
N11 VDDR1#27 VDDC#3 AA22 C133 C134 C135 C136 C137 C138 C139 C140 C141 C142
P7 VDDR1#28 VDDC#4 AA24 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V
R11 VDDR1#29 VDDC#5 AA27
U11 VDDR1#30 VDDC#6 AB16
U7 VDDR1#31 VDDC#7 AB18
Y11 VDDR1#32 VDDC#8 AB21
Y7 VDDR1#33 VDDC#9 AB23
VDDR1#34 VDDC#10 AB26 C148 C149 C150 C151 C152 C153 C154 C155 C156 C157
VDDC#11 AB28 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V
1.8V_REG VDDC#12 AC17
VDDC#13 AC20
VDDC_CT LEVEL VDDC#14 AC22
B12 120R_1.3A TRANSLATION VDDC#15 AC24
(1.8V@110mA VDD_CT) VDDC#16

POWER
AF26 AC27
AF27 VDD_CT#1 VDDC#17 AD18 C758 C759 C760 C761 C762 C763 C764
C170 C171 C172 AG26 VDD_CT#2 VDDC#18 AD21 2.2UF_2.5V 2.2UF_2.5V 2.2UF_2.5V 2.2UF_2.5V 2.2UF_2.5V 2.2UF_2.5V 2.2UF_2.5V
AG27 VDD_CT#3 VDDC#19 AD23
1uF_6.3V 10uF_2.5V 1uF_6.3V VDD_CT#4 VDDC#20 AD26
+3VRUN VDDC#21 AF17
I/O VDDC#22 AF20
AF23 VDDC#23 AF22
AF24 VDDR3#1 VDDC#24 AG16
C185 C186 C187 C188 AG23 VDDR3#2 VDDC#25 AG18 C765 C766 C767 C768 C769 C770 C771
C C
AG24 VDDR3#3 VDDC#26 AG21 2.2UF_2.5V 2.2UF_2.5V 2.2UF_2.5V 2.2UF_2.5V 2.2UF_2.5V 2.2UF_2.5V 2.2UF_2.5V
10uF_X6S 1uF_6.3V 1uF_6.3V 1uF_6.3V VDDR3#4 VDDC#27 AH22
VDDR4 VDDC#28 AH27
AF13 VDDC#29 AH28
AF15 VDDR4#4 VDDC#30 M26
VDDR4 AG13 VDDR4#5 VDDC#31 N24
B13 120R_1.3A AG15 VDDR4#7 VDDC#32 N27 C217 C218 C219 C220 C221
VDDR4#8 VDDC#33 R18
VDDC#34 R21 22uF_2.5V 22uF_2.5V 22uF_2.5V 22uF_2.5V 22uF_2.5V
C199 C200 C201 AD12 VDDC#35 R23
AF11 VDDR4#1 VDDC#36 R26
10uF_2.5V 1uF_6.3V 1uF_6.3V AF12 VDDR4#2 VDDC#37 T17
AG11 VDDR4#3 VDDC#38 T20
VDDR4#6 VDDC#39 BIF_VDDC
T22
VDDC#40 T24
VDDC#41 T27
VDDC#42 U16
M20 VDDC#43 U18
M21 NC_VDDRHA VDDC#44 U21 C795
NC_VSSRHA VDDC#45 U23 C794
PCIE_VDDR VDDC#46 U26 1uF_6.3V 1uF_6.3V
V12 VDDC#47 V17
U12 NC_VDDRHB VDDC#48 V20
R8417 NC_VSSRHB VDDC#49 V22
VDDC#50 V24
0R VDDC#51 V27
VDDC#52 Y16
PCIE_PVDD PLL VDDC#53 Y18
(1.8V@40mA PCIE_PVDD) VDDC#54
B19 AB37 Y21
BLM15BD121SN1 PCIE_PVDD VDDC#55 Y23
C226 C227 C228 H7 VDDC#56 Y26
MPV18 MPV18#1 VDDC#57
H8 Y28
10uF_2.5V 1uF_6.3V 1uF_6.3V MPV18#2 VDDC#58

SPV18 AM10
1.0V_REG B52 120R_3A SPV18 AA13
AN9 VDDCI#1 AB13
B SPV10 VDDCI#2 AC12 B

C229 C230 C231 AN10 VDDCI#3 AC15

SPVSS VDDCI#4 AD13
B44 120R_1.3A SPV18 NS29 10uF_2.5V 1uF_6.3V 100nF VDDCI#5 AD16
(1.8V@75mA SPV18) VDDCI#6
1 2 M15
VDDCI#7 M16
C796 C797 C798 NS_VIA VOLTAGE VDDCI#8 M18
SPVSS SENESE VDDCI#9 M23
10uF_2.5V 1uF_6.3V 100nF VDDCI#10 N13
AF28 VDDCI#11 N15
10 FB_VDDC FB_VDDC VDDCI#12 N17 VDDC
VDDCI#13 N20
SPVSS AG28 VDDCI#14 N22
FB_VDDCI ISOLATED VDDCI#15 R12 C832
CORE I/O VDDCI#16 R13 C799 C792 C234 C235 C236 C238 C833 C834
B45 120R_3A MPV18 AH29 VDDCI#17 R16 2.2UF_2.5V
(1.8V@500mA MPV18) 10 FB_VSSC FB_GND VDDCI#18 T12 1uF_6.3V 1uF_6.3V 2.2UF_2.5V 2.2UF_2.5V 2.2UF_2.5V 2.2UF_2.5V 2.2UF_2.5V 2.2UF_2.5V
VDDCI#19 T15
VDDCI#20 V15
C800 C801 C802 VDDCI#21 Y13
VDDCI#22
10uF_2.5V 1uF_6.3V 100nF
Broadway

1.0V_REG
+3VRUN +5VRUN Overlapped
R8451 0R +5VRUN Q92A Q92B
8,10 VDDCGOOD BSL214N BSL214N
1.0V_REG

R8452 2 4 6 5 R625 0R
+3VRUN R564 R565
PX_MODE =1, for Normal Operation 10K 10K BIF_VDDC
PX_MODE =0, for BACO MODE 10K
3

PX_EN# R620 0R
A R566 C803 100nF A
10K PX_EN##
R621 0R
6

C804
5

U57 Q93A Q93B VDDC 22uF_2.5V

3

1 2 3 3 2
Q96 4 2 5
2 2N7002 2N7002
1 2N7002_NL BSR202N BSR202N VDDC Advanced Micro Devices Inc.
4,10 PX_EN
1

NC7SZ08M5 Q94 Q95 1 Commerce Valley Drive East

3

Markham, Ontario
2

R568 Canada, L3T 7X6

10K
Q=1, Normal operation
Q=0, BACO BACO Title
(905) 882-2600

Whisler MXM3.0 G5
Size Document Number Rev
C 105-C29247-00B 0
Date: Monday, September 13, 2010 Sheet 3 of 12
5 4 3 2 1
 5 4 3 2 1

U1F

AB39 A3
E39 PCIE_VSS#1 GND#1 A37
F34 PCIE_VSS#2 GND#2 AA16
F39 PCIE_VSS#3 GND#3 AA18
G33 PCIE_VSS#4 GND#4 AA2
G34 PCIE_VSS#5 GND#5 AA21
D H31 PCIE_VSS#6 GND#6 AA23 D
H34 PCIE_VSS#7 GND#7 AA26
H39 PCIE_VSS#8 GND#8 AA28
J31 PCIE_VSS#9 GND#9 AA6
1.8V_REG J34 PCIE_VSS#10 GND#10 AB12
K31 PCIE_VSS#11 GND#11 AB15
K34 PCIE_VSS#12 GND#12 AB17
B46 120R_3A DPAB_VDD18 K39 PCIE_VSS#13 GND#13 AB20
L31 PCIE_VSS#14 GND#14 AB22
L34 PCIE_VSS#15 GND#15 AB24
R8413 C805 C806 C807 M34 PCIE_VSS#16 GND#16 AB27
M39 PCIE_VSS#17 GND#17 AC11
10uF_2.5V 1uF_6.3V 100nF N31 PCIE_VSS#18 GND#18 AC13
0R N34 PCIE_VSS#19 GND#19 AC16
R8414 P31 PCIE_VSS#20 GND#20 AC18
P34 PCIE_VSS#21 GND#21 AC2
P39 PCIE_VSS#22 GND#22 AC21
0R R34 PCIE_VSS#23 GND#23 AC23
U1H T31 PCIE_VSS#24 GND#24 AC26
B43 120R_1.3A DPCD_VDD18 T34 PCIE_VSS#25 GND#25 AC28
DPCD_VDD18 DP C/D POWER DP A/B POWER DPAB_VDD18 T39 PCIE_VSS#26 GND#26 AC6
1.0V_REG B22 120R_1.3A DPCD_VDD10 U31 PCIE_VSS#27 GND#27 AD15
C811 C812 C813 AP20 AN24 U34 PCIE_VSS#28 GND#28 AD17
AP21 DPC_VDD18#1 DPA_VDD18#1 AP24 V34 PCIE_VSS#29 GND#29 AD20
1uF_6.3V 1uF_6.3V 100nF C254 C247 C248 DPC_VDD18#2 DPA_VDD18#2 V39 PCIE_VSS#30 GND#30 AD22
DPCD_VDD10 DPAB_VDD10 W31 PCIE_VSS#31 GND#31 AD24
10uF_2.5V 1uF_6.3V 100nF W34 PCIE_VSS#32 GND#32 AD27
AP13 AP31 Y34 PCIE_VSS#33 GND#33 AD9
AT13 DPC_VDD10#1 DPA_VDD10#1 AP32 Y39 PCIE_VSS#34 GND#34 AE2
DPC_VDD10#2 DPA_VDD10#2 PCIE_VSS#35 GND#35 AE6
R8416 GND#36 AF10
AN17 AN27 GND#37 AF16
AP16 DPC_VSSR#1 DPA_VSSR#1 AP27 GND#38 AF18
B31 120R_1.3A DPEF_VDD18 0R AP17 DPC_VSSR#2 DPA_VSSR#2 AP28 GND#39 AF21
AW14
AW16
DPC_VSSR#3
DPC_VSSR#4
DPC_VSSR#5
DPA_VSSR#3
DPA_VSSR#4
DPA_VSSR#5
AW24
AW26 F15
GND#100
GND GND#40
GND#41
GND#42
AG17
AG2
C274 C275 C290 C276 1.0V_REG B23 120R_3A DPAB_VDD10 F17 AG20
DPCD_VDD18 DPAB_VDD18 F19 GND#101 GND#43 AG22
1uF_6.3V 1uF_6.3V 1uF_6.3V 100nF F21 GND#102 GND#44 AG6
C249 C253 C252 AP22 AP25 F23 GND#103 GND#45 AG9
AP23 DPD_VDD18#1 DPB_VDD18#1 AP26 F25 GND#104 GND#46 AH21
100nF 1uF_6.3V 1uF_6.3V DPD_VDD18#2 DPB_VDD18#2 F27 GND#105 GND#47 AJ10
DPCD_VDD10 DPAB_VDD10 F29 GND#106 GND#48 AJ11
R8415 F31 GND#107 GND#49 AJ2
AP14 AN33 F33 GND#108 GND#50 AJ28
AP15 DPD_VDD10#1 DPB_VDD10#1 AP33 F7 GND#109 GND#51 AJ6
0R DPD_VDD10#2 DPB_VDD10#2 F9 GND#110 GND#52 AK11
G2 GND#111 GND#53 AK31
G6 GND#112 GND#54 AK7
AN19 AN29 H9 GND#113 GND#55 AL11
C AP18 DPD_VSSR#1 DPB_VSSR#1 AP29 J2 GND#114 GND#56 AL14 C
1.0V_REG AP19 DPD_VSSR#2 DPB_VSSR#2 AP30 J27 GND#115 GND#57 AL17
B33 120R_1.3A DPEF_VDD10 AW20 DPD_VSSR#3 DPB_VSSR#3 AW30 J6 GND#116 GND#58 AL2
AW22 DPD_VSSR#4 DPB_VSSR#4 AW32 J8 GND#117 GND#59 AL20
DPD_VSSR#5 DPB_VSSR#5 K14 GND#118 GND#60 AL21
K7 GND#119 GND#61 AL23 PX_EN 3,10
C280 C281 C282
R59 150R L11 GND#120 GND#62 AL26
1uF_6.3V 1uF_6.3V 100nF AW18 AW28 R60 150R L17 GND#121 GND#63 AL32
DPCD_CALR DPAB_CALR L2 GND#122 GND#64 AL6
DPEF_VDD18 L22 GND#123 GND#65 AL8
DPAB_VDD18 L24 GND#124 GND#66 AM11
DP E/F POWER DP PLL POWER GND#125 GND#67
AH34 AU28 L6 AM31
AJ34 DPE_VDD18#1 DPA_PVDD AV27 M17 GND#126 GND#68 AM9
DPE_VDD18#2 DPA_PVSS M22 GND#127 GND#69 AN11
DPEF_VDD10 DPAB_VDD18 M24 GND#128 GND#70 AN2
N16 GND#129 GND#71 AN30
AL33 AV29 N18 GND#130 GND#72 AN6
AM33 DPE_VDD10#1 DPB_PVDD AR28 N2 GND#131 GND#73 AN8
DPE_VDD10#2 DPB_PVSS N21 GND#132 GND#74 AP11
N23 GND#133 GND#75 AP7
DPCD_VDD18 N26 GND#134 GND#76 AP9
AN34 AU18 N6 GND#135 GND#77 AR5
AP39 DPE_VSSR#1 DPC_PVDD AV17 R15 GND#136 GND#78 B11
AR39 DPE_VSSR#2 DPC_PVSS R17 GND#137 GND#79 B13
AU37 DPE_VSSR#3 R2 GND#138 GND#80 B15
DPE_VSSR#4 DPCD_VDD18 R20 GND#139 GND#81 B17
AV19 R22 GND#140 GND#82 B19
DPEF_VDD18 DPD_PVDD AR18 R24 GND#141 GND#83 B21
DPD_PVSS R27 GND#142 GND#84 B23
AF34 DPEF_VDD18 R6 GND#143 GND#85 B25
AG34 DPF_VDD18#1 T11 GND#144 GND#86 B27
DPF_VDD18#2 AM37 T13 GND#145 GND#87 B29
DPEF_VDD10 DPE_PVDD AN38 T16 GND#146 GND#88 B31
DPE_PVSS T18 GND#147 GND#89 B33
AK33 DPEF_VDD18 T21 GND#148 GND#90 B7
AK34 DPF_VDD10#1 T23 GND#149 GND#91 B9
DPF_VDD10#2 AL38 T26 GND#150 GND#92 C1
DPF_PVDD AM35 U15 GND#151 GND#93 C39
DPF_PVSS U17 GND#153 GND#94 E35
AF39 U2 GND#154 GND#95 E5
AH39 DPF_VSSR#1 U20 GND#155 GND#96 F11
AK39 DPF_VSSR#2 U22 GND#156 GND#97 F13
AL34 DPF_VSSR#3 U24 GND#157 GND#98
AM34 DPF_VSSR#4 U27 GND#158
DPF_VSSR#5 U6 GND#159
V11 GND#160
V16 GND#161
AM39 V18 GND#163
R63 150R DPEF_CALR V21 GND#164
V23 GND#165
B Broadway V26 GND#166 B
W2 GND#167
W6 GND#168
Y15 GND#169
Y17 GND#170
Y20 GND#171
Y22 GND#172 A39
Y24 GND#173 VSS_MECH#1 AW1
Y27 GND#174 VSS_MECH#2 AW39
U13 GND#175 VSS_MECH#3
V13 GND#152
GND#162
Broadway

A A

Advanced Micro Devices Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
Whisler MXM3.0 G5
Size Document Number Rev
D 105-C29247-00B 0
Date: Monday, September 13, 2010 Sheet 4 of 12
5 4 3 2 1
 1 2 3 4 5 6 7 8

U1C
A A
DDR2 DDR2 U1D
GDDR3/GDDR5 GDDR5/GDDR3 DDR2 DDR2
DDR3 DDR3 GDDR3/GDDR5 GDDR5/GDDR3
DQA0_0 C37 G24 MAA0_0 DDR3 DDR3
DQA0_1 C35 DQA0_0/DQA_0 MAA0_0/MAA_0 J23 MAA0_1 DQB0_0 C5 P8 MAB0_0
DQA0_2 A35 DQA0_1/DQA_1 MAA0_1/MAA_1 H24 MAA0_2 DQB0_1 C3 DQB0_0/DQB_0 MAB0_0/MAB_0 T9 MAB0_1

MEMORY INTERFACE A
DQA0_3 E34 DQA0_2/DQA_2 MAA0_2/MAA_2 J24 MAA0_3 DQB0_[31..0] DQB0_2 E3 DQB0_1/DQB_1 MAB0_1/MAB_1 P9 MAB0_2
DQA0_4 G32 DQA0_3/DQA_3 MAA0_3/MAA_3 H26 MAA0_4 7 DQB0_[31..0] DQB0_3 E1 DQB0_2/DQB_2 MAB0_2/MAB_2 N7 MAB0_3

MEMORY INTERFACE B
DQA0_5 D33 DQA0_4/DQA_4 MAA0_4/MAA_4 J26 MAA0_5 DQB1_[31..0] DQB0_4 F1 DQB0_3/DQB_3 MAB0_3/MAB_3 N8 MAB0_4
DQA0_6 F32 DQA0_5/DQA_5 MAA0_5/MAA_5 H21 MAA0_6 7 DQB1_[31..0] DQB0_5 F3 DQB0_4/DQB_4 MAB0_4/MAB_4 N9 MAB0_5
DQA0_[31..0] DQA0_7 E32 DQA0_6/DQA_6 MAA0_6/MAA_6 G21 MAA0_7 MAB0_[8..0] DQB0_6 F5 DQB0_5/DQB_5 MAB0_5/MAB_5 U9 MAB0_6
6 DQA0_[31..0] D31 DQA0_7/DQA_7 MAA0_7/MAA_7 H19 7 MAB0_[8..0] G4 DQB0_6/DQB_6 MAB0_6/MAB_6 U8
DQA0_8 MAA1_0 DQB0_7 MAB0_7
DQA1_[31..0] DQA0_9 F30 DQA0_8/DQA_8 MAA1_0/MAA_8 H20 MAA1_1 MAB1_[8..0] DQB0_8 H5 DQB0_7/DQB_7 MAB0_7/MAB_7 Y9 MAB1_0
6 DQA1_[31..0] C30 DQA0_9/DQA_9 MAA1_1/MAA_9 L13 7 MAB1_[8..0] H6 DQB0_8/DQB_8 MAB1_0/MAB_8 W9
DQA0_10 MAA1_2 DQB0_9 MAB1_1
MAA0_[8..0] DQA0_11 A30 DQA0_10/DQA_10 MAA1_2/MAA_10 G16 MAA1_3 DQB0_10 J4 DQB0_9/DQB_9 MAB1_1/MAB_9 AC8 MAB1_2
6 MAA0_[8..0] DQA0_11/DQA_11 MAA1_3/MAA_11 DQB0_10/DQB_10 MAB1_2/MAB_10
DQA0_12 F28 J16 MAA1_4 DQB0_11 K6 AC9 MAB1_3
MAA1_[8..0] DQA0_13 C28 DQA0_12/DQA_12 MAA1_4/MAA_12 H16 MAA1_5 DQB0_12 K5 DQB0_11/DQB_11 MAB1_3/MAB_11 AA7 MAB1_4
6 MAA1_[8..0] DQA0_13/DQA_13 MAA1_5/MAA_13_BA2 DQB0_12/DQB_12 MAB1_4/MAB_12
DQA0_14 A28 J17 MAA1_6 DQB0_13 L4 AA8 MAB1_5
DQA0_15 E28 DQA0_14/DQA_14 MAA1_6/MAA_14_BA0 H17 MAA1_7 DQB0_14 M6 DQB0_13/DQB_13 MAB1_5/BA2 Y8 MAB1_6
DQA0_16 D27 DQA0_15/DQA_15 MAA1_7/MAA_A15_BA1 DQB0_15 M1 DQB0_14/DQB_14 MAB1_6/BA0 AA9 MAB1_7
DQA0_17 F26 DQA0_16/DQA_16 A32 DQB0_16 M3 DQB0_15/DQB_15 MAB1_7/BA1
DQA0_17/DQA_17 WCKA0_0/DQMA_0 WCKA0_0 6 DQB0_16/DQB_16
DQA0_18 C26 C32 DQB0_17 M5 H3
DQA0_18/DQA_18 WCKA0B_0/DQMA_1 WCKA0b_0 6 DQB0_17/DQB_17 WCKB0_0/DQMB_0 WCKB0_0 7
DQA0_19 A26 D23 WCKA0_1 6 DQB0_18 N4 H1 WCKB0b_0 7
DQA0_20 F24 DQA0_19/DQA_19 WCKA0_1/DQMA_2 E22 DQB0_19 P6 DQB0_18/DQB_18 WCKB0B_0/DQMB_1 T3
DQA0_20/DQA_20 WCKA0B_1/DQMA_3 WCKA0b_1 6 DQB0_19/DQB_19 WCKB0_1/DQMB_2 WCKB0_1 7
DQA0_21 C24 C14 WCKA1_0 6 DQB0_20 P5 T5 WCKB0b_1 7
DQA0_22 A24 DQA0_21/DQA_21 WCKA1_0/DQMA_4 A14 DQB0_21 R4 DQB0_20/DQB_20 WCKB0B_1/DQMB_3 AE4
DQA0_22/DQA_22 WCKA1B_0/DQMA_5 WCKA1b_0 6 DQB0_21/DQB_21 WCKB1_0/DQMB_4 WCKB1_0 7
DQA0_23 E24 E10 DQB0_22 T6 AF5
DQA0_23/DQA_23 WCKA1_1/DQMA_6 WCKA1_1 6 DQB0_22/DQB_22 WCKB1B_0/DQMB_5 WCKB1b_0 7
DQA0_24 C22 D9 WCKA1b_1 6 DQB0_23 T1 AK6 WCKB1_1 7
DQA0_25 A22 DQA0_24/DQA_24 WCKA1B_1/DQMA_7 DQB0_24 U4 DQB0_23/DQB_23 WCKB1_1/DQMB_6 AK5
DQA0_25/DQA_25 GDDR5/DDR2/GDDR3 DQB0_24/DQB_24 WCKB1B_1/DQMB_7 WCKB1b_1 7
DQA0_26 F22 C34 EDCA0_0 6 DQB0_25 V6
DQA0_27 D21 DQA0_26/DQA_26 EDCA0_0/QSA_0/RDQSA_0 D29 DQB0_26 V1 DQB0_25/DQB_25 GDDR5/DDR2/GDDR3 F6
DQA0_27/DQA_27 EDCA0_1/QSA_1/RDQSA_1 EDCA0_1 6 DQB0_26/DQB_26 EDCB0_0/QSB_0/RDQSB_0 EDCB0_0 7
DQA0_28 A20 D25 DQB0_27 V3 K3
DQA0_28/DQA_28 EDCA0_2/QSA_2/RDQSA_2 EDCA0_2 6 DQB0_27/DQB_27 EDCB0_1/QSB_1/RDQSB_1 EDCB0_1 7
DQA0_29 F20 E20 EDCA0_3 6 DQB0_28 Y6 P3 EDCB0_2 7
DQA0_30 D19 DQA0_29/DQA_29 EDCA0_3/QSA_3/RDQSA_3 E16 DQB0_29 Y1 DQB0_28/DQB_28 EDCB0_2/QSB_2/RDQSB_2 V5
DQA0_30/DQA_30 EDCA1_0/QSA_4/RDQSA_4 EDCA1_0 6 DQB0_29/DQB_29 EDCB0_3/QSB_3/RDQSB_3 EDCB0_3 7
DQA0_31 E18 E12 EDCA1_1 6 DQB0_30 Y3 AB5 EDCB1_0 7
DQA1_0 C18 DQA0_31/DQA_31 EDCA1_1/QSA_5/RDQSA_5 J10 DQB0_31 Y5 DQB0_30/DQB_30 EDCB1_0/QSB_4/RDQSB_4 AH1
DQA1_0/DQA_32 EDCA1_2/QSA_6/RDQSA_6 EDCA1_2 6 DQB0_31/DQB_31 EDCB1_1/QSB_5/RDQSB_5 EDCB1_1 7
DQA1_1 A18 D7 DQB1_0 AA4 AJ9
DQA1_1/DQA_33 EDCA1_3/QSA_7/RDQSA_7 EDCA1_3 6 DQB1_0/DQB_32 EDCB1_2/QSB_6/RDQSB_6 EDCB1_2 7
B DQA1_2 F18 DQB1_1 AB6 AM5 EDCB1_3 7 B
DQA1_3 D17 DQA1_2/DQA_34 A34 DQB1_2 AB1 DQB1_1/DQB_33 EDCB1_3/QSB_7/RDQSB_7
DQA1_3/DQA_35 DDBIA0_0/QSA_0B/WDQSA_0 DDBIA0_0 6 DQB1_2/DQB_34
DQA1_4 A16 E30 DDBIA0_1 6 DQB1_3 AB3 G7 DDBIB0_0 7
DQA1_5 F16 DQA1_4/DQA_36 DDBIA0_1/QSA_1B/WDQSA_1 E26 DQB1_4 AD6 DQB1_3/DQB_35 DDBIB0_0/QSB_0B/WDQSB_0 K1
DQA1_5/DQA_37 DDBIA0_2/QSA_2B/WDQSA_2 DDBIA0_2 6 DQB1_4/DQB_36 DDBIB0_1/QSB_1B/WDQSB_1 DDBIB0_1 7
DQA1_6 D15 C20 DQB1_5 AD1 P1
DQA1_6/DQA_38 DDBIA0_3/QSA_3B/WDQSA_3 DDBIA0_3 6 DQB1_5/DQB_37 DDBIB0_2/QSB_2B/WDQSB_2 DDBIB0_2 7
DQA1_7 E14 C16 DDBIA1_0 6 DQB1_6 AD3 W4 DDBIB0_3 7
DQA1_8 F14 DQA1_7/DQA_39 DDBIA1_0/QSA_4B/WDQSA_4 C12 DQB1_7 AD5 DQB1_6/DQB_38 DDBIB0_3/QSB_3B/WDQSB_3 AC4
DQA1_8/DQA_40 DDBIA1_1/QSA_5B/WDQSA_5 DDBIA1_1 6 DQB1_7/DQB_39 DDBIB1_0/QSB_4B/WDQSB_4 DDBIB1_0 7
DQA1_9 D13 J11 DDBIA1_2 6 DQB1_8 AF1 AH3 DDBIB1_1 7
DQA1_10 F12 DQA1_9/DQA_41 DDBIA1_2/QSA_6B/WDQSA_6 F8 DQB1_9 AF3 DQB1_8/DQB_40 DDBIB1_1/QSB_5B/WDQSB_5 AJ8
DQA1_10/DQA_42 DDBIA1_3/QSA_7B/WDQSA_7 DDBIA1_3 6 DQB1_9/DQB_41 DDBIB1_2/QSB_6B/WDQSB_6 DDBIB1_2 7
DQA1_11 A12 DQB1_10 AF6 AM3
DQA1_11/DQA_43 DQB1_10/DQB_42 DDBIB1_3/QSB_7B/WDQSB_7 DDBIB1_3 7
DQA1_12 D11 J21 ADBIA0 6 DQB1_11 AG4
DQA1_13 F10 DQA1_12/DQA_44 ADBIA0/ODTA0 G19 DQB1_12 AH5 DQB1_11/DQB_43 T7
DQA1_13/DQA_45 ADBIA1/ODTA1 ADBIA1 6 DQB1_12/DQB_44 ADBIB0/ODTB0 ADBIB0 7
DQA1_14 A10 DQB1_13 AH6 W7 ADBIB1 7
DQA1_15 C10 DQA1_14/DQA_46 H27 DQB1_14 AJ4 DQB1_13/DQB_45 ADBIB1/ODTB1
DQA1_15/DQA_47 CLKA0 CLKA0 6 DQB1_14/DQB_46
DQA1_16 G13 G27 DQB1_15 AK3 L9
DQA1_16/DQA_48 CLKA0B CLKA0b 6 DQB1_15/DQB_47 CLKB0 CLKB0 7
DQA1_17 H13 DQB1_16 AF8 L8 CLKB0b 7
DQA1_18 J13 DQA1_17/DQA_49 J14 DQB1_17 AF9 DQB1_16/DQB_48 CLKB0B
DQA1_18/DQA_50 CLKA1 CLKA1 6 DQB1_17/DQB_49
DQA1_19 H11 H14 CLKA1b 6 DQB1_18 AG8 AD8 CLKB1 7
DQA1_20 G10 DQA1_19/DQA_51 CLKA1B DQB1_19 AG7 DQB1_18/DQB_50 CLKB1 AD7
DQA1_20/DQA_52 DQB1_19/DQB_51 CLKB1B CLKB1b 7
DQA1_21 G8 K23 DQB1_20 AK9
DQA1_21/DQA_53 RASA0B RASA0b 6 DQB1_20/DQB_52
DQA1_22 K9 K19 RASA1b 6 DQB1_21 AL7 T10 RASB0b 7
DQA1_23 K10 DQA1_22/DQA_54 RASA1B DQB1_22 AM8 DQB1_21/DQB_53 RASB0B Y10
DQA1_23/DQA_55 DQB1_22/DQB_54 RASB1B RASB1b 7
DQA1_24 G9 K20 CASA0b 6 DQB1_23 AM7
+1.5V_REG DQA1_25 A8 DQA1_24/DQA_56 CASA0B K17 DQB1_24 AK1 DQB1_23/DQB_55 W10
DQA1_25/DQA_57 CASA1B CASA1b 6 DQB1_24/DQB_56 CASB0B CASB0b 7
DQA1_26 C8 DQB1_25 AL4 AA10
DQA1_26/DQA_58 +1.5V_REG DQB1_25/DQB_57 CASB1B CASB1b 7
DQA1_27 E8 K24 CSA0b_0 6 DQB1_26 AM6
DQA1_28 A6 DQA1_27/DQA_59 CSA0B_0 K27 DQB1_27 AM1 DQB1_26/DQB_58 P10
DQA1_28/DQA_60 CSA0B_1 DQB1_27/DQB_59 CSB0B_0 CSB0b_0 7
R8442 DQA1_29 C6 DQB1_28 AN4 L10
40.2R DQA1_30 E6 DQA1_29/DQA_61 M13 DQB1_29 AP3 DQB1_28/DQB_60 CSB0B_1
DQA1_30/DQA_62 CSA1B_0 CSA1b_0 6 DQB1_29/DQB_61
DQA1_31 A5 K16 R8443 DQB1_30 AP1 AD10
DQA1_31/DQA_63 CSA1B_1 DQB1_30/DQB_62 CSB1B_0 CSB1b_0 7
40.2R DQB1_31 AP5 AC10
L18 K21 DQB1_31/DQB_63 CSB1B_1
+1.5V_REG MVREFDA CKEA0 CKEA0 6
L20 J20 CKEA1 6 U10 CKEB0 7
MVREFSA CKEA1 Y12 CKEB0 AA11
MVREFDB CKEB1 CKEB1 7
R8426 C1197 R67 243R L27 K26 AA12
MEM_CALRN0 WEA0B WEA0b 6 MVREFSB
100R 1uF_6.3V R70 243R N12 L15 WEA1b 6 N10 WEB0b 7
+1.5V_REG R68 243R AG12 MEM_CALRN1 WEA1B R8427 C1198 WEB0B AB11
MEM_CALRN2 WEB1B WEB1b 7
100R 1uF_6.3V
C +1.5V_REG C
R71 243R M12 H23 MAA0_8
MEM_CALRP1 MAA0_8
GDDR5

R8428 R73 243R M27 J19 MAA1_8 AD28 T8 MAB0_8

MEM_CALRP0 MAA1_8 TESTEN MAB0_8

GDDR5
40.2R R75 243R AH12 W8 MAB1_8
MEM_CALRP2 R8429 TEST_MCLK AK10 MAB1_8
40.2R TEST_YCLK AL10 CLKTESTA AH11 10R R8430 49.9R R8431
CLKTESTB DRAM_RST DRAM_RST 6,7

R8433 C1202
R8432 C1201 3.01K 120pF_50V
100R 1uF_6.3V
Broadway R8434 C1203 C821
100R 1uF_6.3V 100nF Broadway

C822
100nF

R79

51.1R
2 TESTEN
R80

+3VRUN 51.1R

R570 5.11K

R571 1K

D D

Advanced Micro Devices Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
Whisler MXM3.0 G5
Size Document Number Rev
C 105-C29247-00B 0
Date: Monday, September 13, 2010 Sheet 5 of 12
1 2 3 4 5 6 7 8
 5 4 3 2 1

CH_A0 =U201 & U202

U201 +1.5V_REG U202 GDDR5 +1.5V_REG U401 GDDR5 +1.5V_REG
5 DQA0_[31..0] +1.5V_REG
5 DQA0_[31..0] 5 DQA1_[31..0] 5 DQA1_[31..0] U402 GDDR5
M2 B1 M2 B1 M2 B1
M4 DQ31 | DQ7 VDDQ-B1 B3 M4 DQ31 | DQ7 VDDQ-B1 B3 M4 DQ31 | DQ7 VDDQ-B1 B3 M2 B1
N2 DQ30 | DQ6 VDDQ-B3 B12 N2 DQ30 | DQ6 VDDQ-B3 B12 N2 DQ30 | DQ6 VDDQ-B3 B12 M4 DQ31 | DQ7 VDDQ-B1 B3
N4 DQ29 | DQ5 VDDQ-B12 B14 N4 DQ29 | DQ5 VDDQ-B12 B14 N4 DQ29 | DQ5 VDDQ-B12 B14 N2 DQ30 | DQ6 VDDQ-B3 B12
T2 DQ28 | DQ4 VDDQ-B14 D1 T2 DQ28 | DQ4 VDDQ-B14 D1 T2 DQ28 | DQ4 VDDQ-B14 D1 N4 DQ29 | DQ5 VDDQ-B12 B14
T4 DQ27 | DQ3 VDDQ-D1 D3 T4 DQ27 | DQ3 VDDQ-D1 D3 T4 DQ27 | DQ3 VDDQ-D1 D3 T2 DQ28 | DQ4 VDDQ-B14 D1
V2 DQ26 | DQ2 VDDQ-D3 D12 V2 DQ26 | DQ2 VDDQ-D3 D12 V2 DQ26 | DQ2 VDDQ-D3 D12 T4 DQ27 | DQ3 VDDQ-D1 D3
V4 DQ25 | DQ1 VDDQ-D12 D14 V4 DQ25 | DQ1 VDDQ-D12 D14 V4 DQ25 | DQ1 VDDQ-D12 D14 V2 DQ26 | DQ2 VDDQ-D3 D12
DQA0_17 M13 DQ24 | DQ0 VDDQ-D14 E5 DQA0_15 M13 DQ24 | DQ0 VDDQ-D14 E5 DQA1_15 M13 DQ24 | DQ0 VDDQ-D14 E5 V4 DQ25 | DQ1 VDDQ-D12 D14
DQA0_18 M11 DQ23 | DQ15 VDDQ-E5 E10 DQA0_12 M11 DQ23 | DQ15 VDDQ-E5 E10 DQA1_12 M11 DQ23 | DQ15 VDDQ-E5 E10 DQA1_17 M13 DQ24 | DQ0 VDDQ-D14 E5
DQA0_16 N13 DQ22 | DQ14 VDDQ-E10 F1 DQA0_14 N13 DQ22 | DQ14 VDDQ-E10 F1 DQA1_14 N13 DQ22 | DQ14 VDDQ-E10 F1 DQA1_16 M11 DQ23 | DQ15 VDDQ-E5 E10
DQA0_19 N11 DQ21 | DQ13 VDDQ-F1 F3 DQA0_13 N11 DQ21 | DQ13 VDDQ-F1 F3 DQA1_13 N11 DQ21 | DQ13 VDDQ-F1 F3 DQA1_19 N13 DQ22 | DQ14 VDDQ-E10 F1
DQA0_23 T13 DQ20 | DQ12 VDDQ-F3 F12 DQA0_8 T13 DQ20 | DQ12 VDDQ-F3 F12 DQA1_10 T13 DQ20 | DQ12 VDDQ-F3 F12 DQA1_18 N11 DQ21 | DQ13 VDDQ-F1 F3
D
DQA0_21 T11 DQ19 | DQ11 VDDQ-F12 F14 DQA0_11 T11 DQ19 | DQ11 VDDQ-F12 F14 DQA1_11 T11 DQ19 | DQ11 VDDQ-F12 F14 DQA1_21 T13 DQ20 | DQ12 VDDQ-F3 F12 D
DQA0_22 V13 DQ18 | DQ10 VDDQ-F14 G2 DQA0_10 V13 DQ18 | DQ10 VDDQ-F14 G2 DQA1_9 V13 DQ18 | DQ10 VDDQ-F14 G2 DQA1_22 T11 DQ19 | DQ11 VDDQ-F12 F14
DQA0_20 V11 DQ17 | DQ9 VDDQ-G2 G13 DQA0_9 V11 DQ17 | DQ9 VDDQ-G2 G13 DQA1_8 V11 DQ17 | DQ9 VDDQ-G2 G13 DQA1_20 V13 DQ18 | DQ10 VDDQ-F14 G2
F13 DQ16 | DQ8 VDDQ-G13 H3 F13 DQ16 | DQ8 VDDQ-G13 H3 F13 DQ16 | DQ8 VDDQ-G13 H3 DQA1_23 V11 DQ17 | DQ9 VDDQ-G2 G13
F11 DQ15 | DQ23 VDDQ-H3 H12 F11 DQ15 | DQ23 VDDQ-H3 H12 F11 DQ15 | DQ23 VDDQ-H3 H12 F13 DQ16 | DQ8 VDDQ-G13 H3
E13 DQ14 | DQ22 VDDQ-H12 K3 E13 DQ14 | DQ22 VDDQ-H12 K3 E13 DQ14 | DQ22 VDDQ-H12 K3 F11 DQ15 | DQ23 VDDQ-H3 H12
DQ13 | DQ21 VDDQ-K3 M=1 DQ13 | DQ21 VDDQ-K3 M=1 DQ13 | DQ21 VDDQ-K3 DQ14 | DQ22 VDDQ-H12
E11 K12 E11 K12 E11 K12 E13 K3
B13 DQ12 | DQ20 VDDQ-K12 L2
Mirror B13 DQ12 | DQ20 VDDQ-K12 L2
Mirror B13 DQ12 | DQ20 VDDQ-K12 L2 E11 DQ13 | DQ21 VDDQ-K3 K12
B11 DQ11 | DQ19 VDDQ-L2 L13 B11 DQ11 | DQ19 VDDQ-L2 L13 B11 DQ11 | DQ19 VDDQ-L2 L13 B13 DQ12 | DQ20 VDDQ-K12 L2
A13 DQ10 | DQ18 VDDQ-L13 M1 A13 DQ10 | DQ18 VDDQ-L13 M1 A13 DQ10 | DQ18 VDDQ-L13 M1 B11 DQ11 | DQ19 VDDQ-L2 L13
A11 DQ9 | DQ17 VDDQ-M1 M3 A11 DQ9 | DQ17 VDDQ-M1 M3 A11 DQ9 | DQ17 VDDQ-M1 M3 A13 DQ10 | DQ18 VDDQ-L13 M1
DQA0_7 F2 DQ8 | DQ16 VDDQ-M3 M12 DQA0_30 F2 DQ8 | DQ16 VDDQ-M3 M12 DQA1_26 F2 DQ8 | DQ16 VDDQ-M3 M12 A11 DQ9 | DQ17 VDDQ-M1 M3
DQA0_5 F4 DQ7 | DQ31 VDDQ-M12 M14 DQA0_27 F4 DQ7 | DQ31 VDDQ-M12 M14 DQA1_27 F4 DQ7 | DQ31 VDDQ-M12 M14 DQA1_2 F2 DQ8 | DQ16 VDDQ-M3 M12
DQA0_6 E2 DQ6 | DQ30 VDDQ-M14 N5 DQA0_31 E2 DQ6 | DQ30 VDDQ-M14 N5 DQA1_24 E2 DQ6 | DQ30 VDDQ-M14 N5 DQA1_4 F4 DQ7 | DQ31 VDDQ-M12 M14
DQA0_4 E4 DQ5 | DQ29 VDDQ-N5 N10 DQA0_26 E4 DQ5 | DQ29 VDDQ-N5 N10 DQA1_25 E4 DQ5 | DQ29 VDDQ-N5 N10 DQA1_3 E2 DQ6 | DQ30 VDDQ-M14 N5
DQA0_0 B2 DQ4 | DQ28 VDDQ-N10 P1 DQA0_29 B2 DQ4 | DQ28 VDDQ-N10 P1 DQA1_31 B2 DQ4 | DQ28 VDDQ-N10 P1 DQA1_6 E4 DQ5 | DQ29 VDDQ-N5 N10
DQA0_3 B4 DQ3 | DQ27 VDDQ-P1 P3 DQA0_24 B4 DQ3 | DQ27 VDDQ-P1 P3 DQA1_28 B4 DQ3 | DQ27 VDDQ-P1 P3 DQA1_0 B2 DQ4 | DQ28 VDDQ-N10 P1
DQA0_1 A2 DQ2 | DQ26 VDDQ-P3 P12 DQA0_28 A2 DQ2 | DQ26 VDDQ-P3 P12 DQA1_30 A2 DQ2 | DQ26 VDDQ-P3 P12 DQA1_7 B4 DQ3 | DQ27 VDDQ-P1 P3
DQA0_2 A4 DQ1 | DQ25 VDDQ-P12 P14 DQA0_25 A4 DQ1 | DQ25 VDDQ-P12 P14 DQA1_29 A4 DQ1 | DQ25 VDDQ-P12 P14 DQA1_1 A2 DQ2 | DQ26 VDDQ-P3 P12
DQ0 | DQ24 VDDQ-P14 T1 DQ0 | DQ24 VDDQ-P14 T1 DQ0 | DQ24 VDDQ-P14 T1 DQA1_5 A4 DQ1 | DQ25 VDDQ-P12 P14
+1.5V_REG VDDQ-T1 VDDQ-T1 VDDQ-T1 DQ0 | DQ24 VDDQ-P14
T3 T3 T3 T1
VDDQ-T3 VDDQ-T3 VDDQ-T3 +1.5V_REG VDDQ-T1
CLKA0 R301 60.4R T12 T12 T12 T3
5 CLKA0 VDDQ-T12 VDDQ-T12 VDDQ-T12 VDDQ-T3
CLKA0b R300 60.4R T14 T14 T14 CLKA1 R401 60.4R T12
5 CLKA0b VDDQ-T14 +1.5V_REG VDDQ-T14 +1.5V_REG VDDQ-T14 +1.5V_REG 5 CLKA1 VDDQ-T12 T14
5 MAA0_[8..0] 5 MAA0_[8..0] 5 MAA1_[8..0] CLKA1b R400 60.4R
5 CLKA1b VDDQ-T14 +1.5V_REG
MAA0_8 J5 MAA0_8 J5 MAA1_8 J5 5 MAA1_[8..0]
MAA0_7 K4 RFU/A12/NC C5 MAA0_0 K4 RFU/A12/NC C5 MAA1_0 K4 RFU/A12/NC C5 MAA1_8 J5
MAA0_6 K5 A7/A8 | A0/A10 VDD-C5 C10 MAA0_1 K5 A7/A8 | A0/A10 VDD-C5 C10 MAA1_1 K5 A7/A8 | A0/A10 VDD-C5 C10 MAA1_7 K4 RFU/A12/NC C5
MAA0_5 K10 A6/A11 | A1/A9 VDD-C10 D11 MAA0_3 K10 A6/A11 | A1/A9 VDD-C10 D11 MAA1_3 K10 A6/A11 | A1/A9 VDD-C10 D11 MAA1_6 K5 A7/A8 | A0/A10 VDD-C5 C10
MAA0_4 K11 A5/BA1 | A3/BA3 VDD-D11 G1 MAA0_2 K11 A5/BA1 | A3/BA3 VDD-D11 G1 MAA1_2 K11 A5/BA1 | A3/BA3 VDD-D11 G1 MAA1_5 K10 A6/A11 | A1/A9 VDD-C10 D11
MAA0_3 H10 A4/BA2 | A2/BA0 VDD-G1 G4 MAA0_5 H10 A4/BA2 | A2/BA0 VDD-G1 G4 MAA1_5 H10 A4/BA2 | A2/BA0 VDD-G1 G4 MAA1_4 K11 A5/BA1 | A3/BA3 VDD-D11 G1
MAA0_2 H11 A3/BA3 | A5/BA1 VDD-G4 G11 MAA0_4 H11 A3/BA3 | A5/BA1 VDD-G4 G11 MAA1_4 H11 A3/BA3 | A5/BA1 VDD-G4 G11 MAA1_3 H10 A4/BA2 | A2/BA0 VDD-G1 G4
MAA0_1 H5 A2 /BA0 | A4/BA2 VDD-G11 G14 MAA0_6 H5 A2 /BA0 | A4/BA2 VDD-G11 G14 MAA1_6 H5 A2 /BA0 | A4/BA2 VDD-G11 G14 MAA1_2 H11 A3/BA3 | A5/BA1 VDD-G4 G11
MAA0_0 H4 A1/A9 | A6/A11 VDD-G14 L1 MAA0_7 H4 A1/A9 | A6/A11 VDD-G14 L1 MAA1_7 H4 A1/A9 | A6/A11 VDD-G14 L1 MAA1_1 H5 A2 /BA0 | A4/BA2 VDD-G11 G14
A0/A10 | A7/A8 VDD-L1 L4 A0/A10 | A7/A8 VDD-L1 L4 A0/A10 | A7/A8 VDD-L1 L4 MAA1_0 H4 A1/A9 | A6/A11 VDD-G14 L1
VDD-L4 L11 VDD-L4 L11 VDD-L4 L11 A0/A10 | A7/A8 VDD-L1 L4
VDD-L11 L14 VDD-L11 L14 VDD-L11 L14 VDD-L4 L11
D4 VDD-L14 P11 D4 VDD-L14 P11 D4 VDD-L14 P11 VDD-L11 L14
5 WCKA0_0 WCK01 | WCK23 VDD-P11 5 WCKA0_1 WCK01 | WCK23 VDD-P11 5 WCKA1_1 WCK01 | WCK23 VDD-P11 VDD-L14
C 5 WCKA0b_0 D5 R5 5 WCKA0b_1 D5 R5 D5 R5 D4 P11 C
WCK01# | WCK23# VDD-R5 R10 WCK01# | WCK23# VDD-R5 R10 5 WCKA1b_1 WCK01# | WCK23# VDD-R5 R10 5 WCKA1_0 D5 WCK01 | WCK23 VDD-P11 R5
VDD-R10 VDD-R10 VDD-R10 5 WCKA1b_0 WCK01# | WCK23# VDD-R5
5 WCKA0_1 P4 5 WCKA0_0 P4 P4 R10
WCK23 | WCK01 WCK23 | WCK01 5 WCKA1_0 WCK23 | WCK01 VDD-R10
P5 P5 P5 P4
5 WCKA0b_1 WCK23# | WCK01# 5 WCKA0b_0 WCK23# | WCK01# 5 WCKA1b_0 WCK23# | WCK01# 5 WCKA1_1 WCK23 | WCK01
A1 A1 A1 P5
VSSQ-A1 VSSQ-A1 VSSQ-A1 5 WCKA1b_1 WCK23# | WCK01#
R2 A3 R2 A3 R2 A3 A1
R13 EDC3 | EDC0 VSSQ-A3 A12 R13 EDC3 | EDC0 VSSQ-A3 A12 R13 EDC3 | EDC0 VSSQ-A3 A12 R2 VSSQ-A1 A3
5 EDCA0_2 EDC2 | EDC1 VSSQ-A12 5 EDCA0_1 EDC2 | EDC1 VSSQ-A12 5 EDCA1_1 EDC2 | EDC1 VSSQ-A12 EDC3 | EDC0 VSSQ-A3
C13 A14 C13 A14 C13 A14 5 EDCA1_2 R13 A12
C2 EDC1 | EDC2 VSSQ-A14 C1 C2 EDC1 | EDC2 VSSQ-A14 C1 C2 EDC1 | EDC2 VSSQ-A14 C1 C13 EDC2 | EDC1 VSSQ-A12 A14
5 EDCA0_0 EDC0 | EDC3 VSSQ-C1 5 EDCA0_3 EDC0 | EDC3 VSSQ-C1 5 EDCA1_3 EDC0 | EDC3 VSSQ-C1 EDC1 | EDC2 VSSQ-A14
C3 C3 C3 C2 C1
VSSQ-C3 VSSQ-C3 VSSQ-C3 5 EDCA1_0 EDC0 | EDC3 VSSQ-C1
+1.5V_REG P2 C4 +1.5V_REG P2 C4 +1.5V_REG P2 C4 C3
P13 DBI3# | DBI0# VSSQ-C4 C11 P13 DBI3# | DBI0# VSSQ-C4 C11 P13 DBI3# | DBI0# VSSQ-C4 C11 P2 VSSQ-C3 C4
5 DDBIA0_2 DBI2 #| DBI1# VSSQ-C11 5 DDBIA0_1 DBI2 #| DBI1# VSSQ-C11 5 DDBIA1_1 DBI2 #| DBI1# VSSQ-C11 +1.5V_REG DBI3# | DBI0# VSSQ-C4
+1.5V_REG D13 C12 +1.5V_REG D13 C12 +1.5V_REG D13 C12 5 DDBIA1_2 P13 C11
D2 DBI1# | DBI2# VSSQ-C12 C14 D2 DBI1# | DBI2# VSSQ-C12 C14 D2 DBI1# | DBI2# VSSQ-C12 C14 D13 DBI2 #| DBI1# VSSQ-C11 C12
5 DDBIA0_0 DBI0# | DBI3# VSSQ-C14 5 DDBIA0_3 DBI0# | DBI3# VSSQ-C14 5 DDBIA1_3 DBI0# | DBI3# VSSQ-C14 +1.5V_REG DBI1# | DBI2# VSSQ-C12
E1 E1 E1 D2 C14
VSSQ-E1 VSSQ-E1 VSSQ-E1 5 DDBIA1_0 DBI0# | DBI3# VSSQ-C14
E3 E3 E3 E1
VSSQ-E3 E12 VSSQ-E3 E12 VSSQ-E3 E12 VSSQ-E1 E3
G3 VSSQ-E12 E14 G3 VSSQ-E12 E14 G3 VSSQ-E12 E14 VSSQ-E3 E12
5 RASA0b RAS# | CAS# VSSQ-E14 5 CASA0b RAS# | CAS# VSSQ-E14 5 CASA1b RAS# | CAS# VSSQ-E14 VSSQ-E12
L3 F5 L3 F5 L3 F5 G3 E14
5 CASA0b CAS# | RAS# VSSQ-F5 5 RASA0b CAS# | RAS# VSSQ-F5 5 RASA1b CAS# | RAS# VSSQ-F5 5 RASA1b RAS# | CAS# VSSQ-E14
F10 F10 F10 L3 F5
VSSQ-F10 VSSQ-F10 VSSQ-F10 5 CASA1b CAS# | RAS# VSSQ-F5
H2 H2 H2 F10
J3 VSSQ-H2 H13 J3 VSSQ-H2 H13 J3 VSSQ-H2 H13 VSSQ-F10 H2
5 CKEA0 CKE# VSSQ-H13 5 CKEA0 CKE# VSSQ-H13 5 CKEA1 CKE# VSSQ-H13 VSSQ-H2
CLKA0b J11 K2 CLKA0b J11 K2 CLKA1b J11 K2 5 CKEA1 J3 H13
CLKA0 J12 CK# VSSQ-K2 K13 CLKA0 J12 CK# VSSQ-K2 K13 CLKA1 J12 CK# VSSQ-K2 K13 CLKA1b J11 CKE# VSSQ-H13 K2
CK VSSQ-K13 M5 CK VSSQ-K13 M5 CK VSSQ-K13 M5 CLKA1 J12 CK# VSSQ-K2 K13
VSSQ-M5 M10 VSSQ-M5 M10 VSSQ-M5 M10 CK VSSQ-K13 M5
G12 VSSQ-M10 N1 G12 VSSQ-M10 N1 G12 VSSQ-M10 N1 VSSQ-M5 M10
5 CSA0b_0 CS# | WE# VSSQ-N1 5 WEA0b CS# | WE# VSSQ-N1 5 WEA1b CS# | WE# VSSQ-N1 VSSQ-M10
5 WEA0b L12 N3 5 CSA0b_0 L12 N3 5 CSA1b_0 L12 N3 5 CSA1b_0 G12 N1
WE# | CS# VSSQ-N3 N12 WE# | CS# VSSQ-N3 N12 WE# | CS# VSSQ-N3 N12 L12 CS# | WE# VSSQ-N1 N3
VSSQ-N12 VSSQ-N12 VSSQ-N12 5 WEA1b WE# | CS# VSSQ-N3
N14 N14 N14 N12
R308 120R 1% J13 VSSQ-N14 R1 R358 120R 1% J13 VSSQ-N14 R1 R408 120R1% J13 VSSQ-N14 R1 VSSQ-N12 N14
J10 ZQ VSSQ-R1 R3 J10 ZQ VSSQ-R1 R3 J10 ZQ VSSQ-R1 R3 R458 120R 1% J13 VSSQ-N14 R1
SEN VSSQ-R3 R4 SEN VSSQ-R3 R4 SEN VSSQ-R3 R4 J10 ZQ VSSQ-R1 R3
VSSQ-R4 R11 VSSQ-R4 R11 VSSQ-R4 R11 SEN VSSQ-R3 R4
J2 VSSQ-R11 R12 J2 VSSQ-R11 R12 J2 VSSQ-R11 R12 VSSQ-R4 R11
5,7 DRAM_RST RESET# VSSQ-R12 5,7 DRAM_RST RESET# VSSQ-R12 5,7 DRAM_RST RESET# VSSQ-R12 VSSQ-R11
J1 R14 +1.5V_REG J1 R14 +1.5V_REG J1 R14 5,7 DRAM_RST J2 R12
MF VSSQ-R14 V1 MF VSSQ-R14 V1 MF VSSQ-R14 V1 J1 RESET# VSSQ-R12 R14
VSSQ-V1 V3 VSSQ-V1 V3 VSSQ-V1 V3 MF VSSQ-R14 V1
B VSSQ-V3 V12 VSSQ-V3 V12 VSSQ-V3 V12 VSSQ-V1 V3 B
VSSQ-V12 V14 VSSQ-V12 V14 VSSQ-V12 V14 VSSQ-V3 V12
A5 VSSQ-V14 A5 VSSQ-V14 A5 VSSQ-V14 VSSQ-V12 V14
V5 Vpp,NC V5 Vpp,NC V5 Vpp,NC A5 VSSQ-V14
Vpp,NC1 B5 C389 1uF_6.3V Vpp,NC1 B5 Vpp,NC1 B5 V5 Vpp,NC
VREFD2_A0 A10 VSS-B5 B10 R352 2.37K 1% VREFD1_A0 A10 VSS-B5 B10 VREFD2_A1 A10 VSS-B5 B10 C489 1uF_6.3V Vpp,NC1 B5
VREFD1 VSS-B10 +1.5V_REG VREFD1 VSS-B10 VREFD1 VSS-B10 VSS-B5
V10 D10 R353 5.49K 1% V10 D10 V10 D10 R452 2.37K 1% VREFD1_A1 A10 B10
VREFD2 VSS-D10 VREFD2 VSS-D10 VREFD2 VSS-D10 +1.5V_REG VREFD1 VSS-B10
VREFD1_A0 G5 C390 1uF_6.3V G5 VREFD1_A1 G5 R453 5.49K 1% V10 D10
VSS-G5 G10 VSS-G5 G10 VSS-G5 G10 C490 1uF_6.3V VREFD2 VSS-D10 G5
VSS-G10 H1 C391 1uF_6.3V VSS-G10 H1 VSS-G10 H1 VSS-G5 G10
VSS-H1 H14 R354 2.37K 1% VSS-H1 H14 VSS-H1 H14 C491 1uF_6.3V VSS-G10 H1
VSS-H14 +1.5V_REG VSS-H14 VSS-H14 VSS-H1
K1 R355 5.49K 1% VREFD2_A0 K1 K1 R454 2.37K 1% H14
VSS-K1 VSS-K1 VSS-K1 +1.5V_REG VSS-H14
VREFC_A0 J14 K14 C392 1uF_6.3V J14 K14 VREFC_A1 J14 K14 R455 5.49K 1% VREFD2_A1 K1
VREFC VSS-K14 L5 VREFC VSS-K14 L5 VREFC VSS-K14 L5 C492 1uF_6.3V J14 VSS-K1 K14
VSS-L5 L10 C393 1uF_6.3V VSS-L5 L10 VSS-L5 L10 VREFC VSS-K14 L5
VSS-L10 P10 R356 2.37K 1% VSS-L10 P10 VSS-L10 P10 VSS-L5 L10
VSS-P10 +1.5V_REG VSS-P10 VSS-P10 VSS-L10
J4 T5 R357 5.49K 1% VREFC_A0 J4 T5 J4 T5 C493 1uF_6.3V P10
ABI# VSS-T5 T10 C394 1uF_6.3V ABI# VSS-T5 T10 ABI# VSS-T5 T10 R456 1% 2.37K 1% J4 VSS-P10 T5
VSS-T10 VSS-T10 VSS-T10 +1.5V_REG ABI# VSS-T5
R457 5.49K 1% VREFC_A1 T10
C494 1uF_6.3V VSS-T10

5 ADBIA0 GDDR5 5 ADBIA0 GDDR5 5 ADBIA1 GDDR5

5 ADBIA1 GDDR5

+1.5V_REG

+1.5V_REG

C334 C335 C336 C337 C338 C386 C388 C484 C485 C486 C487 C488
C321

C322

C323

C311

C312

C313

C314

C315

C316

C317

C318

C319

C320

C362

C363

C364

C365

C366

C367

C368

C369

C411

C412

C413

C415

C420

C462

C464

C468

C476

C477

10uF_2.5V

10uF_2.5V

10uF_2.5V

10uF_2.5V

10uF_2.5V

10uF_2.5V

10uF_2.5V

10uF_2.5V

10uF_2.5V

10uF_2.5V

10uF_2.5V

10uF_2.5V
A A
1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

1uF_6.3V

Advanced Micro Devices Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
Whisler MXM3.0 G5
Size Document Number Rev
C 105-C29247-00B 0
Date: Monday, September 13, 2010 Sheet 6 of 12
5 4 3 2 1
 5 4 3 2 1

CH_B0 =U601 & U602

U601 +1.5V_REG U602 GDDR5 +1.5V_REG U801 GDDR5 +1.5V_REG
5 DQB0_[31..0] +1.5V_REG
5 DQB0_[31..0] 5 DQB1_[31..0] 5 DQB1_[31..0] U802 GDDR5
M2 B1 M2 B1 M2 B1
M4 DQ31 | DQ7 VDDQ-B1 B3 M4 DQ31 | DQ7 VDDQ-B1 B3 M4 DQ31 | DQ7 VDDQ-B1 B3 M2 B1
N2 DQ30 | DQ6 VDDQ-B3 B12 N2 DQ30 | DQ6 VDDQ-B3 B12 N2 DQ30 | DQ6 VDDQ-B3 B12 M4 DQ31 | DQ7 VDDQ-B1 B3
N4 DQ29 | DQ5 VDDQ-B12 B14 N4 DQ29 | DQ5 VDDQ-B12 B14 N4 DQ29 | DQ5 VDDQ-B12 B14 N2 DQ30 | DQ6 VDDQ-B3 B12
T2 DQ28 | DQ4 VDDQ-B14 D1 T2 DQ28 | DQ4 VDDQ-B14 D1 T2 DQ28 | DQ4 VDDQ-B14 D1 N4 DQ29 | DQ5 VDDQ-B12 B14
T4 DQ27 | DQ3 VDDQ-D1 D3 T4 DQ27 | DQ3 VDDQ-D1 D3 T4 DQ27 | DQ3 VDDQ-D1 D3 T2 DQ28 | DQ4 VDDQ-B14 D1
V2 DQ26 | DQ2 VDDQ-D3 D12 V2 DQ26 | DQ2 VDDQ-D3 D12 V2 DQ26 | DQ2 VDDQ-D3 D12 T4 DQ27 | DQ3 VDDQ-D1 D3
V4 DQ25 | DQ1 VDDQ-D12 D14 V4 DQ25 | DQ1 VDDQ-D12 D14 V4 DQ25 | DQ1 VDDQ-D12 D14 V2 DQ26 | DQ2 VDDQ-D3 D12
DQB0_18 M13 DQ24 | DQ0 VDDQ-D14 E5 DQB0_14 M13 DQ24 | DQ0 VDDQ-D14 E5 DQB1_13 M13 DQ24 | DQ0 VDDQ-D14 E5 V4 DQ25 | DQ1 VDDQ-D12 D14
DQB0_19 M11 DQ23 | DQ15 VDDQ-E5 E10 DQB0_13 M11 DQ23 | DQ15 VDDQ-E5 E10 DQB1_15 M11 DQ23 | DQ15 VDDQ-E5 E10 DQB1_17 M13 DQ24 | DQ0 VDDQ-D14 E5
DQB0_17 N13 DQ22 | DQ14 VDDQ-E10 F1 DQB0_12 N13 DQ22 | DQ14 VDDQ-E10 F1 DQB1_12 N13 DQ22 | DQ14 VDDQ-E10 F1 DQB1_16 M11 DQ23 | DQ15 VDDQ-E5 E10
DQB0_16 N11 DQ21 | DQ13 VDDQ-F1 F3 DQB0_15 N11 DQ21 | DQ13 VDDQ-F1 F3 DQB1_14 N11 DQ21 | DQ13 VDDQ-F1 F3 DQB1_18 N13 DQ22 | DQ14 VDDQ-E10 F1
D
DQB0_23 T13 DQ20 | DQ12 VDDQ-F3 F12 DQB0_10 T13 DQ20 | DQ12 VDDQ-F3 F12 DQB1_11 T13 DQ20 | DQ12 VDDQ-F3 F12 DQB1_19 N11 DQ21 | DQ13 VDDQ-F1 F3 D
DQB0_22 T11 DQ19 | DQ11 VDDQ-F12 F14 DQB0_8 T11 DQ19 | DQ11 VDDQ-F12 F14 DQB1_8 T11 DQ19 | DQ11 VDDQ-F12 F14 DQB1_21 T13 DQ20 | DQ12 VDDQ-F3 F12
DQB0_21 V13 DQ18 | DQ10 VDDQ-F14 G2 DQB0_11 V13 DQ18 | DQ10 VDDQ-F14 G2 DQB1_9 V13 DQ18 | DQ10 VDDQ-F14 G2 DQB1_22 T11 DQ19 | DQ11 VDDQ-F12 F14
DQB0_20 V11 DQ17 | DQ9 VDDQ-G2 G13 DQB0_9 V11 DQ17 | DQ9 VDDQ-G2 G13 DQB1_10 V11 DQ17 | DQ9 VDDQ-G2 G13 DQB1_23 V13 DQ18 | DQ10 VDDQ-F14 G2
F13 DQ16 | DQ8 VDDQ-G13 H3 F13 DQ16 | DQ8 VDDQ-G13 H3 F13 DQ16 | DQ8 VDDQ-G13 H3 DQB1_20 V11 DQ17 | DQ9 VDDQ-G2 G13
F11 DQ15 | DQ23 VDDQ-H3 H12 F11 DQ15 | DQ23 VDDQ-H3 H12 F11 DQ15 | DQ23 VDDQ-H3 H12 F13 DQ16 | DQ8 VDDQ-G13 H3
E13 DQ14 | DQ22 VDDQ-H12 K3 E13 DQ14 | DQ22 VDDQ-H12 K3 E13 DQ14 | DQ22 VDDQ-H12 K3 F11 DQ15 | DQ23 VDDQ-H3 H12
DQ13 | DQ21 VDDQ-K3 M=1 DQ13 | DQ21 VDDQ-K3 M=1 DQ13 | DQ21 VDDQ-K3 DQ14 | DQ22 VDDQ-H12
E11 K12 E11 K12 E11 K12 E13 K3
B13 DQ12 | DQ20 VDDQ-K12 L2
Mirror B13 DQ12 | DQ20 VDDQ-K12 L2
Mirror B13 DQ12 | DQ20 VDDQ-K12 L2 E11 DQ13 | DQ21 VDDQ-K3 K12
B11 DQ11 | DQ19 VDDQ-L2 L13 B11 DQ11 | DQ19 VDDQ-L2 L13 B11 DQ11 | DQ19 VDDQ-L2 L13 B13 DQ12 | DQ20 VDDQ-K12 L2
A13 DQ10 | DQ18 VDDQ-L13 M1 A13 DQ10 | DQ18 VDDQ-L13 M1 A13 DQ10 | DQ18 VDDQ-L13 M1 B11 DQ11 | DQ19 VDDQ-L2 L13
A11 DQ9 | DQ17 VDDQ-M1 M3 A11 DQ9 | DQ17 VDDQ-M1 M3 A11 DQ9 | DQ17 VDDQ-M1 M3 A13 DQ10 | DQ18 VDDQ-L13 M1
DQB0_5 F2 DQ8 | DQ16 VDDQ-M3 M12 DQB0_29 F2 DQ8 | DQ16 VDDQ-M3 M12 DQB1_26 F2 DQ8 | DQ16 VDDQ-M3 M12 A11 DQ9 | DQ17 VDDQ-M1 M3
DQB0_6 F4 DQ7 | DQ31 VDDQ-M12 M14 DQB0_25 F4 DQ7 | DQ31 VDDQ-M12 M14 DQB1_24 F4 DQ7 | DQ31 VDDQ-M12 M14 DQB1_3 F2 DQ8 | DQ16 VDDQ-M3 M12
DQB0_4 E2 DQ6 | DQ30 VDDQ-M14 N5 DQB0_28 E2 DQ6 | DQ30 VDDQ-M14 N5 DQB1_27 E2 DQ6 | DQ30 VDDQ-M14 N5 DQB1_6 F4 DQ7 | DQ31 VDDQ-M12 M14
DQB0_7 E4 DQ5 | DQ29 VDDQ-N5 N10 DQB0_26 E4 DQ5 | DQ29 VDDQ-N5 N10 DQB1_25 E4 DQ5 | DQ29 VDDQ-N5 N10 DQB1_2 E2 DQ6 | DQ30 VDDQ-M14 N5
DQB0_2 B2 DQ4 | DQ28 VDDQ-N10 P1 DQB0_30 B2 DQ4 | DQ28 VDDQ-N10 P1 DQB1_29 B2 DQ4 | DQ28 VDDQ-N10 P1 DQB1_4 E4 DQ5 | DQ29 VDDQ-N5 N10
DQB0_3 B4 DQ3 | DQ27 VDDQ-P1 P3 DQB0_27 B4 DQ3 | DQ27 VDDQ-P1 P3 DQB1_28 B4 DQ3 | DQ27 VDDQ-P1 P3 DQB1_1 B2 DQ4 | DQ28 VDDQ-N10 P1
DQB0_1 A2 DQ2 | DQ26 VDDQ-P3 P12 DQB0_31 A2 DQ2 | DQ26 VDDQ-P3 P12 DQB1_31 A2 DQ2 | DQ26 VDDQ-P3 P12 DQB1_5 B4 DQ3 | DQ27 VDDQ-P1 P3
DQB0_0 A4 DQ1 | DQ25 VDDQ-P12 P14 DQB0_24 A4 DQ1 | DQ25 VDDQ-P12 P14 DQB1_30 A4 DQ1 | DQ25 VDDQ-P12 P14 DQB1_0 A2 DQ2 | DQ26 VDDQ-P3 P12
DQ0 | DQ24 VDDQ-P14 T1 DQ0 | DQ24 VDDQ-P14 T1 DQ0 | DQ24 VDDQ-P14 T1 DQB1_7 A4 DQ1 | DQ25 VDDQ-P12 P14
+1.5V_REG VDDQ-T1 VDDQ-T1 VDDQ-T1 DQ0 | DQ24 VDDQ-P14
T3 T3 T3 T1
VDDQ-T3 VDDQ-T3 VDDQ-T3 +1.5V_REG VDDQ-T1
CLKB0 R801 60.4R T12 T12 T12 T3
5 CLKB0 VDDQ-T12 T14 VDDQ-T12 T14 VDDQ-T12 T14 VDDQ-T3 T12
CLKB0b R800 60.4R CLKA1 R901 60.4R
5 CLKB0b VDDQ-T14 +1.5V_REG VDDQ-T14 +1.5V_REG VDDQ-T14 +1.5V_REG 5 CLKB1 VDDQ-T12
5 MAB0_[8..0] 5 MAB0_[8..0] 5 MAB1_[8..0] CLKA1b R900 60.4R T14
5 CLKB1b VDDQ-T14 +1.5V_REG
MAB0_8 J5 MAB0_8 J5 MAB1_8 J5
RFU/A12/NC RFU/A12/NC RFU/A12/NC 5 MAB1_[8..0]
MAB0_7 K4 C5 MAB0_0 K4 C5 MAB1_0 K4 C5 MAB1_8 J5
MAB0_6 K5 A7/A8 | A0/A10 VDD-C5 C10 MAB0_1 K5 A7/A8 | A0/A10 VDD-C5 C10 MAB1_1 K5 A7/A8 | A0/A10 VDD-C5 C10 MAB1_7 K4 RFU/A12/NC C5
MAB0_5 K10 A6/A11 | A1/A9 VDD-C10 D11 MAB0_3 K10 A6/A11 | A1/A9 VDD-C10 D11 MAB1_3 K10 A6/A11 | A1/A9 VDD-C10 D11 MAB1_6 K5 A7/A8 | A0/A10 VDD-C5 C10
MAB0_4 K11 A5/BA1 | A3/BA3 VDD-D11 G1 MAB0_2 K11 A5/BA1 | A3/BA3 VDD-D11 G1 MAB1_2 K11 A5/BA1 | A3/BA3 VDD-D11 G1 MAB1_5 K10 A6/A11 | A1/A9 VDD-C10 D11
MAB0_3 H10 A4/BA2 | A2/BA0 VDD-G1 G4 MAB0_5 H10 A4/BA2 | A2/BA0 VDD-G1 G4 MAB1_5 H10 A4/BA2 | A2/BA0 VDD-G1 G4 MAB1_4 K11 A5/BA1 | A3/BA3 VDD-D11 G1
MAB0_2 H11 A3/BA3 | A5/BA1 VDD-G4 G11 MAB0_4 H11 A3/BA3 | A5/BA1 VDD-G4 G11 MAB1_4 H11 A3/BA3 | A5/BA1 VDD-G4 G11 MAB1_3 H10 A4/BA2 | A2/BA0 VDD-G1 G4
MAB0_1 H5 A2 /BA0 | A4/BA2 VDD-G11 G14 MAB0_6 H5 A2 /BA0 | A4/BA2 VDD-G11 G14 MAB1_6 H5 A2 /BA0 | A4/BA2 VDD-G11 G14 MAB1_2 H11 A3/BA3 | A5/BA1 VDD-G4 G11
MAB0_0 H4 A1/A9 | A6/A11 VDD-G14 L1 MAB0_7 H4 A1/A9 | A6/A11 VDD-G14 L1 MAB1_7 H4 A1/A9 | A6/A11 VDD-G14 L1 MAB1_1 H5 A2 /BA0 | A4/BA2 VDD-G11 G14
A0/A10 | A7/A8 VDD-L1 L4 A0/A10 | A7/A8 VDD-L1 L4 A0/A10 | A7/A8 VDD-L1 L4 MAB1_0 H4 A1/A9 | A6/A11 VDD-G14 L1
VDD-L4 L11 VDD-L4 L11 VDD-L4 L11 A0/A10 | A7/A8 VDD-L1 L4
VDD-L11 L14 VDD-L11 L14 VDD-L11 L14 VDD-L4 L11
D4 VDD-L14 P11 D4 VDD-L14 P11 D4 VDD-L14 P11 VDD-L11 L14
C 5 WCKB0_0 5 WCKB0_1 C
D5 WCK01 | WCK23 VDD-P11 R5 D5 WCK01 | WCK23 VDD-P11 R5 5 WCKB1_1 D5 WCK01 | WCK23 VDD-P11 R5 D4 VDD-L14 P11
5 WCKB0b_0 WCK01# | WCK23# VDD-R5 5 WCKB0b_1 WCK01# | WCK23# VDD-R5 5 WCKB1b_1 WCK01# | WCK23# VDD-R5 5 WCKB1_0 WCK01 | WCK23 VDD-P11
R10 R10 R10 D5 R5
VDD-R10 VDD-R10 VDD-R10 5 WCKB1b_0 WCK01# | WCK23# VDD-R5
P4 P4 P4 R10
5 WCKB0_1 WCK23 | WCK01 5 WCKB0_0 WCK23 | WCK01 5 WCKB1_0 WCK23 | WCK01 VDD-R10
P5 P5 P5 P4
5 WCKB0b_1 WCK23# | WCK01# 5 WCKB0b_0 WCK23# | WCK01# 5 WCKB1b_0 WCK23# | WCK01# 5 WCKB1_1 WCK23 | WCK01
A1 A1 A1 P5
R2 VSSQ-A1 A3 R2 VSSQ-A1 A3 R2 VSSQ-A1 A3 5 WCKB1b_1 WCK23# | WCK01# A1
R13 EDC3 | EDC0 VSSQ-A3 A12 R13 EDC3 | EDC0 VSSQ-A3 A12 R13 EDC3 | EDC0 VSSQ-A3 A12 R2 VSSQ-A1 A3
5 EDCB0_2 EDC2 | EDC1 VSSQ-A12 5 EDCB0_1 EDC2 | EDC1 VSSQ-A12 5 EDCB1_1 EDC2 | EDC1 VSSQ-A12 EDC3 | EDC0 VSSQ-A3
C13 A14 C13 A14 C13 A14 R13 A12
EDC1 | EDC2 VSSQ-A14 EDC1 | EDC2 VSSQ-A14 EDC1 | EDC2 VSSQ-A14 5 EDCB1_2 EDC2 | EDC1 VSSQ-A12
C2 C1 C2 C1 C2 C1 C13 A14
5 EDCB0_0 EDC0 | EDC3 VSSQ-C1 5 EDCB0_3 EDC0 | EDC3 VSSQ-C1 5 EDCB1_3 EDC0 | EDC3 VSSQ-C1 EDC1 | EDC2 VSSQ-A14
C3 C3 C3 5 EDCB1_0 C2 C1
P2 VSSQ-C3 C4 P2 VSSQ-C3 C4 P2 VSSQ-C3 C4 EDC0 | EDC3 VSSQ-C1 C3
+1.5V_REG DBI3# | DBI0# VSSQ-C4 +1.5V_REG DBI3# | DBI0# VSSQ-C4 +1.5V_REG DBI3# | DBI0# VSSQ-C4 VSSQ-C3
5 DDBIB0_2 P13 C11 5 DDBIB0_1 P13 C11 5 DDBIB1_1 P13 C11 +1.5V_REG P2 C4
D13 DBI2 #| DBI1# VSSQ-C11 C12 D13 DBI2 #| DBI1# VSSQ-C11 C12 D13 DBI2 #| DBI1# VSSQ-C11 C12 P13 DBI3# | DBI0# VSSQ-C4 C11
+1.5V_REG DBI1# | DBI2# VSSQ-C12 +1.5V_REG DBI1# | DBI2# VSSQ-C12 +1.5V_REG DBI1# | DBI2# VSSQ-C12 5 DDBIB1_2 DBI2 #| DBI1# VSSQ-C11
D2 C14 D2 C14 D2 C14 D13 C12
5 DDBIB0_0 DBI0# | DBI3# VSSQ-C14 5 DDBIB0_3 DBI0# | DBI3# VSSQ-C14 5 DDBIB1_3 DBI0# | DBI3# VSSQ-C14 +1.5V_REG DBI1# | DBI2# VSSQ-C12
E1 E1 E1 5 DDBIB1_0 D2 C14
VSSQ-E1 E3 VSSQ-E1 E3 VSSQ-E1 E3 DBI0# | DBI3# VSSQ-C14 E1
VSSQ-E3 E12 VSSQ-E3 E12 VSSQ-E3 E12 VSSQ-E1 E3
G3 VSSQ-E12 E14 G3 VSSQ-E12 E14 G3 VSSQ-E12 E14 VSSQ-E3 E12
5 RASB0b RAS# | CAS# VSSQ-E14 5 CASB0b RAS# | CAS# VSSQ-E14 5 CASB1b RAS# | CAS# VSSQ-E14 VSSQ-E12
L3 F5 L3 F5 L3 F5 G3 E14
5 CASB0b CAS# | RAS# VSSQ-F5 5 RASB0b CAS# | RAS# VSSQ-F5 5 RASB1b CAS# | RAS# VSSQ-F5 5 RASB1b RAS# | CAS# VSSQ-E14
F10 F10 F10 5 CASB1b L3 F5
VSSQ-F10 H2 VSSQ-F10 H2 VSSQ-F10 H2 CAS# | RAS# VSSQ-F5 F10
J3 VSSQ-H2 H13 J3 VSSQ-H2 H13 J3 VSSQ-H2 H13 VSSQ-F10 H2
5 CKEB0 CKE# VSSQ-H13 5 CKEB0 CKE# VSSQ-H13 5 CKEB1 CKE# VSSQ-H13 VSSQ-H2
CLKB0b J11 K2 CLKB0b J11 K2 CLKB1b J11 K2 J3 H13
CK# VSSQ-K2 CK# VSSQ-K2 CK# VSSQ-K2 5 CKEB1 CKE# VSSQ-H13
CLKB0 J12 K13 CLKB0 J12 K13 CLKB1 J12 K13 CLKB1b J11 K2
CK VSSQ-K13 M5 CK VSSQ-K13 M5 CK VSSQ-K13 M5 CLKB1 J12 CK# VSSQ-K2 K13
VSSQ-M5 M10 VSSQ-M5 M10 VSSQ-M5 M10 CK VSSQ-K13 M5
G12 VSSQ-M10 N1 G12 VSSQ-M10 N1 G12 VSSQ-M10 N1 VSSQ-M5 M10
5 CSB0b_0 CS# | WE# VSSQ-N1 5 WEB0b CS# | WE# VSSQ-N1 5 WEB1b CS# | WE# VSSQ-N1 VSSQ-M10
L12 N3 L12 N3 L12 N3 G12 N1
5 WEB0b WE# | CS# VSSQ-N3 5 CSB0b_0 WE# | CS# VSSQ-N3 5 CSB1b_0 WE# | CS# VSSQ-N3 5 CSB1b_0 CS# | WE# VSSQ-N1
N12 N12 N12 L12 N3
VSSQ-N12 VSSQ-N12 VSSQ-N12 5 WEB1b WE# | CS# VSSQ-N3
N14 N14 N14 N12
R808 120R 1% J13 VSSQ-N14 R1 R858 120R 1% J13 VSSQ-N14 R1 R908 120R1% J13 VSSQ-N14 R1 VSSQ-N12 N14
J10 ZQ VSSQ-R1 R3 J10 ZQ VSSQ-R1 R3 J10 ZQ VSSQ-R1 R3 R958 120R 1% J13 VSSQ-N14 R1
SEN VSSQ-R3 R4 SEN VSSQ-R3 R4 SEN VSSQ-R3 R4 J10 ZQ VSSQ-R1 R3
VSSQ-R4 R11 VSSQ-R4 R11 VSSQ-R4 R11 SEN VSSQ-R3 R4
J2 VSSQ-R11 R12 J2 VSSQ-R11 R12 J2 VSSQ-R11 R12 VSSQ-R4 R11
5,6 DRAM_RST RESET# VSSQ-R12 5,6 DRAM_RST RESET# VSSQ-R12 5,6 DRAM_RST RESET# VSSQ-R12 VSSQ-R11
J1 R14 J1 R14 J1 R14 J2 R12
MF VSSQ-R14 +1.5V_REG MF VSSQ-R14 +1.5V_REG MF VSSQ-R14 5,6 DRAM_RST RESET# VSSQ-R12
V1 V1 V1 J1 R14
B VSSQ-V1 V3 VSSQ-V1 V3 VSSQ-V1 V3 MF VSSQ-R14 V1 B
VSSQ-V3 V12 VSSQ-V3 V12 VSSQ-V3 V12 VSSQ-V1 V3
VSSQ-V12 V14 VSSQ-V12 V14 VSSQ-V12 V14 VSSQ-V3 V12
A5 VSSQ-V14 A5 VSSQ-V14 A5 VSSQ-V14 VSSQ-V12 V14
V5 Vpp,NC C1089 1uF_6.3V V5 Vpp,NC V5 Vpp,NC A5 VSSQ-V14
Vpp,NC1 B5 Vpp,NC1 B5 Vpp,NC1 B5 V5 Vpp,NC
VREFD2_B0 A10 VSS-B5 B10 R852 2.37K 1% VREFD1_B0 A10 VSS-B5 B10 VREFD2_B1 A10 VSS-B5 B10 C1189 1uF_6.3V Vpp,NC1 B5
VREFD1 VSS-B10 +1.5V_REG VREFD1 VSS-B10 VREFD1 VSS-B10 VSS-B5
V10 D10 R853 5.49K 1% V10 D10 V10 D10 +1.5V_REG R952 2.37K 1% VREFD1_B1 A10 B10
VREFD1_B0 VREFD2 VSS-D10 G5 C1090 1uF_6.3V VREFD2 VSS-D10 G5 VREFD1_B1 VREFD2 VSS-D10 G5 R953 5.49K 1% V10 VREFD1 VSS-B10 D10
VSS-G5 G10 VSS-G5 G10 VSS-G5 G10 C1190 1uF_6.3V VREFD2 VSS-D10 G5
VSS-G10 H1 C1091 1uF_6.3V VSS-G10 H1 VSS-G10 H1 VSS-G5 G10
VSS-H1 H14 R854 2.37K 1% VSS-H1 H14 VSS-H1 H14 C1191 1uF_6.3V VSS-G10 H1
VSS-H14 +1.5V_REG VSS-H14 VSS-H14 VSS-H1
K1 R855 5.49K 1% VREFD2_B0 K1 K1 +1.5V_REG R954 2.37K 1% H14
VREFC_B0 J14 VSS-K1 K14 C1092 1uF_6.3V J14 VSS-K1 K14 VREFC_B1 J14 VSS-K1 K14 R955 5.49K 1% VREFD2_B1 VSS-H14 K1
VREFC VSS-K14 L5 VREFC VSS-K14 L5 VREFC VSS-K14 L5 C1192 1uF_6.3V J14 VSS-K1 K14
VSS-L5 L10 C1093 1uF_6.3V VSS-L5 L10 VSS-L5 L10 VREFC VSS-K14 L5
VSS-L10 P10 R856 2.37K 1% VSS-L10 P10 VSS-L10 P10 VSS-L5 L10
VSS-P10 +1.5V_REG VSS-P10 VSS-P10 VSS-L10
J4 T5 R857 5.49K 1% VREFC_B0 J4 T5 J4 T5 C1193 1uF_6.3V P10
ABI# VSS-T5 T10 C1094 1uF_6.3V ABI# VSS-T5 T10 ABI# VSS-T5 T10 R956 1% 2.37K 1% J4 VSS-P10 T5
VSS-T10 VSS-T10 VSS-T10 +1.5V_REG ABI# VSS-T5
R957 5.49K 1% VREFC_B1 T10
C1194 1uF_6.3V VSS-T10

5 ADBIB0 GDDR5 GDDR5 5 ADBIB1 GDDR5

5 ADBIB0 5 ADBIB1 GDDR5

+1.5V_REG

C1034 C1035 C1036 C1037 C1038 C1086 C1088 C1184 C1185 C1186 C1187 C1188

+1.5V_REG

10uF_2.5V

10uF_2.5V

10uF_2.5V

10uF_2.5V

10uF_2.5V

10uF_2.5V

10uF_2.5V

10uF_2.5V

10uF_2.5V

10uF_2.5V

10uF_2.5V

10uF_2.5V
C1021 1uF_6.3V

C1022 1uF_6.3V

C1023 1uF_6.3V

C1011 1uF_6.3V

C1012 1uF_6.3V

C1013 1uF_6.3V

C1014 1uF_6.3V

C1015 1uF_6.3V

C1016 1uF_6.3V

C1017 1uF_6.3V

C1018 1uF_6.3V

C1019 1uF_6.3V

C1020 1uF_6.3V

C1062 1uF_6.3V

C1063 1uF_6.3V

C1064 1uF_6.3V

C1065 1uF_6.3V

C1066 1uF_6.3V

C1067 1uF_6.3V

C1068 1uF_6.3V

C1069 1uF_6.3V

C1111 1uF_6.3V

C1112 1uF_6.3V

C1113 1uF_6.3V

C1115 1uF_6.3V

C1120 1uF_6.3V

C1162 1uF_6.3V

C1164 1uF_6.3V

C1168 1uF_6.3V

C1176 1uF_6.3V

C1177 1uF_6.3V

A A

Advanced Micro Devices Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
Whisler MXM3.0 G5
Size Document Number Rev
C 105-C29247-00B 0
Date: Monday, September 13, 2010 Sheet 7 of 12
5 4 3 2 1
 5 4 3 2 1

+3VRUN
PLACE CAPS ON THIS PAGE AS CLOSE TO CONNECTOR AS POSSIBLE
R8438
+3VRUN
+3VRUN
J1A 10K R614 0R
E1 E2 VDDCGOOD 3,10
G_PWR_SRC PWR_SRC_E1 PWR_SRC_E2
E3 E4 R531 0R R546 C692
C691 GND_E3 Part 1 of 2 GND_E4 1.8VGOOD 11 100K 100nF

5
1nF 1 2 R532 0R NC7SZ08P5X_NL
+3VRUN +3VRUN 3 5V_1 PRSNT_R#_2 4 1.5VGOOD 11 CTFb 1
5 5V_3 WAKE#_4 6 PWRGOOD R542 0R 4 RUNPWROK
7 5V_5 PWR_GOOD_6 8 1.0VGOOD 11 2 RUNPWROK 10,11
R8436 R8440 9 5V_7 PWR_EN_8 10 R8439 0R U50
+5VRUN 5V_9 RSVD_10
11 12

3
C683 C684 13 GND_11 RSVD_12 14
10K 10K 1uF_6.3V 100nF 15 GND_13 RSVD_14 16
17 GND_15 RSVD_16 18 PWR_LEVEL R572 0R
19 GND_17 PWR_LEVEL_18 20 THERMAL_OVERTB GPIO5 2 R8441 0R
21 PEX_STD_SW#_19 TH_OVERT#_20 22 THERMAL_ALERTB
2,9,10 GPIO0 HPD5 FPVCC_MB 23 VGA_DISABLE#_21 TH_ALERT#_22 24
2,9 GPIO1 PNL_PWR_EN_23 TH_PWM_24 TS_FDO 2
BL_ENA 25 26
6

3
BL_BRIGHT_MB 27 PNL_BL_EN_25 GPIO0_26 28
D Q80A Q80B HDMI_CEC 29 PNL_PWM_27 GPIO1_28 30 R8453 0R +3VRUN D
HDMI_CEC_29 GPIO2_30 GENERICA 2
31 32 SMB_DAT R8454 0R
2 5 33 DVI_HPD_31 SMB_DAT_32 34 GENERICB 2
SMB_CLK
2N7002 2N7002 35 LVDS_DDC_DAT_33 SMB_CLK_34 36
DNI DNI 37 LVDS_DDC_CLK_35 GND_36 38
1

4 HPD6 R574 0R 39 GND_37 OEM_38 40 R8450

R579 0R 41 OEM_39 OEM_40 42 20K
2 DDCDATA_AUX7N OEM_41 OEM_42

2
R580 0R 43 44
2 DDCCLK_AUX7P 45 OEM_43 OEM_44 46 1
Q109 CTFb
47 OEM_45 GND_46 48 PCIE_RXN15 MMBT3906
2 DDCDATA_AUX5N GND_47 PEX_TX15#_48 For one time CTF use R8464 47k.

3
PCIE_TXN15 49 50 PCIE_RXP15 R8418 20K
2 DDCCLK_AUX5P

3
51 PEX_RX15#_49 PEX_TX15_50 52 1
PCIE_TXP15
PEX_RX15_51 GND_52 For resetable CTF use R8464 2k. CTF_VCNTL Q110
53 54 PCIE_RXN14 MMBT3904
PCIE_TXN14 55 GND_53 PEX_TX14#_54 56 PCIE_RXP14

2
PCIE_TXP14 57 PEX_RX14#_55 PEX_TX14_56 58 R8420
59 PEX_RX14_57 GND_58 60 PCIE_RXN13 MR1 47K R8419 20K
GND_59 PEX_TX13#_60 2,9 MB_ALERTB
R548 10K PCIE_TXN13 61 62 PCIE_RXP13 20K
PEX_RX13#_61 PEX_TX13_62

3
R583 R576 PCIE_TXP13 63 64
2,9 GPIO9 65 PEX_RX13_63 GND_64 66 1
PCIE_RXN12 R8421 47K R8422 47K CTF_TRIP Q111
2 GPIO19_CTF
3

4.7K PCIE_TXN12 67 GND_65 PEX_TX12#_66 68 PCIE_RXP12 1% MMBT3904

Q81 4.7K PCIE_TXP12 69 PEX_RX12#_67 PEX_TX12_68 70

2
2N7002E 71 PEX_RX12_69 GND_70 72 PCIE_RXN11 D1 R8423 C872 C1204
DNI 1 PCIE_TXN11 73 GND_71 PEX_TX11#_72 74 PCIE_RXP11 BAT54S 100K 1uF_6.3V
PCIE_TXP11 75 PEX_RX11#_73 PEX_TX11_74 76 100nF
+3VRUN 77 PEX_RX11_75 GND_76 78 PCIE_RXN10
2

PCIE_TXN10 79 GND_77 PEX_TX10#_78 80 PCIE_RXP10

PCIE_TXP10 81 PEX_RX10#_79 PEX_TX10_80 82
83 PEX_RX10_81 GND_82 84 PCIE_RXN9
STRAP OPTIONS FROM MOTEHRBOARD DNI PCIE_TXN9 85 GND_83 PEX_TX9#_84 86 PCIE_RXP9 PCIE_RST#
PCIE_TXP9 87 PEX_RX9#_85 PEX_TX9_86 88
89 PEX_RX9_87 GND_88 90 PCIE_RXN8 R8424 2.2K R8425 2.2K
PCIE_TXN8 91 GND_89 PEX_TX8#_90 92 PCIE_RXP8
PCIE_TXP8 93 PEX_RX8#_91 PEX_TX8_92 94
95 PEX_RX8_93 GND_94 96 PCIE_RXN7
PCIE_TXN7 97 GND_95 PEX_TX7#_96 98 PCIE_RXP7
VGA_RED PCIE_TXP7 99 PEX_RX7#_97 PEX_TX7_98 100
2 VGA_RED PEX_RX7_99 GND_100
VGA_GRN 101 102 PCIE_RXN6
2 VGA_GRN 103 GND_101 PEX_TX6#_102 104
VGA_BLU PCIE_TXN6 PCIE_RXP6
2 VGA_BLU 105 PEX_RX6#_103 PEX_TX6_104 106
PCIE_TXP6
107 PEX_RX6_105 GND_106 108 PCIE_RXN5
PCIE_TXN5 109 GND_107 PEX_TX5#_108 110 PCIE_RXP5
PCIE_TXP5 111 PEX_RX5#_109 PEX_TX5_110 112
113 PEX_RX5_111 GND_112 114 PCIE_RXN4 +3VRUN
PCIE_REFCLKP PCIE_TXN4 115 GND_113 PEX_TX4#_114 116 PCIE_RXP4 0R R460 BL_BRIGHT
1 PCIE_REFCLKP PEX_RX4#_115 PEX_TX4_116
PCIE_REFCLKN PCIE_TXP4 117 118
1 PCIE_REFCLKN 119 PEX_RX4_117 GND_118 120 PCIE_RXN3 PWR_LEVEL R587 10K
PCIE_TXN3 121 GND_119 PEX_TX3#_120 122 PCIE_RXP3 HDMI_CEC R588 10K
PEX_RX3#_121 PEX_TX3_122
DNI
PCIE_TXP3 123 124 BL_ENA R461 0R
PCIE_RXP[15..0] 125 PEX_RX3_123 GND_124 BLON_PWM 2
1 PCIE_RXP[15..0] GND_125
Mechanical Key R464 0R
C PCIE_RXN[15..0] 133 134 GPIO7_BLON 2 C
OPTION STRAPS
1 PCIE_RXN[15..0] GND_133 GND_134
PCIE_TXN2 135 136 PCIE_RXN2 R8449
PCIE_TXP[15..0] PCIE_TXP2 137 PEX_RX2#_135 PEX_TX2#_136 138 PCIE_RXP2
1 PCIE_TXP[15..0] 139 PEX_RX2_137 PEX_TX2_138 140 +3VRUN
PCIE_TXN[15..0] PCIE_TXN1 141 GND_139 GND_140 142 PCIE_RXN1 10K
1 PCIE_TXN[15..0] 143 PEX_RX1#_141 PEX_TX1#_142 144
PCIE_TXP1 PCIE_RXP1 U52
145 PEX_RX1_143 PEX_TX1_144 146 BL_BRIGHT_MB 6 2 BL_BRIGHT
PCIE_TXN0 147 GND_145 GND_146 148 PCIE_RXN0 FPVCC_MB 3 1Y 1A 5
PEX_RX0#_147 PEX_TX0#_148 2Y 2A FPVCC 2
PCIE_TXP0 149 150 PCIE_RXP0 R593
151 PEX_RX0_149 PEX_TX0_150 152 10K 8 1 PWRGOOD
GND_151 GND_152 +3VRUN VCC 1OE
PCIE_REFCLKN 153 154 R466 0R 4 7
PCIE_REFCLKP 155 PEX_REFCLK#_153 CLK_REQ#_154 156 PCIE_RST# CLKREQB 2 R467 GND 2OE
PEX_REFCLK_155 PEX_RST#_156 PCIE_RST# 1 DNI C720
RUNPWROK 157 158 R469 10K
10,11 RUNPWROK GND_157 VGA_DDC_DAT_158 74LVC2G126
159 160 100R 100nF
161 RSVD_159 VGA_DDC_CLK_160 162
163 RSVD_161 VGA_VSYC_162 164 VSYNC 2,9
TXOUT_L0-
2 TXOUT_L0- 165 RSVD_163 VGA_HSYC_164 166 HSYNC 2,9
TXOUT_L0+
2 TXOUT_L0+ TXOUT_L1- 167 RSVD_165 GND_166 168 VGA_RED
2 TXOUT_L1- RSVD_167 VGA_RED_168
TXOUT_L1+ TXCLK_U- 169 170 VGA_GRN BL_BRIGHT_MB R471 0R BL_BRIGHT
2 TXOUT_L1+ 171 LVDS_UCLK#_169 VGA_GREEN_170 172
TXOUT_L2- TXCLK_U+ VGA_BLU DNI
2 TXOUT_L2- TXOUT_L2+ 173 LVDS_UCLK_171 VGA_BLUE_172 174 FPVCC_MB R473 0R
2 TXOUT_L2+ GND_173 GND_174 DDC6CLK 2 FPVCC 2
TXOUT_L3- TXOUT_U3- 175 176 TXCLK_L-
2 TXOUT_L3- 177 LVDS_UTX3#_175 LVDS_LCLK#_176 178 DDC6DATA 2
TXOUT_L3+ TXOUT_U3+ TXCLK_L+ R474 R475 R476
2 TXOUT_L3+ 179 LVDS_UTX3_177 LVDS_LCLK_178 180
TXCLK_L- 150R 150R 150R
2 TXCLK_L- GND_179 GND_180
TXCLK_L+ TXOUT_U2- 181 182 TXOUT_L3- R477 R478
2 TXCLK_L+ 183 LVDS_UTX2#_181 LVDS_LTX3#_182 184
TXOUT_U2+ TXOUT_L3+ 2.2K 2.2K
TXOUT_U0- 185 LVDS_UTX2_183 LVDS_LTX3_184 186 +3VRUN
2 TXOUT_U0- TXOUT_U0+ TXOUT_U1- 187 GND_185 GND_186 188 TXOUT_L2-
2 TXOUT_U0+ LVDS_UTX1#_187 LVDS_LTX2#_188
TXOUT_U1- TXOUT_U1+ 189 190 TXOUT_L2+
2 TXOUT_U1- 191 LVDS_UTX1_189 LVDS_LTX2_190 192
TXOUT_U1+
2 TXOUT_U1+ TXOUT_U2- TXOUT_U0- 193 GND_191 GND_192 194 TXOUT_L1-
2 TXOUT_U2- LVDS_UTX0#_193 LVDS_LTX1#_194
TXOUT_U2+ TXOUT_U0+ 195 196 TXOUT_L1+
2 TXOUT_U2+ 197 LVDS_UTX0_195 LVDS_LTX1_196 198
TXOUT_U3-
2 TXOUT_U3- 199 GND_197 GND_198 200
TXOUT_U3+ TXOUT_L0-
2 TXOUT_U3+ 2 TX2M_DPC0N 201 DP_C_L0#_199 LVDS_LTX0#_200 202
TXCLK_U- TXOUT_L0+
2 TXCLK_U- 2 TX2P_DPC0P 203 DP_C_L0_201 LVDS_LTX0_202 204 +3VRUN
TXCLK_U+
2 TXCLK_U+ 205 GND_203 GND_204 206
2 TX1M_DPC1N 207 DP_C_L1#_205 DP_D_L0#_206 208 TX5M_DPD0N 2
2 TX1P_DPC1P DP_C_L1_207 DP_D_L0_208 TX5P_DPD0P 2
209 210
211 GND_209 GND_210 212 DNI R594
FPVCC 2 TX0M_DPC2N 213 DP_C_L2#_211 DP_D_L1#_212 214 TX4M_DPD1N 2
4.7K
2 FPVCC 2 TX0P_DPC2P 215 DP_C_L2_213 DP_D_L1_214 216 TX4P_DPD1P 2
217 GND_215 GND_216 218 0R R595 SM_EN
2 TXCCM_DPC3N DP_C_L3#_217 DP_D_L2#_218 TX3M_DPD2N 2 3,10 VDDCGOOD
219 220
2 TXCCP_DPC3P 221 DP_C_L3_219 DP_D_L2_220 222 TX3P_DPD2P 2
223 GND_221 GND_222 224
2 DDCDATA_AUX3N DP_C_AUX#_223 DP_D_L3#_224 TXCDM_DPD3N 2 +3VRUN
+3VRUN +3VRUN
+3VRUN
225 226
2 DDCCLK_AUX3P DP_C_AUX_225 DP_D_L3_226 TXCDP_DPD3P 2

2
227 228 Q99A
229 RSVD_227 GND_228 230
RSVD_229 DP_D_AUX#_230 DDCDATA_AUX4N 2
231 232 1 6 R599 R600
B 233 RSVD_231 DP_D_AUX_232 234 DDCCLK_AUX4P 2 +3VRUN +3VRUN B
HPD3 R597 R598 100K 100K
235 RSVD_233 DP_C_HPD_234 236 HPD4 4.7K 4.7K
237 RSVD_235 DP_D_HPD_236 238 2N7002
239 RSVD_237 RSVD_238 240 R481 R482
241 RSVD_239 RSVD_240 242 100K 100K DNI 0R R601 SMB_CLK R602 0R
243 RSVD_241 RSVD_242 244 2 GPU_SMBCLK SMB_DAT PBAT_SMBCLK 9
DNI 0R R603 R604 0R
RSVD_243 GND_244 2 GPU_SMBDAT PBAT_SMBDAT 9
245 246 TX5M_DPB0N 2
247 RSVD_245 DP_B_L0#_246 248
RSVD_247 DP_B_L0_248 TX5P_DPB0P 2
HPD1 249 250 THERMAL_ALERTB
2 HPD1 RSVD_249 GND_250 MB_ALERTB 2,9
251 252 TX4M_DPB1N 2 THERMAL_OVERTB 4 3
253 GND_251 DP_B_L1#_252 254 MB_THERMB 9
R470 2 TX2M_DPA0N TX4P_DPB1P 2 Q99B
100K 255 DP_A_L0#_253 DP_B_L1_254 256
2 TX2P_DPA0P DP_A_L0_255 GND_256
257 258 TX3M_DPB2N 2 2N7002

5
259 GND_257 DP_B_L2#_258 260
2 TX1M_DPA1N DP_A_L1#_259 DP_B_L2_260 TX3P_DPB2P 2
HPD2 2 TX1P_DPA1P 261 262 SM_EN
2 HPD2 DP_A_L1_261 GND_262
263 264 TXCBM_DPB3N 2
R472 265 GND_263 DP_B_L3#_264 266
2 TX0M_DPA2N DP_A_L2#_265 DP_B_L3_266 TXCBP_DPB3P 2
100K 2 TX0P_DPA2P 267 268
269 DP_A_L2_267 GND_268 270
GND_269 DP_B_AUX#_270 DDCDATA_AUX2N 2
2 TXCAM_DPA3N 271 272
273 DP_A_L3#_271 DP_B_AUX_272 274 DDCCLK_AUX2P 2
2 TXCAP_DPA3P HPD2
275 DP_A_L3_273 DP_B_HPD_274 276 HPD1 +3VRUN
HPD3 277 GND_275 DP_A_HPD_276 278
2 HPD3 2 DDCDATA_AUX1N DP_A_AUX#_277 3V3_278
279 280
2 DDCCLK_AUX1P 281 DP_A_AUX_279 3V3_280
R479
100K PRSNT_L#_281 C724 C725
MXM 3 10uF_X6S 1uF_6.3V

2 HPD4 HPD4

R480
100K

J1B
HPD5 Part 2 of 2
2 HPD5
MTG1
R605 MTG2 MTG1
100K MTG3 MTG2
MTG4 MTG3
MTG5 MTG4
MTG6 MTG5
HPD6 MTG6
2 HPD6
MXM 3
R606
A 100K A

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

© 2007 Advanced Micro Devices Advanced Micro Devices Inc.
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement 1 Commerce Valley Drive East
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose Markham, Ontario
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to, Date: Monday, September 13, 2010 Rev
any implied warranty of merchantibility or fitness for a particular
0
purpose, and disclaims responsibility forany consequences resulting Sheet 8
from use of the information included herein. of 12
Title Doc No.
Whisler MXM3.0 G5 105-C29247-00B
5 4 3 2 1
 5 4 3 2 1

+3VRUN RECOMMENDED SETTINGS

PIN STRAPS CONFIGURATION STRAPS 0= DO NOT INSTALL RESISTOR
1 = INSTALL 10K RESISTOR
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED, X = DESIGN DEPENDANT
2,8,10 GPIO0 GPIO0 R490 10K NA = NOT APPLICABLE
THEY MUST NOT CONFLICT DURING RESET
D GPIO1 R491 10K D
2,8 GPIO1

2 GPIO2 GPIO2 R492 10K STRAPS PIN DESCRIPTION OF DEFAULT SETTINGS

2 GPIO8 GPIO8 R493 10K

2,8 GPIO9 GPIO9 R494 10K

2,10 GPIO11 GPIO11 R495 10K

2,10 GPIO12 GPIO12 R496 10K

TX_PWRS_ENB GPIO0 PCIE FULL TX OUTPUT SWING 1
2,10 GPIO13 GPIO13 R497 10K
TX_DEEMPH_EN GPIO1 PCIE TRANSMITTER DE-EMPHASIS ENABLED 1
R498 10K
2,8 VSYNC
BIF_GEN2_EN_A GPIO2 PCIE GNE2 ENABLED 1
R499 10K
2,8 HSYNC
BIF_CLK_PM_EN GPIO8 BIF_CLK_PM_EN 0
2 GENERICC R500 10K BIF_VGA DIS GPIO9 VGA ENABLED 0
BIF_RX_PLL_CALIB_BP GPIO21 BIF_RX_PLL_CALIB_BP 0
R501 10K
2 V2SYNC
BIOS_ROM_EN GPIO_22_ROMCSB ENABLE EXTERNAL BIOS ROM 1
R502 10K
2 H2SYNC
ROMIDCFG(2:0) GPIO[13:11] SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT X X X
C C
2 GPIO22 R503 10K
VIP_DEVICE_STRAP_ENA V2SYNC IGNORE VIP DEVICE STRAPS 0

SMS_EN_HARD H2SYNC 0
CCBYPASS GENERICC 0
AUD[1] HSYNC built-in HDMI connector 1
AUD[0] VSYNC Audio functiuon present 1

C727
100nF

R507 0R +3VRUN
2 I2C_CLK
R508 0R
2 I2C_DAT
U53 C728 2.2nF_50V
8 PBAT_SMBCLK
8
SCLK VDD
1 AMD RESERVED CONFIGURATION STRAPS
7 2 ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
8 PBAT_SMBDAT SDATA D+ GPU_DPLUS 2
6 3
GPU_DMINUS 2
THEY MUST NOT CONFLICT DURING RESET
ALERT D-
B B
5 4 R511 0R
GND THERM MB_THERMB 8
R512 0R H2SYNC GENERICC
ADM1032ARMZ R513 0R
R514 0R
MB_ALERTB 2,8
PULLUP PADS ARE NOT REQUIRED FOR THESE STRAPS BUT IF THESE GPIOS ARE USED,
R515 R516 THEY MUST NOT CONFLICT DURING RESET
2.2K 2.2K

GPIO_28_TDO GPIO21_BB_EN

+3VRUN

A CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC. A

© 2007 Advanced Micro Devices Advanced Micro Devices Inc.
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement 1 Commerce Valley Drive East
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose Markham, Ontario
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind Date: Monday, September 13, 2010 Rev
regarding this schematic and design, including, not limited to, 1
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting Sheet 9 of 12
from use of the information included herein.
Title Doc No.
Whisler MXM3.0 G5 105-C29247-00B
5 4 3 2 1
 5 4 3 2 1

GPIO20 GPIO15 GPIO13 GPIO12

VID4 VID3 VID2 VID1 VDDC

0 0 0 0 1.100V
0 0 0 1 1.075V
0 0 1 0 1.050V
0 0 1 1 1.025V
0 1 0 0 1.000V GPU CORE REG
0 1 0 1 0.975V
0 1 1 0 0.950V CORE PWM THREE PHASE REGULATOR 0.8V- 1.10V @ 35A
D
1 1 1 1 0.925V D

1 0 0 0 0.900V
1 0 0 1 0.875V G_PWR_SRC
1 0 1 0 0.850V
1 0 1 1 0.825V
C840
1 1 0 0 0.800V
BSZ100N03MS G 10UF_25V

9
4 5
3 6
2 7
1 8
U61
2 8 Q103 IHLP2020AB-11 0.33uH
+3VRUN +5VRUN PWM UGATE C842 100nF
1
3-PADS/2 G_PWR_SRC +5VRUN 6 BOOT L33 1.0UH_3.7A VDDC
R8356 10K DNI VID0 FCCM 7
R8357 10K R8358 1.8R 5 PHASE

TH#9
R8359 10K DNI VID1 3 VCC 4
R8360 10K R8363 R8457 R8364 GND LGATE C845
BSZ035N03MS G
R8361 10K VID2 C844 ISL6208CRZ 330UF_2V

9
R8362 10K DNI 1R 1uF_6.3V 9
R8365 10K VID3 1R 0R 4 5 R8367 R8368
R8366 10K DNI 3 6 3.65K 1R
R8369 10K VID4 2 7
R8372 10K DNI C846 1 8 R8370
R8371 10K VID5 1uF_6.3V C847 10K
R8458 0R C843 10nF_25V Q104
R8373 10K VID6 ISUM+ ISUM-
1uF_6.3V

25

16

17
U62

VCCP

VDD

VIN
use 147K (3160147300G)
R8374 147K 3 24 G_PWR_SRC
RBIAS LGATE1B/PWM3

R8377 4.42K RT1 470K_5% 5

t
NTC 9 ISEN3_FB2
+3VRUN ISEN3/FB2 C848
R8378 0R VID1 3,8 VDDCGOOD C850 10UF_25V
2,9 GPIO12 BSZ100N03MS G
R8379 2.0K 1
C R8380 0R VID2 4 PGOOG 100nF 9 C
2,9 GPIO13 VR_TT#
R8381 0R R8375 2.0K 40 4 5
2 GPIO16 CLK_EN# 29 3 6
UGATE2 2 7
R8382 0R VID3 VID0 31 C851 100nF 1 8
2 GPIO15 32 VID0 30
R8383 0R VID4 VID1
2 GPIO20 33 VID1 BOOT2 DNI
VID2
VID2 Q105 IHLP2020AB-11 0.33uH
VID3 34
R8385 0R VID4 35 VID3 28
2,8,9 GPIO0 36 VID4 PHASE2
R8376 0R VID5 +3VRUN VID5 L34 1.0UH_3.7A
2,9 GPIO11 DNI VID6 37 VID5 DNI
3-PADS/2 VID6 26
R8386 10K PSI# 2 LGATE2
PSI# BSZ035N03MS G
R8387 10K DNI DPRSLPVR 39 C852
R8388 10K DNI DPRSLPVR 27 9 330UF_2V
R8389 10K VDDC_EN R8390 0R 38 VSSP2 4 5
VR_ON 3 6
10 ISEN2 2 7
R8391 121K 6 ISEN2 C853 1 8
VW R8392 R8393 R8394
R8395 100nF Q106 10K 3.65K 1R
C854 ISUM-
1nF 8.06K 20
UGATE1 ISUM+ ISUM-
C855 270pF_50V C856 100nF
19
OPTIONAL BOOT1
R8398 61.9K C857 560pF_25V
7 21
COMP PHASE1
R8399 G_PWR_SRC
2.37K 8 23
FB LGATE1A
R8400 191R C858 1.5nF_50V
22
C859 VSSP1 C861
560pF_25V R8401 2.2K BSZ100N03MS G 10UF_25V
11 ISEN1
ISEN1 C862 9
R8353 4 5
0R 100nF 3 6
R8402 VDDC 100R C863 330pF 2 7
VDDC
15 1 8
R8403 10R 12 ISUM+
3 FB_VDDC VSEN
Q107 IHLP2020AB-11 0.33uH
DNI 13
C864 RTN
1nF L35 1.0UH_3.7A
R8404 10R
3 FB_VSSC
B R8405 VDDC 100R C865 18 14 BSZ035N03MS G B
THM#1
THM#2
THM#3
THM#4

IMON ISUM- C866

1nF 9 330UF_2V
4 5
3 6
41
42
43
44

2480098900G 2 7
1 8 R8408
R8406 R8407 1R
Q108 10K 3.65K

ISUM+ ISUM-

ISUM+

R8409
C867 2.61K
C868
R8410
39nF 27nF_16V 11K
OPTIONAL RT2
C869 820pF R8411 100R 10K
t
R8412 4.12K
ISUM-

RT2 s/b placed

SET OCP 40A C870
close to phase
100nF
1 ouput
inductor
R607
VDDC_EN
8,11 RUNPWROK VDDCEN 11
10K
3

Q100 C827
22nF_16V
1
3,4 PX_EN
2N7002_NL
2

A A

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

© 2007 Advanced Micro Devices Advanced Micro Devices Inc.
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement 1 Commerce Valley Drive East
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose Markham, Ontario
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to, Date: Monday, September 13, 2010 Rev
any implied warranty of merchantibility or fitness for a particular
1
purpose, and disclaims responsibility forany consequences resulting Sheet 10
from use of the information included herein. of 12
Title Doc No.
Whisler MXM3.0 G5 105-C29247-00B
5 4 3 2 1
 5 4 3 2 1

D D

+5VRUN
+5VRUN

C613
C871 C614
10uF_10V R396 R397 100nF 1uF_6.3V R398 R399
1.5R 1.5R 1.5R 1.5R G_PWR_SRC

BSC150N03LD_G
Q69A
9 C615 C554 U48 C555 C616 1.5V C785
8 1uF_6.3V 1uF_6.3V 3 4 1uF_6.3V 1uF_6.3V
1 7 VCC2 VCC1 10UF_25V

9
5
6
7
8
20 15 ISL_GND2
ISL_GND1 PVCC2 PVCC1 Q72
BSZ100N03MS G

2
28 7
8 1.8VGOOD PGOOD2 PGOOD1 1.5VGOOD 8
2 5
VIN2 VIN1

4
3
2
1
22 13
UGATE2 UGATE1
Overlapped
OCP=7A 21 14
OCP= 11A, 1uH
C562 BOOT2 BOOT1 C678
C C
1.8V_REG +1.5V_REG
L31 2.2UH_2.7A 100nF 100nF L32 1uH_11A
23 12
PHASE2 PHASE1
BSC150N03LD_G
C567 330pF_50V Q69B R405 15.4K C571 6.8nF_25V C568
C564 C565 10 19 16 R403 C570
2.2UF_2.5V R404 54.9K 6 LGATE2 LGATE1 2.0K 330UF_2V 2.2UF_2.5V

9
5
6
7
8
220UF_2V 3 5 18 17
R406 PGND2 PGND1 Q74
R409 BSZ035N03MS G R8444
R407 15K
4

2.0K 54.9K 25 10 R410 C572

20K OCSET2 OCSET1 15.4K
26 9 270pF_50V
C573 VO2 VO1

4
3
2
1
270pF_50V
27 8
FB2 FB1
R411 1 6 R412
FSET2 FSET1
10K R413 10K
C574 R414 C575
12.7K 10nF 24 11 22.1K 10nF
EN2 EN1
ISL_GND1 29 31 ISL_GND2
30 epad1 epad3 32
epad2 epad4
ISL_GND1 ISL6228CRZ ISL_GND2

R415 0R R416 0R
R442 10K
8,10 RUNPWROK
C579 ISL_GND1 ISL_GND2
+3VRUN R609
B B
100nF 1M

R610 10K

6
R567 10K
10 VDDCEN
Q101A
R637 10K R611 1K
R624 10K Overlapped 2
+1.5V_REG 1.8V_REG 2N7002
8,10 RUNPWROK 8 1.0VGOOD

3
C831 C828

1
R622 0R Q101B
100nF 100nF
5
R623 0.05R_0.5W 2 GPIO21 2N7002 ISL_GND2
PCIE 1.0V (3A)

4
R533 0R +5VRUN
8,10 RUNPWROK
R608 10R

U55
C742 1 8
22nF_16V 2 GND EN 7
R538 3 FB POK 6
84.5K 4 VOUT3 VCNTL 5
VOUT4 VIN 9 C746
THM 1uF_6.3V
APL5913KAC-TRG C745
10uF_2.5V
22.1K C747
R540
27pF_50V
1.0V_REG

C750
22uF_2.5V
A A

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

© 2007 Advanced Micro Devices Advanced Micro Devices Inc.
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement 1 Commerce Valley Drive East
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose Markham, Ontario
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to, Date: Monday, September 13, 2010 Rev
1
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting Sheet 11 of 12
from use of the information included herein.
Title Doc No.
Whisler MXM3.0 G5 105-C29247-00B
5 4 3 2 1
 5 4 3 2 1

Title Schematic No. Date:

Whisler MXM3.0 G5 105-C29247-00B Monday, September 13, 2010
NOTE: This schematic represents the PCB, it does not represent any specific SKU.
Rev
REVISION HISTORY For Stuffing options (component values, DNI’s, …) please consult the product specific BOM.

D
Please contact AMD representative to obtain latest BOM closest to the application desired.
1 D
Sch PCB Date REVISION DESCRIPTION
Rev Rev
0 00A 18/08/09 On base B980 + G5 and new VDDC regulator

00B 25/08/10 U62 pin 18 connect to GND, C1204, R8457, R8458 are added; L1- B51, L3- B52

C C

B B

A A

5 4 3 2 1