Broadway

5 4 3 2 1
D D
U1A
PCIE_REFCLKP
(8) PCIE_REFCLKP
PCIE_REFCLKN
(8) PCIE_REFCLKN
PCIE_RXP0 AA38 Y33 PCIE_TXP0
PCIE_RXN0 Y37 PCIE_RX0P PCIE_TX0P Y32 PCIE_TXN0
PCIE_RX0N PCIE_TX0N
PCIE_RXP[15..0]
(8) PCIE_RXP[15..0]
PCIE_RXP1 Y35 W33 PCIE_TXP1
PCIE_RXN[15..0] PCIE_RXN1 W36 PCIE_RX1P PCIE_TX1P W32 PCIE_TXN1
(8) PCIE_RXN[15..0] PCIE_RX1N PCIE_TX1N
PCIE_TXP[15..0]
(8) PCIE_TXP[15..0]
PCIE_RXP2 W38 U33 PCIE_TXP2
PCIE_TXN[15..0] PCIE_RXN2 V37 PCIE_RX2P PCIE_TX2P U32 PCIE_TXN2
(8) PCIE_TXN[15..0] PCIE_RX2N PCIE_TX2N
PCIE_RXP3 V35 U30 PCIE_TXP3

PCIE_RXN3 U36 PCIE_RX3P PCIE_TX3P U29 PCIE_TXN3
PCIE_RX3N PCIE_TX3N
PCIE_RXP4 U38 T33 PCIE_TXP4

PCIE_RXN4 T37 PCIE_RX4P PCIE_TX4P T32 PCIE_TXN4
PCIE_RX4N PCIE_TX4N
PCI EXPRESS INTERFACE

PCIE_RST# R10 7.5K DNI 9 8 GPIO24_TRSTb
(8) PCIE_RST# GPIO24_TRSTb (2)
PCIE_RXP5 T35 T30 PCIE_TXP5
PCIE_RXN5 R36 PCIE_RX5P PCIE_TX5P T29 PCIE_TXN5 MU101C
PCIE_RX5N PCIE_TX5N C60 74LCX125MTC
C C
10
100pF_50V DNI
PCIE_RXP6 R38 P33 PCIE_TXP6 DNI
PCIE_RXN6 P37 PCIE_RX6P PCIE_TX6P P32 PCIE_TXN6
PCIE_RX6N PCIE_TX6N
PCIE_RXP7 P35 P30 PCIE_TXP7

PCIE_RXN7 N36 PCIE_RX7P PCIE_TX7P P29 PCIE_TXN7 R11 7.5K DNI 5 6 PERST#_buf
PCIE_RX7N PCIE_TX7N PERST#_buf (10)
MU101B
PCIE_RXP8 N38 N33 PCIE_TXP8 C61 74LCX125MTC
4
PCIE_RXN8 M37 PCIE_RX8P PCIE_TX8P N32 PCIE_TXN8 100pF_50V DNI
PCIE_RX8N PCIE_TX8N DNI
PCIE_RXP9 M35 N30 PCIE_TXP9 R9 0R DNI

PCIE_RXN9 L36 PCIE_RX9P PCIE_TX9P N29 PCIE_TXN9
PCIE_RX9N PCIE_TX9N +3VRUN
PCIE_RXP10 L38 L33 PCIE_TXP10 C59 100nF_6.3V

PCIE_RXN10 K37 PCIE_RX10P PCIE_TX10P L32 PCIE_TXN10
PCIE_RX10N PCIE_TX10N
14
PCIE_RXP11 K35 L30 PCIE_TXP11
PCIE_RXN11 J36 PCIE_RX11P PCIE_TX11P L29 PCIE_TXN11 PERST#_buf R12 7.5K DNI 2 3
MU101A
PCIE_RXP12 J38 K33 PCIE_TXP12 C62 74LCX125MTC
7
1
PCIE_RXN12 H37 PCIE_RX12P PCIE_TX12P K32 PCIE_TXN12 100pF_50V DNI
PCIE_RX12N PCIE_TX12N DNI
PERST#_buf_delayed
PCIE_RXP13 H35 J33 PCIE_TXP13
PCIE_RXN13 G36 PCIE_RX13P PCIE_TX13P J32 PCIE_TXN13
13
PCIE_RXP14 G38 K30 PCIE_TXP14 12 11 TESTEN

PCIE_RXN14 F37 PCIE_RX14P PCIE_TX14P K29 PCIE_TXN14 TESTEN (5)
PCIE_RX14N PCIE_TX14N MU101D
74LCX125MTC
B B
PCIE_RXP15 F35 H33 PCIE_TXP15 DNI
PCIE_RXN15 E37 PCIE_RX15P PCIE_TX15P H32 PCIE_TXN15
CLOCK
+1.8V_REG PCIE_REFCLKP AB35
PCIE_REFCLKN AA36 PCIE_REFCLKP TP_BP1 TP_BP2
PCIE_REFCLKN
+3VRUN U101 +3VRUN
R6218 CALIBRATION R8 10K 1 8
10K AJ21 Y30 PCIE_CALRP R1009 C58 100nF_6.3V 2 IN2 VCC 7 PCIE_RST#
DNI AK21 NC#1 PCIE_CALRP 1.27K +1.0V_REG PERST#_buf 3 NC IN1 6 TESTEN
AH16 NC#2 Y29 PCIE_CALRN R1010 4 OUT2 OUT3 5 GPIO24_TRSTb
PWRGOOD PCIE_CALRN 2.0K GND OUT1
UX5901
C1401 R7111 PERST#_buf AA30
10nF 1K PERSTB
DNI
Broadway
A A
CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

© 2007 Advanced Micro Devices Advanced Micro Devices Inc.
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement 1 Commerce Valley Drive East
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose Markham, Ontario
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to,
Date: Tuesday, February 16, 2010 Rev
5
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting Sheet 1 of 17
from use of the information included herein.
Title Doc No.
Broadway GDDR5 MXM 3.0 105-B971xx-00F
5 4 3 2 1
5 4 3 2 1
R4 10K
U1B U1G
R1303 10K
AU24 TXCAP_DPA3P (8)

LVDS CONTROL AK27
TXCAP_DPA3P VARY_BL BLON_PWM (8)
AV23 TXCAM_DPA3N (8) AJ27
TXCAM_DPA3N DIGON FPVCC (4,8)
+VDDR3 AT25 TX0P_DPA2P (8)
MUTI GFX TX0P_DPA2P AR24
TX0M_DPA2N TX0M_DPA2N (8)
DPA
AU26 TX1P_DPA1P (8) AK35 TXCLK_U+ (8)
TX1P_DPA1P AV25 TXCLK_UP_DPF3P AL36
TX1M_DPA1N TX1M_DPA1N (8) TXCLK_UN_DPF3N TXCLK_U- (8)
+VDDR3 C1304
1uF_6.3V BIOS1 AR8 AT27 TX2P_DPA0P (8) AJ38 TXOUT_U0+ (8)
U5508 AU8 DVPCNTL_MVP_0 TX2P_DPA0P AR26 TXOUT_U0P_DPF2P AK37
DVPCNTL_MVP_1 TX2M_DPA0N TX2M_DPA0N (8) TXOUT_U0N_DPF2N TXOUT_U0- (8)
GPIO22 1 8 AP8
D
GPIO8 2 CE# VCC 7 BIOS AW8 DVPCNTL_0 AR30 AH35 D
SO HOLD# DVPCNTL_1 TXCBP_DPB3P TXCBP_DPB3P (8) TXOUT_U1P_DPF1P TXOUT_U1+ (8)
3 6 GPIO10 AR3 AT29 TXCBM_DPB3N (8) AJ36 TXOUT_U1- (8)
4 WP# SCK 5 GPIO9 AR1 DVPCNTL_2 TXCBM_DPB3N TXOUT_U1N_DPF1N
GND SI 113-B971XX-XXX AU1 DVPCLK AV31 AG38
DVPDATA_0 TX3P_DPB2P TX3P_DPB2P (8) TXOUT_U2P_DPF0P TXOUT_U2+ (8)
PM25LV010A-100SCE VIDEO BIOS AU3 AU30 TX3M_DPB2N (8) AH37 TXOUT_U2- (8)
FIRMWARE AW3 DVPDATA_1 DPB TX3M_DPB2N TXOUT_U2N_DPF0N
AP6 DVPDATA_2 AR32 AF35
DVPDATA_3 TX4P_DPB1P TX4P_DPB1P (8) TXOUT_U3P TXOUT_U3+ (8)
AW5 AT31 TX4M_DPB1N (8) AG36 TXOUT_U3- (8)
AU5 DVPDATA_4 TX4M_DPB1N TXOUT_U3N
AR6 DVPDATA_5 AT33
SERIAL EEPROM 512K/1M AW6 DVPDATA_6
DVPDATA_7
TX5P_DPB0P
TX5M_DPB0N
AU32
TX5P_DPB0P (8)
TX5M_DPB0N (8)
LVTMDP
PN 2280007900G for 1Mbit (PM25LV010A-100SCE) AU6
AT7 DVPDATA_8 AU14 AP34
DVPDATA_9 TXCCP_DPC3P TXCLK_LP_DPE3P TXCLK_L+ (8)
AV7 AV13 AR34
DVPDATA_10 TXCCM_DPC3N TXCLK_LN_DPE3N TXCLK_L- (8)
AN7
AV9 DVPDATA_11 AT15 AW37
DVPDATA_12 TX0P_DPC2P TXOUT_L0P_DPE2P TXOUT_L0+ (8)
AT9 AR14 AU35 TXOUT_L0- (8)
AR10 DVPDATA_13 TX0M_DPC2N TXOUT_L0N_DPE2N
AW10 DVPDATA_14 DPC AU16 AR37
AU10 AV15 AU39 TXOUT_L1- (8)
AP10 DVPDATA_16 TX1M_DPC1N TXOUT_L1N_DPE1N
AV11 DVPDATA_17 AT17 AP35
AT11 AR16 AR35 TXOUT_L2- (8)
AR12 DVPDATA_19 TX2M_DPC0N TXOUT_L2N_DPE0N
AW12 DVPDATA_20 AU20 AN36
DVPDATA_21 TXCDP_DPD3P TXOUT_L3P TXOUT_L3+ (8)
AU12 AT19 AP37 TXOUT_L3- (8)
AP12 DVPDATA_22 TXCDM_DPD3N TXOUT_L3N
DVPDATA_23 AT21
+VDDR3 TX3P_DPD2P AR20
TX3M_DPD2N
DPD AU22
TX4P_DPD1P AV21 Broadway
R5624 R54 TX4M_DPD1N
4.7K 4.7K I2C AT23
DNI DNI TX5P_DPD0P AR22
TP19 35mil SCL AK26 TX5M_DPD0N
TP20 35mil SDA AJ26 SCL
SDA
C C
AD39
GENERAL PURPOSE I/O R AD37
GPIO0 AH20 RB
(8,9) GPIO0 GPIO_0
GPIO1 AH18 AE36
(8,9) GPIO1 GPIO_1 G
GPIO2 AN16 AD35
(9) GPIO2 GPIO_2 GB
GPIO3_SMBDATA AH23
(8) GPIO3_SMBDATA GPIO_3_SMBDATA
GPIO4_SMBCLK AJ23 AF37
(8) GPIO4_SMBCLK GPIO_4_SMBCLK B
GPIO5_AC_BATT AH17 AE38
(8) GPIO5_AC_BATT GPIO_5_AC_BATT BB
R6215 10K GPIO6 AJ17 DAC1
(10) GPIO6 GPIO_6
GPIO7_BLON AK17 AC36
(8) GPIO7_BLON GPIO_7_BLON HSYNC HSYNC_DAC1 (9)
GPIO8 RP1C 3 6 33R GPIO8_ROMSO AJ13 AC38
(9) GPIO8 GPIO_8_ROMSO VSYNC VSYNC_DAC1 (9)
GPIO9 RP1A 1 8 33R GPIO9_ROMSI AH15
(8,9) GPIO9 GPIO_9_ROMSI
GPIO10 RP1B 2 7 33R GPIO10_ROMSCK AJ16
GPIO11 AK16 GPIO_10_ROMSCK AB34 R5623
(9) GPIO11 GPIO_11 RSET
GPIO12 AL16 499R
+VDDR3 +VDDR3 (9) GPIO12 GPIO_12
GPIO13 AM16 AD34
(9) GPIO13 GPIO_13 AVDD
GPIO14_HPD2 AM14 AE34
(8) GPIO14_HPD2 GPIO_14_HPD2 AVSSQ
GPIO15_PCNTL0 AM13
(10) GPIO15_PCNTL0 GPIO_15_PWRCNTL_0
GPIO16_SSIN AK14 AC33
(9,10) GPIO16_SSIN GPIO_16_SSIN VDD1DI
MR1 R2 (8,9) GPIO17_THERMAL_INT GPIO17_THERMAL_INT AG30 AC34
1K 1K GPIO18_HPD3 AN14 GPIO_17_THERMAL_INT VSS1DI
(8) GPIO18_HPD3 GPIO_18_HPD3
DNI GPIO19_CTF AM17
(10) GPIO19_CTF GPIO_19_CTF
GPIO24_TRSTb GPIO20_PCNTL1 AL13 AC30
(1) GPIO24_TRSTb (10) GPIO20_PCNTL1 GPIO_20_PWRCNTL_1 R2 VGA_RED (8)
GPIO27_TMS GPIO21_BB_EN AJ14 AC31
(9,10) GPIO21_BB_EN GPIO_21_BB_EN R2B
GPIO26_TCK GPIO22 RP1D 4 5 33R GPIO22_SOMCSB AK13
(9) GPIO26_TCK (9) GPIO22 GPIO_22_ROMCSB
(8) GPIO23_CLKREQb GPIO23_CLKREQb AN13 AD30
GPIO_23_CLKREQB G2 VGA_GRN (8)
TP13 35mil GPIO24_TRSTb AM23 AD31
R1 R3 TP14 35mil GPIO25_TDI AN23 JTAG_TRSTB G2B
1K 1K TP15 35mil GPIO26_TCK AK23 JTAG_TDI AF30
JTAG_TCK B2 VGA_BLU (8)
DNI DNI TP16 35mil GPIO27_TMS AL24 AF31
TP17 35mil GPIO28_TDO AM24 JTAG_TMS B2B
AJ19 JTAG_TDO R6118 R6119 R6120
(9) MEM_ID0 GENERICA PLACE RGB
JTAG DEBUG PORT AK19 AC32 150R 150R 150R
(9) MEM_ID1
AJ20 GENERICB C AD32
TERMINATION
(9) MEM_ID2 GENERICC Y RESISTORS CLOSE
AK20 AF32
R5625 0R DNI GENERICE AJ24 GENERICD COMP
(8) MB_GPIO0 GENERICE_HPD4
TO ASIC
R5626 0R DNI GENERICF AH26 DAC2
B (8) MB_GPIO1 GENERICF B
R5627 0R DNI GENERICG AH24 AD29
(8) MB_GPIO2 GENERICG H2SYNC HSYNC_DAC2 (8,9)
AC29
V2SYNC VSYNC_DAC2 (8,9)
R5628 R5629 R5630 AK24 VDD2DI +1.8V_REG
(8) HPD1 HPD1 (VDD2DI: 50mA @ 1.8V)
10K 10K 10K AG31 B10064
DNI DNI DNI VDD2DI AG32 BLM15BD121SN1
VSS2DI
VSS2DI C36 C5610 C5708
+VDDR3 AG33 100nF_6.3V 1uF_6.3V 4.7uF_6.3V NS20
A2VDD 2 1
+1.8V_REG AD33
R5675 499R AH13 A2VDDQ NS_VIA
PLACE VREFG VREFG
R586 249R AF33 VSS2DI
DIVIDER AND CAP C5685 100nF_6.3V A2VSSQ
CLOSE TO ASIC A2VDD
(A2VDD: 130mA @ 3.3V) +VDDR3
+1.8V_REG (DPLL_PVDD: 75mA @ 1.8V) DPLL_PVDD AA29 R55 A2VSSQ B10061
B10098 AM32 R2SET 715R BLM15BD121SN1
BLM15BD121SN1 AN32 DPLL_PVDD
DPLL_PVSS C30 C31 C5706
C5784 C5785 C5786 GND_PVSS DDC/AUX AM26 100nF_6.3V 1uF_6.3V 4.7uF_6.3V
NS23 4.7uF_6.3V 1uF_6.3V 100nF_6.3V AN31 PLL/CLOCK DDC1CLK AN26
1 2 DPLL_VDDC DDC1DATA
AM27
AUX1P DDCCLK_AUX1P (8)
NS_VIA AV33 AL27 DPA
(9) XTALIN XTALIN AUX1N DDCDATA_AUX1N (8) A2VDDQ
GND_PVSS AU34 (A2VDDQ: 1.5mA @ 1.8V) +1.8V_REG
XTALOUT AM19 B10063
DDC2CLK AL19 BLM15BD121SN1
+1.0V_REG DPLL_VDDC AW34 DDC2DATA
(DPLL_VDDC: 125mA @ 1.0V) (9) XO_IN XO_IN
B10099 AN20 C5628 C5627
AUX2P DDCCLK_AUX2P (8)
BLM15BD121SN1 AW35 AM20 DPB 100nF_6.3V 1uF_6.3V NS19
(9) XO_IN2 XO_IN2 AUX2N DDCDATA_AUX2N (8)
2 1
C5787 C6067 C5789 AL30
DDCCLK_AUX3P DDC3CLK (8)
4.7uF_6.3V 1uF_6.3V 100nF_6.3V AM30 LVDS NS_VIA
DDCDATA_AUX3N DDC3DATA (8)
A2VSSQ
AL29
AF29 DDCCLK_AUX4P AM29
(9) GPU_DPLUS DPLUS DDCDATA_AUX4N
GND_PVSS AG29 THERMAL
(9) GPU_DMINUS DMINUS
A AN21 A
DDCCLK_AUX5P DDC5CLK (8)
AM21 VGA
DDCDATA_AUX5N DDC5DATA (8)
AK32
(9) TS_FDO TS_FDO AJ30
DDC6CLK DDC6CLK (9)
AL31 AJ31 External thermal sensor
TS_A DDC6DATA DDC6DATA (9)
+1.8V_REG (TSVDD: 5mA @ 1.8V) TSVDD AK30
B10122 AJ32 DDCCLK_AUX7P AK29 R121 R122 CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
BLM15BD121SN1 AJ33 TSVDD DDCDATA_AUX7N 4.7K 4.7K © 2007 Advanced Micro Devices Advanced Micro Devices Inc.
TSVSS DNI DNI This AMD Board schematic and design is the exclusive property of AMD,
C5923 C5924 TSVSS
NS13 4.7uF_6.3V 1uF_6.3V Broadway is strictly prohibited. Use of this schematic and design for any purpose Markham, Ontario
1 2 +VDDR3 other than evaluation requires a Board Technology License Agreement
NS_VIA 5
TSVSS purpose, and disclaims responsibility forany consequences resulting Sheet 2 of 17
Title Doc No.
5 4 3 2 1
5 4 3 2 1
U1E U1F
MEM I/O
+MVDD PCIE PCIE_VDDR +1.8V_REG
(VDDR1: 1.7A (RMS) 1.9A (Peak) @ 1.5V) (PCIE_VDDR: 400mA @ 1.8V)
AC7 AA31 L115 AB39 A3
AD11 VDDR1#1 PCIE_VDDR#1 AA32 470R_1000mA E39 PCIE_VSS#1 GND#1 A37
AF7 VDDR1#2 PCIE_VDDR#2 AA33 F34 PCIE_VSS#2 GND#2 AA16
C1600 C1601 C1602 C1603 C1604 C1605 C1606 C1607 C1608 C1609 AG10 VDDR1#3 PCIE_VDDR#3 AA34 C5803 C5804 C5929 C5800 C5802 C5928 F39 PCIE_VSS#3 GND#3 AA18
1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V AJ7 VDDR1#4 PCIE_VDDR#4 V28 100nF_6.3V 100nF_6.3V 1uF_6.3V 1uF_6.3V 4.7uF_6.3V 4.7uF_6.3V G33 PCIE_VSS#4 GND#4 AA2
AK8 VDDR1#5 PCIE_VDDR#5 W29 G34 PCIE_VSS#5 GND#5 AA21
AL9 VDDR1#6 PCIE_VDDR#6 W30 H31 PCIE_VSS#6 GND#6 AA23
G11 VDDR1#7 PCIE_VDDR#7 Y31 H34 PCIE_VSS#7 GND#7 AA26
G14 VDDR1#8 PCIE_VDDR#8 H39 PCIE_VSS#8 GND#8 AA28
G17 VDDR1#9 PCIE_VDDC +1.0V_REG J31 PCIE_VSS#9 GND#9 AA6
D VDDR1#10 (PCIE_VDDC: 1.1A @ 1.0V) PCIE_VSS#10 GND#10 D
C1615 C5586 C5969 C5967 C5968 G20 G30 J34 AB12
1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V G23 VDDR1#11 PCIE_VDDC#1 G31 K31 PCIE_VSS#11 GND#11 AB15
G26 VDDR1#12 PCIE_VDDC#2 H29 K34 PCIE_VSS#12 GND#12 AB17
G29 VDDR1#13 PCIE_VDDC#3 H30 C983 C972 C5927 C5930 C973 C1668 K39 PCIE_VSS#13 GND#13 AB20
H10 VDDR1#14 PCIE_VDDC#4 J29 100nF_6.3V 100nF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 4.7uF_6.3V L31 PCIE_VSS#14 GND#14 AB22
J7 VDDR1#15 PCIE_VDDC#5 J30 L34 PCIE_VSS#15 GND#15 AB24
J9 VDDR1#16 PCIE_VDDC#6 L28 M34 PCIE_VSS#16 GND#16 AB27
C5620 C5585 C5665 C5666 K11 VDDR1#17 PCIE_VDDC#7 M28 M39 PCIE_VSS#17 GND#17 AC11
10uF_4V 10uF_4V 10uF_4V 10uF_4V K13 VDDR1#18 PCIE_VDDC#8 N28 N31 PCIE_VSS#18 GND#18 AC13
K8 VDDR1#19 PCIE_VDDC#9 R28 N34 PCIE_VSS#19 GND#19 AC16
L12 VDDR1#20 PCIE_VDDC#10 T28 P31 PCIE_VSS#20 GND#20 AC18
L16 VDDR1#21 PCIE_VDDC#11 U28 P34 PCIE_VSS#21 GND#21 AC2
L21 VDDR1#22 PCIE_VDDC#12 P39 PCIE_VSS#22 GND#22 AC21
L23 VDDR1#23 +VDDC R34 PCIE_VSS#23 GND#23 AC23
VDDR1#24 (VDDC: 30A (RMS) 47A (Peak) @ 1.0V) PCIE_VSS#24 GND#24
C7195 C7196 C7197 C7198 C7199 C7200 C7201 C7202 L26 AA15 T31 AC26
10uF_4V 10uF_4V 10uF_4V 10uF_4V 10uF_4V 10uF_4V 10uF_4V 10uF_4V L7 VDDR1#25 CORE VDDC#1 AA17 T34 PCIE_VSS#25 GND#25 AC28
M11 VDDR1#26 VDDC#2 AA20 T39 PCIE_VSS#26 GND#26 AC6
N11 VDDR1#27 VDDC#3 AA22 C942 C251 C252 C253 C943 C255 C260 C261 C258 C259 U31 PCIE_VSS#27 GND#27 AD15
P7 VDDR1#28 VDDC#4 AA24 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V U34 PCIE_VSS#28 GND#28 AD17
R11 VDDR1#29 VDDC#5 AA27 V34 PCIE_VSS#29 GND#29 AD20
U11 VDDR1#30 VDDC#6 AB16 V39 PCIE_VSS#30 GND#30 AD22
C6069 C6068 C5584 U7 VDDR1#31 VDDC#7 AB18 W31 PCIE_VSS#31 GND#31 AD24
10uF_4V 10uF_4V 10uF_4V Y11 VDDR1#32 VDDC#8 AB21 W34 PCIE_VSS#32 GND#32 AD27
Y7 VDDR1#33 VDDC#9 AB23 Y34 PCIE_VSS#33 GND#33 AD9
VDDR1#34 VDDC#10 AB26 C161 C162 C163 C164 C165 C166 C167 C168 C169 C170 Y39 PCIE_VSS#34 GND#34 AE2
VDDC#11 AB28 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V PCIE_VSS#35 GND#35 AE6
VDDC#12 AC17 GND#36 AF10
VDDC#13 AC20 GND#37 AF16
LEVEL VDDC#14 AC22 GND#38 AF18
+1.8V_REG VDD_CT TRANSLATION VDDC#15 AC24 GND#39 AF21
(VDD_CT: 17mA @ 1.8V) VDDC#16
GND GND#40
POWER
B10100 AF26 AC27 AG17
BLM15BD121SN1 AF27 VDD_CT#1 VDDC#17 AD18 C171 C172 C173 C174 C175 C176 F15 GND#41 AG2
AG26 VDD_CT#2 VDDC#18 AD21 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V F17 GND#100 GND#42 AG20
C5824 C5821 C5826 AG27 VDD_CT#3 VDDC#19 AD23 F19 GND#101 GND#43 AG22
4.7uF_6.3V 1uF_6.3V 100nF_6.3V VDD_CT#4 VDDC#20 AD26 F21 GND#102 GND#44 AG6
VDDC#21 AF17 F23 GND#103 GND#45 AG9
+VDDR3 VDDR3 I/O VDDC#22 AF20 F25 GND#104 GND#46 AH21
(VDDR3: 60mA @ 3.3V) VDDC#23 GND#105 GND#47
C B27 AF23 AF22 F27 AJ10 C
BLM15BD121SN1 AF24 VDDR3#1 VDDC#24 AG16 C181 C182 C183 C191 C192 C193 C194 F29 GND#106 GND#48 AJ11
AG23 VDDR3#2 VDDC#25 AG18 10uF_4V 10uF_4V 10uF_4V 10uF_4V 10uF_4V 10uF_4V 10uF_4V F31 GND#107 GND#49 AJ2
C5591 C5592 AG24 VDDR3#3 VDDC#26 AG21 F33 GND#108 GND#50 AJ28
4.7uF_6.3V 1uF_6.3V VDDR3#4 VDDC#27 AH22 F7 GND#109 GND#51 AJ6
VDDC#28 AH27 F9 GND#110 GND#52 AK11
AF13 VDDC#29 AH28 G2 GND#111 GND#53 AK31
AF15 VDDR4#4 VDDC#30 M26 G6 GND#112 GND#54 AK7
AG13 VDDR4#5 VDDC#31 N24 C6070 C6071 C6072 C6073 H9 GND#113 GND#55 AL11
VDDR4 AG15 VDDR4#7 VDDC#32 N27 22uF_2.5V 22uF_2.5V 22uF_2.5V 22uF_2.5V J2 GND#114 GND#56 AL14
(VDDR4: 170mA @ 1.8V) VDDR4#8 VDDC/BIF_VDDC#33 GND#115 GND#57
B10101 R18 J27 AL17
BLM15BD121SN1 VDDC#34 R21 J6 GND#116 GND#58 AL2
AD12 VDDC#35 R23 J8 GND#117 GND#59 AL20
C5932 C5829 AF11 VDDR4#1 VDDC#36 R26 K14 GND#118 GND#60 AL21
1uF_6.3V 100nF_6.3V AF12 VDDR4#2 VDDC#37 T17 K7 GND#119 GND/PX_EN#61 AL23
AG11 VDDR4#3 VDDC#38 T20 L11 GND#120 GND#62 AL26
VDDR4#6 VDDC#39 T22 L17 GND#121 GND#63 AL32
VDDC#40 T24 L2 GND#122 GND#64 AL6
VDDC#41 T27 L22 GND#123 GND#65 AL8
VDDC/BIF_VDDC#42 U16 L24 GND#124 GND#66 AM11
M20 VDDC#43 U18 L6 GND#125 GND#67 AM31
M21 NC_VDDRHA VDDC#44 U21 M17 GND#126 GND#68 AM9
NC_VSSRHA VDDC#45 U23 M22 GND#127 GND#69 AN11
VDDC#46 U26 M24 GND#128 GND#70 AN2
V12 VDDC#47 V17 N16 GND#129 GND#71 AN30
U12 NC_VDDRHB VDDC#48 V20 N18 GND#130 GND#72 AN6
NC_VSSRHB VDDC#49 V22 N2 GND#131 GND#73 AN8
VDDC#50 V24 N21 GND#132 GND#74 AP11
VDDC#51 V27 N23 GND#133 GND#75 AP7
VDDC#52 Y16 N26 GND#134 GND#76 AP9
PCIE_PVDD PLL VDDC#53 Y18 N6 GND#135 GND#77 AR5
(PCIE_PVDD: 40mA @ 1.8V) VDDC#54 GND#136 GND#78
B10105 AB37 Y21 R15 B11
BLM15BD121SN1 MPV18 PCIE_PVDD VDDC#55 Y23 R17 GND#137 GND#79 B13
H7 VDDC#56 Y26 R2 GND#138 GND#80 B15
C5832 C5833 C5834 H8 MPV18#1 VDDC#57 Y28 R20 GND#139 GND#81 B17
4.7uF_6.3V 1uF_6.3V 100nF_6.3V MPV18#2 VDDC#58 R22 GND#140 GND#82 B19
SPV18 R24 GND#141 GND#83 B21
AM10 +VDDCI R27 GND#142 GND#84 B23
B SPV10 SPV18 (VDDCI : 9.5A @ 1.0V) GND#143 GND#85 B
AA13 R6 B25
AN9 VDDCI#1 AB13 T11 GND#144 GND#86 B27
SPV10 VDDCI#2 AC12 T13 GND#145 GND#87 B29
+1.8V_REG AN10 VDDCI#3 AC15 C1433 C1434 C1435 C1436 C1437 C7102 C7103 C7104 C7105 T16 GND#146 GND#88 B31
(MPV18: 150mA @ 1.8V) SPVSS VDDCI#4 GND#147 GND#89
B10128 AD13 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V T18 B33
BLM15BD121SN1 SPVSS VDDCI#5 AD16 T21 GND#148 GND#90 B7
VDDCI#6 M15 T23 GND#149 GND#91 B9
C7115 C5950 C5951 C5954 VDDCI#7 M16 T26 GND#150 GND#92 C1
4.7uF_6.3V 4.7uF_6.3V 1uF_6.3V 100nF_6.3V VOLTAGE VDDCI#8 M18 U15 GND#151 GND#93 C39
SENESE VDDCI#9 M23 U17 GND#153 GND#94 E35
VDDCI#10 N13 C1443 C1444 C1445 C1446 U2 GND#154 GND#95 E5
AF28 VDDCI#11 N15 10uF_4V 10uF_4V 10uF_4V 10uF_4V U20 GND#155 GND#96 F11
(11) ASIC_FB_VDDC FB_VDDC VDDCI#12 GND#156 GND#97
N17 U22 F13
VDDCI#13 N20 U24 GND#157 GND#98
(SPV18: 50mA @ 1.8V) VDDCI#14 GND#158
B10127 AG28 N22 U27
(12) ASIC_FB_VDDCI FB_VDDCI ISOLATED VDDCI#15 GND#159
BLM15BD121SN1 R12 U6
CORE I/O VDDCI#16 R13 V11 GND#160
C5947 C5948 C5949 AH29 VDDCI#17 R16 C6074 C6075 C6076 C7106 C7107 V16 GND#161
4.7uF_6.3V 1uF_6.3V 100nF_6.3V FB_GND VDDCI#18 T12 22uF_2.5V 22uF_2.5V 22uF_2.5V 22uF_2.5V 22uF_2.5V V18 GND#163
VDDCI#19 T15 V21 GND#164
VDDCI#20 V15 V23 GND#165
VDDCI#21 Y13 V26 GND#166
SPVSS VDDCI#22 W2 GND#167
W6 GND#168
Broadway Y15 GND#169
+1.0V_REG Y17 GND#170
(SPV10: 100mA @ 1.0V) GND#171
B10124 Y20
BLM15BD121SN1 Y22 GND#172 A39
Y24 GND#173 VSS_MECH#1 AW1
C5694 C5614 C45 Y27 GND#174 VSS_MECH#2 AW39
NS21 4.7uF_6.3V 1uF_6.3V 100nF_6.3V U13 GND#175 VSS_MECH#3
1 2 V13 GND#152
GND#162
NS_VIA Broadway
SPVSS
A A

5
Title Doc No.
5 4 3 2 1
5 4 3 2 1
D D
U1H
DP C/D POWER DP A/B POWER

DPAB_VDD18 +1.8V_REG
(DPAB_VDD18: 260mA @ 1.8V)
AP20 AN24 B10130
AP21 DPC_VDD18#1 DPA_VDD18#1 AP24 120R_450mA
DPC_VDD18#2 DPA_VDD18#2
C5956 C5957 C5955
100nF_6.3V 1uF_6.3V 4.7uF_6.3V
AP13 AP31
AT13 DPC_VDD10#1 DPA_VDD10#1 AP32
DPC_VDD10#2 DPA_VDD10#2
AN17 AN27
AP16 DPC_VSSR#1 DPA_VSSR#1 AP27 DPAB_VDD10 +1.0V_REG
DPC_VSSR#2 DPA_VSSR#2 (DPAB_VDD10: 220mA @ 1.0V)
AP17 AP28 B10110
AW14 DPC_VSSR#3 DPA_VSSR#3 AW24 120R_450mA
AW16 DPC_VSSR#4 DPA_VSSR#4 AW26
DPC_VSSR#5 DPA_VSSR#5 C5848 C5847 C5846
100nF_6.3V 1uF_6.3V 4.7uF_6.3V
DPAB_VDD18
+5VRUN AP22 AP25
Q27 AP23 DPD_VDD18#1 DPB_VDD18#1 AP26
+1.8V_REG NDS335N DPEF_VDD18 DPD_VDD18#2 DPB_VDD18#2
3 2 DPAB_VDD10
C27 AP14 AN33
100nF AP15 DPD_VDD10#1 DPB_VDD10#1 AP33
C C
DPD_VDD10#2 DPB_VDD10#2
5
1
U27
1
2 4
(2,8) FPVCC
AN19 AN29
74HCT1G126GW AP18 DPD_VSSR#1 DPB_VSSR#1 AP29
AP19 DPD_VSSR#2 DPB_VSSR#2 AP30
3
AW20 DPD_VSSR#3 DPB_VSSR#3 AW30

AW22 DPD_VSSR#4 DPB_VSSR#4 AW32
DPD_VSSR#5 DPB_VSSR#5
R6078 150R AW18 AW28 R6079 150R

DNI DPCD_CALR DPAB_CALR
+1.8V_REG (DPEF_VDD18: 400mA @ 1.8V) DPEF_VDD18 DP E/F POWER DP PLL POWER DPAB_PVDD (DPAB_PVDD: 40mA @ 1.8V) +1.8V_REG
B10113 AH34 AU28 B10112
120R_450mA AJ34 DPE_VDD18#1 DPA_PVDD AV27 BLM15BD121SN1
DPE_VDD18#2 DPA_PVSS
C5855 C5856 C5857 C5852 C5853 C5854
4.7uF_6.3V 1uF_6.3V 100nF_6.3V DPEF_VDD10 DPAB_PVDD 100nF_6.3V 1uF_6.3V 4.7uF_6.3V NS7
AL33 AV29 2 1
AM33 DPE_VDD10#1 DPB_PVDD AR28
DPE_VDD10#2 DPB_PVSS NS_VIA
DPAB_PVSS
DPAB_PVSS
+1.0V_REG (DPEF_VDD10: 240mA @ 1.0V) AN34 AU18
B10115 AP39 DPE_VSSR#1 DPC_PVDD AV17
120R_450mA AR39 DPE_VSSR#2 DPC_PVSS
AU37 DPE_VSSR#3
C5861 C5862 C5863 DPE_VSSR#4
4.7uF_6.3V 1uF_6.3V 100nF_6.3V AV19
DPD_PVDD AR18
DPEF_VDD18 DPD_PVSS
AF34
AG34 DPF_VDD18#1 DPEF_PVDD
DPF_VDD18#2 (DPEF_PVDD: 40mA @ 1.8V)
AM37 B10119
DPE_PVDD AN38 BLM15BD121SN1
B
DPEF_VDD10 DPE_PVSS B
AK33 C5873 C5874 C5875
AK34 DPF_VDD10#1 DPEF_PVDD 100nF_6.3V 1uF_6.3V 4.7uF_6.3V NS12
DPF_VDD10#2 AL38 2 1
DPF_PVDD AM35
If DPEF ports are not used (i.e no LVDS): DPF_PVSS NS_VIA
DNI B10113, C5855, C5856, B10115, C5861, C5862, B10119, C5874, C5875 and R6080. AF39 DPEF_PVSS
AH39 DPF_VSSR#1 DPEF_PVSS
DNI U27, Q27 and C27. AK39 DPF_VSSR#2
Install 0R resistors on C5857, C5863 and C5873. AL34 DPF_VSSR#3
AM34 DPF_VSSR#4
DPF_VSSR#5
R6080 150R AM39

DPEF_CALR
Broadway
A A

5
Title Doc No.
5 4 3 2 1
5 4 3 2 1
D D
U1C U1D
DDR2 DDR2 DDR2 DDR2
GDDR3/GDDR5 GDDR5/GDDR3 GDDR3/GDDR5 GDDR5/GDDR3
DDR3 DDR3 DDR3 DDR3
DQA0_0 C37 G24 MAA0_0 DQB0_0 C5 P8 MAB0_0
DQA0_1 C35 DQA0_0/DQA_0 MAA0_0/MAA_0 J23 MAA0_1 DQB0_1 C3 DQB0_0/DQB_0 MAB0_0/MAB_0 T9 MAB0_1
DQA0_2 A35 DQA0_1/DQA_1 MAA0_1/MAA_1 H24 MAA0_2 DQB0_2 E3 DQB0_1/DQB_1 MAB0_1/MAB_1 P9 MAB0_2
DQA0_3 E34 DQA0_2/DQA_2 MAA0_2/MAA_2 J24 MAA0_3 DQB0_3 E1 DQB0_2/DQB_2 MAB0_2/MAB_2 N7 MAB0_3
MEMORY INTERFACE A
DQA0_4 G32 DQA0_3/DQA_3 MAA0_3/MAA_3 H26 MAA0_4 DQB0_4 F1 DQB0_3/DQB_3 MAB0_3/MAB_3 N8 MAB0_4
MEMORY INTERFACE B
DQA0_5 D33 DQA0_4/DQA_4 MAA0_4/MAA_4 J26 MAA0_5 DQB0_5 F3 DQB0_4/DQB_4 MAB0_4/MAB_4 N9 MAB0_5
DQA0_6 F32 DQA0_5/DQA_5 MAA0_5/MAA_5 H21 MAA0_6 DQB0_[31..0] DQB0_6 F5 DQB0_5/DQB_5 MAB0_5/MAB_5 U9 MAB0_6
DQA0_[31..0] DQA0_7 E32 DQA0_6/DQA_6 MAA0_6/MAA_6 G21 MAA0_7 (7) DQB0_[31..0] DQB0_7 G4 DQB0_6/DQB_6 MAB0_6/MAB_6 U8 MAB0_7
(6) DQA0_[31..0] DQA0_8 D31 DQA0_7/DQA_7 MAA0_7/MAA_7 H19 MAA1_0 DQB1_[31..0] DQB0_8 H5 DQB0_7/DQB_7 MAB0_7/MAB_7 Y9 MAB1_0
DQA1_[31..0] DQA0_9 F30 DQA0_8/DQA_8 MAA1_0/MAA_8 H20 MAA1_1 (7) DQB1_[31..0] DQB0_9 H6 DQB0_8/DQB_8 MAB1_0/MAB_8 W9 MAB1_1
(6) DQA1_[31..0] DQA0_10 C30 DQA0_9/DQA_9 MAA1_1/MAA_9 L13 MAA1_2 MAB0_[8..0] DQB0_10 J4 DQB0_9/DQB_9 MAB1_1/MAB_9 AC8 MAB1_2
MAA0_[8..0] DQA0_10/DQA_10 MAA1_2/MAA_10 (7) MAB0_[8..0] DQB0_10/DQB_10 MAB1_2/MAB_10
DQA0_11 A30 G16 MAA1_3 DQB0_11 K6 AC9 MAB1_3
(6) MAA0_[8..0] DQA0_11/DQA_11 MAA1_3/MAA_11 MAB1_[8..0] DQB0_11/DQB_11 MAB1_3/MAB_11
DQA0_12 F28 J16 MAA1_4 DQB0_12 K5 AA7 MAB1_4
MAA1_[8..0] DQA0_12/DQA_12 MAA1_4/MAA_12 (7) MAB1_[8..0] DQB0_12/DQB_12 MAB1_4/MAB_12
DQA0_13 C28 H16 MAA1_5 DQB0_13 L4 AA8 MAB1_5
(6) MAA1_[8..0] DQA0_13/DQA_13 MAA1_5/MAA_13_BA2 DQB0_13/DQB_13 MAB1_5/BA2
DQA0_14 A28 J17 MAA1_6 DQB0_14 M6 Y8 MAB1_6
DQA0_15 E28 DQA0_14/DQA_14 MAA1_6/MAA_14_BA0 H17 MAA1_7 DQB0_15 M1 DQB0_14/DQB_14 MAB1_6/BA0 AA9 MAB1_7
DQA0_16 D27 DQA0_15/DQA_15 MAA1_7/MAA_A15_BA1 DQB0_16 M3 DQB0_15/DQB_15 MAB1_7/BA1
DQA0_17 F26 DQA0_16/DQA_16 A32 DQB0_17 M5 DQB0_16/DQB_16 H3
DQA0_17/DQA_17 WCKA0_0/DQMA_0 WCKA0_0 (6) DQB0_17/DQB_17 WCKB0_0/DQMB_0 WCKB0_0 (7)
DQA0_18 C26 C32 WCKA0b_0 (6) DQB0_18 N4 H1 WCKB0b_0 (7)
DQA0_19 A26 DQA0_18/DQA_18 WCKA0B_0/DQMA_1 D23 DQB0_19 P6 DQB0_18/DQB_18 WCKB0B_0/DQMB_1 T3
DQA0_20 F24 E22 WCKA0b_1 (6) DQB0_20 P5 T5 WCKB0b_1 (7)
DQA0_21 C24 DQA0_20/DQA_20 WCKA0B_1/DQMA_3 C14 DQB0_21 R4 DQB0_20/DQB_20 WCKB0B_1/DQMB_3 AE4
DQA0_22 A24 A14 WCKA1b_0 (6) DQB0_22 T6 AF5 WCKB1b_0 (7)
DQA0_23 E24 DQA0_22/DQA_22 WCKA1B_0/DQMA_5 E10 DQB0_23 T1 DQB0_22/DQB_22 WCKB1B_0/DQMB_5 AK6
DQA0_24 C22 D9 WCKA1b_1 (6) DQB0_24 U4 AK5 WCKB1b_1 (7)
DQA0_25 A22 DQA0_24/DQA_24 WCKA1B_1/DQMA_7 DQB0_25 V6 DQB0_24/DQB_24 WCKB1B_1/DQMB_7
DQA0_26 F22 DQA0_25/DQA_25 GDDR5/DDR2/GDDR3 C34 DQB0_26 V1 DQB0_25/DQB_25 GDDR5/DDR2/GDDR3 F6
DQA0_26/DQA_26 EDCA0_0/QSA_0/RDQSA_0 EDCA0_0 (6) DQB0_26/DQB_26 EDCB0_0/QSB_0/RDQSB_0 EDCB0_0 (7)
DQA0_27 D21 D29 EDCA0_1 (6) DQB0_27 V3 K3 EDCB0_1 (7)
DQA0_28 A20 DQA0_27/DQA_27 EDCA0_1/QSA_1/RDQSA_1 D25 DQB0_28 Y6 DQB0_27/DQB_27 EDCB0_1/QSB_1/RDQSB_1 P3
C EDCA0_2 (6) EDCB0_2 (7) C
DQA0_29 F20 DQA0_28/DQA_28 EDCA0_2/QSA_2/RDQSA_2 E20 DQB0_29 Y1 DQB0_28/DQB_28 EDCB0_2/QSB_2/RDQSB_2 V5
DQA0_30 D19 E16 EDCA1_0 (6) DQB0_30 Y3 AB5 EDCB1_0 (7)
DQA0_31 E18 DQA0_30/DQA_30 EDCA1_0/QSA_4/RDQSA_4 E12 DQB0_31 Y5 DQB0_30/DQB_30 EDCB1_0/QSB_4/RDQSB_4 AH1
DQA1_0 C18 J10 EDCA1_2 (6) DQB1_0 AA4 AJ9 EDCB1_2 (7)
DQA1_1 A18 DQA1_0/DQA_32 EDCA1_2/QSA_6/RDQSA_6 D7 DQB1_1 AB6 DQB1_0/DQB_32 EDCB1_2/QSB_6/RDQSB_6 AM5
DQA1_2 F18 DQB1_2 AB1
DQA1_3 D17 DQA1_2/DQA_34 A34 DQB1_3 AB3 DQB1_2/DQB_34 G7
DQA1_3/DQA_35 DDBIA0_0/QSA_0B/WDQSA_0 DDBIA0_0 (6) DQB1_3/DQB_35 DDBIB0_0/QSB_0B/WDQSB_0 DDBIB0_0 (7)
DQA1_4 A16 E30 DDBIA0_1 (6) DQB1_4 AD6 K1 DDBIB0_1 (7)
DQA1_5 F16 DQA1_4/DQA_36 DDBIA0_1/QSA_1B/WDQSA_1 E26 DQB1_5 AD1 DQB1_4/DQB_36 DDBIB0_1/QSB_1B/WDQSB_1 P1
DQA1_6 D15 C20 DDBIA0_3 (6) DQB1_6 AD3 W4 DDBIB0_3 (7)
DQA1_7 E14 DQA1_6/DQA_38 DDBIA0_3/QSA_3B/WDQSA_3 C16 DQB1_7 AD5 DQB1_6/DQB_38 DDBIB0_3/QSB_3B/WDQSB_3 AC4
DQA1_8 F14 C12 DDBIA1_1 (6) DQB1_8 AF1 AH3 DDBIB1_1 (7)
DQA1_9 D13 DQA1_8/DQA_40 DDBIA1_1/QSA_5B/WDQSA_5 J11 DQB1_9 AF3 DQB1_8/DQB_40 DDBIB1_1/QSB_5B/WDQSB_5 AJ8
DQA1_10 F12 F8 DDBIA1_3 (6) DQB1_10 AF6 AM3 DDBIB1_3 (7)
DQA1_11 A12 DQA1_10/DQA_42 DDBIA1_3/QSA_7B/WDQSA_7 DQB1_11 AG4 DQB1_10/DQB_42 DDBIB1_3/QSB_7B/WDQSB_7
DQA1_12 D11 DQA1_11/DQA_43 J21 DQB1_12 AH5 DQB1_11/DQB_43 T7
DQA1_12/DQA_44 ADBIA0/ODTA0 ADBIA0 (6) DQB1_12/DQB_44 ADBIB0/ODTB0 ADBIB0 (7)
DQA1_13 F10 G19 ADBIA1 (6) DQB1_13 AH6 W7 ADBIB1 (7)
DQA1_14 A10 DQA1_13/DQA_45 ADBIA1/ODTA1 DQB1_14 AJ4 DQB1_13/DQB_45 ADBIB1/ODTB1
DQA1_15 C10 DQA1_14/DQA_46 H27 DQB1_15 AK3 DQB1_14/DQB_46 L9
DQA1_15/DQA_47 CLKA0 CLKA0 (6) DQB1_15/DQB_47 CLKB0 CLKB0 (7)
DQA1_16 G13 G27 CLKA0b (6) DQB1_16 AF8 L8 CLKB0b (7)
DQA1_17 H13 DQA1_16/DQA_48 CLKA0B DQB1_17 AF9 DQB1_16/DQB_48 CLKB0B
DQA1_18 J13 DQA1_17/DQA_49 J14 DQB1_18 AG8 DQB1_17/DQB_49 AD8
DQA1_18/DQA_50 CLKA1 CLKA1 (6) DQB1_18/DQB_50 CLKB1 CLKB1 (7)
DQA1_19 H11 H14 CLKA1b (6) DQB1_19 AG7 AD7 CLKB1b (7)
DQA1_20 G10 DQA1_19/DQA_51 CLKA1B DQB1_20 AK9 DQB1_19/DQB_51 CLKB1B
DQA1_21 G8 DQA1_20/DQA_52 K23 DQB1_21 AL7 DQB1_20/DQB_52 T10
DQA1_21/DQA_53 RASA0B RASA0b (6) DQB1_21/DQB_53 RASB0B RASB0b (7)
DQA1_22 K9 K19 RASA1b (6) DQB1_22 AM8 Y10 RASB1b (7)
DQA1_23 K10 DQA1_22/DQA_54 RASA1B DQB1_23 AM7 DQB1_22/DQB_54 RASB1B
DQA1_24 G9 DQA1_23/DQA_55 K20 DQB1_24 AK1 DQB1_23/DQB_55 W10
DQA1_24/DQA_56 CASA0B CASA0b (6) DQB1_24/DQB_56 CASB0B CASB0b (7)
DQA1_25 A8 K17 CASA1b (6) DQB1_25 AL4 AA10 CASB1b (7)
+MVDD DQA1_26 C8 DQA1_25/DQA_57 CASA1B DQB1_26 AM6 DQB1_25/DQB_57 CASB1B
DQA1_27 E8 DQA1_26/DQA_58 K24 +MVDD DQB1_27 AM1 DQB1_26/DQB_58 P10
DQA1_27/DQA_59 CSA0B_0 CSA0b_0 (6) DQB1_27/DQB_59 CSB0B_0 CSB0b_0 (7)
DQA1_28 A6 K27 DQB1_28 AN4 L10
DQA1_29 C6 DQA1_28/DQA_60 CSA0B_1 DQB1_29 AP3 DQB1_28/DQB_60 CSB0B_1
R137 C1458 DQA1_30 E6 DQA1_29/DQA_61 M13 DQB1_30 AP1 DQB1_29/DQB_61 AD10
DQA1_30/DQA_62 CSA1B_0 CSA1b_0 (6) DQB1_30/DQB_62 CSB1B_0 CSB1b_0 (7)
40.2R 1uF_6.3V DQA1_31 A5 K16 R5693 C1459 DQB1_31 AP5 AC10
DQA1_31/DQA_63 CSA1B_1 40.2R 1uF_6.3V DQB1_31/DQB_63 CSB1B_1
MVREFDA L18 K21 CKEA0 (6) U10 CKEB0 (7)
B
MVREFSA L20 MVREFDA CKEA0 J20 MVREFDB Y12 CKEB0 AA11 B
MVREFSA CKEA1 CKEA1 (6) MVREFDB CKEB1 CKEB1 (7)
+MVDD MVREFSB AA12
R138 C149 R6081 243R MEM_CALRN0 L27 K26 MVREFSB N10
MEM_CALRN0 WEA0B WEA0b (6) (1) TESTEN WEB0B WEB0b (7)
100R 1uF_6.3V R6082 243R MEM_CALRN1 N12 L15 WEA1b (6) R5694 C5670 TP9 35mil AB11 WEB1b (7)
+MVDD R6083 243R MEM_CALRN2 AG12 MEM_CALRN1 WEA1B 100R 1uF_6.3V +VDDR3 WEB1B
MEM_CALRN2 +MVDD R1171 1K DNI
R6084 243R MEM_CALRP1 M12 H23 MAA0_8 R43 1K TESTEN AD28 T8 MAB0_8
R6085 243R MEM_CALRP0 M27 MEM_CALRP1 MAA0_8 J19 MAA1_8 TESTEN MAB0_8 W8 MAB1_8
GDDR5
GDDR5
R148 C1462 R6086 243R MEM_CALRP2 AH12 MEM_CALRP0 MAA1_8 CLKTESTA AK10 MAB1_8
40.2R 1uF_6.3V MEM_CALRP2 R5695 C1463 TP7 35mil CLKTESTB AL10 CLKTESTA AH11 R5800 10R R5801 49.9R
40.2R 1uF_6.3V TP8 35mil CLKTESTB DRAM_RST DRAM_RST (6,7)
R163 C5879
C7118 C7119 5.1K 120pF_50V
R149 C148 100nF_6.3V 100nF_6.3V
100R 1uF_6.3V R5696 C5671 DNI DNI
Broadway 100R 1uF_6.3V Broadway
R157 R156
51.1R 51.1R
DNI DNI
TP_BP3 MEM_CALRN0
TP_BP4 MEM_CALRP0
Route 50ohms
single-ended/100ohms
diff and keep short
A A

5
Title Doc No.
5 4 3 2 1
5 4 3 2 1
CH_A0 =U3 & U7004

U3 GDDR5 +MVDD U7004 GDDR5 +MVDD U4 GDDR5 +MVDD U7005 GDDR5 +MVDD
(5) DQA0_[31..0] (5) DQA1_[31..0]
(5) DQA0_[31..0] (5) DQA1_[31..0]
M2 B1 M2 B1 M2 B1 M2 B1
M4 DQ31 | DQ7 VDDQ-B1 B3 M4 DQ31 | DQ7 VDDQ-B1 B3 M4 DQ31 | DQ7 VDDQ-B1 B3 M4 DQ31 | DQ7 VDDQ-B1 B3
N2 DQ30 | DQ6 VDDQ-B3 B12 N2 DQ30 | DQ6 VDDQ-B3 B12 N2 DQ30 | DQ6 VDDQ-B3 B12 N2 DQ30 | DQ6 VDDQ-B3 B12
T2 DQ28 | DQ4 VDDQ-B14 D1 T2 DQ28 | DQ4 VDDQ-B14 D1 T2 DQ28 | DQ4 VDDQ-B14 D1 T2 DQ28 | DQ4 VDDQ-B14 D1
T4 DQ27 | DQ3 VDDQ-D1 D3 T4 DQ27 | DQ3 VDDQ-D1 D3 T4 DQ27 | DQ3 VDDQ-D1 D3 T4 DQ27 | DQ3 VDDQ-D1 D3
V2 DQ26 | DQ2 VDDQ-D3 D12 V2 DQ26 | DQ2 VDDQ-D3 D12 V2 DQ26 | DQ2 VDDQ-D3 D12 V2 DQ26 | DQ2 VDDQ-D3 D12
DQA0_2 M13 DQ24 | DQ0 VDDQ-D14 E5 DQA0_26 M13 DQ24 | DQ0 VDDQ-D14 E5 DQA1_18 M13 DQ24 | DQ0 VDDQ-D14 E5 DQA1_14 M13 DQ24 | DQ0 VDDQ-D14 E5
DQA0_1 M11 DQ23 | DQ15 VDDQ-E5 E10 DQA0_25 M11 DQ23 | DQ15 VDDQ-E5 E10 DQA1_21 M11 DQ23 | DQ15 VDDQ-E5 E10 DQA1_13 M11 DQ23 | DQ15 VDDQ-E5 E10
DQA0_0 N13 DQ22 | DQ14 VDDQ-E10 F1 DQA0_27 N13 DQ22 | DQ14 VDDQ-E10 F1 DQA1_17 N13 DQ22 | DQ14 VDDQ-E10 F1 DQA1_15 N13 DQ22 | DQ14 VDDQ-E10 F1
DQA0_7 N11 DQ21 | DQ13 VDDQ-F1 F3 DQA0_24 N11 DQ21 | DQ13 VDDQ-F1 F3 DQA1_22 N11 DQ21 | DQ13 VDDQ-F1 F3 DQA1_12 N11 DQ21 | DQ13 VDDQ-F1 F3
DQA0_4 T13 DQ20 | DQ12 VDDQ-F3 F12 DQA0_28 T13 DQ20 | DQ12 VDDQ-F3 F12 DQA1_19 T13 DQ20 | DQ12 VDDQ-F3 F12 DQA1_9 T13 DQ20 | DQ12 VDDQ-F3 F12
D
DQA0_3 T11 DQ19 | DQ11 VDDQ-F12 F14 DQA0_30 T11 DQ19 | DQ11 VDDQ-F12 F14 DQA1_23 T11 DQ19 | DQ11 VDDQ-F12 F14 DQA1_11 T11 DQ19 | DQ11 VDDQ-F12 F14 D
DQA0_6 V13 DQ18 | DQ10 VDDQ-F14 G2 DQA0_29 V13 DQ18 | DQ10 VDDQ-F14 G2 DQA1_16 V13 DQ18 | DQ10 VDDQ-F14 G2 DQA1_8 V13 DQ18 | DQ10 VDDQ-F14 G2
DQA0_5 V11 DQ17 | DQ9 VDDQ-G2 G13 DQA0_31 V11 DQ17 | DQ9 VDDQ-G2 G13 DQA1_20 V11 DQ17 | DQ9 VDDQ-G2 G13 DQA1_10 V11 DQ17 | DQ9 VDDQ-G2 G13
F13 DQ16 | DQ8 VDDQ-G13 H3 F13 DQ16 | DQ8 VDDQ-G13 H3 F13 DQ16 | DQ8 VDDQ-G13 H3 F13 DQ16 | DQ8 VDDQ-G13 H3
F11 DQ15 | DQ23 VDDQ-H3 H12 F11 DQ15 | DQ23 VDDQ-H3 H12 F11 DQ15 | DQ23 VDDQ-H3 H12 F11 DQ15 | DQ23 VDDQ-H3 H12
E13 DQ14 | DQ22 VDDQ-H12 K3 E13 DQ14 | DQ22 VDDQ-H12 K3 E13 DQ14 | DQ22 VDDQ-H12 K3 E13 DQ14 | DQ22 VDDQ-H12 K3
DQ13 | DQ21 VDDQ-K3 M=1 DQ13 | DQ21 VDDQ-K3 M=1 DQ13 | DQ21 VDDQ-K3 DQ13 | DQ21 VDDQ-K3
E11 K12 E11 K12 E11 K12 E11 K12
B13 DQ12 | DQ20 VDDQ-K12 L2
Mirror B13 DQ12 | DQ20 VDDQ-K12 L2
Mirror B13 DQ12 | DQ20 VDDQ-K12 L2 B13 DQ12 | DQ20 VDDQ-K12 L2
B11 DQ11 | DQ19 VDDQ-L2 L13 B11 DQ11 | DQ19 VDDQ-L2 L13 B11 DQ11 | DQ19 VDDQ-L2 L13 B11 DQ11 | DQ19 VDDQ-L2 L13
A13 DQ10 | DQ18 VDDQ-L13 M1 A13 DQ10 | DQ18 VDDQ-L13 M1 A13 DQ10 | DQ18 VDDQ-L13 M1 A13 DQ10 | DQ18 VDDQ-L13 M1
A11 DQ9 | DQ17 VDDQ-M1 M3 A11 DQ9 | DQ17 VDDQ-M1 M3 A11 DQ9 | DQ17 VDDQ-M1 M3 A11 DQ9 | DQ17 VDDQ-M1 M3
DQA0_22 F2 DQ8 | DQ16 VDDQ-M3 M12 DQA0_10 F2 DQ8 | DQ16 VDDQ-M3 M12 DQA1_6 F2 DQ8 | DQ16 VDDQ-M3 M12 DQA1_26 F2 DQ8 | DQ16 VDDQ-M3 M12
DQA0_21 F4 DQ7 | DQ31 VDDQ-M12 M14 DQA0_14 F4 DQ7 | DQ31 VDDQ-M12 M14 DQA1_5 F4 DQ7 | DQ31 VDDQ-M12 M14 DQA1_31 F4 DQ7 | DQ31 VDDQ-M12 M14
DQA0_23 E2 DQ6 | DQ30 VDDQ-M14 N5 DQA0_11 E2 DQ6 | DQ30 VDDQ-M14 N5 DQA1_7 E2 DQ6 | DQ30 VDDQ-M14 N5 DQA1_24 E2 DQ6 | DQ30 VDDQ-M14 N5
DQA0_20 E4 DQ5 | DQ29 VDDQ-N5 N10 DQA0_13 E4 DQ5 | DQ29 VDDQ-N5 N10 DQA1_4 E4 DQ5 | DQ29 VDDQ-N5 N10 DQA1_30 E4 DQ5 | DQ29 VDDQ-N5 N10
DQA0_17 B2 DQ4 | DQ28 VDDQ-N10 P1 DQA0_8 B2 DQ4 | DQ28 VDDQ-N10 P1 DQA1_1 B2 DQ4 | DQ28 VDDQ-N10 P1 DQA1_25 B2 DQ4 | DQ28 VDDQ-N10 P1
DQA0_19 B4 DQ3 | DQ27 VDDQ-P1 P3 DQA0_15 B4 DQ3 | DQ27 VDDQ-P1 P3 DQA1_3 B4 DQ3 | DQ27 VDDQ-P1 P3 DQA1_29 B4 DQ3 | DQ27 VDDQ-P1 P3
DQA0_16 A2 DQ2 | DQ26 VDDQ-P3 P12 DQA0_9 A2 DQ2 | DQ26 VDDQ-P3 P12 DQA1_0 A2 DQ2 | DQ26 VDDQ-P3 P12 DQA1_27 A2 DQ2 | DQ26 VDDQ-P3 P12
DQA0_18 A4 DQ1 | DQ25 VDDQ-P12 P14 DQA0_12 A4 DQ1 | DQ25 VDDQ-P12 P14 DQA1_2 A4 DQ1 | DQ25 VDDQ-P12 P14 DQA1_28 A4 DQ1 | DQ25 VDDQ-P12 P14
DQ0 | DQ24 VDDQ-P14 T1 DQ0 | DQ24 VDDQ-P14 T1 DQ0 | DQ24 VDDQ-P14 T1 DQ0 | DQ24 VDDQ-P14 T1
+MVDD VDDQ-T1 VDDQ-T1 VDDQ-T1 +MVDD VDDQ-T1
T3 T3 T3 T3
R1201 60.4R VDDQ-T3 T12 VDDQ-T3 T12 VDDQ-T3 T12 R1202 60.4R VDDQ-T3 T12
(5) CLKA0 VDDQ-T12 VDDQ-T12 VDDQ-T12 (5) CLKA1 VDDQ-T12
R1205 60.4R T14 T14 T14 R1206 60.4R T14
(5) CLKA0b VDDQ-T14 +MVDD VDDQ-T14 +MVDD VDDQ-T14 +MVDD (5) CLKA1b VDDQ-T14 +MVDD
(5) MAA0_[8..0] (5) MAA0_[8..0] (5) MAA1_[8..0] (5) MAA1_[8..0]
MAA0_8 J5 MAA0_8 J5 MAA1_8 J5 MAA1_8 J5
MAA0_7 K4 RFU/A12/NC C5 MAA0_0 K4 RFU/A12/NC C5 MAA1_0 K4 RFU/A12/NC C5 MAA1_7 K4 RFU/A12/NC C5
MAA0_6 K5 A7/A8 | A0/A10 VDD-C5 C10 MAA0_1 K5 A7/A8 | A0/A10 VDD-C5 C10 MAA1_1 K5 A7/A8 | A0/A10 VDD-C5 C10 MAA1_6 K5 A7/A8 | A0/A10 VDD-C5 C10
MAA0_5 K10 A6/A11 | A1/A9 VDD-C10 D11 MAA0_3 K10 A6/A11 | A1/A9 VDD-C10 D11 MAA1_3 K10 A6/A11 | A1/A9 VDD-C10 D11 MAA1_5 K10 A6/A11 | A1/A9 VDD-C10 D11
MAA0_4 K11 A5/BA1 | A3/BA3 VDD-D11 G1 MAA0_2 K11 A5/BA1 | A3/BA3 VDD-D11 G1 MAA1_2 K11 A5/BA1 | A3/BA3 VDD-D11 G1 MAA1_4 K11 A5/BA1 | A3/BA3 VDD-D11 G1
MAA0_3 H10 A4/BA2 | A2/BA0 VDD-G1 G4 MAA0_5 H10 A4/BA2 | A2/BA0 VDD-G1 G4 MAA1_5 H10 A4/BA2 | A2/BA0 VDD-G1 G4 MAA1_3 H10 A4/BA2 | A2/BA0 VDD-G1 G4
MAA0_2 H11 A3/BA3 | A5/BA1 VDD-G4 G11 MAA0_4 H11 A3/BA3 | A5/BA1 VDD-G4 G11 MAA1_4 H11 A3/BA3 | A5/BA1 VDD-G4 G11 MAA1_2 H11 A3/BA3 | A5/BA1 VDD-G4 G11
MAA0_1 H5 A2 /BA0 | A4/BA2 VDD-G11 G14 MAA0_6 H5 A2 /BA0 | A4/BA2 VDD-G11 G14 MAA1_6 H5 A2 /BA0 | A4/BA2 VDD-G11 G14 MAA1_1 H5 A2 /BA0 | A4/BA2 VDD-G11 G14
MAA0_0 H4 A1/A9 | A6/A11 VDD-G14 L1 MAA0_7 H4 A1/A9 | A6/A11 VDD-G14 L1 MAA1_7 H4 A1/A9 | A6/A11 VDD-G14 L1 MAA1_0 H4 A1/A9 | A6/A11 VDD-G14 L1
A0/A10 | A7/A8 VDD-L1 L4 A0/A10 | A7/A8 VDD-L1 L4 A0/A10 | A7/A8 VDD-L1 L4 A0/A10 | A7/A8 VDD-L1 L4
VDD-L4 L11 VDD-L4 L11 VDD-L4 L11 VDD-L4 L11
D4 VDD-L14 P11 D4 VDD-L14 P11 D4 VDD-L14 P11 D4 VDD-L14 P11
(5) WCKA0_1 WCK01 | WCK23 VDD-P11 (5) WCKA0_0 WCK01 | WCK23 VDD-P11 (5) WCKA1_0 WCK01 | WCK23 VDD-P11 (5) WCKA1_1 WCK01 | WCK23 VDD-P11
C D5 R5 D5 R5 D5 R5 D5 R5 C
(5) WCKA0b_1 WCK01# | WCK23# VDD-R5 (5) WCKA0b_0 WCK01# | WCK23# VDD-R5 (5) WCKA1b_0 WCK01# | WCK23# VDD-R5 (5) WCKA1b_1 WCK01# | WCK23# VDD-R5
R10 R10 R10 R10
P4 VDD-R10 P4 VDD-R10 P4 VDD-R10 P4 VDD-R10
(5) WCKA0_0 WCK23 | WCK01 (5) WCKA0_1 WCK23 | WCK01 (5) WCKA1_1 WCK23 | WCK01 (5) WCKA1_0 WCK23 | WCK01
P5 P5 P5 P5
(5) WCKA0b_0 WCK23# | WCK01# (5) WCKA0b_1 WCK23# | WCK01# (5) WCKA1b_1 WCK23# | WCK01# (5) WCKA1b_0 WCK23# | WCK01#
A1 A1 A1 A1
R2 VSSQ-A1 A3 R2 VSSQ-A1 A3 R2 VSSQ-A1 A3 R2 VSSQ-A1 A3
R13 EDC3 | EDC0 VSSQ-A3 A12 R13 EDC3 | EDC0 VSSQ-A3 A12 R13 EDC3 | EDC0 VSSQ-A3 A12 R13 EDC3 | EDC0 VSSQ-A3 A12
(5) EDCA0_0 EDC2 | EDC1 VSSQ-A12 (5) EDCA0_3 EDC2 | EDC1 VSSQ-A12 (5) EDCA1_2 EDC2 | EDC1 VSSQ-A12 (5) EDCA1_1 EDC2 | EDC1 VSSQ-A12
R7019 0R C13 A14 R7031 0R C13 A14 R7032 0R C13 A14 R7020 0R C13 A14
C2 EDC1 | EDC2 VSSQ-A14 C1 C2 EDC1 | EDC2 VSSQ-A14 C1 C2 EDC1 | EDC2 VSSQ-A14 C1 C2 EDC1 | EDC2 VSSQ-A14 C1
(5) EDCA0_2 EDC0 | EDC3 VSSQ-C1 (5) EDCA0_1 EDC0 | EDC3 VSSQ-C1 (5) EDCA1_0 EDC0 | EDC3 VSSQ-C1 (5) EDCA1_3 EDC0 | EDC3 VSSQ-C1
C3 C3 C3 C3
P2 VSSQ-C3 C4 P2 VSSQ-C3 C4 P2 VSSQ-C3 C4 P2 VSSQ-C3 C4
+MVDD DBI3# | DBI0# VSSQ-C4 +MVDD DBI3# | DBI0# VSSQ-C4 +MVDD DBI3# | DBI0# VSSQ-C4 +MVDD DBI3# | DBI0# VSSQ-C4
(5) DDBIA0_0 P13 C11 (5) DDBIA0_3 P13 C11 (5) DDBIA1_2 P13 C11 (5) DDBIA1_1 P13 C11
D13 DBI2 #| DBI1# VSSQ-C11 C12 D13 DBI2 #| DBI1# VSSQ-C11 C12 D13 DBI2 #| DBI1# VSSQ-C11 C12 D13 DBI2 #| DBI1# VSSQ-C11 C12
(5) DDBIA0_2 D2 C14 (5) DDBIA0_1 D2 C14 (5) DDBIA1_0 D2 C14 (5) DDBIA1_3 D2 C14
DBI0# | DBI3# VSSQ-C14 E1 DBI0# | DBI3# VSSQ-C14 E1 DBI0# | DBI3# VSSQ-C14 E1 DBI0# | DBI3# VSSQ-C14 E1
VSSQ-E1 E3 VSSQ-E1 E3 VSSQ-E1 E3 VSSQ-E1 E3
G3 VSSQ-E12 E14 G3 VSSQ-E12 E14 G3 VSSQ-E12 E14 G3 VSSQ-E12 E14
(5) RASA0b RAS# | CAS# VSSQ-E14 (5) CASA0b RAS# | CAS# VSSQ-E14 (5) CASA1b RAS# | CAS# VSSQ-E14 (5) RASA1b RAS# | CAS# VSSQ-E14
(5) CASA0b L3 F5 (5) RASA0b L3 F5 (5) RASA1b L3 F5 (5) CASA1b L3 F5
CAS# | RAS# VSSQ-F5 F10 CAS# | RAS# VSSQ-F5 F10 CAS# | RAS# VSSQ-F5 F10 CAS# | RAS# VSSQ-F5 F10
VSSQ-F10 H2 VSSQ-F10 H2 VSSQ-F10 H2 VSSQ-F10 H2
J3 VSSQ-H2 H13 J3 VSSQ-H2 H13 J3 VSSQ-H2 H13 J3 VSSQ-H2 H13
(5) CKEA0 CKE# VSSQ-H13 (5) CKEA0 CKE# VSSQ-H13 (5) CKEA1 CKE# VSSQ-H13 (5) CKEA1 CKE# VSSQ-H13
CLKA0b J11 K2 CLKA0b J11 K2 CLKA1b J11 K2 CLKA1b J11 K2
CLKA0 J12 CK# VSSQ-K2 K13 CLKA0 J12 CK# VSSQ-K2 K13 CLKA1 J12 CK# VSSQ-K2 K13 CLKA1 J12 CK# VSSQ-K2 K13
CK VSSQ-K13 M5 CK VSSQ-K13 M5 CK VSSQ-K13 M5 CK VSSQ-K13 M5
VSSQ-M5 M10 VSSQ-M5 M10 VSSQ-M5 M10 VSSQ-M5 M10
G12 VSSQ-M10 N1 G12 VSSQ-M10 N1 G12 VSSQ-M10 N1 G12 VSSQ-M10 N1
(5) CSA0b_0 CS# | WE# VSSQ-N1 (5) WEA0b CS# | WE# VSSQ-N1 (5) WEA1b CS# | WE# VSSQ-N1 (5) CSA1b_0 CS# | WE# VSSQ-N1
(5) WEA0b L12 N3 (5) CSA0b_0 L12 N3 (5) CSA1b_0 L12 N3 (5) WEA1b L12 N3
WE# | CS# VSSQ-N3 N12 WE# | CS# VSSQ-N3 N12 WE# | CS# VSSQ-N3 N12 WE# | CS# VSSQ-N3 N12
VSSQ-N12 N14 VSSQ-N12 N14 VSSQ-N12 N14 VSSQ-N12 N14
R1213 120R J13 VSSQ-N14 R1 R7035 120R J13 VSSQ-N14 R1 R7036 120R J13 VSSQ-N14 R1 R1214 120R J13 VSSQ-N14 R1
R1217 1K J10 ZQ VSSQ-R1 R3 R7039 1K J10 ZQ VSSQ-R1 R3 R7040 1K J10 ZQ VSSQ-R1 R3 R1218 1K J10 ZQ VSSQ-R1 R3
SEN VSSQ-R3 R4 SEN VSSQ-R3 R4 SEN VSSQ-R3 R4 SEN VSSQ-R3 R4
VSSQ-R4 R11 VSSQ-R4 R11 VSSQ-R4 R11 VSSQ-R4 R11
J2 VSSQ-R11 R12 J2 VSSQ-R11 R12 J2 VSSQ-R11 R12 J2 VSSQ-R11 R12
(5,7) DRAM_RST RESET# VSSQ-R12 (5,7) DRAM_RST RESET# VSSQ-R12 (5,7) DRAM_RST RESET# VSSQ-R12 (5,7) DRAM_RST RESET# VSSQ-R12
R1221 1K J1 R14 +MVDD R7043 1K J1 R14 +MVDD R7044 1K J1 R14 R1222 1K J1 R14
MF VSSQ-R14 V1 MF VSSQ-R14 V1 MF VSSQ-R14 V1 MF VSSQ-R14 V1
VSSQ-V1 V3 VSSQ-V1 V3 VSSQ-V1 V3 VSSQ-V1 V3
B VSSQ-V3 V12 VSSQ-V3 V12 VSSQ-V3 V12 VSSQ-V3 V12 B
A5 VSSQ-V14 A5 VSSQ-V14 A5 VSSQ-V14 A5 VSSQ-V14
V5 Vpp,NC V5 Vpp,NC V5 Vpp,NC V5 Vpp,NC
C1205 1uF_6.3V Vpp,NC1 B5 C7010 1uF_6.3V Vpp,NC1 B5 C7011 1uF_6.3V Vpp,NC1 B5 C7098 1uF_6.3V Vpp,NC1 B5
R1233 2.37K 1% VREFD1_A0 A10 VSS-B5 B10 R7051 2.37K 1% VREFD1_MA0 A10 VSS-B5 B10 R7052 2.37K 1% VREFD1_MA1 A10 VSS-B5 B10 R7082 2.37K 1% VREFD1_A1 A10 VSS-B5 B10
+MVDD VREFD1 VSS-B10 +MVDD VREFD1 VSS-B10 +MVDD VREFD1 VSS-B10 +MVDD VREFD1 VSS-B10
R1237 5.49K 1% V10 D10 R7055 5.49K 1% V10 D10 R7056 5.49K 1% V10 D10 R7083 5.49K 1% V10 D10
C1201 1uF_6.3V VREFD2 VSS-D10 G5 C7014 1uF_6.3V VREFD2 VSS-D10 G5 C7015 1uF_6.3V VREFD2 VSS-D10 G5 C7100 1uF_6.3V VREFD2 VSS-D10 G5
VSS-G5 G10 VSS-G5 G10 VSS-G5 G10 VSS-G5 G10
C1213 1uF_6.3V VSS-G10 H1 C7018 1uF_6.3V VSS-G10 H1 C7019 1uF_6.3V VSS-G10 H1 C1214 1uF_6.3V VSS-G10 H1
R7085 2.37K 1% VSS-H1 H14 R7059 2.37K 1% VSS-H1 H14 R7060 2.37K 1% VSS-H1 H14 R7087 2.37K 1% VSS-H1 H14
+MVDD VSS-H14 +MVDD VSS-H14 +MVDD VSS-H14 +MVDD VSS-H14
R7086 5.49K 1% VREFD2_A0 K1 R7063 5.49K 1% VREFD2_MA0 K1 R7064 5.49K 1% VREFD2_MA1 K1 R7091 5.49K 1% VREFD2_A1 K1
C1209 1uF_6.3V J14 VSS-K1 K14 C7022 1uF_6.3V J14 VSS-K1 K14 C7023 1uF_6.3V J14 VSS-K1 K14 C1210 1uF_6.3V J14 VSS-K1 K14
VREFC VSS-K14 L5 VREFC VSS-K14 L5 VREFC VSS-K14 L5 VREFC VSS-K14 L5
C7099 1uF_6.3V VSS-L5 L10 C7026 1uF_6.3V VSS-L5 L10 VSS-L5 L10 VSS-L5 L10
R7088 1% 2.37K 1% VSS-L10 P10 R7067 1% 2.37K 1% VSS-L10 P10 C7029 1uF_6.3V VSS-L10 P10 C1222 1uF_6.3V VSS-L10 P10
+MVDD VSS-P10 +MVDD VSS-P10 VSS-P10 VSS-P10
R1253 5.49K 1% VREFC_A0 J4 T5 R7070 5.49K 1% VREFC_MA0 J4 T5 +MVDD R7071 1% 2.37K 1% J4 T5 +MVDD R7089 1% 2.37K 1% J4 T5
C1217 1uF_6.3V ABI# VSS-T5 T10 C7030 1uF_6.3V ABI# VSS-T5 T10 R7074 5.49K 1% VREFC_MA1 ABI# VSS-T5 T10 R7090 5.49K 1% VREFC_A1 ABI# VSS-T5 T10
VSS-T10 VSS-T10 C7033 1uF_6.3V VSS-T10 C1218 1uF_6.3V VSS-T10
(5) ADBIA0 GDDR5 (5) ADBIA0 GDDR5 (5) ADBIA1 GDDR5 (5) ADBIA1 GDDR5
+MVDD +MVDD +MVDD +MVDD

C7034
C7035
C7036
C7037
C7038
C7039
C7040
C7041
C7042
C7043
C7044
C7045
C7046
C7047
C7048
C7073
C7055
C7070
C7095
C7056
C7057
C7071
C7072
C7082
C7083
C7058
C7084
C7074
C7089
C7075
C7076
C7090
C7049
C7059
C7091
C7050
C7096
C7060
C7061
C7077
C7078
C7097
C7079
C7062
C7085
C7063
C7064
C7086
C7092
C7051
C7087
C7093
C7088
C7065
C7066
C7067
C7068
C7094
C7069
C7052
C7080
C7053
C7054
C7081
100nF_6.3V
100nF_6.3V
100nF_6.3V
100nF_6.3V
100nF_6.3V
1uF_6.3V
1uF_6.3V
1uF_6.3V
1uF_6.3V
1uF_6.3V
100nF_6.3V
100nF_6.3V
100nF_6.3V
100nF_6.3V
100nF_6.3V
1uF_6.3V
1uF_6.3V
1uF_6.3V
1uF_6.3V
1uF_6.3V
100nF_6.3V
100nF_6.3V
100nF_6.3V
100nF_6.3V
100nF_6.3V
1uF_6.3V
1uF_6.3V
1uF_6.3V
1uF_6.3V
1uF_6.3V
100nF_6.3V
100nF_6.3V
100nF_6.3V
100nF_6.3V
100nF_6.3V
1uF_6.3V
1uF_6.3V
1uF_6.3V
1uF_6.3V
1uF_6.3V
10uF_4V
10uF_4V
10uF_4V
10uF_4V
10uF_4V
10uF_4V
10uF_4V
10uF_4V
10uF_4V
10uF_4V
10uF_4V
10uF_4V
10uF_4V
10uF_4V
10uF_4V
10uF_4V
22uF_2.5V
22uF_2.5V
22uF_2.5V
22uF_2.5V
22uF_2.5V
22uF_2.5V
22uF_2.5V
22uF_2.5V
A A
DRAM Scan pins CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
SSH [J2] - Scan shift © 2007 Advanced Micro Devices Advanced Micro Devices Inc.
SCK [G12] - Scan clock
SOUT [C2] - Scan output
SEN [J10] - Scan enable is strictly prohibited. Use of this schematic and design for any purpose Markham, Ontario
SOE# [J1] - Scan output enable other than evaluation requires a Board Technology License Agreement
5
Title Doc No.
5 4 3 2 1
5 4 3 2 1
U5 +MVDD U7006 GDDR5 +MVDD U6 GDDR5 +MVDD U7007 GDDR5 +MVDD

(5) DQB1_[31..0]
(5) DQB0_[31..0] (5) DQB1_[31..0]
M2 B1 M2 B1 M2 B1 M2 B1
M4 DQ31 | DQ7 VDDQ-B1 B3 M4 DQ31 | DQ7 VDDQ-B1 B3 M4 DQ31 | DQ7 VDDQ-B1 B3 M4 DQ31 | DQ7 VDDQ-B1 B3
(5) DQB0_[31..0] DQ30 | DQ6 VDDQ-B3 DQ30 | DQ6 VDDQ-B3 DQ30 | DQ6 VDDQ-B3 DQ30 | DQ6 VDDQ-B3
N2 B12 N2 B12 N2 B12 N2 B12
T2 DQ28 | DQ4 VDDQ-B14 D1 T2 DQ28 | DQ4 VDDQ-B14 D1 T2 DQ28 | DQ4 VDDQ-B14 D1 T2 DQ28 | DQ4 VDDQ-B14 D1
T4 DQ27 | DQ3 VDDQ-D1 D3 T4 DQ27 | DQ3 VDDQ-D1 D3 T4 DQ27 | DQ3 VDDQ-D1 D3 T4 DQ27 | DQ3 VDDQ-D1 D3
DQB0_2 M13 DQ24 | DQ0 VDDQ-D14 E5 DQB0_26 M13 DQ24 | DQ0 VDDQ-D14 E5 DQB1_19 M13 DQ24 | DQ0 VDDQ-D14 E5 DQB1_14 M13 DQ24 | DQ0 VDDQ-D14 E5
DQB0_7 M11 DQ23 | DQ15 VDDQ-E5 E10 DQB0_24 M11 DQ23 | DQ15 VDDQ-E5 E10 DQB1_23 M11 DQ23 | DQ15 VDDQ-E5 E10 DQB1_13 M11 DQ23 | DQ15 VDDQ-E5 E10
DQB0_3 N13 DQ22 | DQ14 VDDQ-E10 F1 DQB0_27 N13 DQ22 | DQ14 VDDQ-E10 F1 DQB1_16 N13 DQ22 | DQ14 VDDQ-E10 F1 DQB1_15 N13 DQ22 | DQ14 VDDQ-E10 F1
DQB0_4 N11 DQ21 | DQ13 VDDQ-F1 F3 DQB0_25 N11 DQ21 | DQ13 VDDQ-F1 F3 DQB1_21 N11 DQ21 | DQ13 VDDQ-F1 F3 DQB1_12 N11 DQ21 | DQ13 VDDQ-F1 F3
DQB0_0 T13 DQ20 | DQ12 VDDQ-F3 F12 DQB0_28 T13 DQ20 | DQ12 VDDQ-F3 F12 DQB1_17 T13 DQ20 | DQ12 VDDQ-F3 F12 DQB1_9 T13 DQ20 | DQ12 VDDQ-F3 F12
D
DQB0_5 T11 DQ19 | DQ11 VDDQ-F12 F14 DQB0_31 T11 DQ19 | DQ11 VDDQ-F12 F14 DQB1_20 T11 DQ19 | DQ11 VDDQ-F12 F14 DQB1_11 T11 DQ19 | DQ11 VDDQ-F12 F14 D
DQB0_1 V13 DQ18 | DQ10 VDDQ-F14 G2 DQB0_30 V13 DQ18 | DQ10 VDDQ-F14 G2 DQB1_18 V13 DQ18 | DQ10 VDDQ-F14 G2 DQB1_8 V13 DQ18 | DQ10 VDDQ-F14 G2
DQB0_6 V11 DQ17 | DQ9 VDDQ-G2 G13 DQB0_29 V11 DQ17 | DQ9 VDDQ-G2 G13 DQB1_22 V11 DQ17 | DQ9 VDDQ-G2 G13 DQB1_10 V11 DQ17 | DQ9 VDDQ-G2 G13
F13 DQ16 | DQ8 VDDQ-G13 H3 F13 DQ16 | DQ8 VDDQ-G13 H3 F13 DQ16 | DQ8 VDDQ-G13 H3 F13 DQ16 | DQ8 VDDQ-G13 H3
F11 DQ15 | DQ23 VDDQ-H3 H12 F11 DQ15 | DQ23 VDDQ-H3 H12 F11 DQ15 | DQ23 VDDQ-H3 H12 F11 DQ15 | DQ23 VDDQ-H3 H12
E13 DQ14 | DQ22 VDDQ-H12 K3 E13 DQ14 | DQ22 VDDQ-H12 K3 E13 DQ14 | DQ22 VDDQ-H12 K3 E13 DQ14 | DQ22 VDDQ-H12 K3
DQ13 | DQ21 VDDQ-K3 M=1 DQ13 | DQ21 VDDQ-K3 M=1 DQ13 | DQ21 VDDQ-K3 DQ13 | DQ21 VDDQ-K3
E11 K12 E11 K12 E11 K12 E11 K12
B13 DQ12 | DQ20 VDDQ-K12 L2
Mirror B13 DQ12 | DQ20 VDDQ-K12 L2
Mirror B13 DQ12 | DQ20 VDDQ-K12 L2 B13 DQ12 | DQ20 VDDQ-K12 L2
B11 DQ11 | DQ19 VDDQ-L2 L13 B11 DQ11 | DQ19 VDDQ-L2 L13 B11 DQ11 | DQ19 VDDQ-L2 L13 B11 DQ11 | DQ19 VDDQ-L2 L13
A13 DQ10 | DQ18 VDDQ-L13 M1 A13 DQ10 | DQ18 VDDQ-L13 M1 A13 DQ10 | DQ18 VDDQ-L13 M1 A13 DQ10 | DQ18 VDDQ-L13 M1
A11 DQ9 | DQ17 VDDQ-M1 M3 A11 DQ9 | DQ17 VDDQ-M1 M3 A11 DQ9 | DQ17 VDDQ-M1 M3 A11 DQ9 | DQ17 VDDQ-M1 M3
DQB0_21 F2 DQ8 | DQ16 VDDQ-M3 M12 DQB0_8 F2 DQ8 | DQ16 VDDQ-M3 M12 DQB1_6 F2 DQ8 | DQ16 VDDQ-M3 M12 DQB1_25 F2 DQ8 | DQ16 VDDQ-M3 M12
DQB0_20 F4 DQ7 | DQ31 VDDQ-M12 M14 DQB0_12 F4 DQ7 | DQ31 VDDQ-M12 M14 DQB1_5 F4 DQ7 | DQ31 VDDQ-M12 M14 DQB1_29 F4 DQ7 | DQ31 VDDQ-M12 M14
DQB0_22 E2 DQ6 | DQ30 VDDQ-M14 N5 DQB0_9 E2 DQ6 | DQ30 VDDQ-M14 N5 DQB1_7 E2 DQ6 | DQ30 VDDQ-M14 N5 DQB1_24 E2 DQ6 | DQ30 VDDQ-M14 N5
DQB0_19 E4 DQ5 | DQ29 VDDQ-N5 N10 DQB0_13 E4 DQ5 | DQ29 VDDQ-N5 N10 DQB1_4 E4 DQ5 | DQ29 VDDQ-N5 N10 DQB1_31 E4 DQ5 | DQ29 VDDQ-N5 N10
DQB0_23 B2 DQ4 | DQ28 VDDQ-N10 P1 DQB0_10 B2 DQ4 | DQ28 VDDQ-N10 P1 DQB1_1 B2 DQ4 | DQ28 VDDQ-N10 P1 DQB1_26 B2 DQ4 | DQ28 VDDQ-N10 P1
DQB0_18 B4 DQ3 | DQ27 VDDQ-P1 P3 DQB0_15 B4 DQ3 | DQ27 VDDQ-P1 P3 DQB1_3 B4 DQ3 | DQ27 VDDQ-P1 P3 DQB1_28 B4 DQ3 | DQ27 VDDQ-P1 P3
DQB0_16 A2 DQ2 | DQ26 VDDQ-P3 P12 DQB0_11 A2 DQ2 | DQ26 VDDQ-P3 P12 DQB1_0 A2 DQ2 | DQ26 VDDQ-P3 P12 DQB1_27 A2 DQ2 | DQ26 VDDQ-P3 P12
DQB0_17 A4 DQ1 | DQ25 VDDQ-P12 P14 DQB0_14 A4 DQ1 | DQ25 VDDQ-P12 P14 DQB1_2 A4 DQ1 | DQ25 VDDQ-P12 P14 DQB1_30 A4 DQ1 | DQ25 VDDQ-P12 P14
DQ0 | DQ24 VDDQ-P14 T1 DQ0 | DQ24 VDDQ-P14 T1 DQ0 | DQ24 VDDQ-P14 T1 DQ0 | DQ24 VDDQ-P14 T1
+MVDD VDDQ-T1 VDDQ-T1 VDDQ-T1 +MVDD VDDQ-T1
T3 T3 T3 T3
R1203 60.4R VDDQ-T3 T12 VDDQ-T3 T12 VDDQ-T3 T12 R1204 60.4R VDDQ-T3 T12
(5) CLKB0 VDDQ-T12 VDDQ-T12 VDDQ-T12 (5) CLKB1 VDDQ-T12
R1207 60.4R T14 T14 T14 R1208 60.4R T14
(5) CLKB0b VDDQ-T14 VDDQ-T14 VDDQ-T14 (5) CLKB1b VDDQ-T14 +MVDD
(5) MAB0_[8..0] +MVDD (5) MAB0_[8..0] +MVDD (5) MAB1_[8..0] +MVDD (5) MAB1_[8..0]
MAB0_8 J5 MAB0_8 J5 MAB1_8 J5 MAB1_8 J5
MAB0_7 K4 RFU/A12/NC C5 MAB0_0 K4 RFU/A12/NC C5 MAB1_0 K4 RFU/A12/NC C5 MAB1_7 K4 RFU/A12/NC C5
MAB0_6 K5 A7/A8 | A0/A10 VDD-C5 C10 MAB0_1 K5 A7/A8 | A0/A10 VDD-C5 C10 MAB1_1 K5 A7/A8 | A0/A10 VDD-C5 C10 MAB1_6 K5 A7/A8 | A0/A10 VDD-C5 C10
MAB0_5 K10 A6/A11 | A1/A9 VDD-C10 D11 MAB0_3 K10 A6/A11 | A1/A9 VDD-C10 D11 MAB1_3 K10 A6/A11 | A1/A9 VDD-C10 D11 MAB1_5 K10 A6/A11 | A1/A9 VDD-C10 D11
MAB0_4 K11 A5/BA1 | A3/BA3 VDD-D11 G1 MAB0_2 K11 A5/BA1 | A3/BA3 VDD-D11 G1 MAB1_2 K11 A5/BA1 | A3/BA3 VDD-D11 G1 MAB1_4 K11 A5/BA1 | A3/BA3 VDD-D11 G1
MAB0_3 H10 A4/BA2 | A2/BA0 VDD-G1 G4 MAB0_5 H10 A4/BA2 | A2/BA0 VDD-G1 G4 MAB1_5 H10 A4/BA2 | A2/BA0 VDD-G1 G4 MAB1_3 H10 A4/BA2 | A2/BA0 VDD-G1 G4
MAB0_2 H11 A3/BA3 | A5/BA1 VDD-G4 G11 MAB0_4 H11 A3/BA3 | A5/BA1 VDD-G4 G11 MAB1_4 H11 A3/BA3 | A5/BA1 VDD-G4 G11 MAB1_2 H11 A3/BA3 | A5/BA1 VDD-G4 G11
MAB0_1 H5 A2 /BA0 | A4/BA2 VDD-G11 G14 MAB0_6 H5 A2 /BA0 | A4/BA2 VDD-G11 G14 MAB1_6 H5 A2 /BA0 | A4/BA2 VDD-G11 G14 MAB1_1 H5 A2 /BA0 | A4/BA2 VDD-G11 G14
MAB0_0 H4 A1/A9 | A6/A11 VDD-G14 L1 MAB0_7 H4 A1/A9 | A6/A11 VDD-G14 L1 MAB1_7 H4 A1/A9 | A6/A11 VDD-G14 L1 MAB1_0 H4 A1/A9 | A6/A11 VDD-G14 L1
A0/A10 | A7/A8 VDD-L1 L4 A0/A10 | A7/A8 VDD-L1 L4 A0/A10 | A7/A8 VDD-L1 L4 A0/A10 | A7/A8 VDD-L1 L4
D4 VDD-L14 P11 D4 VDD-L14 P11 D4 VDD-L14 P11 D4 VDD-L14 P11
(5) WCKB0_1 WCK01 | WCK23 VDD-P11 (5) WCKB0_0 WCK01 | WCK23 VDD-P11 (5) WCKB1_0 WCK01 | WCK23 VDD-P11 (5) WCKB1_1 WCK01 | WCK23 VDD-P11
C D5 R5 D5 R5 D5 R5 D5 R5 C
(5) WCKB0b_1 WCK01# | WCK23# VDD-R5 (5) WCKB0b_0 WCK01# | WCK23# VDD-R5 (5) WCKB1b_0 WCK01# | WCK23# VDD-R5 (5) WCKB1b_1 WCK01# | WCK23# VDD-R5
R10 R10 R10 R10
P4 VDD-R10 P4 VDD-R10 P4 VDD-R10 P4 VDD-R10
(5) WCKB0_0 WCK23 | WCK01 (5) WCKB0_1 WCK23 | WCK01 (5) WCKB1_1 WCK23 | WCK01 (5) WCKB1_0 WCK23 | WCK01
P5 P5 P5 P5
(5) WCKB0b_0 WCK23# | WCK01# (5) WCKB0b_1 WCK23# | WCK01# (5) WCKB1b_1 WCK23# | WCK01# (5) WCKB1b_0 WCK23# | WCK01#
A1 A1 A1 A1
R2 VSSQ-A1 A3 R2 VSSQ-A1 A3 R2 VSSQ-A1 A3 R2 VSSQ-A1 A3
R13 EDC3 | EDC0 VSSQ-A3 A12 R13 EDC3 | EDC0 VSSQ-A3 A12 R13 EDC3 | EDC0 VSSQ-A3 A12 R13 EDC3 | EDC0 VSSQ-A3 A12
(5) EDCB0_0 EDC2 | EDC1 VSSQ-A12 (5) EDCB0_3 EDC2 | EDC1 VSSQ-A12 (5) EDCB1_2 EDC2 | EDC1 VSSQ-A12 (5) EDCB1_1 EDC2 | EDC1 VSSQ-A12
R7021 0R C13 A14 R7033 0R C13 A14 R7034 0R C13 A14 R7022 0R C13 A14
C2 EDC1 | EDC2 VSSQ-A14 C1 C2 EDC1 | EDC2 VSSQ-A14 C1 C2 EDC1 | EDC2 VSSQ-A14 C1 C2 EDC1 | EDC2 VSSQ-A14 C1
(5) EDCB0_2 EDC0 | EDC3 VSSQ-C1 (5) EDCB0_1 EDC0 | EDC3 VSSQ-C1 (5) EDCB1_0 EDC0 | EDC3 VSSQ-C1 (5) EDCB1_3 EDC0 | EDC3 VSSQ-C1
C3 C3 C3 C3
P2 VSSQ-C3 C4 P2 VSSQ-C3 C4 P2 VSSQ-C3 C4 P2 VSSQ-C3 C4
(5) DDBIB0_0 P13 C11 (5) DDBIB0_3 P13 C11 (5) DDBIB1_2 P13 C11 (5) DDBIB1_1 P13 C11
D13 DBI2 #| DBI1# VSSQ-C11 C12 D13 DBI2 #| DBI1# VSSQ-C11 C12 D13 DBI2 #| DBI1# VSSQ-C11 C12 D13 DBI2 #| DBI1# VSSQ-C11 C12
(5) DDBIB0_2 D2 C14 (5) DDBIB0_1 D2 C14 (5) DDBIB1_0 D2 C14 (5) DDBIB1_3 D2 C14
DBI0# | DBI3# VSSQ-C14 E1 DBI0# | DBI3# VSSQ-C14 E1 DBI0# | DBI3# VSSQ-C14 E1 DBI0# | DBI3# VSSQ-C14 E1
G3 VSSQ-E12 E14 G3 VSSQ-E12 E14 G3 VSSQ-E12 E14 G3 VSSQ-E12 E14
(5) RASB0b RAS# | CAS# VSSQ-E14 (5) CASB0b RAS# | CAS# VSSQ-E14 (5) CASB1b RAS# | CAS# VSSQ-E14 (5) RASB1b RAS# | CAS# VSSQ-E14
(5) CASB0b L3 F5 (5) RASB0b L3 F5 (5) RASB1b L3 F5 (5) CASB1b L3 F5
CAS# | RAS# VSSQ-F5 F10 CAS# | RAS# VSSQ-F5 F10 CAS# | RAS# VSSQ-F5 F10 CAS# | RAS# VSSQ-F5 F10
VSSQ-F10 H2 VSSQ-F10 H2 VSSQ-F10 H2 VSSQ-F10 H2
J3 VSSQ-H2 H13 J3 VSSQ-H2 H13 J3 VSSQ-H2 H13 J3 VSSQ-H2 H13
(5) CKEB0 CKE# VSSQ-H13 (5) CKEB0 CKE# VSSQ-H13 (5) CKEB1 CKE# VSSQ-H13 (5) CKEB1 CKE# VSSQ-H13
CLKB0b J11 K2 CLKB0b J11 K2 CLKB1b J11 K2 CLKB1b J11 K2
CLKB0 J12 CK# VSSQ-K2 K13 CLKB0 J12 CK# VSSQ-K2 K13 CLKB1 J12 CK# VSSQ-K2 K13 CLKB1 J12 CK# VSSQ-K2 K13
CK VSSQ-K13 M5 CK VSSQ-K13 M5 CK VSSQ-K13 M5 CK VSSQ-K13 M5
VSSQ-M5 M10 VSSQ-M5 M10 VSSQ-M5 M10 VSSQ-M5 M10
G12 VSSQ-M10 N1 G12 VSSQ-M10 N1 G12 VSSQ-M10 N1 G12 VSSQ-M10 N1
(5) CSB0b_0 CS# | WE# VSSQ-N1 (5) WEB0b CS# | WE# VSSQ-N1 (5) WEB1b CS# | WE# VSSQ-N1 (5) CSB1b_0 CS# | WE# VSSQ-N1
(5) WEB0b L12 N3 (5) CSB0b_0 L12 N3 (5) CSB1b_0 L12 N3 (5) WEB1b L12 N3
WE# | CS# VSSQ-N3 N12 WE# | CS# VSSQ-N3 N12 WE# | CS# VSSQ-N3 N12 WE# | CS# VSSQ-N3 N12
VSSQ-N12 N14 VSSQ-N12 N14 VSSQ-N12 N14 VSSQ-N12 N14
R1215 120R J13 VSSQ-N14 R1 R7037 120R J13 VSSQ-N14 R1 R7038 120R J13 VSSQ-N14 R1 R1216 120R J13 VSSQ-N14 R1
R1219 1K J10 ZQ VSSQ-R1 R3 R7041 1K J10 ZQ VSSQ-R1 R3 R7042 1K J10 ZQ VSSQ-R1 R3 R1220 1K J10 ZQ VSSQ-R1 R3
SEN VSSQ-R3 R4 SEN VSSQ-R3 R4 SEN VSSQ-R3 R4 SEN VSSQ-R3 R4
VSSQ-R4 R11 VSSQ-R4 R11 VSSQ-R4 R11 VSSQ-R4 R11
J2 VSSQ-R11 R12 J2 VSSQ-R11 R12 J2 VSSQ-R11 R12 J2 VSSQ-R11 R12
(5,6) DRAM_RST RESET# VSSQ-R12 (5,6) DRAM_RST RESET# VSSQ-R12 (5,6) DRAM_RST RESET# VSSQ-R12 (5,6) DRAM_RST RESET# VSSQ-R12
R1223 1K J1 R14 +MVDD R7045 1K J1 R14 +MVDD R7046 1K J1 R14 R1224 1K J1 R14
MF VSSQ-R14 V1 MF VSSQ-R14 V1 MF VSSQ-R14 V1 MF VSSQ-R14 V1
B VSSQ-V3 V12 VSSQ-V3 V12 VSSQ-V3 V12 VSSQ-V3 V12 B
A5 VSSQ-V14 A5 VSSQ-V14 A5 VSSQ-V14 A5 VSSQ-V14
V5 Vpp,NC V5 Vpp,NC V5 Vpp,NC V5 Vpp,NC
C1207 1uF_6.3V Vpp,NC1 B5 C7012 1uF_6.3V Vpp,NC1 B5 C7013 1uF_6.3V Vpp,NC1 B5 C1208 1uF_6.3V Vpp,NC1 B5
R7075 2.37K 1% VREFD1_B0 A10 VSS-B5 B10 R7053 2.37K 1% VREFD1_MB0 A10 VSS-B5 B10 R7054 2.37K 1% VREFD1_MB1 A10 VSS-B5 B10 R7077 2.37K 1% VREFD1_B1 A10 VSS-B5 B10
+MVDD VREFD1 VSS-B10 +MVDD VREFD1 VSS-B10 +MVDD VREFD1 VSS-B10 +MVDD VREFD1 VSS-B10
R1239 5.49K 1% V10 D10 R7057 5.49K 1% V10 D10 R7058 5.49K 1% V10 D10 R7079 5.49K 1% V10 D10
C1203 1uF_6.3V VREFD2 VSS-D10 G5 C7016 1uF_6.3V VREFD2 VSS-D10 G5 C7017 1uF_6.3V VREFD2 VSS-D10 G5 C7101 1uF_6.3V VREFD2 VSS-D10 G5
VSS-G5 G10 VSS-G5 G10 VSS-G5 G10 VSS-G5 G10
C1215 1uF_6.3V VSS-G10 H1 C7020 1uF_6.3V VSS-G10 H1 C7021 1uF_6.3V VSS-G10 H1 C1216 1uF_6.3V VSS-G10 H1
R7076 2.37K 1% VSS-H1 H14 R7061 2.37K 1% VSS-H1 H14 R7062 2.37K 1% VSS-H1 H14 R7081 2.37K 1% VSS-H1 H14
+MVDD VSS-H14 +MVDD VSS-H14 +MVDD VSS-H14 +MVDD VSS-H14
R7078 5.49K 1% VREFD2_B0 K1 R7065 5.49K 1% VREFD2_MB0 K1 R7066 5.49K 1% VREFD2_MB1 K1 R1248 5.49K 1% VREFD2_B1 K1
C1211 1uF_6.3V J14 VSS-K1 K14 C7024 1uF_6.3V J14 VSS-K1 K14 C7025 1uF_6.3V J14 VSS-K1 K14 C1212 1uF_6.3V J14 VSS-K1 K14
VREFC VSS-K14 L5 VREFC VSS-K14 L5 VREFC VSS-K14 L5 VREFC VSS-K14 L5
C1223 1uF_6.3V VSS-L5 L10 C7027 1uF_6.3V VSS-L5 L10 C7028 1uF_6.3V VSS-L5 L10 C1224 1uF_6.3V VSS-L5 L10
R1251 1% 2.37K 1% VSS-L10 P10 R7068 1% 2.37K 1% VSS-L10 P10 R7069 2.37K 1% VSS-L10 P10 R1252 2.37K 1% VSS-L10 P10
+MVDD VSS-P10 +MVDD VSS-P10 +MVDD VSS-P10 +MVDD VSS-P10
R1255 5.49K 1% VREFC_B0 J4 T5 R7072 5.49K 1% VREFC_MB0 J4 T5 R7073 5.49K 1% VREFC_MB1 J4 T5 R1256 5.49K 1% VREFC_B1 J4 T5
C1219 1uF_6.3V ABI# VSS-T5 T10 C7031 1uF_6.3V ABI# VSS-T5 T10 C7032 1uF_6.3V ABI# VSS-T5 T10 C1220 1uF_6.3V ABI# VSS-T5 T10
VSS-T10 VSS-T10 VSS-T10 VSS-T10
(5) ADBIB0 (5) ADBIB1 (5) ADBIB1
(5) ADBIB0 GDDR5 GDDR5 GDDR5 GDDR5
+MVDD +MVDD +MVDD +MVDD

C527
C528
C529
C530
C531
C6077
C6061
C6062
C6078
C6079
C6080
C6081
C6082
C6131
C6132
C6133
C6083
C6084
C6085
C6086
C6087
C6088
C6089
C6090
C6091
C6092
C6093
C6094
C6095
C6122
C6123
C6124
C6096
C6097
C6098
C6099
C6100
C6101
C6102
C6103
C6104
C6105
C6106
C6107
C6108
C6125
C6126
C6127
C6109
C6110
C6111
C6112
C6113
C6114
C6115
C6116
C6117
C6118
C6119
C6120
C6121
C6128
C6129
C6130
100nF_6.3V
100nF_6.3V
100nF_6.3V
100nF_6.3V
100nF_6.3V
1uF_6.3V
1uF_6.3V
1uF_6.3V
1uF_6.3V
1uF_6.3V
100nF_6.3V
100nF_6.3V
100nF_6.3V
100nF_6.3V
100nF_6.3V
1uF_6.3V
1uF_6.3V
1uF_6.3V
1uF_6.3V
1uF_6.3V
100nF_6.3V
100nF_6.3V
100nF_6.3V
100nF_6.3V
100nF_6.3V
1uF_6.3V
1uF_6.3V
1uF_6.3V
1uF_6.3V
1uF_6.3V
100nF_6.3V
100nF_6.3V
100nF_6.3V
100nF_6.3V
100nF_6.3V
1uF_6.3V
1uF_6.3V
1uF_6.3V
1uF_6.3V
1uF_6.3V
10uF_4V
10uF_4V
10uF_4V
10uF_4V
10uF_4V
10uF_4V
10uF_4V
10uF_4V
10uF_4V
10uF_4V
10uF_4V
10uF_4V
10uF_4V
10uF_4V
10uF_4V
10uF_4V
22uF_2.5V
22uF_2.5V
22uF_2.5V
22uF_2.5V
22uF_2.5V
22uF_2.5V
22uF_2.5V
22uF_2.5V
A A

DRAM Scan pins This AMD Board schematic and design is the exclusive property of AMD,
SSH [J2] - Scan shift
SCK [G12] - Scan clock is strictly prohibited. Use of this schematic and design for any purpose Markham, Ontario
SOUT [C2] - Scan output other than evaluation requires a Board Technology License Agreement
SEN [J10] - Scan enable with AMD. AMD makes no representations or warranties of any kind
SOE# [J1] - Scan output enable 5
Title Doc No.
5 4 3 2 1
5 4 3 2 1
+3VRUN +3VRUN +3VRUN

PLACE CAPS ON THIS PAGE AS CLOSE J1A
+PWR_SRC E1 E2
TO CONNECTOR AS POSSIBLE E3 PWR_SRC_E1 PWR_SRC_E2 E4 R7117 C5978
C5976 C5977 C5979 GND_E3 Part 1 of 4 GND_E4 R6095 100K 100nF_6.3V
5
100nF_50V 100nF_50V 1nF 1 2 R6096 0R 100K +
3 5V_1 PRSNT_R#_2 4 1
5V_3 WAKE#_4 (10) CTFb
5 6 4
5V_5 PWR_GOOD_6 PWRGOOD (9) RUNPWROK (9)
+VDDR3 +VDDR3 7 8 R6098 0R 2
9 5V_7 PWR_EN_8 10
+5VRUN 5V_9 RSVD_10
11 12 - U52
3
R6091 R6092 C5980 C5981 13 GND_11 RSVD_12 14 NC7SZ08P5X_NL
100K 100K 100nF_6.3V 15 GND_13 RSVD_14 16
1uF_6.3V
DNI 17 GND_15 RSVD_16 18 PWR_LEVEL R6089 0R R7109 0R
(2,9) GPIO0 GND_17 PWR_LEVEL_18 GPIO5_AC_BATT (2) CTFb (10)
R6099 0R PEX_STD_SW# 19 20 TH_OVERT#
(2,9) GPIO1 PEX_STD_SW#_19 TH_OVERT#_20 MB_THERMb (9)
R6101 0R DNI VGA_DISABLE# 21 22 TH_ALERT# R6100 0R DNI
VGA_DISABLE#_21 TH_ALERT#_22 GPIO17_THERMAL_INT (2,9)
6
3
FPVCC_MB 23 24 TH_PWM
D PNL_PWR_EN_23 TH_PWM_24 TH_PWM (9) D
Q5536A Q5536B BL_ENA 25 26 MB_GPIO0
PNL_BL_EN_25 GPIO0_26 MB_GPIO0 (2)
BL_BRIGHT_MB 27 28 MB_GPIO1
PNL_PWM_27 GPIO1_28 MB_GPIO1 (2)
2 5 29 30 MB_GPIO2 R6130 R6131 R6132
HDMI_CEC_29 GPIO2_30 MB_GPIO2 (2) 100K
2N7002 2N7002 DVI_HPD 31 32 SMB_DAT 2.61K 100K 100K
33 DVI_HPD_31 SMB_DAT_32 34 SMB_CLK R1130 DNI DNI
(2) DDC3DATA
1
4
35 LVDS_DDC_DAT_33 SMB_CLK_34 36
(2) DDC3CLK LVDS_DDC_CLK_35 GND_36
37 38
39 GND_37 OEM_38 40 +VDDR3 +VDDR3 +VDDR3 +VDDR3
R6225 R6226 41 OEM_39 OEM_40 42
4.7K 4.7K 43 OEM_41 OEM_42 44
45 OEM_43 OEM_44 46
47 OEM_45 GND_46 48 PCIE_RXN15
R6207 10K DNI PCIE_TXN15 49 GND_47 PEX_TX15#_48 50 PCIE_RXP15
(2,9) GPIO9 +VDDR3 PEX_RX15#_49 PEX_TX15_50
PCIE_TXP15 51 52
PEX_RX15_51 GND_52
3
53 54 PCIE_RXN14
Q5537 PCIE_TXN14 55 GND_53 PEX_TX14#_54 56 PCIE_RXP14
2N7002E PCIE_TXP14 57 PEX_RX14#_55 PEX_TX14_56 58
DNI 1 59 PEX_RX14_57 GND_58 60 PCIE_RXN13
PCIE_TXN13 61 GND_59 PEX_TX13#_60 62 PCIE_RXP13
PCIE_TXP13 63 PEX_RX13#_61 PEX_TX13_62 64
2
65 PEX_RX13_63 GND_64 66 PCIE_RXN12 R6103 0R

PCIE_TXP12 69 PEX_RX12#_67 PEX_TX12_68 70 BL_ENA R6104 0R DNI
PEX_RX12_69 GND_70 BLON_PWM (2)
71 72 PCIE_RXN11
STRAP OPTIONS FROM MOTEHRBOARD DNI PCIE_TXN11 73 GND_71 PEX_TX11#_72 74 PCIE_RXP11 R6105 0R
PEX_RX11#_73 PEX_TX11_74 GPIO7_BLON (2)
PCIE_TXP11 75 76
77 PEX_RX11_75 GND_76 78 PCIE_RXN10
PEX_RX10#_79 PEX_TX10_80 The circuit is an option to prevent the leakage from LCD
PCIE_TXP10 81 82
83 PEX_RX10_81 GND_82 84 PCIE_RXN9 U5512
PCIE_TXN9 85 GND_83 PEX_TX9#_84 86 PCIE_RXP9 BL_BRIGHT_MB 6 2 BL_BRIGHT
PCIE_TXP9 87 PEX_RX9#_85 PEX_TX9_86 88 FPVCC_MB 3 1Y 1A 5 FPVCC
89 PEX_RX9_87 GND_88 90 PCIE_RXN8 2Y 2A
PCIE_TXN8 91 GND_89 PEX_TX8#_90 92 PCIE_RXP8 +3VRUN 8 1 R6106 0R
PEX_RX8#_91 PEX_TX8_92 PWRGOOD (9)
PCIE_TXP8 93 94 R6107 4 VCC 1OE 7
95 PEX_RX8_93 GND_94 96 PCIE_RXN7 10K GND 2OE
PCIE_TXN7 97 GND_95 PEX_TX7#_96 98 PCIE_RXP7 C5990 C5991
PEX_RX7#_97 PEX_TX7_98 74LVC2G126
C PCIE_TXP7 99 100 100nF_6.3V 100nF_6.3V C
PCIE_TXP6 105 PEX_RX6#_103 PEX_TX6_104 106
PCIE_REFCLKP PCIE_TXN5 109 GND_107 PEX_TX5#_108 110 PCIE_RXP5
(1) PCIE_REFCLKP PEX_RX5#_109 PEX_TX5_110
PCIE_REFCLKN PCIE_TXP5 111 112
(1) PCIE_REFCLKN PEX_RX5_111 GND_112
113 114 PCIE_RXN4 BL_BRIGHT_MB R6108 0R DNI BL_BRIGHT
PCIE_TXP4 117 PEX_RX4#_115 PEX_TX4_116 118 FPVCC_MB R6109 0R DNI FPVCC
PCIE_RXP[15..0] 119 PEX_RX4_117 GND_118 120 PCIE_RXN3
(1) PCIE_RXP[15..0] GND_119 PEX_TX3#_120
PCIE_TXN3 121 122 PCIE_RXP3
PCIE_RXN[15..0] PCIE_TXP3 123 PEX_RX3#_121 PEX_TX3_122 124
(1) PCIE_RXN[15..0] PEX_RX3_123 GND_124
125
PCIE_TXP[15..0] GND_125
(1) PCIE_TXP[15..0]
133
Mechanical Key 134
PCIE_TXN[15..0] PCIE_TXN2 135 GND_133 GND_134 136 PCIE_RXN2
(1) PCIE_TXN[15..0] PEX_RX2#_135 PEX_TX2#_136
PCIE_TXP2 137 138 PCIE_RXP2
139 PEX_RX2_137 PEX_TX2_138 140
PCIE_TXN1 141 GND_139 GND_140 142 PCIE_RXN1 +VDDR3
PCIE_TXP1 143 PEX_RX1#_141 PEX_TX1#_142 144 PCIE_RXP1
145 PEX_RX1_143 PEX_TX1_144 146
PCIE_TXN0 147 GND_145 GND_146 148 PCIE_RXN0 R6114
PCIE_TXP0 149 PEX_RX0#_147 PEX_TX0#_148 150 PCIE_RXP0 10K
151 PEX_RX0_149 PEX_TX0_150 152 DNI
PCIE_REFCLKN 153 GND_151 GND_152 154 R6113 0R
PEX_REFCLK#_153 CLK_REQ#_154 GPIO23_CLKREQb (2)
PCIE_REFCLKP 155 156 DNI
PEX_REFCLK_155 PEX_RST#_156 PCIE_RST# (1)
TXOUT_L0- 157 158
(2) TXOUT_L0- GND_157 VGA_DDC_DAT_158
TXOUT_L0+ 159 160 R6115
(2) TXOUT_L0+ RSVD_159 VGA_DDC_CLK_160
TXOUT_L1- 161 162 10K
(2) TXOUT_L1- RSVD_161 VGA_VSYC_162 VSYNC_DAC2 (2,9)
TXOUT_L1+ 163 164
(2) TXOUT_L1+ RSVD_163 VGA_HSYC_164 HSYNC_DAC2 (2,9)
TXOUT_L2- 165 166
(2) TXOUT_L2- RSVD_165 GND_166
TXOUT_L2+ 167 168 VGA_RED
(2) TXOUT_L2+ RSVD_167 VGA_RED_168 VGA_RED (2)
TXOUT_L3- TXCLK_U- 169 170 VGA_GRN
(2) TXOUT_L3- LVDS_UCLK#_169 VGA_GREEN_170 VGA_GRN (2) DDC5CLK (2)
TXOUT_L3+ TXCLK_U+ 171 172 VGA_BLU
(2) TXOUT_L3+ LVDS_UCLK_171 VGA_BLUE_172 VGA_BLU (2) DDC5DATA (2)
TXCLK_L- 173 174
(2) TXCLK_L- GND_173 GND_174
TXCLK_L+ TXOUT_U3- 175 176 TXCLK_L-
(2) TXCLK_L+ LVDS_UTX3#_175 LVDS_LCLK#_176
TXOUT_U3+ 177 178 TXCLK_L+ R6121 R6122
B
TXOUT_U0- 179 LVDS_UTX3_177 LVDS_LCLK_178 180 4.7K 4.7K B
(2) TXOUT_U0- GND_179 GND_180
TXOUT_U0+ TXOUT_U2- 181 182 TXOUT_L3-
(2) TXOUT_U0+ LVDS_UTX2#_181 LVDS_LTX3#_182
TXOUT_U1- TXOUT_U2+ 183 184 TXOUT_L3+
(2) TXOUT_U1- LVDS_UTX2_183 LVDS_LTX3_184
TXOUT_U1+ 185 186
(2) TXOUT_U1+ GND_185 GND_186 +VDDR3
TXOUT_U2- TXOUT_U1- 187 188 TXOUT_L2-
(2) TXOUT_U2- LVDS_UTX1#_187 LVDS_LTX2#_188
TXOUT_U2+ TXOUT_U1+ 189 190 TXOUT_L2+
(2) TXOUT_U2+ LVDS_UTX1_189 LVDS_LTX2_190
TXOUT_U3- 191 192
(2) TXOUT_U3- GND_191 GND_192
TXOUT_U3+ TXOUT_U0- 193 194 TXOUT_L1-
(2) TXOUT_U3+ LVDS_UTX0#_193 LVDS_LTX1#_194
TXCLK_U- TXOUT_U0+ 195 196 TXOUT_L1+
(2) TXCLK_U- LVDS_UTX0_195 LVDS_LTX1_196
TXCLK_U+ 197 198
(2) TXCLK_U+ GND_197 GND_198
199 200 TXOUT_L0-
(2) TX5M_DPB0N DP_C_L0#_199 LVDS_LTX0#_200
201 202 TXOUT_L0+
(2) TX5P_DPB0P DP_C_L0_201 LVDS_LTX0_202
203 204 +VDDR3 +VDDR3
205 GND_203 GND_204 206
(2) TX4M_DPB1N DP_C_L1#_205 DP_D_L0#_206
FPVCC 207 208
(2,4) FPVCC (2) TX4P_DPB1P DP_C_L1_207 DP_D_L0_208
209 210 R526 R6127
GND_209 GND_210
1
211 212 100K DNI 10K
(2) TX3M_DPB2N DP_C_L2#_211 DP_D_L1#_212
213 214 Q62 DNI
(2) TX3P_DPB2P DP_C_L2_213 DP_D_L1_214
215 216 SMB_CLK 3 2 R6222 0R
GND_215 GND_216 GPIO4_SMBCLK (2)
217 218 DNI
(2) TXCBM_DPB3N DP_C_L3#_217 DP_D_L2#_218
219 220 BSH111
(2) TXCBP_DPB3P DP_C_L3_219 DP_D_L2_220
221 222
223 GND_221 GND_222 224 R7122 0R DNI
(2) DDCDATA_AUX2N DP_C_AUX#_223 DP_D_L3#_224
225 226
(2) DDCCLK_AUX2P DP_C_AUX_225 DP_D_L3_226
227 228 R128 0R
RSVD_227 GND_228 SMBCLK (9)
DP_A_HPD 229 230
(2) HPD1 RSVD_229 DP_D_AUX#_230
231 232
233 RSVD_231 DP_D_AUX_232 234 DP_C_HPD J1C J1D +VDDR3 +VDDR3
R6116 235 RSVD_233 DP_C_HPD_234 236
RSVD_235 DP_D_HPD_236 Part 3 of 4 Part 4 of 4
100K 237 238
239 RSVD_237 RSVD_238 240 R527 R6128
RSVD_239 RSVD_240
1
241 242 100K DNI 10K
243 RSVD_241 RSVD_242 244 Q63 DNI
RSVD_243 GND_244
G10
245 246 SMB_DAT 3 2 R6224 0R
G1
G2
G3
G4
G5
G6
G7
G8
G9
RSVD_245 DP_B_L0#_246 GPIO3_SMBDATA (2)
(2) GPIO14_HPD2 DP_C_HPD 247 248 BSH111 DNI
249 RSVD_247 DP_B_L0_248 250
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
251 RSVD_249 GND_250 252
R6117 253 GND_251 DP_B_L1#_252 254 614NOPN180 614NOPN180 R7123 0R DNI
A A
(2) TX2M_DPA0N DP_A_L0#_253 DP_B_L1_254
100K 255 256
(2) TX2P_DPA0P DP_A_L0_255 GND_256
257 258 R129 0R
GND_257 DP_B_L2#_258 SMBDATA (9)
259 260
(2) TX1M_DPA1N DP_A_L1#_259 DP_B_L2_260
261 262
(2) TX1P_DPA1P DP_A_L1_261 GND_262
263 264
DVI_HPD 265 GND_263 DP_B_L3#_264 266 J1B
(2) GPIO18_HPD3 (2) TX0M_DPA2N DP_A_L2#_265 DP_B_L3_266
267 268 Part 2 of 4 CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
(2) TX0P_DPA2P DP_A_L2_267 GND_268 Advanced Micro Devices Inc.
269 270 MTG1 © 2007 Advanced Micro Devices
R6123 271 GND_269 DP_B_AUX#_270 272 MTG2 MTG1 This AMD Board schematic and design is the exclusive property of AMD,
(2) TXCAM_DPA3N DP_A_L3#_271 DP_B_AUX_272 MTG2 and is provided only to entities under a non-disclosure agreement 1 Commerce Valley Drive East
100K 273 274 MTG3 with AMD for evaluation purposes. Further distribution or disclosure
(2) TXCAP_DPA3P DP_A_L3_273 DP_B_HPD_274 +3VRUN MTG3
275 276 DP_A_HPD MTG4 is strictly prohibited. Use of this schematic and design for any purpose Markham, Ontario
277 GND_275 DP_A_HPD_276 278 MTG4 other than evaluation requires a Board Technology License Agreement
(2) DDCDATA_AUX1N DP_A_AUX#_277 3V3_278 with AMD. AMD makes no representations or warranties of any kind
279 280 Date: Tuesday, February 16, 2010 Rev
(2) DDCCLK_AUX1P DP_A_AUX_279 3V3_280 regarding this schematic and design, including, not limited to, 5
R6133 0R 281 C6016 C6017 C6018 any implied warranty of merchantibility or fitness for a particular
PRSNT_L#_281 10uF_.095 1uF_6.3V 1uF_6.3V purpose, and disclaims responsibility forany consequences resulting Sheet 8 of 17
Title Doc No.
5 4 3 2 1
5 4 3 2 1
EXTERNAL THERMAL SENSOR PIN STRAPS CONFIGURATION STRAPS

+VDDR3
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
+3VRUN
(2,8) GPIO0 GPIO0 R6134 10K THEY MUST NOT CONFLICT DURING RESET
GPU I2C option
(2,8) GPIO1 GPIO1 R6135 10K
R125 0R DNI C326 100nF_6.3V STRAPS PIN DESCRIPTION OF DEFAULT SETTINGS Default Setting
(2) DDC6CLK
(2) GPIO2 GPIO2 R6136 10K
R126 0R DNI
(2) DDC6DATA
TX_PWRS_ENB GPIO0 Transmitter Power Savings Enable GPIO0 and GPIO1
U14 C329 2.2nF_50V GPIO9 R6138 10K DNI 0: 50% Tx output swing pulls ups need to 1
(2,8) GPIO9 1: Full Tx output swing
8 1 be stuffed with
(8) SMBCLK SCLK VDD Q5536 if system
7 2 (2) GPIO11 GPIO11 R6139 10K TX_DEEMPH_EN GPIO1 PCIE Transmitter De-emphasis Enable board is to control 1
D (8) SMBDATA SDATA D+ GPU_DPLUS (2) 0: Tx de-emphasis disabled D
the PCIE swing
6 3 GPIO12 R6140 10K DNI 1: Tx de-emphasis enabled
ALERT D- GPU_DMINUS (2) (2) GPIO12
5 4 R220 0R DNI (2) GPIO13 GPIO13 R6141 10K BIF_GEN2_EN_A GPIO2 PCIE Gen2 Enable 1
GND THERM MB_THERMB (8) 0: Advertises the PCIE device as 2.5GT/s capable at power-on
R221 0R DNI
EMC1402-1-ACZL R130 0R GPIO22 R6147 10K 1: Advertises the PCIE device as 5.0GT/s capable at power-on
(2) GPIO22
R131 0R DNI
GPIO17_THERMAL_INT (2,8)
BIF_VGA DIS GPIO9 VGA Control GPIO9 pull up needs 0
R132 0R DNI V1SYNC R6142 10K DNI 0: VGA controller capacity enabled to be stuffed with
TH_PWM (8) (2) VSYNC_DAC1 1: VGA controller capacity disabled (for multi-GPU)
R133 0R DNI Q5537 if system
(2) TS_FDO
H1SYNC R6143 10K board is to control
(2) HSYNC_DAC1
the VGA capacity
V2SYNC R6145 10K

(2,8) VSYNC_DAC2
ROMIDCFG[2:0] GPIO[13:11] Serial ROM type or Memory Aperture Size Select 101
If GPIO22 = 0, defines memory aperture size
H2SYNC R6146 10K DNI If GPIO22 = 1, defines ROM type
(2,8) HSYNC_DAC2 100 - 512Kbit M25P05A (ST)
101 - 1Mbit M25P10A (ST)
(2,10) GPIO21_BB_EN GPIO21_BB_EN R6148 10K DNI
101 - 2Mbit M25P20 (ST)
101 - 4Mbit M25P40 (ST)
(2) GPIO8 GPIO8 R6137 10K DNI 101 - 8Mbit M25P80 (ST)
100 - 512Kbit Pm25LV512 (Chingis)
101 - 1Mbit Pm25LV010 (Chingis)
MEM_ID0 R6144 10K DNI BIOS_ROM_EN GPIO22 Enable external BIOS ROM device 1
(2) MEM_ID0 0: Disabled
MEM_ID1 R1235 10K DNI 1: Enabled
(2) MEM_ID1
MEM_ID2 R1236 10K DNI AUD[1] HSYNC 00 - No audio function 10
(2) MEM_ID2 01 - Audio for DP only
AUD[0] VSYNC
LDO Vin = +1.8V +/-5% Vout = +1.0V +/-2% Iout = 1.7A RMS MAX 10 - Audio for DP and HDMI if dongle is detected
11 - Audio for both DP and HDMI
HDMI must only be enabled on systems that are legally entitled. It is the
PCB: 50 to 70mm sq. copper area for cooling responsibility of the system designer to ensure that the system is entitled to
support this feature.
VIP_DEVICE_STRAP_DIS V2SYNC VIP Device Strap Enable 0

0: Slave VIP host port devices present
C 1: No slave VIP host port devices reporting presence C
+1.8V_REG
MR858 1R_1210 +5VRUN
R858 0.50R SMS_EN_HARD H2SYNC Reserved 0
GPIO21_BB_EN GPIO21_BBEN Reserved
Overlap MR859 1R_1210 +1.0V_REG +1.0V_REG BIF_CLK_PM_EN GPIO8 Reserved
R859 0.50R
footprints
Use 0.5R TP850 R853 MEM_ID2 GENERICC Optional memory ID straps XXX
10K MEM_ID1 GENERICB
1/2W <=5% R1 R855 C855 C852 C851 C854 MEM_ID0 GENERICA
U851 2.67K 33pF_50V 10uF_X6S 10uF_X6S 100nF_6.3V
PWRGOOD 1 8
(8) PWRGOOD LDO_EN 2 POK GND#8 7 LDO_FB
LDO_VIN 3 EN FB 6
4 VIN VOUT 5 R856 0R
CNTL REFIN 9 DNI
C856 GND#9 R2 R854 CLOCK
10uF_X6S C858 uP7706U8 10.2K
1uF_6.3V
+VDDR3
B10133 BLM15BD121SN1
VOUT = Vref x (1 + R1/R2) B10134 BLM15BD121SN1
C7143 C7144
Vref = 0.8V 12pF_50V Y2 12pF_50V
C7145 C7146 27.000MHz_10PPM_30R
100nF_6.3V 100nF_6.3V XTALIN_OSC 1 3 XTALOUT
2 4
+VDDR3
U7009
POWER UP SEQUENCE 1
XTALIN XTALOUT
10
R7150 0R
R7143 R7144 VDD33_100M 4 XO_IN2 (2)
5.1K 5.1K VDD33_27M 8 VDD_100M 5 CLK_100M R7142 0R
DNI DNI VDD_27M 100M_OUT DNI GPIO16_SSIN (2,10)
+PWR_SRC SS_SEL0 7 R7152 0R
B
SS_SEL1 3 SS_SEL0 DNI GPIO26_TCK (2) B
SS_SEL1 9 CLK_27M R7151 0R
R502 6 27M_OUT XO_IN (2)
10K VDDC_EN (11) MR3 MR4 2 GND_100M R7149 182R
GND_27M XTALIN (2)
3
5.1K 5.1K 11 DNI

R503 5.1K 1 Q502 GND_PAD
MMBT3904 SL16010DCT R7145
221R
2
3
DNI
R501 5.1K 1 Q501
(8) RUNPWROK MMBT3904
R517
2
C501 0R
1uF_6.3V DNI
DNI VDDCI_EN (12)
PCB1
3
R506 5.1K 1 Q505

MMBT3904 PCB
R512 0R DNI
2
109-B97157-00
+3VRUN +VDDR3 +PWR_SRC
MR517 Q508
0R 2 3
+PWR_SRC ASSY2
Si2301BDS +VDDCI +MVDD R515
1.8V_REG_EN (14) PWRGOOD (8)
10K
ANTISTATIC
1
3
3
+3VRUN +VDDC
BAG
R508 R504 5.1K 1 Q503 1 Q511
10K MMBT3904 R513 R514 MMBT3904
R511 100K 1K 1K 6_X_8
2
2
3
R509 R507 C509
10K 1K MVDDUP 1 Q509 100nF
3
DNI +MVDD MMBT3904 DNI

MR507 1K VDDCUP 1 Q506 R510 10K DNI ASSY1
(11) VDDC_POK
2
DNI MMBT3904
BLANK
3
A A
LABEL
2
3
C505 MVDD_EN (13) Q507 1 MR510 10K
MMBT3904 RUNPWROK (8)
1uF_6.3V VDDCIUP 1 Q510 1.50W_X_0.50H
3
DNI MMBT3904
2
R505 5.1K 1 Q504 C506
2
MMBT3904 1uF_6.3V
C507 C508
2
1uF_6.3V 1uF_6.3V CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

NR507 0R DNI with AMD. AMD makes no representations or warranties of any kind
(11) VDDC_POK Date: Tuesday, February 16, 2010 Rev
PWRGOOD (8) regarding this schematic and design, including, not limited to, 5
Title Doc No.
5 4 3 2 1
5 4 3 2 1
CRITICAL TEMPERATURE FAULT
+PWR_SRC +3VRUN
R4056 3.9R
3
R4055
20K 2N7002E
Q4014 C4013 C4014
1 1uF_6.3V 1uF_6.3V
2
R4054 1K 1 Q4013 1 Q4008 R4050
(1) PERST#_buf
2
MMBT3904 CTF_SET2 MMBT3906 0R
D D
DNI
3
R4061
3
20K R4043
DNI 1 R4060 5.1K 470K
Q4016 R4045
2
MMBT3904 10K
CTFb (8)
3
CTF_VCNTL R4051 1K 1 Q4010
MMBT3904
3
+3VRUN C4015
2
CTF_GATED2 R4044 1K CTF_SET3 1 Q4009 R4047 1uF_6.3V R4053
MMBT3904 100K DNI 100K
DNI
2
R4040
5.1K
3
3
R4038 2.2K CTF_TRIP 1 Q4006 Q4007 1 CTF_FB_CNTL R4046 5.1K
(2) GPIO19_CTF MMBT3904 MMBT3904
1%
2
2
CTF SHOULD BE R4039
ACTIVE HI. 1K
1%
R4052 0R DNI
CTF Bypass
C
POWER PLAY C
+VDDR3 For VDDC Controller
GPIO20 GPIO6 VDDC

R1671 R1672 R1673 R1674 R1675
10K 10K 10K 10K 10K
0 0 1.05V DNI DNI DNI
VID0_VDDC
R1679 0R VID1_VDDC
(2) GPIO6
0 1 1.00V VID2_VDDC
(2) GPIO15_PCNTL0
VID3_VDDC
(2) GPIO20_PCNTL1
R1680 0R DNI VID4_VDDC
(2,9) GPIO16_SSIN
1 0 0.90V
VID_VREF
R1682 R1681 R1678 R1677 R1676
1 1 0.85V 10K 10K 10K 10K 10K U1604
DNI DNI DNI 1 8
+5VRUN 2 VID2 VID3 7
3 VID1 VID4 6
4 VDA GND 5
VDD VIDO
VDDC_FB (11) C1620 RT9401BPV8
R2 100nF
R650 VDDC_REFIN R639 0R R1689 2K74

VDDC & VDDCI Share
13.0K (11) VDDC_REFIN
R2 VDDC FB Lower Resistor
DNI External Reference is used R1690 C1621 +VDDC
C616 7.87K 33nF_16V
0R
0R
0R
0R
0R
0R
0R
0R
R650 must be populated 6.8nF_25V
only if VID is not used. This
1
2
3
4
1
2
3
4
will set VDDC to a fixed value Table 4
R1689 & R1690 must VDDC Vref Mode Selection
B
R636 1K DNI be selected to limit B
5VCC (11,12,13) Vref Mode R636, R650 R639, C616 Vref (V)
8
RP1206A 7
RP1206B 6
RP1206C 5
8
RP1207A 7
RP1207B 6
RP1207C 5
Vout = Vref * (1+Rt/Rb) MAX ref voltage to MAX
RP1206D
RP1207D
Internal Reference is used when VDDC. Internal Populate NC 2.5*R2/(R1+R2)
Dual: Vref = 0.6V, Rt = 10k REFIN is pulled up to >4.5V
Single: Vref = 0.8V, Rt = 10k See BOM for qualified External NC Populate set by VID IC (U1604)
values.
+VDDCI
DNI
GPIO6 GPIO16 VDDCI For VDDCI Controller GPIO21 MVDD For MVDD Controller
- 0 0.90V - 1.5V
1.8V_REG_FB (14)
MVDD_FB (13)
- 1 1.00V - - R2
Rf1 R2
R810
- - - R1249 R710 7.87K
86.6K 6.49K
DNI R2 MVDD FB Lower Resistor
- - - VDDCI_FB (12)
3
Vout = Vref * (1+Rt/R2)

Q1244
- Vref = 0.8V
Rf1 Rf2 R2
(2,9) GPIO21_BB_EN
1 R2 MVDD FB Lower - Rt = 10k
+VDDR3 R1246 R1247 R910 BSS138
40.2K 57.6K 20K DNI Resistor
2
DNI
3
R1244 R1245
- Vref = 0.6V
3
10K 10K Q1242

DNI BSS138 Q1243 - Rt = 10k
A 1 DNI BSS138 Vout = Vref * (1+Rt/Rb) A
(2) GPIO6
1 R2 VDDCI FB Lower
(2,9) GPIO16_SSIN - Vref = 0.8V
2
Resistor - Rt = 10k
2
- Rb = R2 // Rf1
- Vref = 0.6V CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
Vout = Vref * (1+Rt/Rb) - Rt = 10k © 2007 Advanced Micro Devices Advanced Micro Devices Inc.
- Vref = 0.8V and is provided only to entities under a non-disclosure agreement 1 Commerce Valley Drive East
- Rt = 10k is strictly prohibited. Use of this schematic and design for any purpose Markham, Ontario
- Rb = R2 // Rf1// Rf2 with AMD. AMD makes no representations or warranties of any kind
5
Title Doc No.
5 4 3 2 1
8 7 6 5 4 3 2 1
Input Cap ASIC_FB_VDDC (3)
2
R685 0R SS_ICOMP NS600
(9) VDDC_EN +VDDC
R684 0R DNI VDDC_REFIN NS_VIA
+PWR_SRC +PWR_SRC
1
share pad R620 0R
VDDC PWM Whole CHip Enable

C685 C668 VDDC_FB_TRACE
10UF_16V 10UF_16V
X7R, 1206 X7R, 1206 R600
1.8mm Hi 1.8mm Hi VDDC_SV 0R 603
VDDC_FB Reserve for
(10) VDDC_FB Loop Measurement
C601
100nF
Top Side Hmax=4mm VDDC_REFIN DNI
D (10) VDDC_REFIN D
Type III compensation

close to IC VDDC_SV
COMP_GND
+PWR_SRC +PWR_SRC +PWR_SRC +PWR_SRC +PWR_SRC +PWR_SRC +PWR_SRC +PWR_SRC +PWR_SRC (9) VDDC_POK R653
RFB1 R3 2.67K Rj1
R651 402 R657
R611 0R C655 10K 0R
C636 C666 C667 C673 C657 C641 C642 C664 C686 603 Css 6.8nF_25V 402 C3 C653 402
2.2uF_16V 2.2uF_16V 2.2uF_16V 2.2uF_16V 2.2uF_16V 2.2uF_16V 2.2uF_16V 2.2uF_16V 2.2uF_16V 402 2.2nF
X7R, 1206 X7R, 1206 X7R, 1206 X7R, 1206 X7R, 1206 X7R, 1206 X7R, 1206 X7R, 1206 X7R, 1206 402 Rj2
1.3mm Hi 1.3mm Hi 1.3mm Hi 1.3mm Hi 1.3mm Hi 1.3mm Hi 1.3mm Hi 1.3mm Hi 1.3mm Hi
SS_ICOMP
R656
UGATE2 COMP_FB 0R
402 R1
R652
Top Side Hmax=1.5mm C612 3.65K
1uF_25V 402 C2
U601 C651
18
17
16
15
14
13
uPI6201Q 220pF_50V
C1 402
UGATE2
BOOT2
REFOUT/POK
SS/ICOMP
FB
REFIN/EN
+PWR_SRC +PWR_SRC +PWR_SRC +PWR_SRC +PWR_SRC +PWR_SRC +PWR_SRC +PWR_SRC +PWR_SRC C652
10nF
402
PHASE2 19 12
C637 C640 C639 C669 C671 C670 C665 C672 C674 PHASE2 COMP/DROOP
1uF_16V 1uF_16V 1uF_16V 1uF_16V 1uF_16V 1uF_16V 1uF_16V 1uF_16V 1uF_16V
X7R, 1206 X7R, 1206 X7R, 1206 X7R, 1206 X7R, 1206 X7R, 1206 X7R, 1206 X7R, 1206 X7R, 1206 MR655 10K 5VCC
0.95mm Hi 0.95mm Hi 0.95mm Hi 0.95mm Hi 0.95mm Hi 0.95mm Hi 0.95mm Hi 0.95mm Hi 0.95mm Hi
LGATE2 20 11
LGATE2 RT R655 51.1K
R664 R662
100K 21 10 100K
Rdroop VCCDRV/DROOP IOUT/IMAX/DROOP C638
+PWR_SRC +PWR_SRC +PWR_SRC +PWR_SRC +PWR_SRC +PWR_SRC +PWR_SRC +PWR_SRC +PWR_SRC 100nF
Droop Option 402 10V
C X5R C
VCC 22 9
C678 C681 C679 C680 C677 C687 C688 C689 VCC CSP2
1uF_16V 1uF_16V 1uF_16V 1uF_16V 1uF_16V 1uF_16V 1uF_16V 1uF_16V CSP2
X7R, 1206
0.95mm Hi
X7R, 1206
0.95mm Hi
X7R, 1206
0.95mm Hi
X7R, 1206
0.95mm Hi
X7R, 1206
0.95mm Hi
X7R, 1206
0.95mm Hi
X7R, 1206
0.95mm Hi
X7R, 1206
0.95mm Hi
C694
1UF_16V CSN2
Output Cap
X7R LGATE1 23 8
603 LGATE1 CSN2
+VDDC DNI
PHASE1 24
PHASE1
25 7 MC644
+PWR_SRC +PWR_SRC +PWR_SRC +PWR_SRC +PWR_SRC +PWR_SRC +PWR_SRC +PWR_SRC 26 PGND CSN1 220UF_2V
PGND26
UGATE1
27 CSN1
BUSEN
BOOT1
PGND27
AGND
5VCC
C602 28 SP/POSCAP,
CSP1
1uF_25V 29 PGND28 CSP1 SMT 7343
C682 C683 C684 C690 C693 C692 C623 C691 PGND29 Max 1.2mm_H
1uF_16V 1uF_16V 1uF_16V 1uF_16V 1uF_16V 1uF_16V 1uF_16V 1uF_16V
6
X7R, 1206 X7R, 1206 X7R, 1206 X7R, 1206 X7R, 1206 X7R, 1206 X7R, 1206 X7R, 1206
0.95mm Hi 0.95mm Hi 0.95mm Hi 0.95mm Hi 0.95mm Hi 0.95mm Hi 0.95mm Hi 0.95mm Hi Bottom Side Hmax=1.2mm
UGATE1
DNI C660 share pad

Bottom Side Hmax=1.2mm R601 0R 1uF_6.3V
603 402 6.3V R606 MR606 +VDDC Top Side Hmax=2.2mm Top Side Hmax=4mm
Y5V 0R 0R
+PWR_SRC +PWR_SRC +PWR_SRC +PWR_SRC DNI
NC641 NC642 NC644 NC643
(10,12,13) 5VCC 470uF_7mR 470uF_7mR 470uF_7mR 1000uF_5mR
PIN5 PH2_ENb:
C696 C697 C698 C699 - Hi , Ph 2 Disabled, Ph 1 Enabled, 2.5V, 2.5V, 2.5V, 2.5V,
1nF 1nF 1nF 1nF - Lo, Ph 1 and Ph 2 Enabled, SP/POSCAP, SP/POSCAP, SP/POSCAP, SP/POSCAP,
SMT 7343 2MM H SMT 7343 2MM H SMT 7343 2MM H SMT 7343 4MM H
+PWR_SRC
Place close to Q601, Q602, Q611 and Q612

B B
9
5
6
7
8
9
5
6
7
8
8
7
6
5
9
8
7
6
5
9
Q601 Q602 Q611 Q612
BSC120N03LSG BSC120N03LSG BSC120N03LSG BSC120N03LSG
LOW PROFILE POSCAP
+VDDC
4
3
2
1
4
3
2
1
1
2
3
4
1
2
3
4
+VDDC
UGATE1 UGATE1 UGATE2 UGATE2
L601 L611
PHASE1 0.27uH_27A 0.27uH_27A PHASE2 C645 C646 C647 C648 C675 C676
4mm H 4mm H 2.2uF_10V 2.2uF_10V 2.2uF_10V 2.2uF_10V 2.2uF_10V 2.2uF_10V
603 603 603 603 603
R698 R699
9
5
6
7
8
9
5
6
7
8
8
7
6
5
9
8
7
6
5
9
300R 300R
805 Q603 Q604 Q613 Q614 805 +VDDC
BSC030N03LS G BSC030N03LS G BSC030N03LS G BSC030N03LS G
Route like Route like
C618 differential pair differential pair C619 C658 C661 C649 C650
1UF_16V 1UF_16V 100nF 15nF 100nF 15nF
603 603 402 402 402 402
4
3
2
1
4
3
2
1
1
2
3
4
1
2
3
4
MLCC
LGATE1 LGATE1 R604 R614 LGATE2 LGATE2
Place across 221R 221R Place across Bottom Side Hmax=1.2mm
Q613, Q614 1/10W 1/10W Q613, Q614
0603 C604 1UF_16V C614 1UF_16V 0603
RC snubber values shown X7R X7R RC snubber values shown
A are for reference only, are for reference only, A
tuning is required R605 C605 C615 R615 tuning is required
221R 100nF_6.3V 100nF_6.3V 221R
CSN2
CSN1
CSP2
CSP1

+VDDC Place close to Controller Place close to Controller © 2007 Advanced Micro Devices Advanced Micro Devices Inc.
R696 with AMD. AMD makes no representations or warranties of any kind
300R 5
805 purpose, and disclaims responsibility forany consequences resulting Sheet 11
DNI of 17
Title Doc No.
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
+PWR_SRC
D D
C921 C922 C924

+5VRUN C923 2.2uF_16V 2.2uF_16V 2.2uF_16V
150nF_16V X7R, 1206 X7R, 1206 X7R, 1206
603 1.3mm Hi 1.3mm Hi 1.3mm Hi
10K
10K
DNI
Top Side Hmax=1.5mm
Bottom Side
R926 Hmax=1.2mm
10K
R924
R925
DNI
PWM
R927
10K
DNI
MR921
10K 40
39
38
37
36
35
34
33
32
31
47
48
49
50
51
52
53
54
55
56
DNI Q901
DISBL#
CGND#37
GL
VSWH#35
VSWH#34
VSWH#33
VSWH#32
VSWH#31
VSWH#47
VSWH#48
VSWH#49
VSWH#50
VSWH#51
VSWH#52
VSWH#53
VSWH#54
VSWH#55
VSWH#56
PWM
THWN
+VDDCI
R923 L901
+5VRUN 10K 1 30 PHASE 0.27uH_27A
LSDBL# VSWH#30
R903 0R 2 29
VCIN VSWH#29
C903 1UF_16V 3 28
VDRV PGND#28 C937 C941 C939
BOOT 4 27 1000uF_5mR 15nF 10uF_.095
BOOT PGND#27 R919 402 X7R, 0805
5 26 2R7_5% SP/POSCAP,
C
R920 CGND#5 PGND#26 Rs 0603 D Size 7343
C
0R 6 25 4MM H
0402 GH PGND#25
PHASE 7
DrMOS 6x6mm 24 Bottom Side Hmax=1.2mm
C902 100nF VSWH#7 PGND#24 C908
0603 8 23
Cs 390pF_50V Top Side MLCC
VIN#8 PGND#23 X7R Hmax=4mm
9 22 0402
VIN#9 PGND#22 LOW PROFILE POSCAP
10 21 Place Rs and
VIN#10 PGND#21 Cs across QL
44
45 VIN#44 RC snubber values shown
46 VIN#45
are for reference only,
VIN#46
tuning is required
VSWH#15
CGND#41
CGND#42
CGND#43
PGND#16
PGND#17
PGND#18
PGND#19
PGND#20
VIN#11
VIN#12
VIN#13
VIN#14
R2J20653ANP
11
12
13
14
15
16
17
18
19
20
41
42
43
+PWR_SRC
PHASE
Pin Difference Between R2J2062NP and R2J2065NP
R2J2062NP R2J2065NP
3 VLDRV NC
B B
8 VIN NC
ASIC_FB_VDDCI (3)
2 NC LSDBL#
53 NC THWN
1
NS900 Place Sense Point on

NS_VIA the load side and routed
with separate 20mil
trace to PWM IC.
2
+VDDCI
R921 0R
PHASE R902 1.3K
R904
(9) VDDCI_EN
FB_TRACE
U901 24.9K
C911 6.8nF_25V R912 8.06K 1 8 402 Internal Reference is
402 402 ISEN RT/SYN R936 used when REFIN is
R909 0R C912 150PF COMP 2 7 REFIN 1K pull-up to > 4.5V
402 COMP/EN REFIN
R914 0R FB 3 6 VCC
R900 R909 and R914 402 FB VCC
0R can share pads C913 3.9nF R913 0R 4 5 +5VRUN
0603 402 402 GND PWM C907 R908 1R DNI
VDD_SV R911 10K_0.1% uP6113AMT8 100nF_6.3V
402 TSOT23-8 PWM 402 MR908 1R
5VCC (10,11,13)
share pad
(10) VDDCI_FB
A A

5
Title Doc No.
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
+PWR_SRC
C723 C722 C724 C721

150nF_16V 2.2uF_16V 2.2uF_16V 10UF_16V
603 X7R, 1206 X7R, 1206 X7R, 1206
1.3mm Hi 1.3mm Hi 1.8mm Hi
D D
Bottom Side Hmax=1.2mm Top Side Hmax=1.5mm Top Side Hmax=4.0mm
+5VRUN
10K
10K
R726
10K
R724
R725
DNI
PWM
R727
10K
DNI
MR721
10K
40
39
38
37
36
35
34
33
32
31
47
48
49
50
51
52
53
54
55
56
DNI Q701
DISBL#
CGND#37
GL
VSWH#35
VSWH#34
VSWH#33
VSWH#32
VSWH#31
VSWH#47
VSWH#48
VSWH#49
VSWH#50
VSWH#51
VSWH#52
VSWH#53
VSWH#54
VSWH#55
VSWH#56
PWM
THWN
R723 +MVDD
10K L701
+5VRUN 1 30 PHASE 0.27uH_27A
LSDBL# VSWH#30
C R703 0R 2 29 C
VCIN VSWH#29
C703 1UF_16V 3 28
VDRV PGND#28 C737 C741 C739
BOOT 4 27 1000uF_5mR 15nF 10uF_.095
BOOT PGND#27 R719 402 X7R, 0805
5 26 Rs 2R7_5% SP/POSCAP,
R720 CGND#5 PGND#26 0603 SMT 7343
0R 6 25 4MM H
0402 GH PGND#25
PHASE 7
DrMOS 6x6mm 24 Bottom Side Hmax=1.2mm
C702 100nF VSWH#7 PGND#24 C708
0603 8 23
Cs 390pF_50V Top Side MLCC
VIN#8 PGND#23 X7R Hmax=4mm
9 22 0402
VIN#9 PGND#22 LOW PROFILE POSCAP
10 21 Place Rs and
VIN#10 PGND#21 Cs across QL
44
45 VIN#44 RC snubber values shown
46 VIN#45
are for reference only,
VIN#46
tuning is required
VSWH#15
CGND#41
CGND#42
CGND#43
PGND#16
PGND#17
PGND#18
PGND#19
PGND#20
VIN#11
VIN#12
VIN#13
VIN#14
R2J20653ANP
11
12
13
14
15
16
17
18
19
20
41
42
43
+PWR_SRC
PHASE
B B
Pin Difference Between R2J2062NP and R2J2065NP
R2J2062NP R2J2065NP
3 VLDRV NC
8 VIN NC
2 NC LSDBL#
53 NC THWN
+MVDD
1
NS700 Place Sense Point on

NS_VIA the load side and routed
with separate 20mil
trace to PWM IC.
2
PHASE R702 1.3K
R704
(9) MVDD_EN
FB_TRACE
U701 24.9K
C711 6.8nF_25V R712 8.06K 1 8 402 Internal Reference is
402 402 ISEN RT/SYN R736 used when REFIN is
R709 0R C712 150PF COMP 2 7 REFIN 1K pull-up to > 4.5V
402 COMP/EN REFIN
R714 0R FB 3 6 VCC
R700 R909 and R914 402 FB VCC
0R can share pads C713 3.9nF R713 0R 4 5 +5VRUN
402 402 GND PWM C707 R708 1R
VDD_SV R711 10K_0.1% uP6113AMT8 100nF_6.3V
402 TSOT23-8 PWM 402 MR708 1R
5VCC (10,11,12)
share pad
A A
(10) MVDD_FB

5
Title Doc No.
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
C805
100nF
+PW_1.8V_REG_M
603
X7R
R818
0R 1.8V_REG_EN (9)
16
15
14
13
U801
D D
PHASE
IMAX
CSP
BOOT
+1.8V_REG
+PW_1.8V_REG_HGD 1 12
UG CSN
2
2 11
VCC DROOP NS801
+PW_1.8V_REG_LGD 3 10 NS_VIA
LG SS Sense Point
1
R834 4 9 1.8V_REG_COMP
42.2K POK COMP
17 18 C811 1.8V_REG_FB_TRACE
TH1 TH2
RT/EN
REFIN
VREF
15nF
402 C812 R801
FB
X7R 150PF 0R
402 603 Reserve for
5
8
R812 X7R Loop Measurement
+PWR_SRC 2.94K
402
R807 2.2R R814 0R 1.8V_REG_SV
C807 R809
100nF 0R C813
603 X7R 3.9nF
402
RFB1 X7R
R811
10K R813
402 3.65K +5VRUN
1% 402
(10) 1.8V_REG_FB 1V8_REG_FB
+5VRUN +5VRUN
C821 C824 C823 C822

1uF_16V 1uF_16V 1uF_16V 2.2uF_16V
X7R, 1206 X7R, 1206 X7R, 1206 X7R, 1206 C896 C897
0.95mm Hi 0.95mm Hi 0.95mm Hi 1.3mm Hi 1nF 1nF
C C
Bottom Side Top Side

Hmax=1.2mm Hmax=1.5mm Place close to Q801
SSO8 Dual-FET (FT1)
QH
7
8
9
Q801A SM
ML801 4mmH
+PW_1.8V_REG_HGD 2 3.3uH_6A
BSC150N03LD_G
+1.8V_REG
1
L801
+PW_1.8V_REG_M 3.3uH_7A
10
5
6
Overlap
Q801B
+PW_1.8V_REG_LGD 4
BSC150N03LD_G C841
QL R819 Rs C839 15nF
3
2.2R C838 MC838 10uF_.095 402
805 100uF_6.3V 68uF_6.3V X7R, 0805
B SP/POSCAP, SP/POSCAP, B
Top Side H<1.5mm C808
10nF_25V C Size 6032 B Size 3528
402 <4MM H <4MM H
X7R
Cs
25V
Bottom Side
Place Rs and Cs across QL Top Side Hmax=4mm Hmax=1.2mm MLCC
RC snubber values shown
are for reference only, POSCAP
tuning is required
A A

is strictly prohibited. Use of this schematic and design for any purpose Markhaml, Ontario
5
Title Doc No.
8 7 6 5 4 3 2 1
5 4 3 2 1
POWER UP SEQUENCE (not to scale)
+PWR_SRC
D D
+5VRUN
+3VRUN
> 1ms
PWR_EN
VDDR3, A2VDD +VDDR3 should ramp before or simultaneously with +VDDC.

+VDDR3 +VDDC should ramp before or simultaneously with +VDDCI.
+VDDCI should ramp before or simultaneously with +MVDD.
+VDDC should ramp before +1.8V_REG. +VDDC and +1.8V_REG should not ramp-up simultaneously.
For LVDS, DPx_VDD10 should ramp-up before DPx_VDD18 and the PCIe Reference clock should begin before DPx_VDD18.
VDDC The external pull-ups on the DDC/AUX signals (if applicable) should ramp-up before or after both VDDC and +1.8V_REG have ramped up.
+VDDC
C C
VDDCI
+VDDCI
VDDR1, MVDDQ/C
+MVDD
VDDR4, VDD_CT, TSVDD, PCIE_VDDR, PCIE_PVDD, DPLL_PVDD, DPx_PVDD,

+1.8V_REG DPx_VDD18, MPV18, SPV18, AVDD, VDD1DI, A2VDDQ, VDD2DI
PCIE_VDDC, DPLL_VDDC, DPx_VDD10, SPV10

+1.0V_REG
< 20ms
PWR_GODD
< 90ms
B B
A A

is strictly prohibited. Use of this schematic and design for any purpose Markhaml, Ontario
5
Title Doc No.
5 4 3 2 1
5 4 3 2 1
MEMORY CHANNEL A & B
GDDR5 8pcs 64Mx16
D D
CH A&B
POWER REGULATORS LVTMDP
DL LVDS LVDS
From +PWR_SRC LVDS_LTXx/LTXx#
DPE/F LVDS_UTXx/UTXx#
+VDDC, +VDDCI, +MVDD DDC3 LVDS_DDC_CLK/DAT
From +5VRUN HPD3 DVI_HPD

+1.8V_REG
From +3VRUN TMDPAB

+VDDR3, A2VDD DP_A
DPA DP_A_Lx/Lx#
From +VDDC
VDDC DDCAUX1 DP_A_AUX/AUX#
Straps
GPIO HPD1 DP_A_HPD
C From +VDDCI C
VDDCI
DP_C
From +MVDD BIOS DPB DP_C_Lx/Lx#
ROM
VDDR1, MVDDQ/C DDCAUX2 DP_C_AUX/AUX#
From +1.8V_REG HPD2 DP_C_HPD
VDDR4, VDD_CT, TSVDD,

PCIE_VDDR, PCIE_PVDD,
DPLL_PVDD, DPx_PVDD,
OSC/SS GPIO16
DPx_VDD18, MPV18, SPV18, XTALIN/OUT
AVDD, VDD1DI, A2VDDQ,
DAC2
VDD2DI, +1.0V_REG CRT DAC2 VGA
VGA_RED/GREEN/BLUE
From +1.0V_REG Dynamic MVDD GPIO21 DDC5

VGA_DDC_CLK/DAT
PCIE_VDDC, DPLL_VDDC, Dynamic VDDCI GPIO16/6 V/HSync
VGA_VSYNC/HSYNC
DPx_VDD10, SPV10 Dynamic VDDC GPIO20/16/15/6
POWER DELIVERY
MxM3.0 Source
Thermal
+3VRUN +5VRUN +PWR_SRC GPIO3, GPIO4
DDC6 I2C
B B
External SMB_CLK/DAT
D+/D- Temp. Sensing
Broadway Temperature TH_ALERT#
GPIO17 Interrupt
Sensor TH_OVERT#
3V3 delayed circuit GPIO19_CTF
Temperature Critical
GPIO19_CTF
PCIE
SMPS Enable
Circuit
3VRUN
5VRUN MxM3.0 Connector MxM3.0 Broadway GDDR5 1GB
PWR_SRC
DP DP DL-LVDS VGA
A A

5
Title Doc No.
5 4 3 2 1
5 4 3 2 1
Title Schematic No. Date:

Broadway GDDR5 MXM 3.0 105-B971xx-00F Monday, February 22, 2010
NOTE: This schematic represents the PCB, it does not represent any specific SKU.
Rev
REVISION HISTORY For Stuffing options (component values, DNI’s, …) please consult the product specific BOM.
D
Please contact AMD representative to obtain latest BOM closest to the application desired.
5 D
Sch PCB Date REVISION DESCRIPTION
Rev Rev
0 00A 09/05/28 Initial design for Broadway GDDR5 MxM3.0
1 00B 09/05/29 Add U27, Q27, C27 - Gating circuit to delay DPE/F_VDD18;
Add RP1206, RP1207 - For VDDC and VDDCI sharing
Add R1681, R1682 - Pull downs for VID circuits
Add R1, MR1, R2, R7152
Add R5801
2 00C 09/10/30 Add C696, C697, C698, C699, C896, C897 (0402 input caps for power supplies)
Change J1 symbol (includes non-plated tooling holes)
Add TP_BP1, TP_BP2, TP_BP3, TP_BP4 (Bead test points)
Move JTAG TPs out of the back plate area
Increase TP coverage
C C
3 00D 09/12/10 Add U101, MU101, R8~R12, C58~C62, R3 (JTAG workaround)

Pull back power planes
4 00E 10/01/04 Increase spacing between C7042 & C7043 and C5976 & C5977
5 00F 10/02/16 Increase spacing between C6076&C7106&C6075, R1237&R1233&C1205&C1201 and C5706&Q27.

Move C5861&C5784 further away from the heatsink backplate area.
B B
A A
5 4 3 2 1

Broadway

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5 4 3 2 1

PCIE_RXP3 V35 U30 PCIE_TXP3

PCIE_RXP4 U38 T33 PCIE_TXP4

PCI EXPRESS INTERFACE

PCIE_RXP7 P35 P30 PCIE_TXP7

PCIE_RXP9 M35 N30 PCIE_TXP9 R9 0R DNI

PCIE_RXP10 L38 L33 PCIE_TXP10 C59 100nF_6.3V

PCIE_RXP14 G38 K30 PCIE_TXP14 12 11 TESTEN

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

AU24 TXCAP_DPA3P (8)

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

DP C/D POWER DP A/B POWER

AW20 DPD_VSSR#3 DPB_VSSR#3 AW30

R6078 150R AW18 AW28 R6079 150R

R6080 150R AM39

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CH_A0 =U3 & U7004

+MVDD +MVDD +MVDD +MVDD

U5 +MVDD U7006 GDDR5 +MVDD U6 GDDR5 +MVDD U7007 GDDR5 +MVDD

+MVDD +MVDD +MVDD +MVDD

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

+3VRUN +3VRUN +3VRUN

65 PEX_RX13_63 GND_64 66 PCIE_RXN12 R6103 0R

EXTERNAL THERMAL SENSOR PIN STRAPS CONFIGURATION STRAPS

V2SYNC R6145 10K

VIP_DEVICE_STRAP_DIS V2SYNC VIP Device Strap Enable 0

5.1K 5.1K 11 DNI

R506 5.1K 1 Q505

DNI +MVDD MMBT3904 DNI

R505 5.1K 1 Q504 C506

1uF_6.3V 1uF_6.3V CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

CRITICAL TEMPERATURE FAULT

+VDDR3 For VDDC Controller

GPIO20 GPIO6 VDDC

R650 VDDC_REFIN R639 0R R1689 2K74

Vout = Vref * (1+Rt/R2)

10K 10K Q1242

Input Cap ASIC_FB_VDDC (3)

VDDC PWM Whole CHip Enable

Type III compensation

DNI C660 share pad

Place close to Q601, Q602, Q611 and Q612

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

C921 C922 C924

Pin Difference Between R2J2062NP and R2J2065NP

NS900 Place Sense Point on

PHASE R902 1.3K

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

C723 C722 C724 C721

Bottom Side Hmax=1.2mm Top Side Hmax=1.5mm Top Side Hmax=4.0mm

NS700 Place Sense Point on

PHASE R702 1.3K

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

C821 C824 C823 C822

Bottom Side Top Side

SSO8 Dual-FET (FT1)

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

POWER UP SEQUENCE (not to scale)

VDDR3, A2VDD +VDDR3 should ramp before or simultaneously with +VDDC.

VDDR4, VDD_CT, TSVDD, PCIE_VDDR, PCIE_PVDD, DPLL_PVDD, DPx_PVDD,

PCIE_VDDC, DPLL_VDDC, DPx_VDD10, SPV10

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.