Electronic Circuits Basics PDF

Electronic Circuits - Basic
Preliminary
Time Domain Analysis
Phasor Analysis
Laplace Analysis
Two-port Network
Chapter 1
Basic Concepts of Electric Circuit Theory
The electronic circuit theory, as part of the electrical circuit theory, borrows the
mathematical formalism. The chapter presents three of the most important types
of circuit analysis developed in “electric circuit theory”. Namely they are:
1. Time domain analysis;

2. Phasor analysis (steady-state frequency domain analysis);
3. Laplace analysis (complex frequency domain analysis).
For each type of analysis, the presentation will follow the next procedure:
▪ Transform definition - The formal definition of the mathematical transform

is submitted;
▪ Signal representation - The usual relationships for voltages and currents
are presented;
▪ Circuit element modeling - In order to model any electronic components or
devices, only nine types of electric elements are necessary. They are:
resistance, capacitance, inductance, voltage source, current source,
voltage controlled voltage source (VCVS), voltage controlled current
source (VCCS), current controlled voltage source (CCVS), current
controlled current source (CCCS). Taking into account this fact, only
these nine elements are treated;
▪ Principal theorems - Kirchhoff current law, Kirchhoff voltage law, Norton
and Thevenin theorems are presented.
▪ Example – a typical example is studied.
In the same time the usual descriptions for two-port networks is presented. The
outline of the chapter is:
1
Review of Electronic Device Theory
Preliminary
Time Domain Analysis
Phasor Analysis
Laplace Analysis
Two Port Network
1.1 Preliminary
The section is structured in two sub-sections:
Fundamental Electrical Elements;

Explanatory Notes.
1.1.1 Fundamental Electrical Elements
In order to describe the way of operation of the nine electrical elements

mentioned above, an observation must be made: they may be divided into two
classes: one port elements and two port elements. In the first class are included:
1. Resistance;
2. Capacitance;
3. Inductance;
4. Voltage source;
5. Current source;
In the second class one finds:
6. Voltage Controlled Voltage Source (VCVS);
7. Voltage Controlled Current Source (VCCS);
8. Current Controlled Voltage Source (CCVS);
9. Current Controlled Current Source (CCCS).
A generic symbol for an one-port element is presented in figure 1.1. The figure
1.2 shows the two-port element.
Figura 1.1 One-port element Figura 1.2 Two-port element
where:
vT total instantaneous value of the voltage drop across the one-port
element;
iT total instantaneous value of the current flowing through one-
port element;
2
vIN total instantaneous value of the input voltage of the two-port

element;
iIN total instantaneous value of the input current of the two-port
element;
vO total instantaneous value of the output voltage of the two-port
element;
iO total instantaneous value of the output current of the two-port
element;
Observations:
1. An one-port element is fully described by one and only one
characteristic equation (1.1);
2. A two-port element is fully described by two and only two
characteristic equations.
3. A characteristic equation looks like (1.1) relationship.
 di dn i dv dmv 
E i T , T ,K, nT , v T , T ,K, mT , θ1 ,K,θ p  = 0 (1.1)
 dt dt dt dt 
where θ1 ,K,θ p non electric parameters.
Taking into account the fact that the equivalent circuit associated to an
electronic device must be linear, in the following, only linear behavior of the
nine electric elements will be considered.
1.1.2 Explanatory Notes
It is important to mention the explanatory notes that will be used in the book.
Figure 1.3 presents such notations:
Figure 1.3 Explanatory notes
AT DC value;
aT total instantaneous value (DC+AC);
at AC instantaneous value;
At AC amplitude.
3
1.2 Time Domain Analysis

It is called also “t” domain analysis. This type of analysis is the most general
way of analyzing a circuit. The principal problem is that this type of analysis is
– from mathematical point of view - very difficult. It requires differential
equations solving.
1.2.1. The Transform

No transform is needed.
1.2.2 Signal Representation

Both voltages and currents are represented by continuous functions. Table 1.1
presents such functions:
Signal Time domain (t)

Voltage v( t ) = f ( t )
Current i(t ) = g ( t )
Table 1.1 The representation of voltage and current
where:
f :R → R (1.2)
g:R → R (1.3)
Observations:
1 If
d kf
= 0 ∀k ∈ N (1.4)
dt k
dng
= 0 ∀n ∈ N (1.5)
dt n
then the circuit is operating in the so called static regime (DC regime).
2 If
dkf
≅ 0 ∀k ∈ N (1.6)
dt k
dng
≅ 0 ∀n ∈ N (1.7)
dt n
then the circuit is operating in the so called quasi-static regime.
3 If
 d kf dng 
(∃k ∈ N or ∃n ∈ N) :  k ≠ 0 or n ≠ 0  (1.8)
 dt dt 
then the circuit is operating in the so called dynamic regime.
4
1.2.3 Circuit Element Modeling
The section presents the electrical and mathematical model of the principal
electric components. Both ANSI and DIN standards are provided. Table 1.2
makes a synthetic presentation.
Characteristic
Element Symbol ANSI Symbol DIN
equation
Resistor v R ( t ) = Ri R ( t )
di L ( t )
Inductor vL (t) = L
dt
dv C ( t )
Capacitor i C (t ) = C
dt
Voltage source v( t ) = E ( t )
Current source i(t ) = I( t)
Voltage controlled i IN ( t ) = 0
voltage source v O ( t ) = k v IN ( t )
Current controlled v IN (t ) = 0
voltage source v O ( t ) = k i IN (t )
Current controlled v IN ( t ) = 0
current source i O ( t ) = k i IN ( t )
Voltage controlled i IN (t ) = 0
current source i O ( t ) = k v IN ( t)
Table 1.2 The principal electrical elements
5
1.2.4 Principal Theorems
The section deals with Kirchhoff's current law (KCL), Kirchhoff's voltage law,
Thevenin and Norton theorems and finally, the voltage and current dividers are
presented. A procedure to calculate the voltage drop between two terminals of a
circuit and also a procedure to calculate the resistance “seen” between two
terminals of a circuit are added.
a.) Kirchhoff’s Current Law
It is generally known as “KCL”.
Statement: “The sum of the currents flowing into any node equals the sum
of the currents flowing out from that node.”
m p
∑j=1
i+j = ∑i
k =1
−k (1.9)
where:
i+j current entering into the node;
i-k current going out from the node.
Observation: The current entering into a node is noted “+”;

The current going out from a node is noted “-“
Example: Figure 1.4 presents a case study for a node noted “n”.
According to (1.9) KCL becomes:
i Cn + i R n = i Ln + i k Ln + i e = 0 (1.10)
Figure 1.4 Kirchhoff current law - example
where:
iCn the current through the capacitor noted “Cn”;
6
iRn the current through the resistor noted “Rn”;

iLn the current through the inductor noted “Ln”;
i k Ln the current through current controlled current source ikLn;
ie the current of the voltage source noted “En”;
b.) Kirchhoff’s Voltage Law
It is generally known as “KVL”.
Statement: “The sum of the electromotive forces in any closed loop is

equivalent to the sum of the voltage drops in that loop.”
m p
∑j=1
ej = ∑v
k =1
k
(1.11)
where:
ej electromotive force of the “j” source in the loop;
vk voltage drop through the “k” element in the loop.
Example: Figure 1.5 presents a case study for a loop noted “n”.
According to (1.11) KCV becomes:
E = v Cn + v + v L n + v R n (1.12)
Figure 1.5 Kirchhoff voltage law - example

where:
1
v Cn =
Cn ∫
i Cn dt the voltage drop across the capacitor noted “Cn”;
7
vRn = R n i Rn the voltage drop across the resistor noted “Rn”;

di L n
v Ln = L n the voltage drop across the inductor noted “Ln”;
dt
the voltage drop across the current source current
v
controlled
E electromotive force in the loop
Replacing the above voltage drops relationships into (1.12) one

obtains:
1 di L n
E=
Cn ∫
i Cn dt + v + L
dt
+ R n i Rn (1.13)
c.) Voltage Drop Calculation
Problem Consider the circuit presented in figure 1.6. The voltage drop
formulation between the A and B points (figure 1.6) must be calculated.
Figure 1.6 A general circuit

Procedure Step 1 Solve the circuit;
Step 2 Draw an arrow – signifying the voltage drop -
between the two points (figure 1.7);
8
Figure 1.7
Step 3 Consider a false loop containing the arrow. Figure
1.8 presents a possible loop, while figure 1.9
presents another possible loop.
Figure 1.8 Figure 1.9

Step 4 Write Kirchhoff voltage law on the chosen loop.
Step 5 Solve the KVL equation. It will contain a single
unknown value, namely “vAB”.
d.) Resistance “Seen” between two Terminals of a Circuit
This type of calculus may be made only for DC regime. The main idea consists
in introducing a test source (voltage and current) between the two terminals.
That’s why two cases are analyzed.
Case 1 A voltage source is applied between the two terminals.
Problem Consider the circuit presented in figure 1.10. The resistance

formulation “seen” between the A and B points must be calculated.
9
Figure 1.10 A general circuit

Procedure Step 1 The independent voltage sources must be
replaced with short circuits and the independent
current sources must be replaced with open-
circuits (see figure 1.11).
Figure 1.11
Step 2 A voltage source is applied between the two
terminals (figure 1.12).
Figure 1.12
Step 3 Calculate RAB according to (1.14) formula.
ET
R AB = (1.14)
IT
10
Case 2. A current source is applied between the two terminals
Procedure Step 1 The independent voltage sources must be

replaced with short circuits and the independent
current sources must be replaced with open-
circuits (see figure 1.11).
Step 2 A current source is applied between the two
Figure 1.13
Step 3 Calculate RAB according to (1.15) formula.
VT
R AB = (1.15)
IT
e.) Norton Theorem
Also known in Europe as Mayer-Norton Theorem.

Statement: Any circuit containing voltage and/or current sources
(independent and/or dependent) and resistors with two
terminals (noted A and B) is electrically equivalent with an
ideal current source Isc in parallel with a resistor RAB.
Observation: The theorem may be applied for DC circuits.
Consider the circuit presented in figure 1.10. Norton equivalence of the circuit
is presented in figure 1.14.
Figure 1.14 Norton equivalence of the circuit presented in figure 1.10
11
The calculus of the IBsc and RAB is presented below:
Procedure: Let’s consider the circuit presented in figure 1.10.
Step 1: Calculate the open circuit drop voltage the two

terminals. (figure 1.15)
Figure 1.15 IAB sc evaluation

Step 2: Calculate the resistance “seen” between the two
terminals according to formulae (1.14) or (1.15).
Example:
Step 1 Consider the circuit presented in figure 1.16. The
two terminals are noted A and B. Figure 1.17
presents the circuit redrawn.
Figure 1.16 The basic circuit Figure 1.17 The circuit

redrawn
Step 2: Calculate the short-circuit current (IABsc) between the
two terminals:
Figure 1.18 The circuit used for the calculation of IABsc
12
EC
I ABSC = (1.16)
R B1
Step 3:Calculate the resistance “seen” between the two
Finally the circuit transformed according to Norton theorem is presented in
figure 1.19.
1.19 The Norton equivalence of the circuit presented in figure 1.9
f.) Thevenin Theorem
The theorem was first discovered by German scientist Hermann von Helmholds
in 1853.
Observation: The theorem may be applied for DC circuits.

(independent and/or dependent) and resistors with two
ideal voltage VAB0 series with a resistor RAB.
Consider the circuit presented in figure 1.10. Thevenin equivalence of the

circuit is presented in figure 1.20.
Figure 1.20 Thevenin equivalence of the circuit presented in figure 1.10
The calculus of the EAB0 and RAB is presented below:
Procedure: Let’s consider the circuit presented in figure 1.10.
Step 1: Choose the two terminals (figure 1.10)

Step 2: Calculate the open-circuit voltage between the two
13
Figure 1.21 EAB0 evaluation

Example:
Step 1 Consider the circuit presented in figure 1.9. The two

terminals are noted A and B The circuit redrawn is
presented in figure 1.10
Step 2: Calculate the voltage drop (EAB0) between the two
terminals.
Figure 1.22 The circuit used for the calculation of EAB0

R B2
E AB0 = E C (1.17)
R B1 + R B2
Finally the circuit transformed according to Thevenin theorem is presented in

figure 1.23.
14
1.23 The Thevenin equivalence of the circuit presented in figure 1.10
g.) Voltage Divider
Statement Consider the circuit presented in figure 1.24. The voltage drop
across R1 resistor or R2 resistor must be calculated
Figure 1.24 Voltage Divider

a.) The voltage drop across R1 resistor may be
calculated using:
R1
VR1 = E (1.18)
R1 + R 2
b.) The voltage drop across R2 resistor may be
calculated using:
R2
VR 2 = E (1.19)
R1 + R 2
h.) Current Divider
Statement Consider the circuit presented in figure 1.24. The current

flowing through R1 resistor or R2 resistor must be calculated
Figure 1.24. Current Divider

a.) The current flowing through R1 resistor may be
calculated using:
R2
I R1 = I (1.20)
R1 + R 2
15
b.) The current flowing through R2 resistor may be

calculated using:
R1
IR2 = I (1.21)
R1 + R 2
1.2.5 Example
Consider the circuit presented in figure 1.25. Write the Kirchhoff’s equations
according to time domain analysis procedure.
Figure 1.25
Solution:
(1) i R ( t ) + i(t ) = i C ( t ) (1.22)
1
(I) e(t ) = Ri R (t ) +
C ∫ i C ( t)dt (1.23)
di( t ) 1
(II) 0 = −L
dt
+ v( t ) −
C ∫ i C ( t )dt (1.24)
1.3 Phasor Analysis

It is also called phasor domain analysis. This type of analysis is used for
studying the electric circuits with sinusoidal inputs of fixed frequencies.
1.3.1 Explanatory Notes
Let’s take into account a sinusoidal signal (see figure 1.26):

a m ( t ) = A m cos(ωt + ϕ ) (1.25)
Figure 1.26 A sinusoidal signal

where:
t time;
16
a m (t)instantaneous value;
Am amplitude;
ω angular frequency;
ϕ phase;
In the same time one can define:
T period;
2π
T= (1.26)
ω
f frequency;
1
f= (1.27)
T
A p− p peak to peak amplitude
A p− p = 2 A m (1.28)
A rms root-mean-square
Am
A rms = ≅ 0.707A m (1.29)
2
According to (1.27) relationship the phase may be written as:
2π∆t
ϕ= (1.30)
T
where
∆t delay time.
In the same time one can observe:

ω = 2πf (1.31)
Definition: “A phasor is a constant complex number, usually expressed in

exponential form, representing the complex amplitude
(magnitude and phase) of a sinusoidal function of time”
According to this type of transform, a sinusoidal function of time is associated

with its phasor – see 1.32 relationship:
a m ( t ) = A m cos( ωt + ϕ) → A m ( jω) = A m e jωe jϕ (1.32)

where:
A m ( jω) the phasor;
Am the module of the phasor;
17
ϕ the phase of the phasor.

ω radial frequency
Observation: The term “phasor” can also refer to a complex constant as

(1.32’) shows:
a m ( t ) = A m cos( ωt + ϕ) → A m = A m e jϕ (1.32’)
This representation is a shorthand notation used on a large scale in circuit
theory.
Observation: In special cases, namely, if the radial frequency of a circuit is

variable, we can include a representation to show that the
phasors are dependent on the radial frequency.
Taking into account the above observation the definition presented in (1.32’)
relationship becomes:
a m ( t ) = A m (ω) cos( ωt + ϕ) → A m (ω) = A m (ω)e jϕ (1.32”)

where:
A m (ω ) the phasor;
A m (ω ) the module of the phasor;
In respect to (1.32”) relationship, table 1.3 shows the associations of the

voltages, currents with the phasors transform.
Signal Time domain (t) Phasor Transfoms (ω)

Voltage v m ( t) = Vm cos(ωt + ϕ ) Vm = Vm e jϕ
Current i n ( t) = I n cos(ωt + φ ) I n = I n e jφ
Table 1.3 The phasors associated to voltage and current
Definition: The impedance of a circuit element can be defined as the ratio

of the phasor voltage across the element to the phasor current
through the element, as determined by the relative amplitudes
and phases of the voltage and current.
A synthetic presentation of this transform is made in table 1.4
18
Time domain (t) Phasor Transfoms (ω)

Element
Value V-I relationship Impedances V-I relationship
Resistor R vr (t) = R i r (t) Z r (ω ) = R Vr (ω ) = R I r (ω )
d i l (t ) Zl (ω ) = jωL Vl (ω ) = jωL I l (ω )
Inductor L vl (t) = L
dt
1 1 1
Capacitor C vc (t) =
C ∫
i c ( t ) dt Zc (ω ) =
j ωC
Vc (ω ) =
jωC
I c (ω )
Table 1.4 The impedances associated to resistor, inductor and capacitor

Consistent with this transformation, table (1.5) presents both the electrical
models and the mathematical models of the nine important elements.
Phasor domain (ω)

Element Time domain (t)
Electrical model Mathematical model
Resistor Vr (ω ) = R I r (ω )
Inductor Vl (ω ) = jωL I l (ω )
1
Capacitor Vc (ω ) = I c (ω )
j ωC
Voltage V (ω ) = E m (ω )
source
Current I(ω ) = I n (ω )
source
Voltage
controlled
I in (ω ) = 0
voltage Vo (ω ) = k Vin (ω )
source
Current
controlled
Vin (ω ) = 0
voltage Vo (ω ) = k I in (ω )
source
19
Phasor domain (ω)

Current
controlled
Vin (ω ) = 0
current I o (ω ) = k I in (ω )
source
Voltage
controlled
I in (ω ) = 0
current I o (ω ) = k Vin (ω )
source
Table 1.5 The electrical and mathematical models according to Phasor Transform of
the nine principal electrical
1.3.5. Principal Theorems
This section presents the theorems described in section 1.2.4 using the Phasor
transform formalism.
a.) Kirkhhoff Current Law
Statement: “The sum of the current phasors flowing into any node equals
the sum of the current phasors flowing out from that node.”
m p
∑I
j=1
− j (ω ) = ∑I
k =1
+ k (ω ) (1.33)
where:
I − j (ω ) current phasor entering into the node
I + k (ω ) current phasor going out from the node
Example: The circuit presented in figure 1.4 may be modeled – using

“phasor transform” – as figure 1.27 illustrates.
Figure 1.27 The model of the circuit

KCL for this example is presented in (1.34) relationship.
20
I Cn (ω ) + I R n (ω ) = I Ln (ω ) + I k Ln (ω ) + I e (ω ) (1.34)
where:
I Cn (ω ) the current phasor through the capacitor noted “Cn”;
I R n (ω ) the current phasor through the resistor noted “Rn”;
I Ln (ω ) the current phasor through the inductor noted “Ln”;
I k Ln (ω ) the current phasor through the current controlled current source
ikLn;
I e (ω ) the current phasor of the voltage source noted “En”;

Statement: “The sum of the electromotive force phasors in any closed loop
is equivalent to the sum of the voltage drop phasors in that
loop.”
m p
∑j=1
E j (ω ) = ∑I
k =1
k (ω ) Z k (ω ) (1.35)
where:
E j (ω ) electromotive force phasor of the “j” source in
the loop;
I k (ω ) Z k (ω ) voltage drop phasor of the “k” element in the
loop.
Example: Figure 1.28 presents the phasor model of the circuit presented
in figure 1.4.
KVL for this example is presented in (1.36) relationship.
1 (1.36)
E n (ω ) = I C (ω ) + VkILn (ω ) + jωL n I Ln (ω ) + R n I R n (ω )
jω C n n
21
Figure 1.28 The model of the circuit

where:
1
I C (ω ) the voltage drop across the capacitor noted “Cn”;
jωC n n
R n I R n (ω ) the voltage drop across the resistor noted “Rn”;
jωL n I Ln (ω ) the voltage drop across the inductor noted “Ln”;
VkILn (ω ) the voltage drop across the current source current
controlled
E n (ω ) electromotive force in the loop
c.) Norton Theorem

(independent and/or dependent) and impedances with two
ideal current sources Isc in parallel with an impedance ZAB.
Figure 1.29 A general circuit Figure 1.30 Norton equivalence of the

circuit presented in figure 1.29
22
Observation: Both I ABsc (ω ) and Z AB (ω ) may be calculated following the

procedure described in section 1.2.4
d.) Thevenin Theorem
(independent and/or dependent) and impedances with two
ideal voltage source EAB0 series with an impedance ZAB.
Figure 1.31 A general circuit Figure 1.32 Norton equivalence of the

circuit presented in figure 1.31
Observation: Both E AB0 (ω ) and Z AB (ω ) may be calculated following the
procedure described in section 1.2.4
e.) Voltage Divider
Statement Consider the circuit presented in figure 1.33.
Figure 1.33 Voltage Divider

a.) The voltage drop across Z1 (ω ) impedance may be
calculated using:
Z1 (ω )
VZ1 (ω ) = E(ω ) (1.36)
Z1 (ω ) + Z 2 (ω )
b.) The voltage drop across Z 2 (ω ) impedance may be
calculated using:
23
Z 2 (ω )
VZ 2 (ω ) = E(ω ) (1.37)
Z1 (ω ) + Z 2 (ω )
f.) Current Divider
Statement Consider the circuit presented in figure 1.34.
Figure 1.34 Current Divider

a.) The current flowing through Z1 (ω ) impedances
may be calculated using:
Z 2 (ω )
I Z1 (ω ) = E(ω ) (1.38)
Z1 (ω ) + Z 2 (ω )
b.) The current flowing through Z 2 (ω ) impedances
may be calculated using:
Z1 (ω )
I Z 2 (ω ) = E(ω ) (1.39)
Z1 (ω ) + Z 2 (ω )
1.3.6 Example
according to Phasor analysis procedure.
Solution: According to this type of analysis the circuit presented in figure

1.25 must be modeled as figure 1.35 shows:
Figure 1.35 The Phasor transformation of the circuit presented in figure 1.25
The system of equations:
(1) I r (ω ) + I(ω ) = I c (ω ) (1.40)
1
(I) E (ω ) = R I r (ω ) + I c (ω ) (1.41)
jω C
24
1
(II) 0 = − jωLI(ω ) + V(ω ) − I c (ω ) (1.42)
jωC
1.4 Laplace Analysis

Phasor Analysis can be applied only for the electrical circuits which are
operating in the so called “steady-state” sinusoidal regime. That means that the
sources (voltage or current) working in the circuit generate signals with a
constant frequency, namely “ω”. In order to develop a method of analysis the
circuit containing sources that generate arbitrary signals, the complex frequency
“s” must be used. Simplifying, “jω” is replaced by the “complex frequency “s”,
where:
s = σ + jω (1.43)
In accordance with this type of transform, a function of time is associated with

its Laplace transform – see (1.44) formula.
f (t ) → F(s) (1.44)
where:
∞
∫
F(s) = e −st f ( t )dt
0
(1.45)
The usual notation for Laplace transform is:
F(s)=L{f(t)} (1.46)
1.4.2 Signal Representation
Table 1.6 shows the representation of voltage and current using Laplace
transformation.
Signal Time domain (t) Laplace Transfoms (s)

Voltage v m ( t) Vm (s)
Current i n (t) I n (s)
Table 1.6 The Laplace transform for voltages and currents
25
Observation: Resistors, inductors and capacitors are replaced by their

operational impedances (Laplace impedances).
Definition: The operational impedance (Laplace impedance) of a circuit
element can be defined as the ratio of the Laplace transform of
the voltage across the element to the Laplace transform of the
current through the element.
The generalized impedances associated to resistor, inductor and capacitor is

made in table 1.7.
Time domain (t) Laplace Transfom (s)

Element
Value V-I relationship Impedances V-I relationship
Resistor R vr (t) = R i r (t) Z r (s) = R Vr (s) = R I r (s)
d i l (t )
Inductor L vl (t) = L Zl (s) = sL Vl (s) = sL I l (s)
dt
1 1 1
Capacitor C vc (t) =
C ∫
i c ( t ) dt Z c (s) =
sC
Vc (s) =
sC
I c (s)
Table 1.7 The generalized impedances associated to resistor, inductor and capacitor
Table 1.8 makes a synthetic presentation of the electrical models of these circuit
elements:
S - domain
Electrical model
Resistor
Inductor
Capacitor
Table 1.8 The electrical models according to Laplace

Transform for R, L, C elements
26
If there are initial conditions on the circuit elements, then supplementary

sources must be added. Table 1.9 presents the modifications.
S - domain
Electrical model voltage Electrical model current
sources added sources added
Resistor
Inductor
Capacitor
Table 1.9 The electrical models according to Laplace Transform for R, L, C elements
In order to be more explicit, table 1.10 states the electrical and mathematical
models according to Laplace transform for R, L, C elements if voltage sources
are added for initial conditions.
S - domain
voltage sources added voltage sources added
Resistor Vr (s) = R I r (s)
27
S - domain
voltage sources added voltage sources added
Inductor Vl (s) = sLI l (s) − LI 0
1 V
Capacitor Vc (s) = I c (s) + 0
sC s
Table 1.10 The electrical and mathematical models according to Laplace Transform for R,
L, C elements – voltage sources added for initial conditions
If current sources are added, in order to implement the initial conditions, then
the electrical and mathematical models according to Laplace Transform for R,
L, C elements may be used. Table 1.11 shows the modifications.
s- domain
current sources added current sources added
1
Resistor I r (s) = Vr (s)
R
1 I
Inductor I l (s) = Vl (s) − 0
sL s
28
s- domain
current sources added current sources added
Capacitor I c (s) = sCVc (s) − CV0
Table 1.11 The electrical and mathematical models according to Laplace Transform for R,
L, C elements – current sources added for initial conditions
Synthesizing Table 1.12 shows the electrical model for the nine basic elements.
“s” - domain
Element Time domain (t) Electrical model voltage Electrical model
sources added current sources added
Resistor
Inductor
Capacitor
Voltage
source
29
“s” - domain
Element Time domain (t) Electrical model voltage Electrical model
sources added current sources added
Current
source
Voltage
controlled
voltage
source
Current
controlled
voltage
source
Current
controlled
current
source
Voltage
controlled
current
source
Table 1.12 The electrical models according to Laplace Transform of the nine principal
electrical elements
1.4.4 Principal Theorems
Only Kirchhoff's current law (KCL), Kirchhoff's voltage law will be presented.
a.) Kirchhoff’s Current Law
Statement: The sum of the currents Laplace transform flowing into any
node equals the sum of the currents Laplace transform flowing
out from that node.
m p
∑ I(s)
j=1
+j = ∑ I(s)
k =1
−k (1.47)
where:
I(s) + j current Laplace transform entering into the node;
I(s) −k current Laplace transform going out from the node.
30
Observation: The current Laplace transform entering into a node is noted

“+”;
The current Laplace transform going out from a node is noted
“-“
Example: Figure 1.36 presents a case study for a node noted “n” .
According to (1.47) KCL becomes:
I(s) Cn + I(s) R n = I(s) Ln + I(s) k Ln + I(s) e = 0 (1.48)
Figure 1.36 Kirchhoff current law - example

where:
I(s) Cn the current Laplace transform through the capacitor noted “Cn”;
I(s) R n the current Laplace transform through the resistor noted “Rn”;
I(s) L n the current Laplace transform through the inductor noted “Ln”;
i k Ln the current Laplace transform through current controlled
current source I(s)kLn;
I(s) e the current Laplace transform of the voltage source noted “En”;

Statement: The sum of Laplace transform of the electromotive forces in
any closed loop is equivalent to the sum of the Laplace
transform of the voltage drops in that loop.
m p
∑
j=1
E (s) j = ∑ V(s)
k =1
k
(1.49)
where:
E (s ) j Laplace transform of the “j” electromotive force in the
loop;
V (s) k Laplace transform of the “k” voltage drop in the loop.
31
Example: Figure 1.37 presents a case study for a loop noted “n”.
According to (1.49) KCV becomes:
1
E(s) = I(s) Cn + V(s) + sL n I(s) L n + R n I(s) R n (1.50)
sC n
Figure 1.37 Kirchhoff voltage law - example

where:
1
I(s) Cn the voltage drop across the capacitor noted “Cn”;
sC n
R n I(s) R n the voltage drop across the resistor noted “Rn”;
sL n I(s) L n the voltage drop across the inductor noted “Ln”;
V (s)
the voltage drop across the current source current
controlled
E (s) electromotive force in the loop
1.4.5 Example
according to Laplace analysis procedure.
Solution: According to this type of analysis the circuit presented in figure

1.25 must be modeled as figure 1.38 shows:
Figure 1.38 The Laplace model of the circuit presented in figure 1.25
32
(1) I r (s) + I(s) = I c (s) (1.51)

1
(I) E(s) = RI r (s) + I c (s) (1.52)
sC
1
(II) 0 = −sLI(s) + V(s) − I c (s ) (1.53)
sC
1.5 Two Port Network
Generally speaking the theory of electrical circuits uses two types of phrases:
one-port network and two-port network. The present section deals with two-port
network. The mathematical model – associated with the electrical model - will
be showed.
The outline of the section is:
Preliminary
Impedances parameters;
Admittances parameters;
Hybrid parameters;
Inverse Hybrid Parameters;
A,B,C,D Parameters;
A’,B’,C’,D’ Parameters;
1.5.1 Preliminary
Definition: A two-port network circuit is an electrical circuit with four

terminals (quadripole) that may be coupled as two pairs of
terminals connected together internally by an electrical network
that satisfies the so called condition “port condition” – namely
the same current must enter and leave a port.
Definition A port is a pair of terminals at which a signal may enter or
leave.
A symbolic presentation of a two-port network is shown in figure 1.39:
Figure 1.39 Two-port network – general case

According to “port condition”:
I1 = I1 ' (1.54)
I2 = I2 ' (1.55)
33
And by consequence, a two-port network may be modeled as figure 1.40 shows:
Figure 1.40 Two-port network
In the following, only linear behavior of the network is analyzed. Taking into
account this assumption, the network presentation will be made in “s” domain
(fig. 1.41).
Figure 1.41 Two-port network – “s” domain
Observation: In order to describe the behavior of a two-port network, only

two equations are necessary.
Starting from this observation, it must be noted that there are four quantities
{Vin(s), Iin (s), Vo(s), Io(s)} that have to be linked into two equations. By
consequence there are six types of parameters that may describe the behavior of
a two-port network. (1.56) relationship proves this statement:
n = C 26 (1.56)
and more
4×3
n= =6 (1.57)
1× 2
In the following, these types of parameters are presented.
1.5.2 Impedance Parameters (“z” parameters)
Note:
Input variables are: {I1(s), I2(s)}
Output variables are: {V1(s), V2(s)}
The impedances parameters are: {z11(s), z12(s), z21(s), z22(s)}.
Both mathematical model and electrical model of this type of description are
presented in figure 1.42, respectively figure 1.43.
34
V1 (s) = z11 (s)I1 (s) + z12 (s)I 2 (s)

V2 (s) = z 21 (s)I1 (s) + z 22 (s)I 2 (s)
Figure 1.42 The mathematical model Figure 1.43 The electrical model
Observation: The matrix form of the mathematical model is:
 V1 (s)   z11 (s) z12 (s)   I1 (s) 

 = ×  (1.58)
V2 (s) z 21 (s) z 22 (s) I 2 (s) 
1.5.3 Admittance Parameters (“y” parameters)
Note:
Input variables are: {V1(s), V2(s)}
Output variables are: {I1(s), I2(s) }
The admittances parameters are: {y11(s), y12(s), y21(s), y22 (s)}.
I1 (s) = y11 (s)V1 (s) + y12 (s)V2 (s)
I 2 (s) = y 21 (s)V1 (s) + y 22 (s)V2 (s)
 I1 (s)   y11 (s) y12 (s)   V1 (s) 

I (s) =  y (s) y (s) × V (s) (1.59)
 2   21 22   2 
1.5.4 Hybrid Parameters (“h” parameters)
Note:
Input variables are: {I1(s), V2(s)}
Output variables are: {I2(s), V1(s) }
The hybrid parameters are: {h11(s), h12(s), h21(s), h22(s)}.
35
V1 (s) = h11 (s)I1 (s) + h12 (s)V2 (s)

I 2 (s) = h 21 (s)I1 (s) + h 22 (s)V2 (s)
V1 (s)  h11 (s) h12 (s)   I1 (s) 

 = ×   (1.60)
 I 2 (s)  h 21 (s) h 22 (s) V2 (s)
1.5.5 Inverse Hybrid Parameters (“g” parameters)
Note:
Input variables are: {I2(s), V1(s) }
Output variables are: {I1(s), V2(s)}
The inverse hybrid parameters are: {g11(s), g12(s), g21(s), g22(s)}.
I1 (s) = g11 (s)V1 (s) + g12 (s)I 2 (s)

V2 (s) = g 21 (s)V1 (s) + g 22 (s)I 2 (s)
 I1 (s)   g11 (s) g12 (s)  V1 (s)

V (s) = g (s) g (s) ×  I (s)  (1.61)
 2   21 22   2 
1.5.6 A,B,C,D Parameters
The ABCD-parameters are also known as “a” parameters or “transmission

parameters”.
Note:
36
Input variables are: {I1(s), V1(s) }

Output variables are: {-I2(s), V2(s)}
The A,B,C,D parameters are: {A11(s), B12(s), C21(s), D22(s)}.
The mathematical model of this type of description is:
V1 (s) = A(s)V2 (s) − B(s)I 2 (s) (1.62)

I1 (s) = C(s)V2 (s) − D(s) I 2 (s) (1.63)
V1 (s) A (s) B(s)   V2 (s) 

 = ×   (1.64)
 I1 (s)   C(s) D(s) − I 2 (s)
In many cases a different notation is used:
a11 (s) = A(s) (1.65)

a12 (s) = B(s) (1.66)
a 21 (s) = C(s) (1.67)
a 22 (s) = D(s) (1.68)
In these conditions (1.64) relationship becomes:
V1 (s) a 11 (s) a 12 (s)   V2 (s) 

 = ×   (1.69)
 I1 (s)  a 21 (s) a 22 (s) − I 2 (s)
1.5.7 A’,B’,C’,D’ Parameters
The A’B’C’D’-parameters are also known as “b” parameters or “inverse

transmission parameters”.
Note:
Input variables are: {-I2(s), V2(s) }
Output variables are: {-I1(s), V1(s)}
The A’,B’,C’,D’ parameters are: {A’11(s), B’12(s), C’21(s), D’22(s)}.
The mathematical model of this type of description is:
V2 (s) = A' (s)V1 (s) − B' (s)I1 (s) (1.70)
37
−I 2 (s) = C' (s)V1 (s) − D' (s)I1 (s) (1.71)
 V2 (s)  A' (s) B' (s)  V1 (s)

 = ×  (1.72)
− I 2 (s)  C' (s) D' (s)  I1 (s) 
In many cases a different notation is used:
b11 (s) = A' (s) (1.73)

b12 (s) = B' (s) (1.74)
b 21 (s) = C' (s) (1.75)
b 22 (s) = D' (s) (1.76)
In these conditions (1.72) relationship becomes:
V1 (s)  b11 (s) b12 (s)   V2 (s) 

 I (s)  = b (s) b (s) × − I (s) (1.77)
 1   21 22   2 
38
Basic Concepts of Electric Circuit Theory

Tests
1. 1p A generic symbol for an one-port element is presented in

figure:
a.) b.)
c.) d.)
where:
vT total instantaneous value of the voltage drop across the one-
port element;
iT total instantaneous value of the current flowing through
one-port element
2. 1p A generic symbol for a two-port element is presented in figure:

a.) b.)
c.) d.)
Where:
vIN total instantaneous value of the input voltage of the two-
port element;
iIN total instantaneous value of the input current of the two-
port element;
vO total instantaneous value of the output voltage of the two-
port element;
iO total instantaneous value of the output current of the two-
port element;
3. 2p An one-port element is fully described by:

a.) one and only one characteristic equation;
b.) at least one characteristic equation
39
c.) two and only two characteristic equations;

d.) at least two characteristic equations.
4. 2p A two-port element is fully described by:

a.) one and only one characteristic equation;
b.) at least one characteristic equation
c.) two and only two characteristic equations;
d.) at least two characteristic equations.
5. 2p The general form of a characteristic equation looks like:

 di dn i 
a.) E i, , K , n , θ1 , K , θp  = 0
 dt dt 
 di n
d i dv dmv 
b.) E i, , K , n , v, , K , m , θ1 , K , θp  = 0
 dt dt dt dt 
 dv m
d v 
c.) E v, , K , m , θ1 , K , θ p  = 0
 dt dt 
d.) E(i, v,) = 0
where θ1 ,K, θ p are non electric parameters.
6. 1p Let’s assume a signal written “a” that contains both DC and

AC components. The DC value of this signal is noted:
a.) At b.) AT c.) at d.) aT

AC components. The total instantaneous value of this signal is
noted:

AC components. The AC instantaneous value of this signal is
noted:

AC components. The AC amplitude of this signal is noted:
10. 2p Consider a signal (voltage or current) noted am(t). “Time

Domain Analysis”, also called “t Domain Analysis” may imply
40
a mathematical transform such as:

a.) a m ( t ) → a m ( t ) b.) a m (t) → − a m ( t)
c.) a m ( t ) → a m (− t ) d.) a m (t ) → − a m (−t )
11. 2p Consider a sine wave signal (voltage or current) noted

a m ( t ) = A m cos( ωt + ϕ) . “Phasor Analysis”, may imply a
mathematical transform (shorthand representation) such as:
a.) a m ( t ) = A m cos( ωt + ϕ) → A m = A m e − jϕ
b.) (
a m ( t ) = A m cos( ωt + ϕ) → A m = A m e jϕ + e − jϕ )
c.) a m ( t ) = A m cos( ωt + ϕ) → A m = A m e jϕ
(
d.) a m ( t ) = A m cos( ωt + ϕ) → A m = A m e jϕ − e − jϕ )
where:
a m ( t ) the signal;
Am transformation;
Am the amplitude of the signal am(t);
ω angular frequency

a m ( t ) = A m cos( ωt + ϕ) . “Phasor Analysis”, may imply a
mathematical transform (general representation) such as:
− jω − jϕ
a.) a m ( t ) = A m cos( ωt + ϕ) → A m = A m e e
b.) a m ( t ) = A m cos( ωt + ϕ) → A m = A m e jωe jϕ
c.) (
a m ( t ) = A m cos( ωt + ϕ) → A m = A m e jω + e jϕ )
d.) a m ( t ) = A m cos( ωt + ϕ) → A m = A m (e jω
−e − jϕ
)
where:
a m ( t ) the signal ;
Am transformation;
Am the amplitude of the signal am(t);
ω angular frequency
13. 3p Consider a signal (voltage or current) noted f(t). “Laplace
41
Analysis”, may imply a mathematical transform such as:

∞
a.) ∫
f ( t ) → F(s) = est f ( t )dt
0
∞
∫e
st
b.) f ( t ) → F(s) = f ( t )dt
−∞
∞
∫e
− st
c.) f ( t ) → F(s) = f ( t )dt
−∞
∞
d.) ∫
f ( t ) → F(s) = e − st f ( t )dt
0
14. 2p Figure 1 presents an one port element.
Figure 1
Both voltage and current are represented by two continuous
functions: v( t) = f ( t) and i( t ) = g( t ) . The static regime (DC
regime) assumes:
dkf dng
a.) k
= 0 ∀k ∈ N = 0 ∀n ∈ N
dt dt n
dkf dng
b.) ≅ 0 ∀k ∈ N ≅ 0 ∀n ∈ N
dt k dt n
 dkf dng 
c.) (∃k ∈ N or ∃n ∈ N) :  k ≠ 0 or n ≠ 0 
 dt dt 
 dkf d ng 
d.) (∃k ∈ N and ∃n ∈ N) :  k ≠ 0 or n ≠ 0 
 dt dt 
15. 2p Figure 1 presents an one port element. Both voltage and

current are represented by two continuous functions:
v( t ) = f ( t) and i( t ) = g( t ) . The quasi-static regime assumes:
dkf dng
a.) = 0 ∀k ∈ N = 0 ∀n ∈ N
dt k dt n
42
dkf dng
b.) ≅ 0 ∀k ∈ N ≅ 0 ∀n ∈ N
dt k dt n
 dkf dng 
c.) (∃k ∈ N or ∃n ∈ N) :  k ≠ 0 or n ≠ 0 
 dt dt 
 dkf d ng 
d.) (∃k ∈ N and ∃n ∈ N) :  k ≠ 0 or n ≠ 0 
 dt dt 

v( t ) = f ( t ) and i( t ) = g ( t ) . The dynamic regime assumes:
dkf dng
a.) = 0 ∀k ∈ N = 0 ∀n ∈ N
dt k dt n
dkf dng
b.) ≅ 0 ∀k ∈ N ≅ 0 ∀n ∈ N
dt k dt n
 dkf dng 
c.) (∃k ∈ N or ∃n ∈ N) :  k ≠ 0 or n ≠ 0 
 dt dt 
 dkf d ng 
d.) (∃k ∈ N and ∃n ∈ N) :  k ≠ 0 or n ≠ 0 
 dt dt 
17. 1p The symbol of an inductor is:
The characteristic equation is:

a.) v L ( t ) = Li L
b.) v L ( t ) = jωLi L
di L ( t )
c.) vL (t) = L
dt
1
d.) v L (t) = iL
jωL
18. 1p The symbol of an capacitor is:
43

1
a.) v C ( t ) = iC
jω C
di ( t )
b.) v C ( t ) = C C
dt
1
c.) v C ( t ) = iC
jω C
dv ( t )
d.) i C ( t ) = C C
dt
19. 1p The ANSI symbol for a voltage source is:
a.) b.)
c.) d.)
20. 1p The DIN symbol for a voltage source is:
a.) b.)
c.) d.)
21. 1p The ANSI symbol for a current source is:
a.) b.)
c.) d.)
22. 1p The DIN symbol for a current source is:
a.) b.)
44
c.) d.)
23. 1p The ANSI symbol for a voltage controlled voltage source is:
a.) b.)
c.) d.)
24. 1p The DIN symbol for a voltage controlled voltage source is:
a.) b.)
c.) d.)
25. 1p The ANSI symbol for a voltage controlled current source is:
a.) b.)
c.) d.)
26. 1p The DIN symbol for a voltage controlled current source is:
a.) b.)
c.) d.)
27. 1p The ANSI symbol for a current controlled voltage source is:
45
a.) b.)
c.) d.)
28. 1p The DIN symbol for a current controlled voltage source is:
a.) b.)
c.) d.)
29. 1p The ANSI symbol for a current controlled current source is:
a.) b.)
c.) d.)
30. 1p The DIN symbol for a current controlled current source is:
a.) b.)
c.) d.)
31 2p Kirchhoff’s Current Law states:

“The sum of the currents flowing into any node equals the
a.)
sum of the currents flowing out from that node.”
“The sum of the electromotive forces in any closed loop is
b.)
“The sum of the currents flowing into any loop equals the
c.)
sum of the currents flowing out from that loop.”
46
“The sum of the electromotive forces in any closed node is

d.)
equivalent to the sum of the voltage drops in that node.”
32 2p Kirchhoff’s Voltage Law states:

“The sum of the currents flowing into any node equals the
a.)
sum of the currents flowing out from that node.”
“The sum of the electromotive forces in any closed loop is
b.)
“The sum of the currents flowing into any loop equals the
c.)
sum of the currents flowing out from that loop.”
“The sum of the electromotive forces in any closed node is
d.)
equivalent to the sum of the voltage drops in that node.”
33 3p For the circuit presented below find the resistance “seen”

between A and B points:
a.) R = R1 b.) R = R1 + R 2
c.) R = R1 + R 3 d.) R = R1 + (R 2 R 3 )

a.) R = R1 b.) R = R1 + R 2
c.) R = R1 + (1 + k )R 3 d.) R = R1 + (R 2 R 3 )
35 5p For the circuit presented below find the voltage drop noted
“V”
47
(1 + k )(E1 − E)
a.) V=E+ R3
R 1 + (1 + k )R 3
(1 + k )( E1 − E)
b.) V=E+ R2
R 1 + (1 + k )R 3
E1
c.) V = E1 + (1 + kR 2 )
R 1 + (1 + k )R 3
E1
d.) V = E1 + (1 − kR 2 )
R 1 + (1 + k ) R 3
36 2p For the circuit presented below the Thevenin equivalence of

this circuit between A and B points is presented in figure
noted:
a. b.
c. d.
37 2p For the circuit presented below the Norton equivalence of this
48
circuit between A and B points is presented in figure noted:
a. b.
c. d.
38 5p Figure 1 presents a test circuit. The Thevenin equivalence

(between A, B points) of this circuit is presented in figure 2
Figure 1 Figure 2
The value of RAB is:
a.) R AB = R1 b.) R AB = R1 + R 2
c.) R AB = R1 + R 3 d.) R AB = R 1 + (R 2 R 3 )

49
Figure 3 Figure 4
The value of EAB0 is:
a.) E AB0 = E − IR 2 b.) E AB0 = E − IR 3
c.) E AB0 = E + IR 2 d.) E AB 0 = E + IR 3
40 5p Figure 5 presents a test circuit. The Norton equivalence

Figure 5 Figure 6
a.) R AB = R1 b.) R AB = R1 + R 2
c.) R AB = R1 + R 3 d.) R AB = R1 + (R 2 R 3 )

Figure 7 Figure 8
The value of Isc is:
a.) b.)
IR + E IR 2 − E
I ABsc = 2 I ABsc =
R2 + R3 R2 + R3
c.) d.)
IR − E IR 2 − E
I ABsc = 2 I ABsc =
R1 + R 3 R1 + R 2
42 3p Figure 9 presents a test circuit. The voltage drop across R3
50
resistor is:
Figure 9
a.) b.)
R3 R3
VR 3 = E VR 3 = E
R1 + R 2 R 3 R1 R 2 R 3
c.) d.)
R1 R 2 R3
VR 3 = E VR 3 = E
R1 R 2 R 3 R1 + R 2 + R 3
43 3p Figure 10 presents a test circuit. The current flowing through

R3 resistor is:
Figure 10
a.) b.)
R1 R 2 R3
IR3 = I I R3 = I
R 3 + R1 R 2 R1 R 2 R 3
c.) d.)
R1 R 2 R3
I R3 = I IR3 = I
R1 R 2 R 3 R1 + R 2 + R 3
44 3p Consider the circuit presented in figure 13. Write the

Kirchhoff’s equations according to time domain analysis
procedure.
a.) (1) i R ( t ) + i( t ) = i C ( t )
51
1
C∫
(I) e(t ) = Ri R (t ) − iC (t )dt
di( t ) 1
(II) 0 = −L
dt
+ v( t ) −
C ∫
i C ( t )dt
b.) (1) i R ( t ) + i( t ) = i C ( t )
1
C∫
(I) e(t ) = Ri R (t ) − iC (t )dt
di( t ) 1
(II) 0 = −L + v( t ) + ∫ i C ( t )dt
dt C
c.) (1) i R ( t ) + i(t ) = i C ( t )
1
(I) e(t ) = Ri R (t ) +
C ∫ i C ( t)dt
di( t ) 1
(II) 0 = −L
dt
+ v( t ) −
C∫ i C ( t )dt
d.) (1) i R ( t ) + i( t ) = i C ( t )
1
C∫
(I) e(t ) = Ri R (t ) − iC (t )dt
di( t ) 1
(II) 0 = − L − v (t ) + ∫ i C (t )dt
dt C
45 1p Phasor analysis is used for studying the electric circuits

containing sources:
a.) with sinusoidal inputs of variable frequencies
b.) with sinusoidal inputs of fixed frequencies
c.) with periodic input signal of fixed frequencies
d.) with periodic input signal of variable frequencies
46 4p Consider the circuit presented below. Write the Kirchhoff’s

equations according to Phasor analysis procedure.
a.) (1) I r (ω ) + I(ω ) = I c (ω )

1
(I) E(ω) = R I r (ω) − Ic (ω)
j ωC
52
1
(II) 0 = − jωLI(ω ) + V(ω ) − I c (ω )
j ωC
b.) (1) I r (ω ) + I(ω ) = I c (ω )
1
(I) E(ω) = R I r (ω) + I c (ω)
jωC
1
( II) 0 = − jωLI(ω) − V(ω) − I c (ω)
jωC
c.) (1) I r (ω ) + I(ω ) = I c (ω )
1
(I) E(ω) = R I r (ω) + I c (ω)
jωC
1
(II) 0 = − jωLI(ω) − V(ω) + I c (ω)
jωC
d.) (1) I r (ω ) + I(ω ) = I c (ω )
1
(I) E(ω ) = R I r (ω ) + I c (ω )
j ωC
1
(II) 0 = − jωLI(ω ) + V(ω ) − I c (ω )
j ωC
47 1p Laplace analysis is used for studying the electric circuits

containing sources:
a.) with sinusoidal inputs of variable frequencies
b.) with sinusoidal inputs of fixed frequencies
c.) that generate arbitrary signals of fixed frequencies
d.) that generate arbitrary signals of variable frequencies
48. 3p Consider the circuit presented below. Write the Kirchhoff’s

equations according to Laplace analysis procedure
a.) (1) I r (s) + I(s) = I c (s)

1
(I) E (s) = RI r (s) − Ic (s) 1.52)
sC
1
(II) 0 = sLI(s) + V (s) − I c (s)
sC
53
b.) (1) I r (s) + I(s) = I c (s)

1
(I) E(s) = RI r (s) + I c (s ) 1.52)
sC
1
(II) 0 = sLI(s) + V (s) − I c (s)
sC
c.) (1) I r (s) + I(s) = I c (s)
1
(I) E(s) = RI r (s) + I c (s) 1.52)
sC
1
(II) 0 = −sLI(s) + V(s) + I c (s)
sC
d.) (1) I r (s) + I(s) = I c (s)
1
(I) E(s) = RI r (s) + I c (s) 1.52)
sC
1
(II) 0 = −sLI(s) + V(s) − I c (s )
sC
49 2p The mathematical model associated with “z” parameters is:

V1 (s) = z11 (s)I1 (s) + z12 (s)I 2 (s)
V2 (s) = z 21 (s)I1 (s) + z 22 (s)I 2 (s)
The matrix form of this model is:
a.)  V1 (s)   z11 (s) z12 (s)   I1 (s) 
V (s)  = z (s) ×
z 22 (s)   I 2 (s)
 2   21
b.) V2 (s)   z11 (s) z12 (s)   I1 (s) 
 V (s)  = z (s) ×
z 22 (s)  I 2 (s)
 1   21
c.)  V1 (s)   z11 (s) z12 (s)  I 2 (s)
V (s)  = z (s) ×
z 22 (s)   I1 (s) 
 2   21
d.)  V1 (s)   z11 (s) z12 (s)   I1 (s) 
V (s)  = z (s) ×
z 21 (s)   I 2 (s) 
 2   22
50 2p The mathematical model associated with “y” parameters is:

I1 (s) = y11 (s)V1 (s) + y12 (s) V2 (s)
I 2 (s) = y 21 (s) V1 (s) + y 22 (s)V2 (s)
54
a.) I 2 (s)  y11 (s) y12 (s)   V1 (s) 

 I (s)  =  y (s) y (s) ×  V (s)
 1   21 22   2 
b.)  I1 (s)   y11 (s) y12 (s)   V1 (s) 
 I (s)  =  y (s) y (s)  ×  V (s)
 2   21 22   2 
c.)  1   11
I (s ) y (s ) y12 (s )  V2 (s)
I (s) =  y (s) y (s)  ×  V (s) 
 2   21 22   1 
d.)  I1 (s)   y11 (s) y 21 (s)   V1 (s) 
I (s) =  y (s) y (s)  × V (s)
 2   12 22   2 
51 2p The mathematical model associated with “h” parameters is:

V1 (s) = h11 (s)I1 (s) + h 12 (s)V2 (s)
I 2 (s) = h 21 (s) I1 (s) + h 22 (s)V2 (s)
a.) V1 (s)  h11 (s) h12 (s)   I1 (s) 
 = × 
 I 2 (s)  h 21 (s) h 22 (s) V2 (s)
b.) V1 (s)  h11 (s) h 12 (s)   I 2 (s) 
 I (s)  =  h (s) h (s) × V (s )
 2   21 22   1 
c.) V1 (s)  h11 (s) h12 (s)   I1 (s) 
 = ×  
 I 2 (s)  h 21 (s) h 22 (s) V2 (s)
d.)  V1 (s)  h11 (s) h 21 (s)   I1 (s) 
 I (s)  = h (s) h (s)  ×  V (s) 
 2   12 22   2 
52 2p The mathematical model associated with “g” parameters is:

I1 (s) = g11 (s)V1 (s) + g12 (s)I 2 (s)
V2 (s) = g 21 (s)V1 (s) + g 22 (s)I 2 (s)
a.)  I 2 (s)   g11 (s) g12 (s)  V2 (s)
 V (s) = g (s) ×
g 22 (s)  I1 (s) 
 1   21
b.)  I1 (s)   g11 (s) g12 (s)  V2 (s)
 V (s) = g (s) ×
g 22 (s)  I 2 (s) 
 1   21
c.)  I1 (s)   g11 (s) g 21 (s)   V1 (s)
 V (s)  = g (s) ×
g 22 (s)   I 2 (s) 
 2   12
55
d.)  I1 (s)   g11 (s) g12 (s)   V1 (s) 

 V (s) = g (s) g (s)  ×  I (s) 
 2   21 22   2 
53 2p The mathematical model associated with “a” parameters is:

V1 (s) = A(s)V2 (s) − B(s)I 2 (s)
I1 (s) = C(s)V2 (s) − D(s) I 2 (s)
a.) V1 (s)   A(s) B(s)   V2 (s) 
 I (s)  =  C(s) ×
D(s)   − I 2 (s)
 1  
b.)  V1 (s)  A(s) B(s)   V2 (s) 
 I (s)  =  C(s) ×
D(s)  I 2 (s) 
 1  
c.) V1 (s) A (s) B(s)  − V2 (s)
 I (s)  =  C(s) ×
D(s)  − I 2 (s) 
 1  
d.) − V1 (s)   A(s) B(s)   V2 (s) 
 I (s)  =  C(s) ×
D(s)   − I 2 (s) 
 1  
54 2p The mathematical model associated with “b” parameters is:

V2 (s) = A' (s) V1 (s) − B' (s) I1 (s)
− I 2 (s) = C' (s)V1 (s) − D' (s)I1 (s)
a.) V2 (s) A ' (s) B' (s)  V1 (s)
 I (s)  =  C' (s) D' (s)  ×  I (s) 
 2     1 
b.)  V2 (s)  A ' (s) B' (s)   V1 (s) 
− I (s)  =  C' (s) D' (s) × − I (s) 
 2     1 
c.)  V2 (s)   A' (s ) B' (s)  − V1 (s)
 − I (s)  =  C' (s ) D' (s) ×  I (s ) 
 2     1 
d.)  V2 (s)   A' (s) B' (s)   V1 (s) 
 − I (s)  =  C' (s) D' (s)  ×  I (s) 
 2     1 

V1 (s) = z11 (s)I1 (s) + z12 (s)I 2 (s)
V2 (s) = z 21 (s)I1 (s) + z 22 (s)I 2 (s)
The electrical model associated with this mathematical model
56
is:
a.)
b.)
c.)
d.)

I1 (s) = y11 (s)V1 (s) + y12 (s) V2 (s)
I 2 (s) = y 21 (s) V1 (s) + y 22 (s)V2 (s)
is:
a.)
b.)
57
c.)
d.)

V1 (s) = h11 (s)I1 (s) + h 12 (s)V2 (s)
I 2 (s) = h 21 (s) I1 (s) + h 22 (s)V2 (s)
is:
a.)
b.)
c.)
d.)

I1 (s) = g11 (s)V1 (s) + g12 (s)I 2 (s)
58
V2 (s) = g 21 (s)V1 (s) + g 22 (s)I 2 (s)

is:
a.)
b.)
c.)
d.)
59 4p For “z” parameters of a diport the input variables are:

a.) {I1(s), I2(s)} c.) {I1(s), V2(s)}
b.) {V1(s), V2(s)} d.) {V1(s), I2(s)}
60 4p For “y” parameters of a diport the input variables are:

a.) {I1(s), I2(s)} c.) {I1(s), V2(s)}
b.) {V1(s), V2(s)} d.) {V1(s), I2(s)}
61 4p For “h” parameters of a diport the input variables are:

a.) {I1(s), I2(s)} c.) {I1(s), V2(s)}
b.) {V1(s), V2(s)} d.) {V1(s), I2(s)}
62 4p For “g” parameters of a diport the input variables are:

a.) {I1(s), I2(s)} c.) {I1(s), V2(s)}
b.) {V1(s), V2(s)} d.) {V1(s), I2(s)}
63 4p For “z” parameters of a diport the output variables are:
59
a.) {I1 (s), I2(s)} c.) {I1(s), V2(s)}

b.) {V1(s), V2(s)} d.) {V1(s), I2(s)}
64 4p For “y” parameters of a diport the output variables are:

a.) {I1 (s), I2(s)} c.) {I1(s), V2(s)}
b.) {V1(s), V2(s)} d.) {V1(s), I2(s)}
65 4p For “h” parameters of a diport the output variables are:

a.) {I1 (s), I2(s)} c.) {I1(s), V2(s)}
b.) {V1(s), V2(s)} d.) {V1(s), I2(s)}
66 4p For “g” parameters of a diport the output variables are:

a.) {I1 (s), I2(s)} c.) {I1(s), V2(s)}
b.) {V1(s), V2(s)} d.) {V1(s), I2(s)}
60
Answers
1. 1p A generic symbol for an one-port element is presented in

figure:
Correct answer b.)
2. 1p A generic symbol for a two-port element is presented in

figure:
Correct answer d.)
3. 2p An one-port element is fully described by:

Correct answer a.)
4. 2p A two-port element is fully described by:

Correct answer c.)
5. 2p A characteristic equation looks like:

Correct answer b.)

AC components. The DC value of this signal is noted:
Correct answer b.)

AC components. The total instantaneous value of this signal
is noted:
Correct answer d.)

AC components. The AC instantaneous value of this signal is
noted:
Correct answer c.)

AC components. The AC amplitude of this signal is noted:
Correct answer a.)
10. 2p Consider a signal (voltage or current) noted a m(t). “Time

Domain Analysis”, also called “t Domain Analysis” may
imply a mathematical transform such as:
61
Correct answer a.)

a m ( t ) = A m cos( ωt + ϕ) .
“Phasor Analysis”, may imply a mathematical transform
(shorthand representation) such as:
Correct answer c.)

a m ( t ) = A m cos( ωt + ϕ) .
“Phasor Analysis”, may imply a mathematical transform
(general representation) such as:
Correct answer b)
13. 3p Consider a signal (voltage or current) noted f(t). “Laplace

Analysis”, may imply a mathematical transform such as:
Correct answer d.)
14. 2p Figure 1 presents an one port element.
Figure 1
Both voltage and current are represented by two continuous
functions: v( t ) = f ( t) and i( t ) = g( t ) . The static regime (DC
regime) assumes:
Correct answer a.)

v( t ) = f ( t) and i( t ) = g ( t ) . The quasi-static regime assumes:
Correct answer b.)

v( t ) = f ( t ) and i( t ) = g ( t ) . The dynamic regime assumes:
Correct answer c.)
17. 1p The symbol of an inductor is:
62

Correct answer c.)
18. 1p The symbol of an capacitor is:

Correct answer d.)
19. 1p The ANSI symbol for a voltage source is:

Correct answer a.)
20. 1p The DIN symbol for a voltage source is:

Correct answer b.)
21. 1p The ANSI symbol for a current source is:

Correct answer c.)
22. 1p The DIN symbol for a current source is:

Correct answer d.)
23. 1p The ANSI symbol for a voltage controlled voltage source is:
Correct answer a.)
24. 1p The DIN symbol for a voltage controlled voltage source is:
Correct answer b.)
25. 1p The ANSI symbol for a voltage controlled current source is:
Correct answer c.)
26. 1p The DIN symbol for a voltage controlled current source is:
Correct answer d.)
27. 1p The ANSI symbol for a current controlled voltage source is:
Correct answer a.)
28. 1p The DIN symbol for a current controlled voltage source is:
63
Correct answer b.)
29. 1p The ANSI symbol for a current controlled current source is:
Correct answer c.)
30. 1p The DIN symbol for a current controlled current source is:
Correct answer d.)
31 2p Kirchhoff’s Current Law states:

Correct answer a.
32 2p Kirchhoff’s Voltage Law states:

Correct answer b.)

Correct answer c.)

Solution: ”R” may be calculated using the circuit presented
below:
Observation: Current source “I” was replaced by an open circuit

and voltage source “E” was replaced by a short circuit.
In these conditions:
E
R= T
IT
Where:
ET-test source
IT the current generated by the source test
Solving the circuit IT is:
ET
IT =
R1 + R 3
64
And by consequence:
R = R1 + R 3

Correct answer c.)

Solution: ”R” may be calculated using the circuit presented
below:
Observation: Voltage source “E” was replaced by a short circuit.

E
R= T
IT
Where:
ET - test source
IT - the current generated by the source test
Solving the circuit one obtains:
(1) I T + kI T = I R 3
(I) E T = I T R1 − kI T R 2 + V
(II) 0 = I R 3R 3 − V + kI T R 2
Solving the system of equations “IT” becomes:
ET
IT =
R 1 + (1 + k ) R 3
And by consequence:
R = R1 + kR 3
35 5p For the circuit presented below find the voltage drop noted
65
“V”
Correct answer a.)

Solution: ”V” may be calculated in two steps:
First: Solving the circuit;
Second: The calculation of voltage drop “V”
using the algorithm in section 1.2.4 c.
First step: Solve the circuit
The system of equations is:

(1) I + kI = I R 3
(I) E1 = IR1 − kIR 2 + VI
(II) − E = I R 3R 3 − VI + kIR 2
Solving the system of equations one obtains:
E1 − E
I=
R1 + (1 + k ) R 3
(1 + k )( E1 − E )
IR3 =
R1 + (1 + k ) R 3
E1 − E
VI = E1 − ( R1 − kR 2 )
R 1 + (1 + k )R 3
Second step: The calculation of voltage drop “V” may be made
using the circuit presented below:
The TK2 must be written on red mesh:
66
E = V − I R 3R 3
And finally:
(1 + k )(E1 − E)
V=E+ R3
R 1 + (1 + k )R 3
36 2p For the circuit presented below the Thevenin equivalence of

noted:
Correct answer a.)
37 2p For the circuit presented below the Norton equivalence of

noted:
Correct answer c.)

Figure 1 Figure 2
Correct answer c
Solution: ”RAB” may be calculated using the circuit presented
below:
67

E
R AB = T
IT
Where:
ET- test source
ET
IT =
R1 + R 3
And by consequence:
R AB = R 1 + R 3

Figure 3 Figure 4
The value of EAB0 is:
Correct answer d.)
Solution: The algorithm presented in section 1.2.4 f.) must be
applied:
EAB0 calculation: EAB0 may be calculated using the circuit
presented below:
68
Step one: Solve the circuit presented below:

Observing that:
I R1 = 0
IR3 = I
On the red mesh may be written
− E = − V + IR 2 + IR 3
By consequence:
V = E + I( R 2 + R 3 )
I R1 = 0
IR3 = I
Step two: Calculate EAB0: The circuit used is:
On the red mesh one can write:

0 = I R1R 1− IR 2 + V − E AB0
Finally:
E AB 0 = E + IR 3
69
Figure 5 Figure 6
Correct answer c.)
Solution: The algorithm presented in section 1.2.4 e.) must be
applied:
”RAB” may be calculated using the circuit presented below:

E
R AB = T
IT
Where:
ET- test source
ET
IT =
R1 + R 3
And by consequence:
R AB = R 1 + R 3

Figure 7 Figure 8
70
The value of Isc is:

Correct answer b.)
Solution: ”Isc” may be calculated using the circuit presented
below:

(1) I ABsc + I = I R 3
(I) 0 = I ABsc R 1 − IR 2 + V
(II) − E = I R 3R 3 − V − IR 2
The solution is:
IR 2 − E
I ABsc =
R2 + R3
42 3p Figure 9 presents a test circuit. The voltage drop across R3

resistor is:
Figure 9
Correct answer d.)
Solution: ”VR3” may be calculated using the circuit presented
below:

E = IR 1 + IR 2 + IR 3
The solution is:
71
E
I=
R1 + R 2 + R 3
By consequence:
R3
VR 3 = IR 3 = E
R1 + R 2 + R 3
43 3p Figure 10 presents a test circuit. The current flowing

through R3 resistor is:
Figure 10
Correct answer a.)
Solution: ”VR3” may be calculated using the circuit presented in
figure 11
Figure 11
In order to simplify the mathematical solution of the circuit
presented in figure 11, this one may redrawn as figure 12 shows:
Figure 12
where :
R 1R 2
R12 =
R1 R 2
By consequence according to (1.19) the current flowing through
R3 resistor is:
72
R1 R 2
IR3 = I
R 3 + R1 R 2
44 3p Consider the circuit presented in figure 13. Write the

Kirchhoff’s equations according to time domain analysis
procedure.
Correct answer a.)
45 1p Phasor analysis is used for studying the electric circuits

containing sources:
Correct answer b.)
46 4p Consider the circuit presented below. Write the Kirchhoff’s

equations according to Phasor analysis procedure.
Correct answer d.)
47 1p Laplace analysis is used for studying the electric circuits

containing sources:
Correct answer c.)
48. 3p Consider the circuit presented below. Write the Kirchhoff’s

equations according to Laplace analysis procedure
73
Correct answer d.)

V1 (s) = z11 (s)I1 (s) + z12 (s)I 2 (s)
V2 (s) = z 21 (s)I1 (s) + z 22 (s)I 2 (s)
Correct answer a.)

I1 (s) = y11 (s ) V1 (s) + y12 (s ) V2 (s )
I 2 (s) = y 21 (s) V1 (s) + y 22 (s)V2 (s)
Correct answer b.)

V1 (s) = h11 (s)I1 (s) + h 12 (s)V2 (s)
I 2 (s) = h 21 (s) I1 (s) + h 22 (s)V2 (s)
Correct answer c.)

I1 (s) = g11 (s)V1 (s) + g12 (s)I 2 (s)
V2 (s) = g 21 (s)V1 (s) + g 22 (s)I 2 (s)
Correct answer d.)
53 2p The mathematical model associated with “a” parameters is:

V1 (s) = A(s)V2 (s) − B(s)I 2 (s)
I1 (s) = C(s)V2 (s) − D(s)I 2 (s)
Correct answer a.)
54 2p The mathematical model associated with “b” parameters is:

V2 (s) = A' (s) V1 (s) − B' (s) I1 (s)
− I 2 (s) = C' (s)V1 (s) − D' (s)I1 (s)
Correct answer d.)
74
V1 (s) = z11 (s)I1 (s) + z12 (s)I 2 (s)

V2 (s) = z 21 (s)I1 (s) + z 22 (s)I 2 (s)
The electrical model associated with this mathematical
model is:
Correct answer a.)

I1 (s) = y11 (s)V1 (s) + y12 (s) V2 (s)
I 2 (s) = y 21 (s) V1 (s) + y 22 (s)V2 (s)
model is:
Correct answer a.)

V1 (s) = h11 (s)I1 (s) + h 12 (s)V2 (s)
I 2 (s) = h 21 (s) I1 (s) + h 22 (s)V2 (s)
model is:
Correct answer b.)

I1 (s) = g11 (s)V1 (s) + g12 (s)I 2 (s)
V2 (s) = g 21 (s)V1 (s) + g 22 (s)I 2 (s)
model is:
Correct answer c.)
59 4p For “z” parameters of a diport the input variables are:

Correct answer a.)
60 4p For “y” parameters of a diport the input variables are:

Correct answer b.)
61 4p For “h” parameters of a diport the input variables are:

Correct answer c.)
62 4p For “g” parameters of a diport the input variables are:

Correct answer d.)
75
63 4p For “z” parameters of a diport the output variables are:

Correct answer b.)
64 4p For “y” parameters of a diport the output variables are:

Correct answer a.)
65 4p For “h” parameters of a diport the output variables are:

Correct answer d.)
66 4p For “g” parameters of a diport the output variables are:

Correct answer c.)
76
Operating Regimes
Usual Models for the Main Electronic
Components
DC Operating Points Analysis
Large Signal Analysis (DC Sweep Analysis)
Small Signal Analysis
Chapter 2
The electronic device theory deals with the presentation of the so called
“electronic components and devices”. In fact, the chapter treats only the major
components such as:
diodes,
bipolar junction transistors, and
field effect transistors.
The presentation is focused on the behavior of these major components. Each

device is analyzed considering large signal quasi-static regime, small signal
quasi-static regime and small signal dynamic regime. Mathematical models and
equivalent circuits are presented. Starting from these models, two type of
analysis are described:
large signal quasi-static regime analysis with two components:
• DC operating points;
• transfer characteristic;
small signal quasi-static regime (middle band).
The outline of this chapter is:
2.1 Operating Regimes

2.1.1 Quasi-static Large Signal Regime
2.1.2 Quasi-static Small Signal Regime
2.1.3 Dynamic Large Signal Regime
2.1.4 Dynamic Small Signal Regime
2.2 Usual Models for the Main Electronic Components

2.2.1 Usual Models for P-N Diodes
2.2.2 Usual Models for Bipolar Junction Transistor
77
2.2.3 Usual Models for Field Effect Transistor
2.3 DC Operating Point Analysis

2.3.1 Diode Circuits
2.3.2 Bipolar Junction Transistor Circuits
2.3.3 Field Effect Transistor Circuits
2.4 Large Signal Analysis (DC Sweep Analysis)

2.5 Small Signal Analysis (Middle Band Analysis)

2.1 Operating Regimes

The classification of the operating modes may be made started from the
“characteristic equation”. The (1.1) relationship presents such a formula. Once
again this equation is presented in the following:
 di dn i dv dm v 
E i T , T ,K, nT , v T , T ,K, mT , θ1 ,K,θ p  = 0 (1.1)
 dt dt dt dt 
Starting from this formula the four operating modes (operating regimes) must
be defined as follows:
2.1.1 Quasi-static Large Signal Regime
Taking into account the restrictions imposed by this type of regime, the (1.1)
( )
E i T , v T , θ1 ,K,θ p = 0 (2.1)
where
iT total instantaneous value of the current
vT total instantaneous value of the voltage
θ1 ,…,θp non-electric parameters
78
2.1.2 Quasi-static Small Signal Regime
Taking into account the restrictions imposed by this type of regime, the (1.1)
v t = ri t (2.2)
where:
it AC instantaneous value of the current;
vt AC instantaneous value of the voltage
r Differential resistance of the electronic device
2.1.3 Dynamic Large Signal Regime
Dynamic system analysis is done considering only the first derivative of the
voltage. In this condition the (1.1) relationship becomes:
 dv 
E  i T , v T , T , θ 1 , K, θ p  = 0 (2.3)
 dt 
where
iT total instantaneous value of the current
vT total instantaneous value of the voltage
θ1,…,θp non-electric parameters
2.1.4 Dynamic Small Signal Regime
In this condition, (1.1) relationship becomes:

1
v t = ri t +
C ∫
i t dt (2.4)
where
it AC instantaneous value of the current;

vt AC instantaneous value of the voltage;
r Differential resistance of the electronic
device;
C Differential capacitance of the electronic
device.
79
2.2 Usual Models for the Main Electronic Components

As it was mentioned, any type of electronic circuits may be analyzed following
three steps. The first one is “Modeling of the electronic devices”. At this step,
the electronic device is replaced by its model. The electronic circuit becomes a
simply electrical circuit. This new circuit is usually named modeled circuit. One
says that electronic problem is reduced to an electrical problem”. That is why it
is necessary to present the usual models for the main electronic components.
The section deals with P-N diodes, bipolar junction transistor and field effect
transistor.
2.2.1 Usual Models for P-N Diodes
Table 2.1 presents the equivalent circuit for diodes operating in quasi-static
large signal regime.
Large signal
Symbol
quasi-static regime
Symbol ANSI First Order Model First Order Model

(Conduction) (Cut-off)
Symbol DIN
Zero Order Model Zero Order Model
(Conduction) (Cut-off)
Table 2.1 Diode models for large signal quasi-static regime - first and second order
Observation: RA has a small value (smaller than 100 Ώ)

RR has a high value (greater than 1 MΏ)
Table 2.2 presents the equivalent circuit for diodes operating both in quasi-static
small signal regime and dynamic small signal regime.
80
Small signal Small signal

Symbol
quasi-static regime dynamic regime
Symbol ANSI
Symbol DIN
Table 2.2 Diode models for small signal quasi-static regime
2.2.2 Usual Models for Bipolar Junction Transistor
Table 2.3 presents both the equivalent circuit and mathematical models for npn
bipolar junction transistor and pnp bipolar junction transistor operating in quasi-
static large signal regime, working in active region. The second order models
for npn transistor are presented.
Large signal, quasi-static regime. Active region

Symbol
Second order model
Equivalent Circuit Mathematical Model
IS v 
iB = exp  BE 
β  VT 
iC = β i B
BJT current controlled BJT current controlled
(Π Model) (Π Model)
IS v 
iB = exp  BE 
Symbol ANSI β  VT 
v 
i C = IS exp  BE 
 VT 
BJT voltage controlled BJT voltage controlled
Symbol DIN
IS v 
iE = exp  BE 
α  VT 
iC = α i E
81

Symbol
Second order model
(T Model) (T Model)
IS v 
iE = exp  BE 
α  VT 
v 
i C = I S exp  BE 
 VT 
(T Model) (T Model)
Table 2.3 NPN Bipolar Junction Transistor
Large signal, quasi-static regime. Active region; Second order models
Table 2.4 presents both the equivalent circuit and mathematical models for pnp
bipolar junction transistor operating in quasi-static large signal regime, working
in active region. The second order models for pnp transistor are presented.

Symbol
Second order model
IS v 
iB = exp  EB 
β  VT 
Symbol ANSI iC = β i B
IS v 
iB = exp  EB 
β  VT 
v 
i C = IS exp  EB 
 VT 
82

Symbol
Second order model
IS v 
iE = exp  EB 
α  VT 
iC = α i E
Symbol DIN

(T Model) (T Model)
IS v 
iE = exp  EB 
α  VT 
v 
i C = I S exp  EB 
 VT 
(T Model) (T Model)
Table 2.4 PNP Bipolar Junction Transistor
Large signal, quasi-static regime; Active region; Second order models
Table 2.5 presents both the equivalent circuit and the mathematical models for
npn bipolar junction transistor operating in quasi-static large signal regime,
working in active region. The first and zero order models for npn transistor are
presented.

Symbol
First order model; Zero order model
VBE = const .
iC = β iB
Symbol ANSI
First Order Model First Order Model

83

Symbol
VBE = const .
Symbol DIN iC = α i E

(T Model) (T Model)
VBE = const .
iC ≅ iE

(T Model) (TModel)
Large signal, quasi-static regime. Active region; First and zero order models
pnp bipolar junction transistor operating in quasi-static large signal regime,
working in active region. The first and zero order models for pnp transistor are
presented.

Symbol
VEB = const .
iC = β iB
Symbol ANSI
84

Symbol
VEB = const .
Symbol DIN iC = α i E

(T Model) (T Model)
VEB = const .
iC ≅ iE

(T Model) (T Model)
Large signal, quasi-static regime. Active region; First and zero order models
working in saturation region. The first and zero order models for npn transistor
are presented.
Large signal, quasi-static regime. Saturation region
Symbol
VBE = VBEsat
VCE = VCEsat
Symbol ANSI
VBE ≅ 0
VCE ≅ 0
Symbol DIN Zero Order Model Zero Order Model
Large signal, quasi-static regime. Saturation region; First and zero order models
85
working in saturation region. The first and zero order models for npn transistor
are presented.
Large signal, quasi-static regime. Saturation region

Symbol
VEB = VEBsat
VEC = VECsat
Symbol ANSI
VEB ≅ 0
VEC ≅ 0
Large signal, quasi-static regime. Saturation region; First and zero order models
working in cut-off region. The zero order models for npn transistor are
presented.
Large signal, quasi-static regime. Cut off region

Symbol
Zero order model
Symbol ANSI iB ≅ 0
iC ≅ 0

Small signal, quasi-static regime. Cut-off region; Zero order model
86
working in cut-off region. The zero order models for pnp transistor are
presented.
Large signal, quasi-static regime. Cut off region

Symbol
Zero order model
Symbol ANSI iB ≅ 0
iC ≅ 0

Small signal, quasi-static regime. Cut-off region; Zero order model
npn bipolar junction transistor operating in small signal regime, working in
active region.
Small signal, quasi-static regime.

Symbol
Π model; T model
Vbe
Ib =
rπ
I c = g m Vbe
Symbol ANSI
Π Model Π Model
JBT voltage controlled JBT voltage controlled
Vbe
Ib =
rπ
Ic = β I b
Symbol DIN Π Model Π Model
JBT current controlled JBT current controlled
87

Symbol
Π model; T model
Vbe
Ie =
re
I c = g m Vbe
T Model T Model
Vbe
Ie =
re
Ic = α Ie
T Model T Model
Small signal, quasi-static regime. Π model; T model
pnp bipolar junction transistor operating in small signal regime, working in
active region.

Symbol
Π model; T model
Veb
Ib =
rπ
I c = g m Veb
Symbol ANSI Π Model Π Model
JBT voltage controlled JBT voltage controlled
Veb
Ib =
rπ
Ic = β I b
Symbol DIN
Π Model Π Model
88

Symbol
Π model; T model
Veb
Ie =
re
I c = g m Veb
T Model T Model
Veb
Ie =
re
Ic = α Ie
T Model T Model
Small signal, quasi-static regime. Π model; T model
npn bipolar junction transistor operating in dynamic regime, working in active
region.
Small signal,
Symbol
dynamic regime.
Equivalent circuit Mathematical Model
Giacoletto Equivalent Circuit Giacoletto Equivalent Circuit

Symbol ANSI
89
Small signal,
Symbol
dynamic regime.
Π model
Vbe = h ie I b + h re Vce
I c = h fe I b + h oe Vce
Symbol DIN H parameter model H parameter model
Small signal, dynamic regime. Giacoletto model; Π model and H parameter model
Notes:
• 'e' because it is a common-emitter topology
• hie– The input impedance of the transistor (corresponding to the
base resistance rπ).
• hre– Represents the dependence of the transistor's IB– VBE curve on
the value of VCE. It is usually very small and is often neglected
(assumed to be zero).
• hfe– The current-gain of the transistor. This parameter is often
specified as hFE or the DC current-gain (βDC) in datasheets.
• hoe– The output impedance of transistor. This term is usually
specified as an admittance and has to be inverted to convert it to an
impedance.
2.2.3. Field Effect Transistor (FET) Models
Table 2.14 presents the symbols of the principal types of field effect transistors:
N-channel P-channel
Symbol ANSI Symbol DIN Symbol ANSI Symbol DIN
JFET
D-MOSFET
D-MOSFET
(no bulk)
90
E-MOSFET
E-MOSFET
(no bulk)
Table 2.14 Field Effect Transistor Symbols
Table 2.15a presents both the equivalent circuit and the mathematical models
for a field effect transistor (D-MOSFET or E-MOSFET) operating in large
signal regime, working in saturation region (n channel).
Large signal, quasi-static regime.

iG = 0
β
iD = (v GS − VT )2
2
Saturation region Saturation region
iG = 0
v DS
iD =
R
1
R≅
β(v GS − VT )
Linear region Linear region
iG = 0
iD = 0
Cut-off region Cut-off region

Table 2.15a N channel Field Effect Transistor
Large signal, quasi-static regime
Table 2.15b presents both the equivalent circuit and the mathematical models
for junction field effect transistor (JFET) operating in large signal regime,
working in saturation region (n channel).
91

iG = 0
2
 v 
i D = I DSS 1 − GS 
 VT 
iG = 0
v DS
iD =
R
1
R≅
I DSS
(v GS − VT )
VT2
iG = 0
iD = 0

Table 2.15b N channel Junction Field Effect Transistor
Table 2.16a presents both the equivalent circuit and the mathematical models
for a field effect transistor (D-MOSFET or E-MOSFET) operating in large
signal regime, working in saturation region (p channel).

iG = 0
β
iD = (vSG − VT )2
2
iG = 0
1
iD = v SD
R
1
R=
β(v SG − VT )
92

iG = 0
iD = 0

Table 2.16a P channel Field Effect Transistor
Table 2.16b presents both the equivalent circuit and the mathematical models
for junction field effect transistor (JFET) operating in large signal regime,
working in saturation region (p channel)

iG = 0
2
 v 
i D = I DSS 1 − SG 
 VT 
iG = 0
v DS
iD =
R
1
R≅
I DSS
(vSG − VT )
VT2
iG = 0
iD = 0

Table 2.16b P channel Junction Field Effect Transistor
junction field transistor operating in small signal regime, working in saturation
region (n channel).
93

Ig = 0
I d = g m Vgs
2i D
gm =
v GS − VT QP
N channel N channel
Ig = 0
I d = g m Vsg
2i D
gm =
v SG − VT QP
P channel P channel
Table 2.17 Field Effect Transistor Small Signal Regime.
Small signal, quasi-static regime
2.3 DC Operating Point Analysis

As it was mentioned above, any type of circuit analysis follows three steps:
1. Model the electronic devices. At this step, the electronic device is

replaced by its model. The electronic circuit becomes a simply
electrical circuit. This new circuit is usually named modeled circuit.
One says that electronic problem is reduced to an electrical
problem.
2. Solve the modeled circuit. The modeled circuit is analyzed
according to operation regime using the convenient technique
(Kirchhoff, Laplace, etc…). One obtains a system of equations.
One says that electrical problem is reduced to an algebraic
problem
3. Solve the algebraic problem.
Observation: DC analysis must be made using “large signal models” for

the components.
94
2.3.1 DC Operating Point Analysis - Diode Circuits
The section presents the way to apply this type of analysis for circuits
containing diodes and also circuits containing bipolar junction transistors.
In case of diode circuits an additional problem appears. A diode may be forward

biased or reverse biased and by consequence the large-signal model must be
chosen according to this constraint. The algorithm of testing the diode state is:
1. Suppose that diode is forward biased;
2. Model the circuit according to this hypotheses;
3. Determine the current through the diode;
4. Compare the current value with zero:
if current is greater than zero the hypotheses was right
if current is smaller than zero the hypotheses was wrong
There is also possible another algorithm:
1. Suppose that diode is reverse bias;
2. Model the circuit according to this hypotheses;
3. Determine the voltage across the diode;
4. Compare the voltage value with zero:
if voltage is smaller than zero the hypotheses was right
if voltage is greater than zero the hypotheses was wrong
In conclusion, in diode case, the state of the diode must be established. After
that, the general algorithm may be applied.
Example
Problem formulation. For the circuit below the operating point for the
diode {IA, VA} must be calculated.
Figure 2.1 Example circuits

Solution
I. The test of the diode state. The zero order model for the diode will be used.
a.) One supposes that the diode is reverse biased. That means that the diode
will be replaced as figure 2.2 shows:
95
Figure 2.2 The model of a diode reversed biased, zero order model.
b). One models the circuit. The schematic diagram from figure 2.1 is modeled
as figure 2.3 exposes.
Figure 2.3 The modeled circuit, considering the diode reverse biased.
c.). One solves the circuit.
Observing that
IA = 0 (2.5)
The circuit presented in figure 2.4 may be simplified – see figure 2.4
Figure 2.4 The simplified circuit

According to Kirchhoff theorems, the system of equations associated to this
circuit is:
I E = I + II (2.6)
0 = IIR I − V (2.7)
E = II R I + I E R E (2.8)
The unknown variables are {V, II, IE}. Solving the (2.6)÷(2.8) system one
obtains:
E − IR E (2.9)
V= R I
RI + RE
E − IR E (2.10)
II =
RI + RE
E − IR E (2.11)
IE = I +
RI + RE
d.). One compares the voltage drop across the diode “VA” with “0”.
96
In order to calculate the voltage drop across the diode the circuit presented in
figure 2.5 is used:
Figure 2.5 The circuit used for VA calculation.
Applying TK2 on the red mesh one finds:

V − VA = 0 (2.12)
By consequence:
VA = V (2.13)
and yet:
E − IR E 1 − 2 × 10 −3 × 103 3
VA = RI = 10 < 0 (2.14)
RI + RE 1 × 103 + 2 × 103
Conclusion: The diode D is operating in cut off regime.
II. The calculation of the operating point.

a.). The modeled circuit .The modeled circuit is presented in figure 2.3
b). The system of equations: The system of equation is formed by (2.6), (2.7)
and (2.8) equations.
c.) The problem solution. By simple inspection it may be observed:
I A = 0 mA (2.15)
For VA evaluation it must be observed that:
E − IR E 1 − 2 × 10 −3 × 2 × 10 3 3
VA = RI = 10 = −1 V (2.16)
RI + RE 1 × 103 + 2 × 10 3
Conclusion: {IA, VA}={0 mA, -1 V}
2.3.2 DC Operating Point Analysis - Bipolar Junction Transistor

Circuits
The algorithm presented in section 2.3 is applied in two situations:

1. BJT is modeled using first order model;
2. BJT is modeled using zero order model
97
a) BJT is modeled using first order model

Example
Problem formulation. For the circuit presented below, the operating point
of the BJT {VCE, VBE, VBC, IC, IB, IE} must be
calculated. Consider: EC=25V, RB1=15kΩ,
RB2=10kΩ; RC=1kΩ; RE=9.3kΩ; β=100; VBE=0.7V.
Figure 2.5 Example circuits

Solution
I.) Model the BJT. The circuit presented in figure 2.5 is modeled as figure 2.7
shows:
Figure 2.7 The modeled circuits

II.) Solve the modeled circuit
Kirchhoff equations for the circuit presented in figure 2.7 are (see fig. 2.8 for
notations):
98
Figure 2.8 The modeled circuits (Kirchhoff Laws)
I = I1 + βI B (2.17)
I1 = I B + I 2 (2.18)
I E = I B + βI B (2.19)
E C = R C β I B + VCE + R E I E (2.20)
− VBE = R B1I1 − VCE − R C β I B (2.21)
VBE = R B2 I 2 − R E I E (2.22)
III.) Solve the algebraic problem
Solving the system of six equations mentioned above and taking into account
the relationships:
I C = βI B (2.23)
VCB = VCE − VBE (2.24)
one finds:
I E ≅ 0.99mA (2.25)
I C ≅ 0.98mA (2.26)
I B ≅ 0.01mA (2.27)
VBE = 0.7V (2.28)
VCE ≅ 17.8V (2.29)
VCB ≅ 17.1V (2.30)
b) BJT is modeled using zero order model

Example
Problem formulation. Consider the problem formulated in the above
section.
99
Solution: The algorithm that must be used in this case is

presented below.
Init the counter m = 0
For k=1 to n step 1
Init the base current I (Bm) = 0
k
End For
Repeat
For k=1 to n step 1
Compute the collector currents I(Cm )
k
End For
Increase counter m = m + 1
For k=1 to n step 1
I (Cm−1)
Compute the base currents I (Bm ) = k
k
βk
End For
I (Cm) − I (Cm−1)
k k
Until <ε
I (Cm)
k
End
Example
Figure 2.9 Zero order model analysis

Step 1
Suppose I B(0) = 0 mA (2.31)
R B2 10
Calculate VB(0) = E C = 25 = 10 V (2.32)
R B1 + R B2 15 + 10
Calculate VE(0) = VB( 0) − VBE = 10 − 0.7 = 9.3V (2.33)
VE(0) 9.3
Calculate I C( 0) = = = 1 mA (2.34)
RE 9.3
100
I (C0) 1
Calculate I B(1) = = = 0.01 mA (2.35)
β 100
Step 2
Calculate (
VB(1) = E C − R B1I (B1) )R R B2
= (25 − 15 × 0.01)
10
= 9.94V (2.36)
B1 + R B2 15 + 10
Calculate VE(1) = VB(1) − VBE = 9.94 − 0.7 = 9.24V (2.37)
VE(1) 9.24
Calculate I C(1) = = ≅ 0.994 mA (2.38)
RE 9.3
I (C0) 1
Calculate I B(1) = = = 0.01 mA (2.39)
β 100
I C(1) − I C(0 ) 0.994 − 1
Evaluate = ≅ 0.006 = 0.6% (2.40)
I C(1) 0.994
If the accepted error – noted “ε” – is lower than 3% (for example) - then the
established value for collector current is:
I C ≅ 1 mA (2.41)
Taking into account this value, the operating point (quiescent point) may be
evaluated as follows:
VC = E C − R C I C = 25 − 1 ×1 = 24 V (2.42)
VCE = VC − VE = 24 − 9.3 = 14.7 V (2.43)
VBE = 0.7 V (2.44)
VCB = VCE − VBE = 14.7 − 0.7 = 14 V (2.45)
I C ≅ 1 mA (2.46)
IC
IB = ≅ 10 µA (2.47)
β
I E = I C + I B ≅ 1.01 mA (2.48)
2.3.3 DC Operating Point Analysis - Metal Oxide Semiconductor

Transistor Circuits
Example
Problem formulation. For the circuit presented below, the operating point
of the MOSFET {VDS, VGS, VDG, IG, IS, IG} must be
calculated. Consider: ED=25V, RG1=15MΩ,
RG2=10MΩ; RD=1kΩ; RS=9.3kΩ; VT=-2V;
β=0.05mA/V2.
101
Figure 2.10 Example circuit

Solution
I.) Model the MOSFET. The circuit presented in figure 2.10 is modeled as
figure 2.10 shows:
Figure 2.11 The modeled circuit

II.) Solve the modeled circuit
Kirchhoff equations for the circuit presented in figure 2.11 are (see fig. 2.12 for
notations):
Figure 2.12 The modeled circuit (Kirchhoff Laws)
I = I D + I RG1 (2.49)
102
I RG1 = I RG2 + IG (2.50)

IS = IG + I D (2.51)
E D = R D I D + VDS + R S IS (2.52)
0 = R G1 I RG1 + VGS − VDS − R D I D (2.53)
0 = R G 2 I RG2 − VGS − R S IS (2.54)
III.) Solve the algebraic problem
The system of equations presented above has eight unknown variables. They are
{I, IRG1, IRG2, IG, ID, IS, VGS, VDS}. That is why two more equations must be
added. Namely they are the so called the device equations:
β
ID = ( VGS − VT ) 2 (2.55)
2
IG ≅ 0 (2.56)
Much more, the VGD value may be calculated taking into account the relation:
VDG = VGS − VDS (2.57)
Finally one finds:
I G ≅ 0mA (2.58)
I D ≅ 1.22mA (2.59)
I S ≅ 1.22mA (2.60)
VDS ≅ 12.48V (2.61)
VGS ≅ −1.3V (2.62)
VDG ≅ 13.38V (2.63)
2.4 Large Signal Analysis (DC Sweep Analysis)

The section focuses on DC Sweep Analysis. This type of analysis is usually
used in order to develop transfer function of a circuit. The (2.64) relationship
shows such a function:
103
v O = v O ( v IN ) (2.64)
where:
vO the total instantaneous value of the output voltage;
vIN the total instantaneous value of the input voltage;
The section deals with the circuits containing diodes and bipolar junction
transistors and field effect transistors.
Observation: DC sweep analysis must be made using “large signal

models” for the components.
2.4.1 Large Signal Analysis - Diode Circuits
In this case, the algorithm presented in section 2.3 – being a general algorithm -
may be applied. The best way to prove the previous statement is to set an
example.
Example:
Problem formulation. For the circuit presented in figure 2.13 find the
transfer function.

Solution:
I.) Test the diode state
Suppose that the diode is on. The circuit presented in figure 2.13 is
modeled, according to this hypotheses, in figure 2.14
Figure 2.14 The modeled circuit supposing that the diode is on

b.) Solve the circuit
104
−E = −v IN + Ri A (2.65)
c.) Test the current value:
v IN − E
iA = (2.66)
R
and hence:
> 0 if v IN > E
iA ⇒  (2.67)
< 0 if v IN < E
Conclusion:
The diode is on if vIN>E
The diode is off if vIN<E.
II.) The voltage calculation
A. vIN>E; Diode is on. Inspecting figure 2.14 one finds:
vO=vIN (2.68)
B. vIN<E. Diode is off. The schematic diagram from figure 2.13 may be
modeled as figure 2.15 shows. It results:
Figure 2.15 The modeled circuit supposing that the diode is off
vO=E (2.69)
Finally, one can write:
v IN if v IN > E
vO ⇒  (2.70)
 E if v IN < E
Figure 2.16 displays the transfer characteristic.
Figure 2.16 The transfer characteristic of the circuit presented in figure 2.13
105
2.4.2 Large Signal Analysis - Bipolar Junction Transistor Circuits
The general algorithm used in section 2.4.1 for diode circuits, may be applied
for bipolar junction transistor circuits. The only difference resides in model type
used for the electronic devices. The best way to prove the previous statement is
to set an example.
Example:
transfer function.

Solution:
Theoretically, vIN may vary between - ∞ and + ∞ . This large range of variation
implies the usage of different types of models for the transistor, according to its
state:
I. For
(
v IN ∈ − ∞, Vγ ) (2.71)
the transistor is blocked. The circuit presented in figure 2.17 must be modeled
as figure 2.18 shows.
Figure 2.18 The modeled circuit - BJT in cut-off region.

It is obvious that:
v O = EC (2.72)
II. For:
106
[
v IN ∈ Vγ , v BEsat ) (2.73)
the transistor is in active region. The circuit diagram from figure 2.17 is
modeled in figure 2.19.
Figure 2.19 The modeled circuit - BJT in active region

Observing that:
vO=EC-iCRC (2.74)
and
v BE
i C = IS exp (2.75)
VT
v BE = v IN (2.76)
for output voltage one finds:
v IN
vO = E C − IS R C exp (2.77)
VT
III. For:
v IN ≈ v BEsat (2.78)
the transistor is in saturation. The circuit diagram presented in figure 2.17 is
Figure 2.20 The modeled circuit - BJT in saturation region.

One may observe that the output voltage is:
v O ≈ v CEsat . (2.79)
Taking into account (2.72), (2.77) and (2.79), the output characteristic becomes:
107
E C if (
v IN ∈ − ∞, Vγ )
 v
v O = E C − IS R C exp IN if v IN ∈ [Vγ , v BEsat ) (2.80)
 VT
v CEsat if v IN ≈ v BEsat
The graphic form of this characteristic is presented in figure 2.21.
Figure 2.21 The output characteristic of the circuit presented in figure 2.6
2.4.3 Large Signal Analysis - Field Effect Transistor Circuits
The study of field effect transistor circuits involves the algorithm used in the
previous sections. By consequence an example will be presented. In the same
time an observation must be made: In order to simplify the presentation, only
the cut-off, saturation and linear region will be analyzed.
Example:
transfer function.

Solution:
108
Theoretically, vIN may vary between - ∞ and + ∞ . This large range of variation
implies the usage of different types of models for the transistor, according to its
state:
I. For
v IN ∈ (− ∞, VT ) (2.81)
the transistor is blocked. The circuit presented in figure 2.22 must be modeled
as figure 2.23 shows.
Figure 2.23 The modeled circuit - MOSFET in cut-off region.

It is obvious that:
vO = E D (2.82)
II. For:
v IN > VT and v DS > VDS sat (2.83)
the transistor is in saturation region. The circuit diagram from figure 2.22 is
Figure 2.24 The modeled circuit - MOSTET in saturation region
Observing that:
vO = E D − R Di D (2.84)
and
β
i D = (v DS − VT )
2
(2.85)
2
v GS = v IN (2.86)
109
for the output voltage one finds:

β
v O = E D − (v IN − VT )
2
(2.87)
2
III. For:
v IN > VT and v DS ≤ VDSsat (2.88)
the transistor is in linear region (in order to simplify the analysis, the triode
region was neglected. The circuit diagram presented in figure 2.22 is modeled
in figure 2.25.
Figure 2.25 The modeled circuit - FET in linear region.

One may observe that the output voltage is:
1
R β(vIN − VT ) 1
vO = ED = ED = ED . (2.89)
RD + R 1 1 + R Dβ(vIN − VT )
RD +
β(vIN − VT )
Taking into account (2.82), (2.87) and (2.89), the output characteristic becomes:

E if v IN ∈ (− ∞, VT )
 D
 β
vO = E D − R C ( vGS − VT )2 if v IN > VT and v DS > VDSsat (2.90)
 2
 1
E if v IN > VT and v DS < VDSsat
1 + R Dβ( v IN − VT ) D
The graphic form of this characteristic is presented in figure 2.26
110
Figure 2.26 The output characteristic of the circuit presented in figure 2.22
2.5 Small Signal Analysis (Middle Band Analysis)

AC analysis is used to compute the so called “small signal parameters” of an
amplifier, such as:
voltage gain;
input impedances (resistances);
output impedances (resistances).
The calculation is made using middle band convention. That means that all
electronic devices are modeled using the models presented in section 2.1,
derived from DC quiescent point. In the same time, the models for the main
electrical parts must be reminded. Table 2.18 presents these models.
Element DC Analysis AC analysis
Resistor
Inductor
Capacitor
Voltage
source
111
Element DC Analysis AC analysis
Current
source
Table 2.18 AC model for the main electrical components
Generally, the algorithm used in this case may follow the next steps:
a.) DC analysis – the purpose of this type of analysis is to find the

operating points for the active components:
b.) Calculation of the small signal parameters for active devices (diodes,
BJT’s, MOSFET’s etc);
c.) AC analysis – this type of analysis must be made following the
algorithm presented in section 2.2. Namely, that means:
• Model the circuit;

• Solve the electrical problem;
• Solve the algebraic problem.
The section presents AC analysis techniques for diodes circuit, bipolar junction
transistor circuits and field effect transistor circuits.
2.5.1 Small Signal Analysis (Middle Band Analysis) - Diode

Circuits
Following the procedure of the above presentation, an example will be

presented.
Example:
Problem formulation. For the circuit presented in figure 2.11 find the AC
component of the voltage across the load resistor.
Consider “zero order model” for the diode,
EC=20V; Vs=1mV; R=1kΩ,; RL=1kΩ; C=1000µF,
f=1kHz.
112

Solution:
I. DC analysis
The modeled circuit of the circuit presented in figure 2.27, according to DC

modeling rules, is exposed in figure 2.28.
Figure 2.28 DC Model of the circuit presented in figure 2.27

The system of equations associated with the circuit presented above is:
E C = I AR + IA R L (2.91)
The solution is:
EC 20V
IA = = = 10 mA (2.92)
R + R L 1kΩ + 1kΩ
The DC voltage across the load becomes:
VL = I A R L = 10mA ×1kΩ = 10 V (2.93)
II. AC Small Signal Parameters

g a = 40I A = 40 × 10 = 400 mS (2.94)
hence
1
ra = = 25 Ω (2.95)
ga
III. AC analysis
Figure 2.29 shows the AC partial model of the circuit presented in figure 2.27.
In this figure the diode is not modeled. Figure 2.30 presents the complete model
of the circuit presented in figure 2.27.
113
Figure 2.29 An incomplete model (the diode is not Figure 2.30 The complete model of
modeled) of the circuit presented in figure 2.27 the circuit presented in figure 2.27
The system of equations associated with the circuit presented in figure 2.30 is:
Is = Il + I r
(2.96)
Vs = I r R
(2.97)
0 = ra I l + R L Il − I r R (2.98)
The solution of the system of equation (2.96), (2.97) and (2.98) is:
Vs
Il = (2.99)
ra + R L
Vs
Ir = (2.100)
R
Vs V
Is = + s (2.101)
ra + R L R
By consequence, the voltage drop across the load resistor is:
Vs 1mV
Vl = RL = ×1kΩ ≅ 1 mV (2.102)
ra + R L 25Ω + 1kΩ
IV. The final result
v L ( t ) = VL + Vl sin( 2πft ) = [10 + 10 −3 sin 2000πt ] V
2.5.2 Small Signal Analysis (Middle Band Analysis) – Bipolar

Junction Transistor Circuits
Following the procedure used in section 2.5, an example will be presented.
114
Problem formulation: Consider the circuit presented in figure 2.31. Assume

that: EC=25V, RS=50Ω, RB1=15kΩ, RB2=10kΩ; RE9.3kΩ; RC=1kΩ;
RL=100kΩ; β=100; VBE=0.7V, C1→∞, C2=→∞, CE→∞.
Figure 2.31 A bipolar transistor circuit - example

For this circuit determine:
• voltage gain (see figure 2.32)
Figure 2.32 The modeled circuit for the voltage calculation

The voltage calculation may be calculation using (2.103) formula:
Vo
Av = t (2.103)
Vin t
Observation: Vint is a test source:
• input impedance (see figure 2.33)
Figure 2.33 The modeled circuit for the input impedance calculation
115
The input voltage calculation may be calculation using (2.103) formula:

Vin t
Zin = (2.104)
Iin t
• output impedance (see figure 2.34)
Figure 2.34 The modeled circuit for the output impedance calculation
The output voltage calculation may be calculation using (2.105)
formula
Vo
Zo = t (2.105)
I ot Vin =0
a). DC Analysis
The DC modeled circuit for the circuit presented in figure 2.31 is redrawn in
figure 2.35
Figure 2.35 The DC circuit for the circuit presented in figure 2.31
Comparing this circuit with the circuit put forward in figure 2.5, one can see
that they are identical. In this case it is simply to observe that:
I C = 1mA (2.106)
b). AC Small Signal Parameters
Kipping in mind that:
116
g m [ mS] = 40I C [ mA ] (2.107)

the transconductance gm is:
g m = 40mS (2.108)
In the same time
g m rπ = β (2.109)
And therefore:
β 100
rπ = = = 2.5kΩ (2.110)
g m 40
c). Small Signal Analysis
• Voltage gain
The AC circuit associated with the circuit presented in figure 2.31 without the
BJT modeling is presented in figure 2.36. Figure 2.32 illustrates the AC model
of the circuit presented in figure 2.31, but in this case the BJT is modeled using
the current controlled model.
Figure 2.36 The AC circuit associated Figure 2.37 AC model of the circuit presented in
with the circuit presented in figure 2.31 figure 2.31
The system of equation associated with the AC model of the circuit presented
in figure 2.31 (see figure 2.37) is:
I in t = I r + I b (2.111)
I e = I b + βI b (2.112)
Vin t = I r R B1, 2 (2.113)
0 = I b rπ + I e R 4 − I r R B1, 2 (2.114)
0 = βI b R C ,L + Vce (2.115)
Adding:
Vot = −β I b R C ,L (2.116)
And taking into account (2.103) the voltage gain may be expressed as:
Vo
A v = t = g m R C,L ≅g m R C = 40 (2.117)
Vin t
117
• Input impedance
Starting from the system of equation (2.109)÷(2.113) and remembering (2.104)

relationship one obtains:
Zin =
Vin t
Iin t
[ ]
≅ R B1, 2 rπ = rπ = 2.5kΩ (2.118)
• Output impedance
In this case an output voltage test source must be introduced at the output of the
circuit presented in figure 2.31. Figure 2.34 shows such an issue. The modeled
circuit of the circuit mentioned above is (see figure 2.38):
Figure 2.38
Figure 2.38 may modeled as figure 2.39 shows:
Figure 2.39 The modeled circuit presented in figure 2.34

Observing that:
Ib = 0 (2.119)
The circuit presented in figure 2.39 may be modeled as figure 2.40 shows:
Figure 2.40 The simplified circuit of the circuit presented in figure 2.39
Finally the output impedance (taking into account all simplifications) is:
118
R o ≅ R C = 1kΩ (2.120)
Observation:
The same calculus may be made using the so called “By Hand Small-Signal
Analysis”. An efficient small signal analysis must rely on the following
techniques:
1. Prior knowledge of the incremental resistances “seen looking into the

device terminals”. For bipolar transistor (figure 2.41) they are:
Figure 2.41
• resistance seen looking into the base
ℜ B = rπ + (β + 1) R E (2.121)
if R E = 0 (2.122)
then ℜ B = rπ (2.123)
else ℜB ≅ βR E (2.124)
endif
The (2.121) relationship is valid only if

rπ << βR E (2.125)
• resistance seen looking into the emitter
r + RB
ℜE = π (2.126)
β +1
if R B = 0 (2.127)
r 1
then ℜ E ≅ π = (2.128)
β gm
RB
else ℜ E ≅ (2.129)
β
endif
• resistance seen looking into the collector
ℜC ≅ R C (2.130)
119
2. Prior knowledge of the voltage gain for simple frequently repeated circuits.
• signal voltage measured in emitter related to base signal voltage
Ve ≅ Vb
(2.131)
• signal voltage measured in collector related to base signal voltage
R
Vc ≅ − Vb C (2.132)
RE
if R E = 0 (common emitter connection) (2.133)

then Vc ≅ −g m R C Vb (2.134)
endif
3. Prior knowledge of the current gain for simple frequently repeated

circuits.
• collector current
I c = βI b (2.135)
or
β
I c = αI e = I ≅I (2.136)
β +1 e e
• emitter current
I e = (β + 1)I b ≅ βI b (2.134)
or
Ic β + 1
Ie =
= I ≅ Ic (2.135)
α β c
• base current
I I
Ib = c ≅ e (2.136)
β β
Example
Consider the circuit presented in figure 2.31. For this circuit estimate the
voltage gain, input impedance and output impedance.
• Voltage gain:
The voltage gain must be calculated using the circuit presented in figure 2.36.
The following procedure must be followed:
The calculation of the

Step 1 Vot = I c R C ,L (2.137)
output voltage Vot
120
The calculation of the

Step 2 I c = βI b (2.138)
collector current I c
The calculation of the base Vin t Vin t
Step 3 Ib = ≅ (2.139)
current I b R B1, 2 rπ rπ
Multiplying (2.137) ÷ (2.139) one by one, the output voltage becomes:
Vot = I c R C ,L
I c = βI b
Vin t Vin t
Ib = ≅
R B1, 2 rπ rπ
β
Vot ≅ R LC Vin t = g m R C,L Vin ≅ g m R C Vin t (2.140)
rπ
According to (2.103) the gain voltage becomes:
A v ≅ gm R C (2.141)
• Input impedance
The input impedance must be calculated using the circuit presented in figure
2.36. By simple inspection:
R in ≅ R B rπ ≅ rπ (2.142)
• Output impedance
The input impedance must be calculated using the circuit presented in figure
2.38. By simple inspection:
Ro ≅ RC (2.143)
2.5.3 Small Signal Analysis (Middle Band Analysis) – Field Effect

Transistor Circuits
Following the procedure used in section 2.5, an example will be presented.
121
Problem formulation: Consider the circuit presented in figure 2.42. Assume

that: ED=25V, RG1=15MΩ, RG2=10MΩ; R D=1kΩ; RS=9.3kΩ; VT=-2V;
β=0.05mA/V2, C1→∞, C2=→∞, CE→∞.
Figure 2.42 A field effect transistor circuit - example

For this circuit estimate the voltage gain, input impedance and output
impedance.
Solution:
a). DC Analysis
The DC modeled circuit for the circuit presented in figure 2.42 is redrawn
in figure 2.10. By consequence according to (2.59) ID=1.22mA, and taking
into account (2.62) VGS=-1.3V
b.). AC Small Signal Parameters

g m = β( VGS − VT ) (2.143)
Remembering that
β
I D = (VGS − VT ) 2 (2.144)
2
By consequence
2ID
β= (2.145)
(VGS − VT ) 2
In these circumstances ”gm” becomes:
2I D
gm = (2.146)
VGS − VT
Replacing the actual values one obtains:
2I D 2 × 1.22
gm = = = 3.49mS (2.147)
VGS − VT − 1.3 − (−2)
c.) AC analysis
• Voltage gain
122
In order to evaluate the voltage gain, a voltage source must be introduced at the
input of the circuit presented in figure 2.43. Figure 2.44 displays the new
circuit.
Figure 2.44 The circuit used for the voltage gain and input resistance evaluation
Figure 2.45 presents the AC circuit associated with the circuit presented in
figure 2.44 without the FET modeling.
Figure 2.45 The AC circuit associated with the circuit presented in figure 2.44 without the
FET modeling
Starting from this circuit, the AC model of the circuit presented in figure 2.44,
is modeled in figure 2.46.
Figure 2.46 The AC modeled circuit of the circuit presented in figure 2.44
Simplifying, the Kirchhoff theorems for this circuit are:
Vin t = I r R G1, 2 (2.148)

0 = −g m Vgs R D,L + Vds (2.149)
Observing that:
123
Vot = −Vds (2.150)

Vin t = Vgs (2.151)
And taking into account (2.103) the voltage gain may be expressed as:
Vo
A v = t = g m R D,L ≅g m R D = 3.49 (2.152)
Vin t
• Input resistance
In order to evaluate the input resistance the circuit presented in figure 2.44
may be used. Of course the AC model of this circuit is presented in figure
2.46 but the circuit may be simplified as figure 2.47 shows:
Figure 2.47 The simplified AC model of the circuit presented in figure 2.46
In this case it is simply to observe:
R G1 R G 2 15 × 10
R in = R G1, 2 = = = 6MΩ (2.153)
R G1 + R G2 15 + 10
• Output resistance
The output resistance may be evaluated starting from the circuit presented
in figure 2.48
Figure 2.48 The circuit used for the output resistance evaluation
Obviously, this circuit may be modeled according to AC conditions.
Modeling only the passive components, one obtains the circuit presented in
figure 2.49.
124
Figure 2.49 The AC passive model of the circuit presented in figure 2.49
Figure 2.50 presents the full AC model of the circuit displayed in figure
2.48.
Figure2.50 The complete AC model of the Figure2.51 The simplified AC model of

circuit presented in figure 2.48 the circuit presented in figure2.50
Taking into account the circuit presented in figure 2.51, it is simply to

observe that the output resistance is:
R o = R D = 1KΩ (2.154)
125
126

Tests
1. 3p Assume that a ”npn” bipolar junction transistor operates in

large signal, quasi-static regime, active region. The
mathematical model (second order Π model) - considering the
transistor current controlled – is:
a.) b.) I v 
IS  v BE  i B = S exp BE 
i B = exp  β  VT 
β  VT 
v 
iC = β i B i C = IS exp BE 
 VT 
c.) d.) I v 
IS  v BE  i E = S exp BE 
i E = exp  

α  VT 
α  VT 
v 
iC = α i E i C = IS exp BE 
 VT 

mathematical model (second order T model) - considering the
a.) b.) I v 
i B = exp  β  VT 
β  VT 
v 
 VT 
c.) d.) IS v 
I v  iE = exp BE 
i E = S exp  BE  α  VT 
α  VT 
v 
 VT 

127

transistor voltage controlled – is:
a.) b.) I v 
i B = exp  β  VT 
β  VT 
v 
 VT 
c.) d.) I v 
i E = exp   α  VT 
α  VT 
v 
iC = α i E i C = I S exp BE 
 VT 

a.) b.) I v 
i B = exp  β  VT 
β  VT 
v 
 VT 
c.) d.) I v 
i E = exp   α  VT 
α  VT 
v 
 VT 

large signal, quasi-static regime, active region. The equivalent
circuit of this transistor is presented below.
The mathematical model associated is:
128
a.) b.) IS v 
I v  iB = exp BE 
i B = S exp BE  β  VT 
β  VT 
v 
 VT 
c.) d.) IS v 
I v  iE = exp BE 
i E = S exp  BE  α  VT 
α  VT 
v 
 VT 


a.) b.) IS v 
IS  v BE  iB = exp BE 
i B = exp  β  VT 
β  VT 
v 
 VT 
c.) d.) IS v 
I v  iE = exp BE 
i E = S exp  BE  α  VT 
α  VT 
v 
 VT 

129

a.) b.) IS v 
i B = exp  β  VT 
β  VT 
v 
 VT 
c.) d.) I v 
I v  i E = S exp BE 
i E = S exp  BE  α  VT 
α  VT 
v 
 VT 


a.) b.) IS v 
i B = exp  β  VT 
β  VT 
v 
 VT 
130
c.) d.) IS v 
I v  iE = exp BE 
i E = S exp  BE  α  VT 
α  VT 
v 
 VT 

mathematical model of this transistor is presented below.
I v 
i B = S exp BE 
β  VT 
iC = β i B
The equivalent circuit associated is:
a.) b.)
c.) d.)

I v 
β  VT 
v 
i C = I S exp BE 
 VT 
131
a.) b.)
c.) d.)

I v 
i E = S exp BE 
α  VT 
iC = α i E
a.) b.)
c.) d.)

132
IS v 
iE = exp BE 
α  VT 
v 
 VT 
a.) b.)
c.) d.)
13. 3p Assume that a ”pnp” bipolar junction transistor operates in

a.) b.) I v 
IS  v EB  i B = S exp EB 
i B = exp  β  VT 
β  VT 
v 
iC = β i B i C = IS exp EB 
 VT 
c.) d.) I v 
IS  v EB  i E = S exp EB 
i E = exp   α  VT 
α  VT 
v 
iC = α i E i C = IS exp EB 
 VT 

133
a.) b.) IS v 
I v  iB = exp EB 
i B = S exp EB  β  VT 
β  VT 
v 
iC = β i B i C = I S exp EB 
 VT 
c.) d.) IS v 
I v  iE = exp EB 
i E = S exp  EB  α  VT 
α  VT 
v 
iC = α i E i C = I S exp EB 
 VT 

a.) b.) I v 
i B = exp  β  VT 
β  VT 
v 
 VT 
c.) d.) I v 
IS  v EB  i E = S exp EB 
i E = exp   α  VT 
α  VT 
v 
 VT 

a.) b.) I v 
i B = exp  β  VT 
β  VT 
v 
 VT 
134
c.) d.) IS v 
I v  iE = exp EB 
i E = S exp  EB  α  VT 
α  VT 
v 
 VT 


a.) b.) IS v 
I  v  iB = exp EB 
i B = S exp EB  β  VT 
β  VT 
v 
 VT 
c.) d.) IS v 
I v  iE = exp EB 
i E = S exp  EB  α  VT 
α  VT 
v 
 VT 

135
a.) b.) IS v 
I v  iB = exp EB 
i B = S exp EB  β  VT 
β  VT 
v 
 VT 
c.) d.) IS v 
I v  iE = exp EB 
i E = S exp  EB  α  VT 
α  VT 
v 
 VT 


a.) b.) IS v 
I  v  iB = exp EB 
i B = S exp EB  β  VT 
β  VT 
v 
 VT 
c.) d.) IS v 
I v  iE = exp EB 
i E = S exp  EB  α  VT 
α  VT 
v 
 VT 

136

a.) b.) IS v 
IS  v EB  iB = exp EB 
i B = exp  β  VT 
β  VT 
v 
 VT 
c.) d.) IS v 
I v  iE = exp EB 
i E = S exp  EB  α  VT 
α  VT 
v 
 VT 

I v 
i B = S exp EB 
β  VT 
iC = β iB
a.) b.)
c.) d.)
137

I v 
β  VT 
v 
i C = IS exp EB 
 VT 
a.) b.)
c.) d.)
23 2p Assume that a ”pnp” bipolar junction transistor operates in

I v 
i E = S exp EB 
α  VT 
iC = α i E
a.) b.)
138
c.) d.)
24 2p Assume that a ”npn” bipolar junction transistor operates in

I v 
i E = S exp  EB 
α  VT 
v 
 VT 
a.) b.)
c.) d.)

circuit (first order Π model) of this transistor is:
a.) b.)
139
c.) d.)

circuit (first order T model) of this transistor is:
a.) b.)
c.) d.)

a.) b.)
140
c.) d.)

a.) b.)
c.) d.)

VBE = const .
iC = β iB
141
a.) b.)
c.) d.)

VBE = const .
iC = α i E
a.) b.)
c.) d.)

142

VEB = const .
iC = β iB
a.) b.)
c.) d.)

VEB = const .
iC ≅ α i E
a.) b.)
143
c.) d.)


a.) VBE = const . b.) VBE = const .
iC = β i B iC = α iE
c.) VEB = const . d.) VEB = const .


144


iC = β iB iC = α i E



mathematical model (zero order) of this transistor is:
c.) VBE = const . d.) VEB = const .
iC ≅ i E iC ≅ iE
145

c.) VBE = const . d.) VEB = const .
iC ≅ iE iC ≅ i E

large signal, quasi-static regime, saturation region. The
VBE = VBEsat
VCE = VCEsat
a.) b.)
c.) d.)

VEB = VEBsat
VEC = VECsat
a.) b.)
146
c.) d.)

small signal, quasi-static regime, active region. The
mathematical model (Π model) - considering the transistor
current controlled – is:
a.) V b.) V
I b = be I b = be
rπ rπ
I c = g m Vbe Ic = β I b
c.) V d.) V
I e = be I e = be
re re
I c = g m Vbe Ic = α Ie

voltage controlled – is:
a.) V b.) V
I b = be I b = be
rπ rπ
c.) V d.) V
I e = be I e = be
re re

mathematical model (T model) - considering the transistor
a.) V b.) V
I b = be I b = be
rπ rπ
147
c.) Vbe d.) Vbe

Ie = Ie =
re re

a.) V b.) V
I b = be I b = be
rπ rπ
c.) V d.) V
I e = be I e = be
re re

small signal, quasi-static regime, active region. The equivalent

a.) V b.) Vbe
I b = be Ib =
rπ rπ
c.) V d.) V
I e = be I e = be
re re

148

a.) V b.) Vbe
I b = be Ib =
rπ rπ
c.) V d.) V
I e = be I e = be
re re


a.) V b.) Vbe
I b = be Ib =
rπ rπ
c.) V d.) V
I e = be I e = be
re re

149

a.) V b.) Vbe
I b = be Ib =
rπ rπ
c.) V d.) V
I e = be I e = be
re re

V
I b = be
rπ
I c = g m Vbe
a.) b.)
c.) d.)

150
Vbe
Ib =
rπ
Ic = β I b
a.) b.)
c.) d.)

V
I e = be
re
I c = g m Vbe
a.) b.)
c.) d.)

151
Vbe
Ie =
re
Ic = α Ie
a.) b.)
c.) d.)

a.) V b.) V
I b = eb I b = eb
rπ rπ
I c = g m Veb Ic = β I b
c.) V d.) V
I e = eb I e = eb
re re
I c = g m Veb Ic = α Ie

a.) V b.) V
I b = eb I b = eb
rπ rπ
c.) V d.) V
I e = eb I e = eb
re re
152

a.) V b.) V
I b = eb I b = eb
rπ rπ
I c = g m Veb Ic = β Ib
c.) V d.) V
I e = eb I e = eb
re re

a.) V b.) V
I b = eb I b = eb
rπ rπ
c.) V d.) V
I e = eb I e = eb
re re


a.) V b.) Veb
I b = eb Ib =
rπ rπ
153
c.) Veb d.) Veb

Ie = Ie =
re re


a.) V b.) Veb
I b = eb Ib =
rπ rπ
c.) V d.) V
I e = eb I e = eb
re re


a.) V b.) Veb
I b = eb Ib =
rπ rπ
c.) V d.) V
I e = eb I e = eb
re re
154


a.) V b.) Veb
I b = eb Ib =
rπ rπ
c.) V d.) V
I e = eb I e = eb
re re

V
I b = eb
rπ
I c = g m Veb
a.) b.)
c.) d.)
155

V
I b = eb
rπ
Ic = β Ib
a.) b.)
c.) d.)

V
I b = eb
rπ
Ic = β Ib
a.) b.)
c.) d.)
156

V
I e = eb
re
I c = g m Veb
a.) b.)
c.) d.)

V
I e = eb
re
Ic = α Ie
a.) b.)
157
c.) d.)

mathematical model of this transistor is presented below
Vbe = h ie I b + h reVce
I c = h feI b + h oe Vce
Notes:
• hie– The input impedance of the transistor
(corresponding to the base resistance rπ).
• hre– Represents the dependence of the transistor's IB–
VBE curve on the value of VCE. It is usually very small
and is often neglected (assumed to be zero).
• hfe– The current-gain of the transistor. This
parameter is often specified as hFE or the DC
current-gain (βDC) in datasheets.
• hoe– The output impedance of transistor. This term is
usually specified as an admittance and has to be
inverted to convert it to an impedance.
a.) b.)
c.) d.)

158
Notes:

a.) Vbe = h ie I b + h re Vce b.) Vce = h ie I b + h re Vbe
I c = h fe I b + h oe Vce I c = h fe I b + h oe Vbe
c.) Vbe = h ie I c + h re Vce d.) Vbe = h ie I c + h re Vce
I b = h fe I c + h oe Vce I c = h feI c + h oe Vce
67 3p The Giacoletto equivalent circuit of a npn bipolar junction

transistor is presented in figure noted:
a.) b.)
c.) d.)
68 1p The ANSI symbol of a “n channel” JFET is:

a.) b.)
c.) d.)
159
69 1p The DIN symbol of a “n channel” JFET is:

a.) b.)
c.) d.)
70 1p The ANSI symbol of a “p channel” JFET is:

a.) b.)
c.) d.)
71 1p The DIN symbol of a “p channel” JFET is:

a.) b.)
c.) d.)
72 1p The symbol presented below represents:
a.) a “n channel” JFET ANSI symbol

b.) a “n channel” JFET DIN symbol
c.) a “p channel” JFET ANSI symbol
d.) a “p channel” JFET DIN symbol

160


76 1p The ANSI symbol of a “n channel” D-MOSFET is:

a.) b.)
c.) d.)
77 1p The DIN symbol of a “n channel” D-MOSFET is:

a.) b.)
c.) d.)
78 1p The ANSI symbol of a “p channel” D-MOSFET is:

a.) b.)
c.) d.)
161
79 1p The DIN symbol of a “p channel” D-MOSFET is:

a.) b.)
c.) d.)
80 1p The ANSI symbol of a “n channel” D-MOSFET (no bulk) is:

a.) b.)
c.) d.)
81 1p The ANSI symbol of a “p channel” D-MOSFET (no bulk) is:

a.) b.)
c.) d.)
82 1p The DIN symbol of a “n channel” D-MOSFET (no bulk) is:

a.) b.)
c.) d.)
83 1p The DIN symbol of a “p channel” D-MOSFET (no bulk) is:

a.) b.)
c.) d.)
84 1p The ANSI symbol of a “n channel” E-MOSFET is:
162
a.) b.)
c.) d.)
85 1p The ANSI symbol of a “p channel” E-MOSFET is:

a.) b.)
c.) d.)
86 1p The DIN symbol of a “n channel” E-MOSFET is:

a.) b.)
c.) d.)
87 1p The DIN symbol of a “p channel” E-MOSFET is:

a.) b.)
c.) d.)
88 1p The ANSI symbol of a “n channel” E-MOSFET (no bulk) is:

a.) b.)
c.) d.)
89 1p The ANSI symbol of a “p channel” E-MOSFET (no bulk) is:

a.) b.)
163
c.) d.)
90 1p The DIN symbol of a “n channel” E-MOSFET (no bulk) is:

a.) b.)
c.) d.)
91 1p The DIN symbol of a “p channel” E-MOSFET (no bulk) is:

a.) b.)
c.) d.)
92 3p Assume that a JFET – n-channel -operates in large signal, quasi-

static regime, saturation region. The mathematical model is:
a.) i =0 b.) iG = 0
G
2
β  v 
iD = (v GS − VT )2 i D = I DSS 1 − GS 
2  VT 
c.) iG = 0 d.) iG = 0
2
β  v 
iD = (vSG − VT )2 i D = I DSS 1 − SG 
2  VT 
93 3p Assume that a JFET – p-channel -operates in large signal, quasi-

a.) i =0 b.) iG = 0
G
2
β  v 
2  VT 
c.) iG = 0
d.) iG = 0
2
β  v 
2  VT 
94 3p Assume that a D-MOSFET– n-channel -operates in large signal,
164
quasi-static regime, saturation region. The mathematical model

is:
a.) i =0 b.) iG = 0
G
2
β  v 
iD = (v GS − VT )2 i D = I DSS  1 − GS 
2  VT 
c.) iG = 0
d.) iG = 0
2
β  v 
2  VT 
95 3p Assume that a D-MOSFET– p-channel -operates in large signal,

is:
a.) i =0 b.) iG = 0
G
2
β  v 
2  VT 
c.) iG = 0 d.) iG = 0
2
β  v 
2  VT 
96. 2p Assume that a JFET –n channel -operates in large signal, quasi-

static regime, saturation region. The mathematical model of this
transistor is presented below.
iG = 0
2
 v 
i D = I DSS 1 − GS 
 VT 
a.) b.)
c.) d.)
97. 2p Assume that a JFET –p channel -operates in large signal, quasi-

165

iG = 0
2
 v 
i D = I DSS 1 − SG 
 VT 
a.) b.)
c.) d.)
98. 2p Assume that a DMOSFET –n channel -operates in large signal,

of this transistor is presented below.
iG = 0
β
iD = (v GS − VT )2
2
a.) b.)
c.) d.)
99. 2p Assume that a DMOSFET –p channel -operates in large signal,

iG = 0
β
iD = (v SG − VT )2
2
166
a.) b.)
c.) d.)
100. 2p Assume that a JFET – n channel - operates in large signal,

quasi-static regime, saturation region. The equivalent circuit of
this transistor is presented below.

a.) i =0 b.) iG = 0
G
2
β  v 
2  VT 
c.) iG = 0 d.) iG = 0
2
β  v 
2  VT 
101. 2p Assume that a JFET – p channel - operates in large signal,


a.) i =0 b.) iG = 0
G
2
β  v 
2  VT 
167
c.) iG = 0 d.) iG = 0
2
β  v 
2  VT 
102. 2p Assume that a D MOSFET – n channel - operates in large signal,


a.) i =0 b.) iG = 0
G
2
β  v 
2  VT 
c.) iG = 0
d.) iG = 0
2
β  v 
2  VT 
103. 2p Assume that a D MOSFET – p channel - operates in large signal,


a.) i =0 b.) iG = 0
G
2
β  v 
2  VT 
c.) iG = 0 d.) iG = 0
2
β  v 
2  VT 
104 3p Assume that a FET– n-channel -operates in small signal, quasi-

168
a.) Ig = 0 b.) Ig = 0
I d = g m Vgs I d = g m Vsg
2i D 2i D
gm = gm =
vGS − VT QP vSG − VT QP
c.) iG = 0 d.) iG = 0
2
β  v 
2  VT 
105 3p Assume that a FET– p-channel -operates in small signal, quasi-

a.) Ig = 0 b.) Ig = 0
I d = g m Vgs I d = g m Vsg
2i D 2i D
gm = gm =
vGS − VT QP vSG − VT QP
c.) iG = 0 d.) iG = 0
2
β  v 
2  VT 
106. 2p Assume that a DMOSFET –n channel -operates in small signal,

Ig = 0
I d = g m Vgs
2i D
gm =
vGS − VT QP

a.) b.)
169
c.) d.)

Ig = 0
I d = g m Vsg
2i D
gm =
vSG − VT QP

a.) b.)
c.) d.)
108. 2p Assume that a JFET –n channel -operates in small signal, quasi-

Ig = 0
I d = g m Vgs
2i D
gm =
v GS − VT QP

a.) b.)
170
c.) d.)
109. 2p Assume that a JFET –p channel -operates in small signal, quasi-

Ig = 0
I d = g m Vsg
2i D
gm =
vSG − VT QP

a.) b.)
c.) d.)
171
172
Answers
Correct answer: a.)

Correct answer: c.)

Correct answer: b.)

Correct answer: d.)


Correct answer: a.)

173

Correct answer: b.)


Correct answer: c.)


Correct answer: d.)

174
IS v 
iB = exp BE 
β  VT 
iC = β i B
Correct answer: a.)

I v 
β  VT 
v 
 VT 
Correct answer: b.)

I v 
i E = S exp  BE 
α  VT 
iC = α i E
Correct answer: c.)

I v 
i E = S exp BE 
α  VT 
v 
 VT 
Correct answer: d.)
175

Correct answer: a.)

Correct answer: c.)

Correct answer: b.)

Correct answer: d.)


Correct answer: a.)

176

Correct answer: b.)


Correct answer: c.)


Correct answer: d.)

I v 
i B = S exp  EB 
β  VT 
iC = β iB
177
Correct answer: a.)

I v 
β  VT 
v 
 VT 
Correct answer: b.)

I v 
α  VT 
iC = α i E
Correct answer: c.)

I v 
α  VT 
v 
 VT 
Correct answer: d.)

Correct answer: a.)
178

Correct answer: b.)

Correct answer: c.)

Correct answer: d.)

VBE = const .
iC = β iB
Correct answer: a.)

VBE = const .
iC = α iE
Correct answer: b.)

VEB = const .
iC = β iB
Correct answer: c.)
179

VEB = const .
iC ≅ α iE
Correct answer: d.)


Correct answer: a.)


Correct answer: b.)

180
Correct answer: c.)


Correct answer: d.)

Correct answer: c.)

Correct answer: d.)

VBE = VBEsat
VCE = VCEsat
Correct answer: c.)

VEB = VEBsat
VEC = VECsat
Correct answer: b.)
181

Correct answer: b.)

Correct answer: a.)

Correct answer: c.)

Correct answer: d.)


Correct answer: a.)

182

Correct answer: b.)


Correct answer: c.)


Correct answer: d.)

V
I b = be
rπ
I c = g m Vbe
Correct answer: a.)
183

V
I b = be
rπ
Ic = β I b
Correct answer: b.)

V
I e = be
re
I c = g m Vbe
Correct answer: c.)

V
I e = be
re
Ic = α Ie
Correct answer: c.)

Correct answer: b.)

Correct answer: a.)
184

Correct answer: c.)

Correct answer: d.)


Correct answer: a.)


Correct answer: b.)

185

Correct answer: c.)


Correct answer: d.)

V
I b = eb
rπ
I c = g m Veb
Correct answer: a.)

V
I b = eb
rπ
Ic = β Ib
Correct answer: a.)
186

V
I b = eb
rπ
Ic = β I b
Correct answer: b.)

V
I e = eb
re
I c = g m Veb
Correct answer: c.)

V
I e = eb
re
Ic = α Ie
Correct answer: d.)

mathematical model of this transistor is presented below
Vbe = h ie I b + h re Vce
I c = h fe I b + h oe Vce
Notes:
187

Correct answer: d.)

Notes:

Correct answer: a.)
67 3p The Giacoletto equivalent circuit of a npn bipolar junction

transistor is presented in figure noted:
Correct answer: b.)
68 1p The ANSI symbol of a “n channel” JFET is:

Correct answer: a.)
69 1p The DIN symbol of a “n channel” JFET is:
188
Correct answer: b.)
70 1p The ANSI symbol of a “p channel” JFET is:

Correct answer: c.)
71 1p The DIN symbol of a “p channel” JFET is:

Correct answer: d.)
Correct answer: a.)
Correct answer: b.)
Correct answer: c.)
Correct answer: d.)
76 1p The ANSI symbol of a “n channel” D-MOSFET is:

Correct answer: a.)
77 1p The DIN symbol of a “n channel” D-MOSFET is:

Correct answer: b.)
78 1p The ANSI symbol of a “p channel” D-MOSFET is:

Correct answer: c.)
189
79 1p The DIN symbol of a “p channel” D-MOSFET is:

Correct answer: d.)
80 1p The ANSI symbol of a “n channel” D-MOSFET (no bulk) is:

Correct answer: a.)
81 1p The ANSI symbol of a “p channel” D-MOSFET (no bulk) is:

Correct answer: c.)
82 1p The DIN symbol of a “n channel” D-MOSFET (no bulk) is:

Correct answer: b.)
83 1p The DIN symbol of a “p channel” D-MOSFET (no bulk) is:

Correct answer: d.)
84 1p The ANSI symbol of a “n channel” E-MOSFET is:

Correct answer: a.)
85 1p The ANSI symbol of a “p channel” E-MOSFET is:

Correct answer: c.)
86 1p The DIN symbol of a “n channel” E-MOSFET is:

Correct answer: b.)
87 1p The DIN symbol of a “p channel” E-MOSFET is:

Correct answer: d.)
88 1p The ANSI symbol of a “n channel” E-MOSFET (no bulk) is:

Correct answer: a.)
89 1p The ANSI symbol of a “p channel” E-MOSFET (no bulk) is:

Correct answer: c.)
90 1p The DIN symbol of a “n channel” E-MOSFET (no bulk) is:

Correct answer: b.)
91 1p The DIN symbol of a “p channel” E-MOSFET (no bulk) is:

Correct answer: d.)
92 3p Assume that a JFET – n-channel -operates in large signal, quasi-

190
Correct answer: b.)
93 3p Assume that a JFET – p-channel -operates in large signal, quasi-

Correct answer: d.)
94 3p Assume that a D-MOSFET– n-channel -operates in large signal,

is:
Correct answer: a.)
95 3p Assume that a D-MOSFET– p-channel -operates in large signal,

is:
Correct answer: c.)
96. 2p Assume that a JFET –n channel -operates in large signal, quasi-

iG = 0
2
 v 
i D = I DSS 1 − GS 
 VT 
Correct answer: b.)
97. 2p Assume that a JFET –p channel -operates in large signal, quasi-

iG = 0
2
 v 
i D = I DSS 1 − SG 
 VT 
Correct answer: d.)
98. 2p Assume that a DMOSFET –n channel -operates in large signal,

191
iG = 0
β
iD = (v GS − VT )2
2
Correct answer: a.)
99. 2p Assume that a DMOSFET –p channel -operates in large signal,

iG = 0
β
iD = (v SG − VT )2
2
Correct answer: d.)
100. 2p Assume that a JFET – n channel - operates in large signal,


Correct answer: b.)
101. 2p Assume that a JFET – p channel - operates in large signal,


Correct answer: d.)
102. 2p Assume that a D MOSFET – n channel - operates in large signal,

192

Correct answer: a.)
103. 2p Assume that a D MOSFET – p channel - operates in large signal,


Correct answer: c.)
104 3p Assume that a FET– n-channel -operates in small signal, quasi-

Correct answer: a.)
105 3p Assume that a FET– p-channel -operates in small signal, quasi-

Correct answer: c.)

Ig = 0
I d = g m Vgs
2i D
gm =
vGS − VT QP

Correct answer: b.)

193
Ig = 0
I d = g m Vsg
2i D
gm =
vSG − VT QP

Correct answer: d.)
108. 2p Assume that a JFET –n channel -operates in small signal, quasi-

Ig = 0
I d = g m Vgs
2i D
gm =
v GS − VT QP

Correct answer: b.)
109. 2p Assume that a JFET –p channel -operates in small signal, quasi-

Ig = 0
I d = g m Vsg
2i D
gm =
vSG − VT QP

Correct answer: d.)
194

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Electronic Circuits - Basic

1. Time domain analysis;

▪ Transform definition - The formal definition of the mathematical transform

Fundamental Electrical Elements;

1.1.1 Fundamental Electrical Elements

In order to describe the way of operation of the nine electrical elements

Figura 1.1 One-port element Figura 1.2 Two-port element

vIN total instantaneous value of the input voltage of the two-port

1.1.2 Explanatory Notes

Figure 1.3 Explanatory notes

1.2 Time Domain Analysis

1.2.1. The Transform

1.2.2 Signal Representation

Signal Time domain (t)

1.2.3 Circuit Element Modeling

Current source i(t ) = I( t)

Table 1.2 The principal electrical elements

1.2.4 Principal Theorems

a.) Kirchhoff’s Current Law

It is generally known as “KCL”.

Observation: The current entering into a node is noted “+”;

Figure 1.4 Kirchhoff current law - example

iRn the current through the resistor noted “Rn”;

b.) Kirchhoff’s Voltage Law

It is generally known as “KVL”.

Statement: “The sum of the electromotive forces in any closed loop is

Figure 1.5 Kirchhoff voltage law - example

vRn = R n i Rn the voltage drop across the resistor noted “Rn”;

Replacing the above voltage drops relationships into (1.12) one

c.) Voltage Drop Calculation

Figure 1.6 A general circuit

Figure 1.8 Figure 1.9

d.) Resistance “Seen” between two Terminals of a Circuit

Case 1 A voltage source is applied between the two terminals.

Problem Consider the circuit presented in figure 1.10. The resistance

Figure 1.10 A general circuit

Case 2. A current source is applied between the two terminals

Procedure Step 1 The independent voltage sources must be

Also known in Europe as Mayer-Norton Theorem.

Observation: The theorem may be applied for DC circuits.

Figure 1.14 Norton equivalence of the circuit presented in figure 1.10

The calculus of the IBsc and RAB is presented below:

Procedure: Let’s consider the circuit presented in figure 1.10.

Step 1: Calculate the open circuit drop voltage the two

Figure 1.15 IAB sc evaluation

Figure 1.16 The basic circuit Figure 1.17 The circuit

Figure 1.18 The circuit used for the calculation of IABsc

1.19 The Norton equivalence of the circuit presented in figure 1.9

f.) Thevenin Theorem

Observation: The theorem may be applied for DC circuits.

Statement: Any circuit containing voltage and/or current sources

Consider the circuit presented in figure 1.10. Thevenin equivalence of the

Figure 1.20 Thevenin equivalence of the circuit presented in figure 1.10

The calculus of the EAB0 and RAB is presented below:

Procedure: Let’s consider the circuit presented in figure 1.10.

Step 1: Choose the two terminals (figure 1.10)

terminals (figure 1.21).

Figure 1.21 EAB0 evaluation

Step 1 Consider the circuit presented in figure 1.9. The two

Figure 1.22 The circuit used for the calculation of EAB0

Finally the circuit transformed according to Thevenin theorem is presented in

1.23 The Thevenin equivalence of the circuit presented in figure 1.10

g.) Voltage Divider