Professional Documents
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0.1
-0.1
Acceleration (g)
-0.2
-0.3
-0.4
-0.5
0 2 4 6 8 10 12 14 16 18
Time (sec)
0.1
tem
ADXL 202E Silicon Designs 1221L -0.1
Acceleration (g)
Type MEMS MEMS -0.2
For this test, channel for Silicon Designs 1221L had range
of -2G 2G. -1
0 2 4 6 8 10 12 14 16 18
Time (sec)
Node 1
Spatial jitter
0.5
Acceleration (g)
Temporal jitter
0 Node 2
-0.5
Node 3
-1
0 2 4 6 8 10 12 14 16 18
Time (sec)
-0.04
-0.06
4.2 Jitter Test
We tested jitter of HighFrequencySampling component. In-
-0.08
6
Interval: 1000ms
1000
Jitter (us)
4 900
3
800
2
700
1
600
Sample
0
500
-1
450 460 470 480 490 500 510 520 530 540 550
400
Sample
300
200
100
Interval: 200ms 0
10 -1 0 1 2 3 4 5 6 7 8 9 10
Jitter (us)
6
Jitter (us)
-1
450 460 470 480 490 500 510 520 530 540 550
Sample
Interval: 200ms
1000
900
800
6.67KHz, flash memory write takes too much portion of time 500
200
memory write should not affect that many sampling. How- 100
900
800
700
500
9
400
8
300
7
6 200
Jitter (us)
5 100
4 0
-1 0 1 2 3 4 5 6 7 8 9 10
3 Jitter (us)
0
Figure 9: Histogram of Jitter (1KHz, 5KHz,
-1
450 460 470 480 490 500
Sample
510 520 530 540 550
6.67KHz respectively)
Open
Ack for
Open
Data
Block 1
Data
Block 2
Sender Receiver
Data
Block 1
Figure 13: Open is lost Data
Block 2
Sender Receiver
Data
Open Block 3
Ack for Data
Open Block 4
Ack for
DONE
Open Data
Data
Ack for
Block 4
Open
Ack for
Data
Data
Block 1
DONE
Data
Block 2
Figure 16: Ack for Data is lost
More try
Ack Timer .fired Timout / FAIL
S_O
Sender Receiver
Nack / FAIL
Data process_ack_msg
Data decode_ackBuf
Last slot
Block 2 Timer .fired
update_slotNumWin
More slot
Data
Ack
Block 4 S_A
More try
Data
Block 4 Figure 19: State Transition Diagram of Sender
Ack for
DONE
Data
DONE Open No
IDLE send_ack_msg(A)
process_open_msg_common init_receive
Yes
receive_done
send_ack_msg(O) clear_mem(ackWin)
Figure 17: Data Block 4 is lost (no timeout to send Timer .start
LRXReceive.accepted
TransferDone
encode_ackBuf
ack) Timer .stop
update_slotNumWin
Data Open
R_O Timer .stop
send_ack_msg(D)
SUCCESS
Sender Receiver
Data
Figure 20: State Transition Diagram of Receiver
Block 1
Data
Block 2 data is lost. Sender times out. This is clearer in Figure 17.
Data As shown, receiver does not timeout to send Ack. There
Block 3 are two reasons why only sender times out and stimulate
Data receiver for Ack. The first reason is shown in Figure 16.
Block 4 If sender doesnt time out, for a receiver to make sure Ack
Ack for is delivered to sender, receiver should get acknowledgement
Data from sender for Ack itself. This is not good. So it is clear
Data that sender should timeout. Given that sender times out,
Block 2 timeout of receiver makes no difference except that chan-
Data Ack for nel is wasted by unnecessary Ack from receiver. So timeout
Block 3 Data in only sender side is desirable. As a second reason, if re-
ceiver times out, in case like Figure 18 (if first Data after
Ack is lost), second Data always collide with resent Ack of
receiver. This is not a good phenomenon. Therefore, after
sending last packet in each round, if acknowledgement does
Figure 18: After Ack, when the first Data is lost not come, sender sends the last packet in that round again to
stimulate acknowledgement. However, this does not mean
receiver has no timeout. Receiver waits sufficient amount of
time, and if nothing happens, it regards the situation as a
failure. Figure 19 shows state transition diagram of sender,
and Figure 20 shows state transition diagram of receiver.
Throughput vs Window Size Throughput vs Loss Rate
300
Throughput
300
Loss Rate X 1000 Throughput
250
# of packets sent / 10
Throughput (Byte/s)
250
200
Throughput (Byte/s)
200
150
150
100
100
50
50
0
1 2 4 8 16 Optimal
0
Window Size 0 5 10 15 20 25
Loss Rate
Figure 21: Throughput vs Window Size