ICFAI Foundation for Higher Education, Hyderabad

IcfaiTech (Faculty of Science and Technology)

Second Semester, 2019-20
Course Handout

Course No Course Title L P U

EC322 Analog & Digital VLSI Design 3 0 3

Instructor-in-charge: Dr. B. Naresh Kumar Reddy

Learning Outcomes:
After successful completion of the course student will be able to

1. Design & Analyze any CMOS Circuits such as Arithmetic and Logic Blocks.
2. Design any Logic Circuit and their stick diagrams in all formats of design.
3. Design Layout with Design Constraints using MICROWIND hardware design software.
4. Analyze Circuits in advanced circuits of the current trends.
5. Visualize practically the fabrication process of the Intel Processors, IBM Processors.

CMOS Digital Integrated Circuits: Analysis and Design, S. M. Kang, Y

Text Book T
Leblebici, McGraw Hill Intl Edition, 2003.
CMOS VLSI Design : Circuits and systems perspective, Neil H.E.Weste,
Reference book(s) R1
DavidHarris, Ayan Banerjee, PEARSON Education.
Analog Integrated Circuit Design, John David and K. Martin, John Wiley &
Reference book(s) R2
Sons Inc., 2002.
Principles of CMOS VLSI Design, Neil H.E. Weste, Kamran Eshragan,
R3
Addison-Wesley, 2005.
VLSI Design Techniques for analog and digital circuits, Randall A. Geiger,
R4
Phillips E. Allen et al., McGraw Hill Intl. Edition 1990
SWAYAM https://swayam.gov.in/nd1_noc20_ee29/preview
NPTEL https://nptel.ac.in/courses/117/101/117101105/
MOOC

Lecture-wise plan:
Lecture
Learning Objective
Nos.
Introduction to VLSI Design
1 Ch.1.1- T
Flow concepts and methods
Basic steps in MOS
Fabrication, Layout
2-4
design rules and effect
of MOS Capacitances
Reference
(Chapter/Sec./Page
Topics to be covered
Nos. of Text/Ref.
Books)
Introduction to VLSI Design
Methodologies
MOS Processing, Design rules,
Ch 2.1-2.5-T
stick diagrams

5-6 MOSFET Transistor
MOSFET Current -voltage
7-8
characteristics
Understanding the operation
and DC characteristics of the
9-11
MOS Inverters with different
loads
Switching characteristics of
MOS inverters , delay
12-15
estimation and the effect of
interconnects
Implementation of
16,18 combinational circuits using
NMOS depletion loads
Implementing CMOS logic
19-21 gates, Layout of CMOS logic
circuits, Pass Gates
CMOS
Implementation of
22-25 sequential circuits,
Introduction to
dynamic logic circuits
26-30 Understanding the operation
of semiconductor memories
31-34
Introduction to the Low
power CMOS logic circuits
Introduction to Analog
35-38
Circuits
Basic Operational amplifier
39-41
design
DAC and ADC converter
42-45
Basics
Chamber Consultation Hour:
S.No Faculty Name
1 Dr. B. Naresh Kumar Reddy
Structure & operation of MOS,
Ch.3.3,3.6- T
MOS Capacitances
Non-saturation and saturation, Gradual
Channel approximation, Channel length Ch 3.4-T Ch.1 R4
modulation
VTC, Resistive load inverter, Inverters
with n-Type MOSFET load, CMOS Ch 5.1-5.4- T
inverter
MOS Inverter - Switching
Ch 6.1-6.6 T
Characteristics and interconnect effects
NMOS Combinational logic circuits Ch 7.1-7.3 T
CMOS Combinational logic circuits Ch 7.4-7.5 T
Dynamic Logic Gates and Flip-
Flops: Design of Sequential Ch 8.1-8.5 T
circuits
Semiconductor memories
(i) Introduction, DRAM ,
Ch 10.1-10.6 T
SRAM
(ii) Flash Memory and FRAM
Power consumptions
i)switching power dissipation&
reduction Ch 11.1-11.3 T
ii)Short circuit power dissipation
ii) Leakage power dissipation
MOS small-signal model,
(i)Common source Amplifier
Ch 1.1-1.4 R1
(ii)CMOS inverter as an Amp.
(iii)Current Mirrors
Operational Amplifiers Ch 1.5-1..6 R1
Analog to Digital converter
Ch 1.7- 1.9 R1
Digital to Analog converter
Day Timings
Tuesday 3:00 PM – 4:00 PM
 Evaluation Scheme:
Student evaluation is based on the series of tests and quizzes conducted during the course of
semester followed by a comprehensive examination.

Evaluation Syllabus
Duration Weightage Date Remarks
Component (Lec.No.)
Test1 50 Minutes 20M 07/02/2020 1-15 CB
Test2 50 Minutes 20M 06/03/2020 1-30 CB
Test3 50 Minutes 10M 17/04/2020 1-45 OB
Unannounced
20 Minutes 10M
Quizzes(2)
Comprehensive
3 hours 40M 14/05/2020 1-45 CB
Exam

Make-up Policy: Prior and proper information to the concerned instructor is a must and the student
should maintain a minimum attendance.

General: All students are advised to attend classes regularly and strictly maintain an attendance of
75% at least. Students failing to maintain the required percentage of theory/practical attendance will
not be permitted to appear for the tests and examinations.

It is expected that students refrain from using cell phones during lectures and in the labs. The cell
phone must be kept switched off and used only during recess or outside class hours.

Dr. B. Naresh Kumar Reddy

Instructor-In-charge