PROJECT REPORT

Title: To Implement a switched capacitor current reference by using a high

gain designed OpAmp with UMC 180 nm technology scale.

BITS PILANI , KK BIRLA GOA CAMPUS

Submitted by: Sourav Satpathy

Reg No: 2018H1230169G
Ravi Raushan
Reg No:2018H1230163G

1
CONTENTS:

TOPICS PAGE

Introduction 3

Schematic and output of current reference 4

Final Design of OpAmp 7

Gain and phase margin 9

Slew rate 10

Power calculations 11

Bandwidth and Voltage swing 12-13

References 14

2
INTRODUCTION
switched capacitor is an electronic circuit element implementing a filter. It works by
moving charges into and out of capacitors when switches are opened and closed.
Usually, non-overlapping signals are used to control the switches, so that not all
switches are closed simultaneously. Filters implemented with these elements are
termed "switched-capacitor filters", and depend only on the ratios between
capacitances. This makes them much more suitable for use within integrated circuits,
where accurately specified resistors and capacitors are not economical to construct.
The simplest switched-capacitor (SC) circuit is the switched-capacitor resistor, made of
one capacitor C and two switches S1 and S2 which connect the capacitor with a given
frequency alternately to the input and output of the SC. Each switching cycle transfers
a charge q from the input to the output at the switching frequency.
Switched-capacitor circuits are analysed by writing down charge conservation
equations, as in this article, and solving them with a computer algebra tool. For hand
analysis and for getting more insight into the circuits, it is also possible to do a Signal-
flow graph analysis, with a method that is very similar for switched-capacitor and
continuous-time circuits.

Figure 1:switched capacitor basic circuit

3
CADENCE SCHEMATIC AND OUTPUT WINDOW

Figure 2:Schematic of the switched capacitor current reference

Figure 3:output waveforms of the designed current source

4
DESIGN OF OPAMP:
As depicted in the circuit above, a two stage op-amp was designed with first stage as a
differential single ended op-amp with current mirror loading, and second stage a
common source stage. Tail of first stage was designed in PMOS to achieve high CMRR .
Cascode tail was designed for differential pair due CMRR requirements. As a result of
tail cascode, Sooch current mirror was used to bias the cascode with low power
consumption of only 10uW in bias circuit. To achieve fast slewing per 5ns settling time
requirement, second stage was biased in large bias current. Discussion of the design will
be provided in Discussion section of the report. To have fast settling time and stability
in unity feedback configuration, phase margin of 60 degrees was designed, using miller
capacitance with nulling resistor technique. Per compensation technique used, the zero
generated was used to cancel the second pole, leaving first dominant pole and 3rd pole
the only poles in the system.

TRANSISTOR AND BIAS SUMMARY:

M1 M2 M3 M4 M5 M6 M7 M8

W(um) 12.74 12.74 7.54 7.54 54.925 145.795 39.065 36.205

L(um) 0.18 0.18 0.18 0.18 0.18 0.18 0.18 0.18

Id(uA) 155.5 155.5 155.5 155.5 1280.1 1280.1 311.1 311.1

Vgs(mv) 480 480 401 401 401 407 414 407

gm(mS) 2.5 2.5 3.0 3.0 25.2 23.9 6.2 5.8

go(uS) 24.3 24.3 33.8 33.8 274 199 49 47

5
DESIGN -1: Vcm=1.6v ,((W/L)7=37.5um/500nm) , Cc=800ff

Parameter Design Specification Cadence Result

Gain 60db 58.71db

Bandwith 30Mhz 26.45Mhz

Phase Margin 60deg 65.6deg

Power Dissip. 300uw 311.12uw

Slewrate 30/usec 26.07v/usec

Avg.Current 130uA 133.35uA

Voltage Swing <=1.2v 0.95v

We want to increase the unity gain bandwidth,and we can do it by varying miller capacitance
whose minimum value is 500ff.

DESIGN-2: Vcm=1.6v ,((W/L)7=37.5um/500nm) , Cc=600ff

Parameter Design Specification Cadence Result

Gain 60db 54db

Bandwith 30Mhz 31Mhz

Phase Margin 60deg 59.2deg

Power Dissip. 300uw 311.12uw

Slewrate 30/usec 31.06v/usec

Avg.Current 130uA 153.025uA

Voltage Swing <=1.2v 0.95v

In this case we get very less gain like 54db compare to 60 db,So to increase that we try to
increase the length that lead to increase in Rds as length modulation parameter get
decreases.

6
DESIGN-3(FINAL DESIGN): Vcm=1.6v ,((W/L)7=75um/1000nm) , Cc=800ff

Parameter Design Specification Cadence Result

Gain 60db 61db

Bandwith 30Mhz 33.13Mhz

Phase Margin 60deg 61deg

Power Dissip. 300uw 302.12uw

Slewrate 20v/usec 24v/usec

Avg.Current 130uA 133.35uA

Voltage Swing <=1.2v 1.02v

FINAL OPAMP DESIGN (UMC 180 nm scale )

Figure 4:Final OpAmp design

7
 • Discussion:

In this section I will explain how I designed the op-amp to meet the spec
listed in Performance section. I also provide hspice wave plots showing the
results. This section is divided into subsections for each metric: 1. Open Loop
DC gain, 2. pole-zero calculations (phase response) 3. Slew rate 4.Power
dissipation 5. Phase margin and 6.output swing.

1. Open Loop Differential Mode DC Gain:

Open Loop Different Mode DC Gain, Adm, is defined as:

Adm = vo/(inp - inn) = vo/vid

Adm_second_stage = gm1(ro2||ro4) * gm5(ro5||ro6)

2. Pole and Zero Calculation:

There are three node that can have poles: output node, output of first stage, and
gate of current mirror load in first stage, node 3. First let's see node 3 is a show
stopper:

C3=2/3W3L3Cox + 2/3W4L4Cox, where cox is eox/tox= 13.27 fF/um2.

Before I came up with final W and L values which are listed in the table of
Transistors Summary, I used smallest value for W and L, 190nm and 130nm
respectively, and a typical value for 1/gm3 which is the resistance seen by this

8
cap, C3, .1k for 1mA current in M3 and 0.1v vov3. The value for pole frequency at
this node came up to be 3.5THz. So, even making R and C associated for this pole
1000x larger which is not the case here, this pole is out of range of our operation,
so it can be ignored. Simulation results later confirmed this assumption.

Figure 5:Gain and Phase margin plot

The maximum gain we got as 61.13 db and the phase margin was turned to
be 58.17 degree

SLEW RATE : It is defined as the change of voltage or current, or any other

electrical quantity, per unit of time. Expressed in SI units, the unit of measurement
is volts/second or amperes/second or the unit being discussed, (but is usually
expressed in V/μs). Electronic circuits may specify minimum or maximum limits
on the slew rates for their inputs or outputs, with these limits only valid under
some set of given conditions (e.g. output loading). When given for the output of a
circuit, such as an amplifier, the slew rate specification guarantees that the speed
of the output signal transition will be at least the given minimum, or at most the
given maximum. When applied to the input of a circuit, it instead indicates that
the external driving circuitry needs to meet those limits in order to guarantee the
correct operation of the receiving device. If these limits are violated, some error
might occur and correct operation is no longer guaranteed. In other cases, a
maximum slew rate is specified in order to limit the high frequency content present

9
in the signal, thereby preventing such undesirable effects as ringing or radiated
EMI.

Figure 6:slew rate calculation table

Therefore the slew rate represents the maximum value for the OpAmp ie. 34.47 V/uS.

POWER DISSIPATION: The power consumed in a device is composed of two

types – dynamic, sometimes called switching power, and static, sometimes
called leakage power. In geometries smaller than 90nm, leakage power has
become the dominant consumer of power whereas for larger geometries,
switching is the larger contributor. Power reduction strategies can be used to
minimize both types of power.
Total power is the sum of the dynamic and leakage power

Total Power = Pswitching + Pshort-circuit + Pleakage

10
Dynamic power is the sum of two factors: switching power plus short-circuit power.

Switching power is dissipated when charging or discharging internal and net capacitances.
Short-circuit power is the power dissipated by an instantaneous short-circuit connection
between the supply voltage and the ground at the time the gate switches state.

Pswitching = a.f.Ceff.Vdd2

Where a = switching activity, f = switching frequency, Ceff = the effective capacitance and
Vdd = the supply voltage.

The DC power which we calculated turned out to be 302.01 uW.

11
BANDWIDTH: Devices such as operational amplifiers that are designed to have a
simple one-pole frequency response, the gain–bandwidth product is nearly
independent of the gain at which it is measured; in such devices the gain–
bandwidth product will also be equal to the unity-gain bandwidth of the amplifier
(the bandwidth within which the amplifier gain is at least) . For an amplifier in
which negative feedback reduces the gain to below the open-loop gain, the gain–
bandwidth product of the closed-loop amplifier will be approximately equal to that
of the open-loop amplifier.

Figure 7: Bandwidth Calculation

The bandwidth of the system designed is 35.2137 KHz

12
VOLTAGE SWING: Output voltage Swing: The ac output compliance PP is
the maximum unclipped peak to peak output voltage that an OPAMP can
produce. Since the quiescent output is ideally zero, the ac output voltage
can swing positive or negative. This also indicates the values of positive and
negative saturation voltages of the OPAMP.

Swing is the difference of maximum output voltage and minimum output voltage.
Maximum possible swing in output you can have is VDD-VSS. where VDD is most
positive voltage and VSS is most negative voltage. It does not mean that your swing
is VDD-VSS. It may be smaller than this. This depends on circuit design .For CMOS
logic family it is VDD-GND. It means CMOS logic family have full voltage swing.

Figure 8:Voltage Swing

The swing was calculated as 1.76 V – 0.617 V = 1.15 Volts.

13
 REFERENCES :

 Design of Analog CMOS integrated circuits by Behzad Razavi.

 National Programe on technology enhanced learning (OPAMP DESIGNING).
 A Low Jitter Digital Phase-Locked Loop With a Hybrid Analog/Digital PI Control
By Seok Min Jung and Janet Meiling Roveda .
 Frequency Synthesizers in Nanometer CMOS By R. Bogdan Staszewski IEEE
Dallas CAS CHAPTER.
 "Designs of All Digital Phase Locked Loop," 2014 Recent Advances in
Engineering and Computational Sciences (RAECS), Chandigarh, 2014, pp. 1-5.
doi: 10.1109/RAECS.2014.6799523
 A. M. Fahim, "A compact, low-power low-jitter digital PLL," ESSCIRC 2004 - 29th
European Solid-State Circuits Conference (IEEE Cat. No.03EX705), Estoril,
Portugal, 2003, pp. 101-104. doi: 10.1109/ESSCIRC.2003.1257082
 www.edaboard.com/showthread.php?75624
 https://www.youtube.com/
 https://en.wikipedia.org/wiki/Phase-locked_loop

14