LEC Runtime Reduction

Conformal LEC: Strategies for Runtime
Reduction
Product Version Conformal 15.1
September 2015
Copyright Statement
© 2015 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and the Cadence logo are
registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective
holders.
Learn more at Cadence Online Support - http://support.cadence.com

© 2015 Cadence Design Systems, Inc. All rights reserved worldwide. Page 2
Conformal LEC: Strategies for Runtime reduction
Contents
Purpose ....................................................................................................................... 4
How to monitor the runtime and memory used for the LEC process?.......................... 4
How to reduce runtime while reading the design and library files? .............................. 5
How to handle modeling of the design to reduce runtime? .......................................... 6
How to reduce the runtime for mapping? ..................................................................... 7
How to reduce runtime for Netlist to netlist comparison? ............................................. 9
How to handle runtime during a dynamic hierarchical run? ....................................... 10
How to handle the long runtime of comparison? ........................................................ 11
How to reduce runtime when facing aborts in the comparison? ................................ 12
How to speed up "analyze datapath" runtime using multithreading and other options?
................................................................................................................................... 13
Recommended dofile for faster runtime ..................................................................... 14
Summary ................................................................................................................... 17
References ................................................................................................................ 17
Support ...................................................................................................................... 17
Feedback ................................................................................................................... 17

Purpose
As the technology nodes are shrinking with time, the amount of logic placed on a chip is
increasing. The increased functionality on a single chip is resulting into highly complex
SoCs. Verification of these kinds of chips is a challenging and runtime-intensive activity.
This document provides the strategies that can help reduce the runtime at various
stages of the Conformal Equivalence Check flow.
How to monitor the runtime and memory used for the

LEC process?
The “Usage” is one of the most helpful command in monitoring the runtime. It displays
the total CPU runtime and memory used since the starting of the tool.
The Usage –auto –elapse command should be made a part of the run script. While
it will have a little overhead on runtime, the information can be used to track the step
that is taking long. You can use the information printed by the command to estimate the
runtime of the subsequent runs and debugging.
The “-auto” option will display the CPU and Memory usage at the end of every
command. For example:
CPU time: 72.01 seconds

Memory usage: 134.01 M bytes
The CPU time is the time consumed by the processor, and is not the same as the wall
clock time. Based on the output of this command, the machine and memory can be
chosen to make Conformal runs. Additionally, the runtime reduction technique can be
applied to the step taking the maximum time.
The “–elapse” option displays the wall time elapsed.

How to reduce runtime while reading the design and

library files?
Reading the design and libraries are basic inputs to the tool. Taking the right steps at
this stage will help reduce the runtime significantly. While reading the design and library
files, the following tips can help reduce the runtime:
• Before reading in the design and library files, make a list of all the analog blocks
and memories, and declare these as black box using the “add notranslate
module” command. Since the analog blocks and memories are hard macros and
are pre-verified, handle the digital blocks verification using Conformal.
• Reading Verilog libraries is faster than Liberty libraries because the Liberty cell
definition has a larger footprint than the equivalent Verilog definition.
• For single language design, use a single “read design” command instead of
multiple “read design”. To read the VHDL designs, use the mapfile option to
compile multiple files in different libraries.
For example, if you have two Verilog design files, test1.v and test2.v, you can
read both the files with the same read design command:
read design test1.v test2.v
• The use of “-keep_unreach” should be avoided in the “read design”

command because the unreachable logic will not reach any primary output. This
will add to runtime as the tool will take longer to elaborate the design.
• If you are aware of the top module of the design, you can specify it with the “-
root” option of the “read design” command. Along with this, use the “-
rootonly” switch as well. This will reduce the elaboration runtime because only
the root module will get elaborated instead of complete design scope.
• Large don’t care spaces can also increase the runtime. Hence, it is
recommended to have less number of X assignments in the RTL. The large
number of don’t care gates can also cause aborts later in the flow.

• Suppose you want to make some changes to one of the modules and then
reread that module. In such a scenario, you need not read the complete design
again. Instead, you can use the “-append” option. If you have made changes to
the “top.v” file, you can read this file again using the following command:
read design top.v –append –lastmod
Note: In the case of top module being read again, the parameter values will not
pass over.
How to handle modeling of the design to reduce

runtime?
During modeling, Conformal flattens/models the design on the basis of constraints and
modeling options specified in the setup mode.
Here are a few tips which can help resolve runtime related issues during modeling:
• Review all the specified flattening/modeling options because it is possible that a

few of these might not be required. Flatten model options allow to tailor the
modeling of design and should be in sync with the techniques used during
synthesis.
• Immediately before switching to LEC mode, run the “set flatten model”
command. This will show the complete list of flattening options with the status
ON or OFF. All those options whose defaults are changed will be shown with an
asterisk (*). Hence, you can check this list and disable the options which are not
required.
• One major cause of high runtime is the result of using the “set flatten
model –seq_merge” command. If this option is turned ON, the tool will try to
apply sequential merge on the complete design.
The recommended approach:
1. Read the log file of the synthesis tool using the “read setup
information” command. It helps because Conformal can read the merge
information from the log files. However, this information is verified by the tool
before use.
2. If you have either “set analyze option -auto” or “analyze setup”,

the tool will automatically run sequential merge in the LEC mode. The
advantage here is that the tool will try to merge only the not-mapped points.
3. If above two fail, get the list of merged points from the synthesis tool, and
read these using the “add instance equivalence” command.
• Look for the modeling message F34. It reports the message: F34: Convert X
assignment(s) as don’t care(s) (Occurrence: 1).
The high number of “X” increases the verification space because the tool will need to do
verification for all the combinations. If the occurrence is huge, it is recommended to
check the RTL because a high number of don’t care gates can increase the compare
runtime and also lead to aborts.
How to reduce the runtime for mapping?

Mapping happens immediately after the flattening/modeling of the design. During this
step, the key points on either side are mapped to each other. The mapping happens
automatically when the tool is switched from setup to LEC mode. By default, Conformal
tries to map the key points first on the basis of names and then based on functions (for
example, the driving logic to a key point). If the need is to specify certain commands
before mapping, use the “set system mode lec –nomap” command. In a primary
input and output, mapping happens strictly on the basis of names.
Here are the few things to consider while debugging runtime related issues during
mapping:
• If the message // Warning more than 1/3 of the key points have
mismatched names is encountered in the transcript window, It means that a
large number of key points have mismatched names. To handle this, create
renaming rules to match the names on either side. This reduces the runtime as
function-based mapping takes a lot of time as compared to name-based
mapping.
To apply the renaming rules, you can use the “add renaming rule” command. For
example:
add renaming rule my_rule “ABC” XYZ –golden

The rule will change the string “ABC” to “XYZ” on the golden side. For the detailed
description of this command, refer to Conformal reference manual.
The best approach to apply renaming rules is to do an iterative name-based mapping:
set mapping method –name only // This will turn on name based
mapping only.
set system mode lec
add renaming rule <rule name> ….
map key points
add renaming rule <rule name> ….
map key points
….
….
While it is iterative, it saves runtime because the name-based mapping is much faster
than the function-based mapping. This should be tried until the number of not-mapped
key points is zero.
• Check for the “set mapping method” command in your script. The command
can be used to change the default setting for mapping sequence, name-based
and then function-based. It is recommended not to change this setting because it
might result in higher runtime.
• To do phase mapping, turn on phase mapping only when you have already
compared the design. Here is the flow to use:
set mapping method –name first // Conformal’s default

map key points
add compare points –all
compare
delete mapped points –noneq
set mapping method –phase
map key points
add compare points –all
compare
In this case, phase mapping will run only on the nonequivalent key points. It will
save the runtime considerably because phase mapping takes much more time
than the normal mapping.

How to reduce runtime for Netlist to netlist

comparison?
While running netlist to netlist compare, consider the following points:
• First, ensure that the two netlists are of the same design flow. It is important
because if the netlists are of different flows, they can have different datapath
architectures for the arithmetic operators. In such a case, the run may result into
irresolvable aborts.
• For netlist to netlist comparison, use the “–gate_to_gate” option with compare
command. This option of the compare command enables an algorithm that might
improve runtime of large gate-to-gate netlist comparisons.
• The gate_to_gate is the most effective option in improving compare runtime

when the percentage of design similarity between the netlists is high. Using the
gate_to_gate option on netlists with low design similarity is not recommended
because it could lead to longer runtime.
• The "Report design similarity" command can be used in Conformal to

determine the similarity of design between golden and revised netlist.

How to handle runtime during a dynamic hierarchical

run?
For large hierarchical designs, it is recommended to run hierarchical compare while
doing RTL vs. netlist comparison. Conformal breaks the design into smaller modules
and then compares the modules one by one. There are two types of hierarchical
compare flows:
• Static Hierarchical Run
• Dynamic Hierarchical Run
Dynamic hierarchical compare is the recommended approach because the

nonequivalent sub-modules get compared at the parent level. For more details please
refer to the Chapter “Running Hierarchical Comparison” of Conformal User Guide.
The following key guidelines can help reduce runtime while using dynamic flow.
• In a dynamic hierarchical run, it is not recommended to use multithreading

because the overhead of multithreading process will negate the runtime
advantages of using multiple threads.
• Netlist to netlist comparison can also be done using dynamic hierarchical flow if
the two netlist are hierarchical.
• In a dynamic hierarchical run, if a large module is nonequivalent, it automatically

gets re-compared at its parent level. It is better to add it as a “nobbox” for
subsequent runs to reduce runtime. It can be done with the help of “add
noblack box” command. It will ensure that this module does not get written out
in the hierarchical dofile.

How to handle the long runtime of comparison?

• Comparison should be done with the default effort first. The comparison effort will
increase only if aborts are encountered. It can be controlled using the “set
compare effort” command.
• Using the “set compare effort auto” command might lead to a huge
runtime for comparison. If it is present in the dofile, it should be removed to
reduce the runtime.
• Compare runtime can be drastically reduced using the multithreading capability

of Conformal. The option “-threads” with compare allows multithreaded runs.
• The multithreading feature can be enabled automatically using the “set

parallel option” command.
• Using the “set compare effort light” command will also reduce the
runtime considerably. The compare engine in LEC can find non-eq more quickly
than it can find EQs. Hence, this option can be used to make sure that proper
design constraints and settings have been applied for the run. However, it result
in aborts.
• If datapath components are present, check the result of “analyze datapath”

for the datapath quality. Low datapath quality can lead to high runtime and
aborts.

How to reduce runtime when facing aborts in the

comparison?
Aborts are the key points that the tool is unable to categorize as equivalent or
nonequivalent in the specified time. This time depends on the compare effort used.
Aborts majorly contribute to runtime consumption. Hence, it is recommended to specify
the abort resolution commands in Conformal script. Some important tips:
• In general, using Hierarchical comparison, as against flat comparison, helps

avoiding aborts as the design is compared in small blocks or modules, one at a
time.
• For designs, especially with a large number of arithmetic operators, it is

recommended to do the synthesis planning based on the MDP flow. For more
details, you can refer to the Chapter “Resolving Aborts” of Conformal User
Guide.
• It is recommended to increase the compare effort before moving to abort analysis

and resolution.
• Also, the “analyze abort –verbose” command provides suggestions that

can help in abort resolution.
• Additionally, using multithreading also helps in abort resolution and reducing the
runtime.
• The following command can be used to enable multithreading:
SET PARALLEL OPTION -THREADS [<integer>[,<integer>]]
For example, in set parallel option –threads 2,4 command, ‘-thread

2, 4’ specifies a minimum of two and a maximum of four threads.

How to speed up "analyze datapath" runtime using

multithreading and other options?
The “analyze datapath” command analyzes datapath modules. Based on results of
the analysis, Conformal can automatically resolve multipliers, operator merging, and
resource sharing problems. It is very helpful in resolving aborts. However, the execution
of this command consumes a significant amount of runtime.
Here are a few suggestions which can optimize the runtime performance of “analyze
datapath”:
• Use the "-threads" option to speed up runtime as in the following example:
analyze datapath -module -threads 4 -verbose
Important points:
a. This "-threads" option ONLY works with module-based datapath analysis. Hence,
you must also specify "-module" option.
b. The "set parallel option -threads" command currently has no effect on

"analyze datapath" command. Hence, you will need to specify "-threads"
option within the "analyze datapath" command if you want to run multiple threads.
• Use "-effort low" to reduce the runtime of "analyze datapath".
Note: The analyze datapath (without -module) is not affected by the threads option.

Recommended dofile for faster runtime

The following dofile can be used for RTL to netlist hierarchical comparison as a
template for speeding up the runs:
//**************************************************************************
//*
//* Copyright (C) 2012-2015 Cadence Design Systems, Inc.
//* All rights reserved.
//*
//**************************************************************************
//**************************************************************************
//* The following illustrates a sample dofile for running
//* RTL vs gate netlist with hierarchical comparison flow.
//**************************************************************************
//**************************************************************************
//* Note: For more information on the commands/options used in
//* this sample dofile, launch the specific product and use the "MAN"
//* command or refer to that product's reference manual.
//**************************************************************************
//**************************************************************************
//* Optional lines of code are commented out. Uncomment if needed.
//**************************************************************************
//**************************************************************************
//* Sets up the log file and instructs the tool to display usage information
//**************************************************************************
set log file lec.hier.log.$LEC_VERSION -replace

usage -auto -elapse
//**************************************************************************
//* Specifies the LEC project that will collect and consolidate
//* information from multiple LEC runs
//**************************************************************************
set project name <project name>

set verification information <verification_information_directoy>
//**************************************************************************
//* Black box the memory and analog blocks
//**************************************************************************
add notranslate modules –both < module-names>
//**************************************************************************
//* Reads in the library and design files
//**************************************************************************

// * For Verilog library files

read library -verilog -replace -both \
<libfile1>.v \
<libfile2>.v
// * For Liberty library files

//read library -liberty -replace -both \
// <libfile1>.lib \
// <libfile2>.lib
read design -verilog -replace -golden -noelaborate \

<designfile1>.v \
<designfile2>.v
// * Use the following to specify a command file
//read design -verilog -replace -golden -noelaborate \

-file <commandfile>
elaborate design -golden
read design -verilog -replace -revised -noelaborate \

<designnetlist>.v
elaborate design -revised

report design data
report black box -detail
uniquify -all –nolibrary
report black box
//**************************************************************************
//* Specifies renaming rules
//**************************************************************************
//add renaming rule <rulename> <string><string> [-Golden |-Revised |-BOth]
//**************************************************************************
//* Specifies user constraints for test/dft/etc.
//**************************************************************************
//add pin constraint 0 scan_en -golden/revised
//add ignore output scan_out -golden/revised
//**************************************************************************
//* Specifies the modeling directives for constant optimization
//* or clock gating
//**************************************************************************
set flatten model -seq_constant
set flatten model -gated_clock
//**************************************************************************
//* Enables auto analysis to help resolve issues from sequential
//* redundancy, sequential constants, clock gating, or sequential merging
//* This option automatically enables 'analyze abort -compare' if there
//* are any aborts to solve the aborts.
//**************************************************************************

set analyze option -auto –noanalyze_abort

set datapath option -auto
//**************************************************************************
//* Specifies the number of threads to enable multithreading
//**************************************************************************
set parallel option -threads 4 -norelease_license
//**************************************************************************
//* Generates the hierarchical dofile script for hierarchical comparison
//**************************************************************************
write hier_compare dofile hier.do -replace -usage –threshold 500 \
-constraint -noexact_pin_match -verbose \
-prepend_string "report design data; usage; \
analyze datapath -module -resourcefile <file> -verbose; usage; \
analyze datapath -verbose; usage " \
-balanced_extraction -input_output_pin_equivalence \
-function_pin_mapping
//************************************************************************
// Executes the hier.do script
//**************************************************************************
run hier_compare hier.do -verbose
//**************************************************************************
//* Generates the reports for all compared hierarchical modules
//**************************************************************************
report hier result -all -usage

report hier result -abort -usage
report hier result -noneq -usage

Summary
It is recommended that you review the Conformal dofile before firing a run, and customize
it as per the design and synthesis strategy adopted. Add the suggested commands in the
flow from the beginning to make best use of the strategies provided. Applying the
strategies upfront will result in a significant reduction in the runtime and help in saving
unnecessary iterations.
References
Encounter Conformal Equivalence Checking User Guide
Encounter Conformal Equivalence Checking Command Reference
Visit Conformal 15.1 Product Manual Landing page for all the product manuals pertaining
to Conformal 15.1 release stream.
Documents for Conformal can be found on https://support.cadence.com
To get the product documentation for Conformal 15.1 go to Resources  Product

Manuals  Select Conformal 15.1
Support
Cadence Online Support provides access to support resources, including an extensive
knowledge base, access to software updates for Cadence products, and the ability to
interact with Cadence Customer Support. Visit https://support.cadence.com.
Feedback
Email comments, questions, and suggestions to content_feedback@cadence.com.


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Conformal LEC: Strategies for Runtime

Learn more at Cadence Online Support - http://support.cadence.com

Learn more at Cadence Online Support - http://support.cadence.com

How to monitor the runtime and memory used for the

CPU time: 72.01 seconds

The “–elapse” option displays the wall time elapsed.

Learn more at Cadence Online Support - http://support.cadence.com

How to reduce runtime while reading the design and

read design test1.v test2.v

• The use of “-keep_unreach” should be avoided in the “read design”

Learn more at Cadence Online Support - http://support.cadence.com

read design top.v –append –lastmod

How to handle modeling of the design to reduce

• Review all the specified flattening/modeling options because it is possible that a

The recommended approach:

2. If you have either “set analyze option -auto” or “analyze setup”,

How to reduce the runtime for mapping?

add renaming rule my_rule “ABC” XYZ –golden

Learn more at Cadence Online Support - http://support.cadence.com

The best approach to apply renaming rules is to do an iterative name-based mapping:

set mapping method –name first // Conformal’s default

Learn more at Cadence Online Support - http://support.cadence.com

How to reduce runtime for Netlist to netlist

• The gate_to_gate is the most effective option in improving compare runtime

• The "Report design similarity" command can be used in Conformal to

Learn more at Cadence Online Support - http://support.cadence.com

How to handle runtime during a dynamic hierarchical

Dynamic hierarchical compare is the recommended approach because the

• In a dynamic hierarchical run, it is not recommended to use multithreading

• In a dynamic hierarchical run, if a large module is nonequivalent, it automatically

Learn more at Cadence Online Support - http://support.cadence.com

How to handle the long runtime of comparison?

• Compare runtime can be drastically reduced using the multithreading capability

• The multithreading feature can be enabled automatically using the “set

• If datapath components are present, check the result of “analyze datapath”

Learn more at Cadence Online Support - http://support.cadence.com

How to reduce runtime when facing aborts in the

• In general, using Hierarchical comparison, as against flat comparison, helps

• For designs, especially with a large number of arithmetic operators, it is

• It is recommended to increase the compare effort before moving to abort analysis

• Also, the “analyze abort –verbose” command provides suggestions that

• The following command can be used to enable multithreading:

SET PARALLEL OPTION -THREADS [<integer>[,<integer>]]

For example, in set parallel option –threads 2,4 command, ‘-thread

Learn more at Cadence Online Support - http://support.cadence.com

How to speed up "analyze datapath" runtime using

• Use the "-threads" option to speed up runtime as in the following example:

analyze datapath -module -threads 4 -verbose

b. The "set parallel option -threads" command currently has no effect on

• Use "-effort low" to reduce the runtime of "analyze datapath".

Learn more at Cadence Online Support - http://support.cadence.com

Recommended dofile for faster runtime

set log file lec.hier.log.$LEC_VERSION -replace

set project name <project name>

add notranslate modules –both < module-names>

Learn more at Cadence Online Support - http://support.cadence.com

// * For Verilog library files

// * For Liberty library files

read design -verilog -replace -golden -noelaborate \

//read design -verilog -replace -golden -noelaborate \

elaborate design -golden

read design -verilog -replace -revised -noelaborate \

elaborate design -revised