10 Ways to fix SETUP and HOLD violation: Static Timing Analysis (STA) Basic (Part-8) |VLSI Concepts 10/07/18,

10/07/18, 10(36 PM

More

VLSI Concepts
Subscribe To VLSI EXPERT

Posts

Comments

An online information center for all who have Interest in Semiconductor Industry.
Translate page

Select Language

VLSI Basic STA & SI Extraction & DFM Low Power Physical Design Vlsi Interview Questions Job Posting Video Lectures VLSI Industr

Recommended Book

Index Search This Blog

Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Chapter7 Chapter8

STA & SI
Introduction Static Timing Analysis Clock Advance STA Signal Integrity EDA Tools Timing Models Other Topics
VLSI Basics
Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6
Extraction & Index
DFM Introductio Parasitic Interconnect Corner (RC Manufacturing Effects and Their Dielectric Process Other
n Corner) Modeling Layer Variation Topic Chapter 1: Digital Backgroun
Chapter 2: Semiconductor b
Chapter 3: CMOS Processin
Friday, January 10, 2014
Chapter 4: CMOS Basics
Chapter 5: CMOS Layout De
10 Ways to fix SETUP and HOLD violation: Static Timing Analysis (STA)
Basic (Part-8) Featured Post

Implant P+ Impurities: CM
STA & SI:: Chapter 2: Static Timing Analysis 5)
2.1 2.2 2.3a 2.3b 2.3c 2.4a
Implant P+ Impurities: CMOS P
Basic Concept Of Basic Concept of Setup-Hold Examples:S-H Chapter1 Chapter2 Chapter3
Timing Paths Time Borrowing Timing Path Delay
Setup-Hold Violation Time/Violation
2.4b 2.4c 2.5a 2.5b 2.6a 2.6b
Interconnect Delay Delay - Wire Load Maximum Clock Calculate “Max Clock Freq”- Fix Setup-Hold
Fix Setup-Hold Violation-1
Models Model Frequency Examples Violation-2
2.6c 2.7a 2.7b 2.7c 2.8
Fix Setup-Hold Incr/Decr Delay Incr/Decr Delay 10 ways to fix Setup-Hold
Incr/Decr Delay Method-3
Violation-3 Method-1 Method-2 Violation.

Static Timing analysis is divided into several parts:

Vlsi expert
Like Page
Part1 -> Timing Paths
Part2 -> Time Borrowing
Be the first of your friends to
Part3a -> Basic Concept Of Setup and Hold
Part3b -> Basic Concept of Setup and Hold Violation
Part3c -> Practical Examples for Setup and Hold Time / Violation
Part4a -> Delay - Timing Path Delay
Part4b -> Delay - Interconnect Delay Models
Part4c -> Delay - Wire Load Model
Part5a -> Maximum Clock Frequency
Part5b -> Examples to calculate the “Maximum Clock Frequency” for different circuits.
Part 6a -> How to solve Setup and Hold Violation (basic example)
Part 6b -> Continue of How to solve Setup and Hold Violation (Advance examples)
Part 6c -> Continue of How to solve Setup and Hold Violation (more advance examples)
VLSI EXPERT (vlsi EG)
google.com/+Vlsi-expert
Part 7a -> Methods for Increase/Decrease the Delay of Circuit (Effect of Wire Length On the Slew)
Bridging Gap Between
Part 7b -> Methods for Increase/Decrease the Delay of Circuit (Effect of Size of the Transistor On the Slew) Acdamia and Industry

Part 7c -> Methods for Increase/Decrease the Delay of Circuit (Effect of Threshold voltage On the Slew) Follow
Part 8 -> 10 ways to fix Setup and Hold Violation.
397 followers

10 Ways to fix SETUP and HOLD violation: Total Pageviews

Till now, We have discussed basic concepts of fixing the Setup and Hold violation which include

http://www.vlsi-expert.com/2014/01/10-ways-to-fix-setup-and-hold-violation.html Page 1 of 10
10 Ways to fix SETUP and HOLD violation: Static Timing Analysis (STA) Basic (Part-8) |VLSI Concepts 10/07/18, 10(36 PM

Different formulas + explanation to identify the type of violation in design.

How to fix those violations?
6,395,826
Different methods of Increasing and Decreasing the Delay in the circuit to fix these type of violations?
And Now it’s the time to list down different methods to fix these violations. I have also explained in brief each and every method, which
also referring previous post for reference. One point to remember here that Fixing the Setup and Hold Violation are reverse in nature. All the
methods which are applicable to fix one type of methods , hold true and can be apply to fix other type of if we will do the opposite thing. E.g - if
setup can be fix by adding 1 buffer in some path then Hold can be fix by removing buffer in that path. (You will see these things below in the post) Popular Posts

In the last you will also find DOs and DON'Ts and recommended approach to fix these violations. These Recommendations helps designer in "Timing Paths" : Static
reducing iteration and fix the violations fast. Timing Analysis (STA)
basic (Part 1)

8 Ways To Fix Setup violation: Basic of Timing

Setup violations are essentially where the data path is too slow compared to the clock speed at the capture flip-flop. Analysis in Physical
Design
With that in mind there are several things a designer can do to fix the setup violations.
"Setup and Hold Time"
Method 1 : Reduce the amount of buffering in the path. : Static Timing Analysis
(STA) basic (Part 3a)
It will reduce the cell delay but increase the wire delay. So if we can reduce more cell delay in comparison to
wire delay, the effective stage delay decreases. "Examples Of Setup
and Hold time" : Static
Timing Analysis (STA)
Method 2 : Replace buffers with 2 Inverters place farther apart basic (Part 3c)

Adding 2 inverters in place of 1 buffer, reducing the overall stage delay. "Setup and Hold Time
Violation" : Static
Adding inverter decreases the transition time 2 times then the existing buffer gate. Due to that, the Timing Analysis (STA)
RC delay of the wire (interconnect delay) decreases. basic (Part 3b)

As such cell delay of 1 buffer gate ≈ cell delay of 2 Inverter gate Delay - "Wire Load
So stage delay (cell delay + wire delay) in case of single buffer < stage delay in case of 2 inverter in Model" : Static Timing
Analysis (STA) basic
the same path. (Part 4c)
You will get the clear understanding by following figure and you can refer the first post to understand
how transition time varies across the wire. Delay - "Interconnect
Delay Models" : Static
Timing Analysis (STA)
basic (Part 4b)

"Time Borrowing" :
Static Timing Analysis
(STA) basic (Part 2)

10 Ways to fix SETUP

and HOLD violation:
Static Timing Analysis
(STA) Basic (Part-8)

5 Steps to Crack VLSI

Interview

EDN Feed

ReRAM enhances
edge AI -
Expect glitches… Is
your design
validated? -
How to sculpt a 16-
core 2 GHz
processor -
Parasitic extraction
must solve advanced
node issues -
Analog IC co-design
for latch-up
compliance -

Recent Visitors
Method 3 : HVT swap. Means change HVT cells into SVT/RVT or into LVT.
Low Vt decrease the transition time and so propagation delay decreases. Video Lectures
HVT/NVT/LVT type cells have same size and pin position. In both leakage current and speed, LVT>NVT>HVT.
So replace HVT with NVT or LVT will speed up the timing without disturb layout.
Followers
Negative effect: Leakage current/power also increases.
Followers (523) Next

Method 4 : Increase Driver Size or say increase Driver strength (also known as upsize the cell)
Explained the basic and details in the previous post
Note: Normally larger cell has higher speed. But some special cell may have larger cell slower than normal
cell. Check the technology library timing table to find out these special cells. Increasing driver is very
commonly used in setup fix.
Negative effect: Higher power consumption and more area used in the layout. Follow
I have notice one explanation in book <book name>. I am copying and pasting (not 100%) that here because I
like that one. J Marked the important part by Bold.
The basic layout technique for reducing the gate delay consists in connecting MOS devices in

http://www.vlsi-expert.com/2014/01/10-ways-to-fix-setup-and-hold-violation.html Page 2 of 10
10 Ways to fix SETUP and HOLD violation: Static Timing Analysis (STA) Basic (Part-8) |VLSI Concepts 10/07/18, 10(36 PM

parallel.
The equivalent width of the resulting MOS device is the sum of each elementary gate width. Both
nMOS and pMOS devices are designed using parallel elementary devices.
Most cell libraries include so-called x1, x2, x4, x8 inverters.
The x1 inverter has the minimum size, and is targeted for low speed, low power operations.
The x2 inverter uses two devices x1 inverters, in parallel. The resulting circuit is an inverter
with twice the current capabilities. The output capacitance may be charge and discharged
twice as fast as for the basic inverter (see below figure), because the Ron resistance of the
MOS device is divided by two. The price to pay is a higher power consumption.
The equivalent Ron resistance of the x4 inverter is divided by four.
The clock signals, bus, ports and long wires with severe time constraints use such high drive circuits.

Method 5 : Insert Buffers

Some time we insert the buffer to decrease over all delay in case of log wire.
Inserting buffer decreases the transition time, which decreases the wire delay.
If, the amount of wire delay decreases due to decreasing of transition time > Cell delay of buffer, over all delay
decreases.
Negative Effect: Area will increase and increase in the power consumption.

Method 6 : Inserting repeaters:

Concepts of Repeaters are same as I have discussed in “Inserting the Buffer” (above point). Just I am trying to
explain this in a different way but the over concept are same.

http://www.vlsi-expert.com/2014/01/10-ways-to-fix-setup-and-hold-violation.html Page 3 of 10
10 Ways to fix SETUP and HOLD violation: Static Timing Analysis (STA) Basic (Part-8) |VLSI Concepts 10/07/18, 10(36 PM

Long distance routing means a huge RC loading due to a series of RC delays, as shown in figure. A good
alternative is to use repeaters, by splitting the line into several pieces. Why can this solution be better in
terms of delay? Because the gate delay is quite small compared to the RC delay.

In case of Interconnect driven by a single inverter, the propagation delay become

Tdelay= tgate+ nR.nC = tgate + n​2RC
If two repeaters are inserted, the delay becomes:
Tdelay=tgate (delay of inverter) + 2tgate (delay of repeater) +3RC = 3tgate + 3RC
So you can see how RC delay is impacting in case of non-repeater in the circuit.
Consequently, if the gate delay is much smaller than the RC delay, repeaters improve the switching speed
performances, at the price of higher power consumption.
Below figure helps you to understand the practical use of this.

Method 7 : Adjust cell position in layout.

Let’s assume there are 2 gate (GATE A and GATE B) separated by 1000um. There is another GATE C placed
at the distance of 900um from GATE A.
If we re-position the GATE C at 500um from GATE A (center of GATE A and B), overall delay between GATE A
and B decreases.
You will get the clear understanding by first post and the following diagram.
Note: The placement in layout may prevent such movement. Always use layout viewer to check if there are
any spare space to move the critical cell to an optimal location.

http://www.vlsi-expert.com/2014/01/10-ways-to-fix-setup-and-hold-violation.html Page 4 of 10
10 Ways to fix SETUP and HOLD violation: Static Timing Analysis (STA) Basic (Part-8) |VLSI Concepts 10/07/18, 10(36 PM

Method 8 : Clock skew:

By delaying the clock to the end point can relax the timing of the path, but you have to make sure the
downstream paths are not critical paths.
Related to clock skew basic – I will discuss that in SI section.

2 Ways to Fix Hold Violations:

Hold violation is the opposite of setup violation. Hold violation happen when data is too fast compared to the clock
speed. For fixing the hold violation, delay should be increases in the data path.
Note: Hold violations is critical and on priority basis in comparison are not fixed before the chip is made, more there is
nothing that can be done post fabrication to fix hold problems unlike setup violation where the clock speed can be
reduced.
The designer needs to simply add more delay to the data path. This can be done by

Method 9 : By Adding delays.

Adding buffer / Inverter pairs /delay cells to the data path helps to fix the hold violation.
Note: The hold violation path may have its start point or end point in other setup violation paths. So we have to
take extra care before adding the buffer/delay.
E.G. if the endpoint of hold violation path has setup violation with respect to some other path, insert
the buffer/delay nearer to start point of hold violation path. Else the setup violation increases in other
path.
if the start point of hold violation path has setup violation with respect to some other path, insert the
buffer/delay nearer to end point of hold violation path. Else the setup violation increases in other path.
I am sure you may be asking what is this and why?
Below figure and explanation can help you to understand this.
From below figure, you can also conclude that don’t add buffer/delay in the common segment of 2
paths (where one path has hold violation and other setup violation).

http://www.vlsi-expert.com/2014/01/10-ways-to-fix-setup-and-hold-violation.html Page 5 of 10
10 Ways to fix SETUP and HOLD violation: Static Timing Analysis (STA) Basic (Part-8) |VLSI Concepts 10/07/18, 10(36 PM

Method 10 : Decreasing the size of certain cells in the data path.

It is better to reduce the cells closer to the capture flip flop because there is less likely hood of affecting other
paths and causing new errors.

Note: Following points are recommended while fixing setup and hold violations.
Make modification to the data path only.
Adjusting register location or removing/adding buffers to the clock path will fix the violation that but it
may cause more violations for some other paths which may not present before.
First try to fix setup violation as much as possible. Then later on start fixing hold violation.
In general, hold time will be fixed during back-end work (during PNR) while building clock tree. If u r a front-end designer, concentrate on
fixing setup time violations rather than hold violations.
Fix all the hold violation, if you have to choose between setup and hold.
If a chip is done with some setup violations it can work by reducing the frequency.
If a chip is done with hold violations, we have “JUST DUMP” the chip.

Effect of Threshold voltage On the Slew (Previous) Index Clock Skew.html (Next)

Posted by VLSI EXPERT at 5:17 PM

Reactions: Excellent (16) Good (1) Interesting (0) Need More (2)

36 comments:
Anonymous February 16, 2014 at 2:00 PM
Awesome Learning Experience. It is a very interesting blog to refresh the concepts on STA. Thank you:)

Reply

Anonymous March 7, 2014 at 2:24 AM

Kudos to you!! This is one great blog for learners like me! Thank you loads for all your effort! May god bless you!
Reply

Anonymous April 20, 2014 at 7:31 PM

really nice to learn...

Reply

http://www.vlsi-expert.com/2014/01/10-ways-to-fix-setup-and-hold-violation.html Page 6 of 10