11/9/2017 Fixing Setup and Hold Violation : Static Timing Analysis (STA) Basic ( Part 6c) |VLSI Concepts

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STA & SI
Introduction Static Timing Analysis Clock Advance STA Signal Integrity EDA Tools Timing Models Other Topics

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Wednesday, November 21, 2012

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Fixing Setup and Hold Violation : Static Timing Analysis (STA) Basic ( Part 3Ps (Passion, Pati
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Part1 Part2 Part3a Part3b Part3c Part4a Part4b Part4c Part5a
Part5b Part6a Part6b Part6c Part7a Part7b Part7c Part 8

Static Timing analysis is divided into several parts:

Part1 -> Timing Paths

Part2 -> Time Borrowing
Part3a -> Basic Concept Of Setup and Hold
Part3b -> Basic Concept of Setup and Hold Violation
Part3c -> Practical Examples for Setup and Hold Time / Violation
Part4a -> Delay - Timing Path Delay
Part4b -> Delay - Interconnect Delay Models VLSI EXPERT (v
google.com/+Vlsi-e
Part4c -> Delay - Wire Load Model
Bridging Gap Betw
Part5a -> Maximum Clock Frequency Acdamia and Indu
Part5b -> Examples to calculate the “Maximum Clock Frequency” for different circuits.
Part 6a -> How to solve Setup and Hold Violation (basic example)
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Part 6b -> Continue of How to solve Setup and Hold Violation (Advance examples)
Part 6c -> Continue of How to solve Setup and Hold Violation (more advance examples)
Part 7a -> Methods for Increase/Decrease the Delay of Circuit (Effect of Wire Length On the Slew)
Part 7b -> Methods for Increase/Decrease the Delay of Circuit (Effect of Size of the Transistor On the Slew) Total Pageviews

Part 7c -> Methods for Increase/Decrease the Delay of Circuit (Effect of Threshold voltage On the Slew)
5,366,378
Part 8 -> 10 ways to fix Setup and Hold Violation.

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11/9/2017 Fixing Setup and Hold Violation : Static Timing Analysis (STA) Basic ( Part 6c) |VLSI Concepts

In the last part/post we have discussed 2 more examples with different specifications with more restrictions (Both net delay and
Tck2Q were ideal means 0ns) and figure out that if you want to fix the violation by increasing/decreasing the delay in the data path
then following condition should be satisfied. Subscribe To VLSI EXP

Min delay of Combinational path > Hold time of Capture FF. Posts
Max delay of Combinational path < Clock Period - Setup time of Capture FF. Comments

Clock Period >= Setup time + Hold time.

But in case if you can’t touch the data path and you have to increase/decrease the delay in the clock path (means between “Clk pin
to Launch FF clock pin” Or between “Clk pin and capture FF clock pin”), then following conditions should satisfied.

Max Delay/ Setup Condition:

Td < Clk_Period + (T_capture - T_launch) – T_setup

Min Delay / Hold Condition:

Td > (T_capture - T_launch ) + T_hold Edusaksham
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Where: INR 5,750.00
Td -> Combinational path delay (between the 2 FFs)
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T_capture -> Delay of circuit present between “Clk pin and capture FF clock pin”
T_launch -> Delay of circuit present between “Clk pin to Launch FF clock pin”

In this post we will discuss few more examples with more restrictions.
Let’s consider the following figure common to all examples until unless it’s specified.

Edusaksham
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(Part 4c)

Specification of the FF Circuit "Setup and Hold Tim

Setup Hold Clock period Tck2q delay Net Delay Combinational Logic Delay Violation" : Static
3ns 2ns 10ns 0ns (Ideal) 0ns (Ideal) 11ns (can’t be further reduced) Timing Analysis (ST
basic (Part 3b)

On the basic of last post …let’s start with checking few conditions directly. "Examples Of Setup
and Hold time" : Sta
Clock Period Condition: (Satisfied) Timing Analysis (ST
basic (Part 3c)
Setup time +Hold time = 5ns
Clock period = 10ns Delay - "Interconnec
Clock Period > Setup time +Hold time (10> 5) Delay Models" : Sta
Timing Analysis (ST
basic (Part 4b)
Min delay / Hold Condition: (Satisfied)
Combinational Delay (11ns) > Hold time. "Time Borrowing" :
Means - NO HOLD VIOLATION Static Timing Analys
(STA) basic (Part 2)
Max Delay / Setup Condition:
5 Steps to Crack VL
Combinational delay (11ns) Is Not Less Than “Clock period (10ns) – Setup (3ns)” Interview
Means - SETUP VIOLATION.
10 Ways to fix SETU
Since adding delay in the data path is not going to fix this violation and we can’t reduce the combinational delay. So as we have and HOLD violation
Static Timing Analys
discussed in our last post, we will try with Clock path. (STA) Basic (Part-8)

From the last post, if T_capture is the delay of buffer which is inserted between the CLK and Capture’s FF and T_launch is the
delay of buffer which is inserted between the CLK and Launch’s FF, then Recent Visitors

Max Delay /Setup condition is :

Td < Clock Period + (T_capture - T_launch) – T_setup

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11/9/2017 Fixing Setup and Hold Violation : Static Timing Analysis (STA) Basic ( Part 6c) |VLSI Concepts
=> 11ns < 10ns – 3ns + (T_capture - T_launch) Live Traffic Feed
=> 11ns < 7ns + (T_capture - T_launch) A visitor from Ban
=> 4ns < (T_capture - T_launch) Karnataka arrived f
google.co.in and vi
Now we can choose any combination of T_capture and T_launch such that their difference should be less than 4ns. ""Setup and Hold T
Note: Remember in the design if you are fixing the violation by increasing or decreasing the delay in the Clock path then always Static Timing Anal
prefer not to play too much with this path. (STA)
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basic (Part 1) |VLS
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=> 11ns > 5ns + 2ns Sequential Circuit
=> 11ns > 7ns – Means No Hold Violation. A visitor from Sant
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3ns 5ns 10ns 0ns (Ideal) 0ns (Ideal) 2ns (can’t be further reduced and viewed "Synopsys
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Td > (T_capture - T_launch ) + T_hold
Combinational Delay = 2ns
There is no delay in the clock path till now, so T_capture=T_launch=0ns
=> Td (2ns) is not greater than 0ns + T_hold (5ns)
Means HOLD VIOLATION
Followers

Since we can’t make change in the delay path, so we have to touch the clock path.
For Hold fixing -
=> Td > (T_capture - T_launch ) + T_hold
=> 2ns > (T_capture - T_launch ) + 5ns
=> -3ns > (T_capture - T_launch )

For Satisfying the above equation T_launch should have more value in comparison to T_capture.
We can choose any combination of T_capture and T_launch.

Note: Remember in the design if you are fixing the violation by increasing or decreasing the delay in the Clock path then always
prefer not to play too much with this path.

I will never prefer to use T_capture in this case (For Hold fixing, I ignore to use T_capture).
So let’s assume T_capture =0ns and T_launch = 4ns

Then

T_launch + Td > 5ns (hold time)

=> 4ns +2ns > 5ns NO HOLD Violation.
Check once again the Setup Condition:
Td < Clock Period + (T_capture - T_launch) – T_setup
=> 2ns < 10ns + 0ns -4ns – 3ns
=> 2ns < 3ns Means No Setup Violation.

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11/9/2017 Fixing Setup and Hold Violation : Static Timing Analysis (STA) Basic ( Part 6c) |VLSI Concepts

Note: (T_capture - T_launch) also known as CLOCK SKEW. I will explain this later in this blog. Right now, it’s Just for your info.

Example 7:
Specification of the FF Circuit
Setup Hold Clock period Tck2q delay Net Delay Combinational Logic Delay
6ns 5ns 10ns 0ns (Ideal) 0ns (Ideal) 0.5ns

Note: this is the same example which we have discussed in the part-6a. Let’s check all the conditions one by one.

Clock Period Condition (Not Satisfied):

Setup time +Hold time = 11ns
Clock period = 10ns
Clock Period is not greater than Setup time +Hold time
Means we can’t fix violations, if there is any.

But still we will try once again with all other conditions, just to prove that above mention condition should be true for fixing
the violations.

Max Delay/ Setup Condition (Satisfied):

Td < Clk_Period + (T_capture - T_launch) – T_setup
Combinational Delay = 0.5ns
There is no delay in the clock path till now, so T_capture=T_launch=0ns
=> Td (0.5ns) < Clk_period (10ns) + 0ns – T_setup (6ns)
=> 0.5ns < 4ns – Means NO SETUP Violations

Min Delay / Hold Condition (Not Satisfied):

Td > (T_capture - T_launch ) + T_hold
Combinational Delay = 0.5ns
There is no delay in the clock path till now, so T_capture=T_launch=0ns
=> Td (0.5ns) is not greater than 0ns + T_hold (5ns)
Means HOLD VIOLATION

If you want to fix the Hold violation, then we have already seen that by increasing/decreasing the delay in the data path it can’t be
fixed. Even if this will fixed, then Setup violation will occur.
Let’s Try with T_capture or T_launch. Means by adding delay in the clock circuit.

As per the above equations/conditions and corresponding values:

Max Delay/ Setup Condition :
Td < Clock Period + (T_capture - T_launch) – T_setup
=> Td < 10ns -6ns + (T_capture - T_launch)
=> Td < 4ns + (T_capture - T_launch)

Min Delay / Hold Condition:

Td > (T_capture - T_launch ) + T_hold
=> Td > (T_capture - T_launch ) + 5ns

Remember all 3 variable Td,T_capture,T_launch are positive number.

Possible values of (T_capture - T_launch) = +/-A (where A is a positive number)

Case 1: (T_capture - T_launch) = +A

=> Td < 4ns+A - Condition (a)

=> Td> 5ns+A – Condition (b)
Satisfying both the conditions (“a” and “b” ) not possible for any +ive value of A.

Case 1: (T_capture - T_launch) = -A

=> Td< 4ns-A => Td+A < 4ns - Condition (a)

=> Td> 5ns-A => Td +A > 5ns - Condition (a)
Satisfying both the conditions (“a” and “b”) not possible for any +ive value of A.

That means, I am successfully able to prove that if following condition is not satisfied then you can’t fix any type of violation by
increasing/decreasing delay in either data_path or clock_path.

Clock Period > Setup time + Hold time.

Summary of this post:

Clock Period Condition:

Clock period > Setup time + Hold Time
For fixing any type of violation (without changing Clock period) - This condition should be satisfied.

Max Delay/ Setup Condition:

Td < Clk_Period + (T_capture - T_launch) – T_setup
For Fixing the Setup Violation – Always prefer T_capture over T_launch
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11/9/2017 Fixing Setup and Hold Violation : Static Timing Analysis (STA) Basic ( Part 6c) |VLSI Concepts

Min Delay / Hold Condition:

Td > (T_capture - T_launch ) + T_hold
For Fixing the hold Violation – Always prefer T_launch over T_capture.

Till now we have discussed almost all the necessary basic of fixing the violation of Setup and Hold time. You have been noticed that
everywhere I have talked about the increasing/decreasing the delay. If I have mentioned anywhere adding/removing the buffer, that
also mean increasing/decreasing the delay.

There are several other ways through which you can increase/decreasing the delay of the circuit. In the next post we will discuss

Different methods for increasing/decreasing the delay in a circuit/path.

Also try to capture the basics behind above said methods one by one

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Posted by VLSI EXPERT at 11:53 AM

Reactions: Excellent (2) Good (0) Interesting (0) Need More (0)

13 comments:
Anonymous January 4, 2013 at 3:01 PM

Hi,

I have a doubt i.e., in Max delay/setup condition you used

Td < Clk_Period + (T_capture - T_launch) – T_setup
But for setup T_capture - T_launch is nothing but clock period. so you are adding clk_period twice what is the reason behind that.

Reply

Replies

Master May 29, 2013 at 12:22 PM

I guess (T_capture - T_launch) is the SKEW and not the period, it is the time taken by the launch clock to reach the capture clock
incorpofrating wired delays etc.

Reply

dissertation help January 12, 2013 at 10:34 AM

Thanks for announcement this advisory article.

Reply

Anonymous March 21, 2013 at 1:39 PM

Hi,

Thanks for providing the materiel on setup and hold time violations.But I Have one doubt,how to findout the timing violations,the logfile will report the
0(Zeros) and 1(once) and how to find out the which FF having the violation.

Thanks & Regards

Subbu

Reply

Anonymous July 19, 2013 at 9:32 AM

eagerly waiting for the next post... thanx for sharing the info :)

Reply

Ankita Sharma September 3, 2013 at 12:59 PM

sir can you provide some questions considering all the delay (in form of waveforms)pls

Reply

Ranjan Kumar September 6, 2013 at 7:18 PM

Wow... Thanks a lot for your such supreme explanation and providing us very neat answers.

Also please continue this post explanation with clock-->Q delay for FF.

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11/9/2017 Fixing Setup and Hold Violation : Static Timing Analysis (STA) Basic ( Part 6c) |VLSI Concepts

Thanks you so much.

Reply

Srinivas G September 14, 2013 at 8:52 PM

Great blog for timing analysis stuff.. Looking forward for your next blog.
It would be good if you can give tips on fixing the violations from RTL coding point of view.

Reply

SAMEER GARG October 23, 2013 at 6:32 PM

EXCELLENT....now i got clock skew concept ...thanks a lott sir...

Reply

vijay December 2, 2013 at 12:46 AM

Wow... Last few posts explaining concepts with examples are ULTIMATE.... These examples made me to think rather than just knowing the concepts
alone... Great work !!! Looking forward for your future posts of 7 series....
Thank you so much
Vijay

Reply

Sulman December 9, 2013 at 4:35 AM

Nice and easy explanation of different possible cases.

Great Job... THANKS

Reply

Saar Barkai August 5, 2015 at 12:28 PM

First of all, Thank you for this blog. It has been very useful.

Second, I'd like to correct a possible mistake:

On example 5 you said: "Now we can choose any combination of T_capture and T_launch such that their difference should be less than 4ns".
In fact, (as you stated in the equation) the difference between T_capture and T_launch should be GREATER than 4ns.

Reply

Deepak kumar May 31, 2017 at 9:51 AM

what a blog! one of the nicest teaching styles and intuition I have ever encountered ..

Reply

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