Design Name :- MP Design

Design QoR
Utilization Total cells Flops Buffers Inverters
Floor plan 63.4 232 43 13 12
Placemnet 66.5 235 43 11 12
CTS 69.3 243 43 11 25
Route 1 243 43 11 25

Timing QoR
Setup Hold
DRV's No . DRV's
WNS TNS Of WNS TNS No . Of
violations violations
Floor plan 23.794 0 0 NILL NILL NILL
Placemnet 23.794 0 0 NILL NILL NILL
CTS 23.645 0 0 0.069 0 0
Route 23.83 0 0 0.001 0 0

Routing QoR
Antenna Shorts Opens DRC
Floor plan 44 0 0 0
Placemnet 120 762 50 978
CTS 44 0 0 985
Route 44 45 0 47
Design Name :-

Design QoR
Utilization Total cells Flops Buffers Inverters
Floor plan
Placemnet
CTS
Route

Timing QoR
Setup Hold
DRV's No . DRV's
WNS TNS Of WNS TNS No . Of
violations violations
Floor plan 0 0 0 0 0
Placemnet 49.03 0 0 0 0 0
CTS 49.03 0 0 0.05 0 0
Route 49.03 0 0 0.05 0 0

Routing QoR
Antenna Shorts Opens DRC
Floor plan 6 0 0 0
Placemnet 10 81 0 161
CTS 10 91 0 171
Route 10 4 0 4
Design Name :- Dma_mac

Design QoR
Utilization Total cells Flops Buffers Inverters
Floor plan 0% 0 0 0 0
Placemnet 58% 27248 5026 214 2580
CTS
Route

Timing QoR
Setup Hold Setup

DRV's No . DRV's
WNS TNS Of violating WNS TNS No . Of max_cap
paths violations

Floor plan 0 0 0 0 0 0
Placemnet -0.105 -0.191 2 0 0 0 0
CTS
Route

Routing QoR
Antenna Shorts Opens DRC
Floor plan - - - -
Placemnet 377 250 246 1000
CTS
Route
 Setup hold

max_tran Worst max_fanout max_cap max_tran Worst

Violation Violation max_fanout

44 (66) -1.052 0 0 0 0 0
Design Name :- Dma_mac in Rectilinear shape

Design QoR

Buffers /CLK Inverters /

Utilization / Total cells Flops CLK
Density Buffers Inverters
Floor plan 69% / 25.50% 23816 5027 1 2400
Placemnet 70% 26008 5026 1102 / 120 2783 / 98
CTS
Route

Timing QoR
Setup Hold

DRV's No . DRV's
WNS TNS Of violating WNS TNS No . Of
paths violations

Floor plan -1.469 -159.245 152 0 0 0

Placemnet -0.033 -0.237 13 0 0 0
CTS
Route

Routing QoR
Antenna Shorts Opens DRC
Floor plan 10 - - -
Placemnet 354 306 296 0
CTS
Route
 Setup hold

max_cap max_tran Worst max_fanout max_cap max_tran Worst

Violation Violation max_fanout

0 0 0 0 0 0 0 0
0 52 (96) -1.336 0 0 0 0 0