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(Ver. 1.5_P. 1)
P-Sub, Mixed-Mode and RFCMOS Process
1. Contents Page
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1. Content 2
2. Revision History 3
3. Model Description 7
3.1 Model Description 7
3.2 N/PMOS Model 7
3.2.1 Description 7
3.3 Resistor Model 8
3.3.1 Description 8
3.4 BJT Model 8
3.4.1 Description 8
3.5 Diode Model 9
3.5.1 Description 9
3.6 MIM Model 9
4. Appendix 10
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2. Revision History:
Ver. Phase Approved From To Remark
Date (Purpose)
1.2 1 11/06/2002 (1). separate model card (1). modified and unified These models
format: model card format: are for 8C only.
G-05-MIXEDMODE/RFCMOS G-05-MIXED_MODE/RFCM
18-1.8V-SPICE OS18-1.8V/3.3V-TRIPLE_W Modified and
G-05-MIXEDMODE/RFCMOS ELL/MMC-SPICE-8C unified model
18-1.8V-TRIW-SPICE card format and
G-05-MIXEDMODE/RFCMOS device model
18-3.3V-SPICE name .
G-05-MIXEDMODE/RFCMOS
18-3.3V-TRIW-SPICE Triple well
G-05-MIXEDMODE/RFCMOS 1.8V/3.3V
18-1.8V-ZEROVT-SPICE regular Vt
NMOS device
models are
replaced by twin
(2). Delete (2). New device model name well 1.8V/3.3V
1.8V/3.3V NMOS/TW 1.8V N/PMOS regular Vt
1.8V LOW VT N/P MOS N_BPW_18_MM NMOS device
3.3V LOW VT N/PMOS 3.3V N/PMOS models.
1.8V/3.3V ZERO VT NMOS N_BPW_33_MM
salicide N+/P-well diode
(2). Change device model DION_MM Revised some
name salicide P+/N-well diode typo for diode
1.8V N/PMOS DIOP_MM model.
N salicide N_well/P-sub diode
3.3V N/PMOS DIONW_MM Add
N temperature
salicide N+/P-well diode (3).Replace triple well parameters for
DN 1.8V/3.3 V regular vt NMOS diode model.
salicide P+/N-well diode device model by twin well
DP 1.8V/3.3V regular vt NMOS Add resistor
salicide N_well/P-sub diode device model model.
DNW
(3). No resistor model (4). Add resistor model
Salicide N_well/P-sub
diode:
IBV=1E-03
TLEV=1
TLEVC=1
1.3 1 04/30/2003
(1)DLC=4.00E-8,LLC=-6.64E- (1)Revised DLC=2.9E-8
15 for 1.8V regular Vt NMOS ,LLC=-2.14E-15 for 1.8V
model regular Vt NMOS model Add ADS
simulator model
(2)No ADS simulator model (2)Add ADS sumulator format
format model format
Typo fixed
(3)No TRM1 parameter in (3)Add TRM1=0.0035 in
both PNP_V50X50_MM and PNP_V50X50_MM BJT
PNP_V100X100_MM BJT model and TRM1=0.004 in
model PNP_V100X100_MM BJT
model
(4)Typo CTA=1.0E-3,
CTP=7.53E-4, PTA=1.55E-3 , (4)Revise CTA=9.19E-4,
PTP=1.24E-3 in N+/PWELL CTP=9.14E-4,PTA=1.58E-3
SPECTRE Diode Model , PTP=9.24E-4 inN+/PWE
LL SPECTRE Diode Model
3. Model Description
3.1 Model Description
3.1.1 Simulators : HSPICE Version 2003.3 SP1 , SPECTRE Version 4.4.6 and ELDO Version 5.6 and ADS Version
2002C.200
File Name :
a. 1.8V Device :
MM180_REG18BPW_V123.lib
MM180_REG18BPW_V123.mdl
MM180_REG18BPW_V123.pdf
b. 3.3V Device :
MM180_REG33BPW_V123.lib
MM180_REG33BPW_V123.mdl
MM180_REG33BPW_V123.pdf
Usage :
File Name :
MM180_RES_V141 .lib
MM180_RES_V141 .mdl
MM180_RES_V141 .pdf
Usage :
3.4.1 Description
File Name :
MM180_BJT_V112.mdl
MM180_BJT_V112.pdf
Usage :
Layout issue :
Users should notice that the model is non-scalable,the model
doesn't guarantee the behavior if using other sizes.
3.5.1 Description
File Name :
MM180_DIODE_V113.mdl
MM180_DIODE_V113.pdf
Usage :
4. Appendix
4.1 Warning message VS Ignore highlight
Model name HSPICE SPECTRE ELDO ADS Ignore
Highlight
MIM model mimcaps_mm -- -- -- --
Resistor model rnnpo_mm -- -- -- --
rnppo_mm -- -- -- --
rnhr1000_mm -- -- -- --
Diode model DION_MM -- -- -- --
DIOP_MM -- -- -- --
DIONW_MM -- -- -- --
MOS model N_BPW_18_MM device Warning.xckt.m -- Please ignore
geometries will 1: `Pdiblc2' = the warning in
not be checked -15.6508e-03 is the hspice
against the negative. simulation
limits set by xckt.m1: `Cdscd' t’s necessary
lmin, lmax, = -500e-06 is to get good fit,
wmin and negative. but would
wmax. To cause a
enable this harmless
check, add a warning in
period(.) SPECTRE.
to the model
name(i.e.
enable model
selector).
large.
N_ BPW_33_MM -- -- --
BJT model pnp_v50x50_mm -- Warning -- -- Please ignore
pnp_v100x100_mm xckt.q1: the warning in
Parasitic theSPECTRE
resistor `re' has simulation
been deleted
because its
value of 1
mOhm ( R /
(Area *
MFactor) ) was
smaller than
`minr'.
* END *