Compal La-9901p r1.0 Schematics PDF

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1 1
2
Compal Confidential 2
G400S/G500S DIS M/B Schematics Document

Intel Ivy Bridge Processor with DDRIII + Panther Point PCH
nVIDIA N14X
LA-9901P
3
2013-03-20 3
REV:1.0
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VILG1/G2 MB LA9901P Schematic
Date: Wednesday, March 20, 2013 Sheet 1 of 63
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Compal confidential
File Name :LA-9901P
1
Chief River 1
NVIDIA GB4-128 29 x 29 mm PEG 8x Intel Memory Bus 204pin DDRIII-SO-DIMM X2
ˢˢ1600MHz
N14M-GE/N14P-GV2/N14P-GS Gen2 / Gen3 Processor Dual Channel BANK 0, 1, 2 page 12,13
VRAM 512MB/1GB/2GB DDR3
Ivy Bridge
ˢ1333MHz
N14M-GE/N14P-GV2: DDR3 x 4
N14P-GS: DDR3 x 8 page 23~32 DDR3
DDR3 1066MHz
rPGA989
37.5mm x 37.5mm
page 5~11
FDI *8 DMI2 *4
2.7GT/s 5GT/s
2 LVDS Conn. Left USB3.0 x2 Right USB2.0 Int. Camera

2
page 33
USB30 x2 USB30 Port 0,1 USB20 Port 9 USB20 Port 3
page 45 page 43 page 33
HDMI Conn. USB20 x6 Touch Screen Card Reader

page 35
Realtek RTS5170
USB20 Port 2
page 45 USB20 Port 11 page 43
CRT Conn. Intel
page 34
PCH
LAN Panther Point SATA Gen3 HDD Conn.
PCIe Port 1 PCIe x1
RJ45 Conn. Atheros SATA Port 0
page 38 page 40
AR8162/QCA8172(10/100)
page 37
FCBGA 989Balls
25mm x 25mm SATA ODD Conn.
SATA Port 2
page 40
3
PCIe Mini Card 3
WiMax PCIe x1
USB20 Port 10
page 36 Audio Codec
AZALIA CONEXANT
PCIe Mini Card USB20 x1 CX20757
page 41
WLAN
PCIe Port 2
page 36
page 14~22
Int. MIC Conn. Int. Speaker Conn. Audio Combo Jacks

page 41 page 41
HP & MIC
page 43
SPI ROM EC
Sub-borad 2MB + 4MB ENE KB9012
page 14 page 42
15"
14"
4 4
Power/B Thermal Sensor Touch Pad Int. KBD

page 39 page 43 page 43
LS9902P LED/B
LS9903P
page 43 page 43
IO/B ODD/B
LS9901P LS9904P MB Block Diagram
page 43 page 40 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom VILG1/G2 MB LA9901P Schematic 1.0
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SIGNAL
Voltage Rails BOARD ID Table STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Board ID PCB Revision Full ON HIGH HIGH HIGH HIGH ON ON ON ON
+5VS
0 1.0 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
+3VS
1 0.3
power 2 0.2 S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
plane +1.5VS
+V1.05S_VCCP
3 0.1 S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
1 1
+5VALW +1.5V +VCC_CORE

4
5 S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+B +VGA_CORE
+3VALW +VCC_GFXCORE_AXG
6
+1.8VS
7 Board ID table for AD channel
State +0.75VS Vcc 3.3V
+1.05VS Ra 100K +/- 1%
Board ID Rb VAD_BID min V AD_BID typ VAD_BID max EC AD
0 0 0 V 0 V 0.300 V 0x00 - 0x0B MP
1 12K +/- 1% 0.347 V 0.354 V 0.360 V 0x0C - 0x1C PVT
2 15K +/- 1% 0.423 V 0.430 V 0.438 V 0x1D - 0x26 DVT
3 20K +/- 1% 0.541 V 0.550 V 0.559 V 0x27 - 0x30 EVT
S0
O O O O
S3
O O O X
2
USB Port Table BOM Structure Table 2
S5 S4/AC BTO Item BOM Structure

O O X X 3 External
USB 2.0 Port USB Port 45 LEVEL 45@
S5 S4/ Battery only Connector ME@
O X X X 0 USB Port (Left Side) USB3.0
UHCI0 For VILG2 (14") 14@
S5 S4/AC & Battery
1 USB Port (Left Side) USB3.0
X X X X For VILG1 (15") 15@
don't exist 2 Touch Screen
UHCI1 GPU:N14M-GE N14@
Address 3 USB Camera
EC SM Bus1 address EC SM Bus2 address EHCI1 HDMI HDMI@
USB3.0
4
UHCI2 Camera CMOS@
5
Device Device Address LAN LDO Mode LDO@
Smart Battery 0001 011X b Thermal Sensor 1001 100xb
6
UHCI3 LAN Switch mode SWR@
7
10/100 LAN(AR8162L) 8162@
8
PCH SM Bus address UHCI4 10/100 LAN(QCA8172) 8172@
9 USB/B (Right Side USB2.0)
N14M-GE SKU GE@
10 Mini Card(WLAN)
Device Address EHCI2 UHCI5 N14P-GS SKU GS@
DDR DIMM0 1010 000Xb
11 Card Reader
N14P-GV2 SKU GV2@
DDR DIMM2 1010 010Xb
12
3 UHCI6 N14P-GV2&N14P-GS SKU GVGS@ 3
13
Green clock(DIS sku) GCLK304@
NV-GPU SM Bus address Green clock(UMA sku) GCLK244@
Green clk support GCLK@
Device Address No Green clk support NOGCLK@
Internal thermal sensor 1001 111Xb (0x9E)
Nvidia GC6 state GC6@
Touch Screen SKU TS@
Optimus SKU OPT@
UMA SKU UMA@
SMBUS Control Table PCH(NM70 sku) NM70@
PCH(HM70 sku) HM70@
SOURCE VGA BATT KB9012 SODIMM Thermal PCH
WLAN Sensor PCH(HM76 sku) HM76@
X V X X X X X
VRAM(1000MHz) 1000M@
SMB_EC_CK1 KB9012 VRAM(900MHz) 900M@
SMB_EC_DA1 +3VALW +3VALW
V X X X X X V
Unpop @
SMB_EC_CK2 KB9012
SMB_EC_DA2 +3VALW +3VS_VGA +3VS
SMBCLK
X X X V V X X
4 4
PCH
SMBDATA +3VALW +3VS +3VS
SML0CLK
SML0DATA PCH
+3VALW
X X X X X X X
SML1CLK
V X V X X V X
PCH 2011/06/15 2012/07/11 Title
SML1DATA +3VALW +3VS_VGA +3VS +3VS Issued Date Deciphered Date
Notes List
Size
Document Number Rev
B 1.0
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5 4 3 2 1
For N14P-GV2 strap table X76

N14x GPIO Pin Definition Table
Pin Functional Frenq. Memory Size Memory Config strap0 strap1 strap2 strap3 strap4 ROM_SI ROM_SO ROM_SCLK
Normal Function I/O Default GPU
Name Description PU/PD N14P-GV2 1 GHz
128M* 16* 4 Samsung R R R R R R R R
1GB K4W2G1646E-BC1A PU 45K PD 45K PD 15K PD 5K PD 45K PD 45K PU 5K PU 5K
GPIO0 FB_CLAMP_MON I FB Clamp monitor 128M* 16* 4 Micron R R R R R R R R
N14P-GV2 1 GHz
MEM VID:Strap to 1GB MT41J128M16JT-093G:K PU 45K PD 45K PD 15K PD 5K PD 45K PD 30K PU 5K PU 5K
GPIO1 MEM_VDD_CTL O Memory VDD VID boot FBVDD/Q 128M* 16* 4 Hynix R R R R R R R R
N14P-GV2 1 GHz
100k PD 1GB H5TC2G63FFR-11C PU 45K PD 45K PD 15K PD 5K PD 45K PD 25K PU 5K PU 5K
GPIO2~4 Non-support for LCD O Panel 256M* 16* 4 Samsung R R R R R R R R
N14P-GV2 900 MHz
2GB K4W4G1646B-HC11 PU 45K PD 45K PD 15K PD 5K PD 45K PD 20K PU 5K PU 5K
GPIO5 Reserve 256M* 16* 4 Micron R R R R R R R R
N14P-GV2 900 MHz
2GB MT41K256M16HA-107G:E PU 45K PD 45K PD 15K PD 5K PD 45K PD 10K PU 5K PU 5K
D GPIO6 FB_CLAMP_TGL_REQ# O Active low FB Clamp toggle request D
GPIO7 3DVision O 3D Vision L/R signal 100k PD For N14P-GS strap table X76
GPIO8 OVERT IO Active Low Thermal Catastrophic 100k PU
Frenq. Memory Size Memory Config strap0 strap1 strap2 strap3 strap4 ROM_SI ROM_SO ROM_SCLK
GPU
Over Temperature 128M* 16* 8 Samsung R R R R R R R R
N14P-GS 1 GHz
2GB K4W2G1646E-BC1A PU 45K PD 5K PD 20K PD 5K PD 45K PD 45K PU 5K PD 15K
GPIO9 ALERT IO Active Low Thermal Alert 100k PU
128M* 16* 8 Micron R R R R R R R R
N14P-GS 1 GHz
100k PD 2GB MT41J128M16JT-093G:K PU 45K PD 5K PD 20K PD 5K PD 45K PD 30K PU 5K PD 15K
GPIO10 MEM_VREF_CTL O Memory VREF Control 128M* 16* 8 Hynix R R R R R R R R
N14P-GS 1 GHz
2GB H5TC2G63FFR-11C PU 45K PD 5K PD 20K PD 5K PD 45K PD 25K PU 5K PD 15K
GPIO11 PWM_VID O GPU Core VDD PWM control 256M* 16* 8 Samsung R R R R R R R R
N14P-GS 900 MHz
supply overdraw input 4GB K4W4G1646B-HC11 PU 45K PD 5K PD 20K PD 5K PD 45K PD 20K PU 5K PD 15K
N14P-GS 256M* 16* 8 Micron R R R R R R R R
900 MHz
4GB MT41K256M16HA-107G:E PU 45K PD 5K PD 20K PD 5K PD 45K PD 10K PU 5K PD 15K
GPIO12 PWR_LEVEL I AC power detact or control signal 100k PU
GPIO13 PSI O Phase Shedding PSI:100k PU to For N14M-GE strap table X76
enable two phase
GPIO14~19 Non-support for HDA I Hot Plug GPU Frenq. Memory Size Memory Config strap0 strap1 strap2 strap3 strap4 ROM_SI ROM_SO ROM_SCLK
GPIO20~21 Reserve 128M* 16* 4 Samsung
N14M-GE R R R R R R R R
1 GHz K4W2G1646E-BC1A
1GB PU 10K PD 10K PU 10K PD 10K PD 10K PD 10K PD 10K PD 10K
GPU Power On GPU Power Down N14M-GE 1 GHz 1GB MT41J128M16JT-093G:K PU 10K PD 10K PD 10K PD 10K PD 10K PD 10K PD 10K PD 10K
128M* 16* 4 Hynix R R R R R R R R
N14M-GE 1 GHz 1GB H5TC2G63FFR-11C PD 10K PD 10K PU 10K PU 10K PD 10K PD 10K PD 10K PD 10K
+3VS_VGA 256M* 16* 4 Samsung R R R R R R R R
N14M-GE 900 MHz
(VDD33) First 2GB K4W4G1646B-HC11 PU 10K PU 10K PD 10K PU 10K PD 10K PD 10K PD 10K PD 10K
Rail 256M* 16* 4 Micron R R R R R R R R
N14M-GE 900 MHz 2GB MT41K256M16HA-107G:E PU 10K PD 10K PU 10K PU 10K PD 10K PD 10K PD 10K PD 10K
C +VGA_CORE C
(NVVDD)
Last Optimus Typical Power-Up Sequence
+1.5VS_VGA
tNVVDD >0 Rail
GPU Power On GPU init begin
(FBVDDQ)
tFBVDDQ >0 Tpower-off <10ms NVIDIA Driver X Waiting GPU-Init
+1.05VS_VGA
(PEX_VDD) DGPU_PWR_EN T1>40uS
tPEX_VDD >0
+3VS_VGA
1. all power rail ramp up time should be larger than 40us 1.All GPU power rails should be turned off within 10ms
GCLK_27MHZ/XTALIN T2>0
2. The total time for all rails to ramp should be within 6ms.
3. A power rail has to ramp up 90% before the next power rail in sequence CLK_REQ_VGA# T3>0
can start ramping up.
4. No signal should be applied to the GPU before the power rail are fully
ramped. CLK_PCIE_VGA
CLK_PCIE_VGA#
T4>100uS
GPU Reset Sequence Power sequencing violations
All non-3.3V GPU Rails X
T1>0
90%
+1.05VS_VGA PLT_RST_VGA# T5>0 T6>2mS
B
+3VS_VGA B
T3>0 Violations
+VGA_CORE > +3VS_VGA
PCIE Link X Link Training Link Stable
PLT_RST#
Optimus Typical Power-Down Sequence
As short as possible
PLT_RST_VGA# +VGA_CORE GPU disable call Call return
NVIDIA Driver X Waiting X
DGPU_PWR_EN T2>0 T4>0
GC6 Entry/Exit Sequence Timing Diagram

+3VS_VGA T3>0
DGPU_PWR_EN
GCLK_27MHZ/XTALIN
+3VS_VGA
CLK_REQ_VGA#
+1.5VS_VGA
CLK_PCIE_VGA
CLK_PCIE_VGA#
DGPU_PWROK
0~5ms 0~50ms
>3.3ms
CLAMP_TGL_REQ# Min 0.01~1ms All non-3.3V GPU Rails
Max 10ms T1>0
A 0~1ms A
FB_CLAMP PLT_RST_VGA#
0~1ms <50ms
PLT_RST_VGA# 0.01~1ms 0.1~5ms
PCIE Link Stable Link Tear Down X
FBA_CKE_L
FBC_CKE_L X SEFT-REFRESH NOT-SEFT-REFRESH
PCIE STATE X NOT_L2 L2 NOT_L2
VGA Notes List
Normal Operation GC6 Normal Operation AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
VILG1/G2 MB LA-9901P Schematic 0.3
5 4 3 2 1
5 4 3 2 1
ZZZ1 ZZZ2
PEG_ICOMPI and RCOMPO signals should be

shorted and routed
PCB PCB
with - max length = 500 mils - typical
DAG1@ DAG2@ +V1.05S_VCCP impedance = 43 mohms
PEG_ICOMPO signals should be routed with -
1
max length = 500 mils
R1
D
24.9_0402_1% - typical impedance = 14.5 mohms D
JCPU1A
2
J22 PEG_COMP
PEG_ICOMPI J21
B27 PEG_ICOMPO H22
<16> DMI_CRX_PTX_N0 DMI_RX#[0] PEG_RCOMPO PEG Static Lane Reversal - CFG2 is for the 16x
<16> DMI_CRX_PTX_N1 B25
A25 DMI_RX#[1]
<16> DMI_CRX_PTX_N2 DMI_RX#[2] PCIE_CRX_GTX_N[0..15] <23>
<16> DMI_CRX_PTX_N3
B24 K33 PCIE_CRX_GTX_N15 1: Normal Operation; Lane # definition matches
DMI_RX#[3] PEG_RX#[0] M35 PCIE_CRX_GTX_N14
PEG_RX#[1] CFG2 socket pin map definition
<16> DMI_CRX_PTX_P0 B28 L34 PCIE_CRX_GTX_N13
B26 DMI_RX[0] PEG_RX#[2] J35 PCIE_CRX_GTX_N12
<16> DMI_CRX_PTX_P1 DMI_RX[1] PEG_RX#[3]
A24 J32 PCIE_CRX_GTX_N11 0:Lane Reversed
<16> DMI_CRX_PTX_P2
*
DMI
B23 DMI_RX[2] PEG_RX#[4] H34 PCIE_CRX_GTX_N10
<16> DMI_CRX_PTX_P3 DMI_RX[3] PEG_RX#[5] H31 PCIE_CRX_GTX_N9
G21 PEG_RX#[6] G33 PCIE_CRX_GTX_N8
<16> DMI_CTX_PRX_N0 DMI_TX#[0] PEG_RX#[7]
E22 G30 PCIE_CRX_GTX_N7
F21 F35 PCIE_CRX_GTX_N6
D21 E34 PCIE_CRX_GTX_N5
<16> DMI_CTX_PRX_N3 DMI_TX#[3] PEG_RX#[10] E32 PCIE_CRX_GTX_N4
G22 PEG_RX#[11] D33 PCIE_CRX_GTX_N3
<16> DMI_CTX_PRX_P0 DMI_TX[0] PEG_RX#[12]
D22 D31 PCIE_CRX_GTX_N2
F20 B33 PCIE_CRX_GTX_N1
PCI EXPRESS* - GRAPHICS

C21 C32 PCIE_CRX_GTX_N0
PCIE_CRX_GTX_P[0..15] <23>
J33 PCIE_CRX_GTX_P15
PEG_RX[0] L35 PCIE_CRX_GTX_P14
PEG_RX[1] K34 PCIE_CRX_GTX_P13
A21 PEG_RX[2] H35 PCIE_CRX_GTX_P12
<16> FDI_CTX_PRX_N0 FDI0_TX#[0] PEG_RX[3]
C H19 H32 PCIE_CRX_GTX_P11 C
E19 G34 PCIE_CRX_GTX_P10
F18 G31 PCIE_CRX_GTX_P9
Intel(R) FDI
B21 F33 PCIE_CRX_GTX_P8
C20 F30 PCIE_CRX_GTX_P7
D18 E35 PCIE_CRX_GTX_P6
E17 E33 PCIE_CRX_GTX_P5
<16> FDI_CTX_PRX_N7 FDI1_TX#[3] PEG_RX[10] F32 PCIE_CRX_GTX_P4
PEG_RX[11] D34 PCIE_CRX_GTX_P3
A22 PEG_RX[12] E31 PCIE_CRX_GTX_P2
<16> FDI_CTX_PRX_P0 FDI0_TX[0] PEG_RX[13]
G19 C33 PCIE_CRX_GTX_P1
E20 B32 PCIE_CRX_GTX_P0
G18
<16> FDI_CTX_PRX_P3 FDI0_TX[3] PCIE_CTX_GRX_N[0..15] <23>
B20 M29 PCIE_CTX_GRX_C_N15 C1 GS@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N15
<16> FDI_CTX_PRX_P4 FDI1_TX[0] PEG_TX#[0]
C19 M32 PCIE_CTX_GRX_C_N14 C2 GS@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N14
D19 M31 PCIE_CTX_GRX_C_N13 C3 GS@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N13
F17 L32 PCIE_CTX_GRX_C_N12 C5 GS@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N12
<16> FDI_CTX_PRX_P7 FDI1_TX[3] PEG_TX#[3] L29 PCIE_CTX_GRX_C_N11 C7 GS@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N11
J18 PEG_TX#[4] K31 PCIE_CTX_GRX_C_N10 C8 GS@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N10
+V1.05S_VCCP <16> FDI_FSYNC0 FDI0_FSYNC PEG_TX#[5]
<16> FDI_FSYNC1
J17 K28 PCIE_CTX_GRX_C_N9 C9 GS@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N9
FDI1_FSYNC PEG_TX#[6] J30 PCIE_CTX_GRX_C_N8 C10 GS@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N8
H20 PEG_TX#[7] J28 PCIE_CTX_GRX_C_N7 C11 GVGS@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N7
<16> FDI_INT FDI_INT PEG_TX#[8] H29 PCIE_CTX_GRX_C_N6 C12 GVGS@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N6
PEG_TX#[9]
1
<16> FDI_LSYNC0
J19 G27 PCIE_CTX_GRX_C_N5 C13 GVGS@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N5
R7 H17 FDI0_LSYNC PEG_TX#[10] E29 PCIE_CTX_GRX_C_N4 C14 GVGS@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N4
<16> FDI_LSYNC1 FDI1_LSYNC PEG_TX#[11]
24.9_0402_1% F27 PCIE_CTX_GRX_C_N3 C15 GVGS@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N3
PEG_TX#[12] D28 PCIE_CTX_GRX_C_N2 C16 GVGS@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N2
PEG_TX#[13] F26 PCIE_CTX_GRX_C_N1 C17 GVGS@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N1
2
PEG_TX#[14] E25 PCIE_CTX_GRX_C_N0 C18 GVGS@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N0

EDP_COMP A18 PEG_TX#[15]
B eDP_COMPIO PCIE_CTX_GRX_P[0..15] <23> B
eDP_COMPIO and ICOMPO signals A17 M28 PCIE_CTX_GRX_C_P15 C19 GS@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P15
eDP_HPD B16 eDP_ICOMPO PEG_TX[0] M33 PCIE_CTX_GRX_C_P14 C20 GS@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P14
should be shorted near balls eDP_HPD# PEG_TX[1] M30 PCIE_CTX_GRX_C_P13 C21 GS@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P13
PEG_TX[2] L31 PCIE_CTX_GRX_C_P12 C22 GS@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P12
and routed with typical PEG_TX[3]
C15 L28 PCIE_CTX_GRX_C_P11 C23 GS@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P11
impedance <25 mohms D15 eDP_AUX PEG_TX[4] K30 PCIE_CTX_GRX_C_P10 C24 GS@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P10
eDP_AUX# PEG_TX[5] K27 PCIE_CTX_GRX_C_P9 C25 GS@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P9
eDP
PEG_TX[6] J29 PCIE_CTX_GRX_C_P8 C26 GS@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P8

C17 PEG_TX[7] J27 PCIE_CTX_GRX_C_P7 C27 GVGS@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P7
F16 eDP_TX[0] PEG_TX[8] H28 PCIE_CTX_GRX_C_P6 C28 GVGS@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P6
C16 eDP_TX[1] PEG_TX[9] G28 PCIE_CTX_GRX_C_P5 C29 GVGS@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P5
G15 eDP_TX[2] PEG_TX[10] E28 PCIE_CTX_GRX_C_P4 C30 GVGS@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P4
eDP_TX[3] PEG_TX[11] F28 PCIE_CTX_GRX_C_P3 C31 GVGS@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P3
C18 PEG_TX[12] D27 PCIE_CTX_GRX_C_P2 C32 GVGS@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P2
E16 eDP_TX#[0] PEG_TX[13] E26 PCIE_CTX_GRX_C_P1 C36 GVGS@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P1
D16 eDP_TX#[1] PEG_TX[14] D25 PCIE_CTX_GRX_C_P0 C37 GVGS@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P0
F15 eDP_TX#[2] PEG_TX[15] C11 C12 C13 C14 C15 C16 C17 C18
eDP_TX#[3]
TYCO_2013620-2_IVY BRIDGE
ME@
0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K

SE102104K00 SE102104K00 SE102104K00 SE102104K00 SE102104K00 SE102104K00 SE102104K00 SE102104K00
GE@ GE@ GE@ GE@ GE@ GE@ GE@ GE@
C27 C28 C29 C30 C31 C32 C36 C37
A A
0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K

SE102104K00 SE102104K00 SE102104K00 SE102104K00 SE102104K00 SE102104K00 SE102104K00 SE102104K00
GE@ GE@ GE@ GE@ GE@ GE@ GE@ GE@

PROCESSOR(1/7) DMI,FDI,PEG
Custom 1.0
5 4 3 2 1
5 4 3 2 1
JCPU1B
D D
A28
C26 BCLK A27 CLK_CPU_DMI <15>
MISC
CLOCKS
<19> H_SNB_IVB# PROC_SELECT# BCLK# CLK_CPU_DMI# <15>
AN34
SKTOCC# A16 2 R12 1 1K_0402_5%
+V1.05S_VCCP DPLL_REF_CLK A15 2 R13 1 1K_0402_5%
DPLL_REF_CLK# +V1.05S_VCCP
T48 H_CATERR# AL33

CATERR#
1
R9
62_0402_5%
THERMAL
AN33 R8 H_DRAMRST#
<42> H_PECI PECI SM_DRAMRST# H_DRAMRST# <7>
2
R15 +V1.05S_VCCP
DDR3
MISC
56_0402_5%
H_PROCHOT# 1 2 H_PROCHOT#_R AL32 AK1 SM_RCOMP0 2 R16 1 140_0402_1%
<42,47,55> H_PROCHOT# PROCHOT# SM_RCOMP[0] A5 SM_RCOMP1 2 R17 1 25.5_0402_1%
SM_RCOMP[1] A4 SM_RCOMP2 2 R18 1 200_0402_1%
SM_RCOMP[2]
AN32 DDR3 Compensation Signals
<19> H_THRMTRIP# THERMTRIP#
RP13
XDP_TRST# 8 1
AP29 XDP_PRDY# XDP_TDI 7 2
PRDY# AP27 XDP_PREQ# T18 PAD XDP_TMS 6 3
PREQ# T19 PAD XDP_TCK 5 4
AR26 XDP_TCK
C TCK AR27 XDP_TMS 51_0804_8P4R_5% C
PWR MANAGEMENT
TMS
JTAG & BPM

AM34 AP30 XDP_TRST# @
<16> H_PM_SYNC PM_SYNC TRST#
AR28 XDP_TDI
TDI AP26 XDP_TDO
AP33 TDO T20 PAD
<19> H_CPUPWRGD UNCOREPWRGOOD
2
R29 AL35 XDP_DBRESET# R28 2 1 1K_0402_5%

DBR# +3VS
1 R27 1 2 PM_DRAM_PWRGD_R V8
C549 130_0402_5% SM_DRAMPWROK
10K_0402_5%
1
AT28 XDP_BPM#0
BPM#[0] AR29 T21 PAD
100P_0402_50V8J XDP_BPM#1 C45
1
2 BPM#[1] AR30 T22 PAD 0.047U_0402_16V7K

XDP_BPM#2
2
BUF_CPU_RST# AR33 BPM#[2] AT30 XDP_BPM#3 T23 PAD
RESET# BPM#[3] AP32 XDP_BPM#4 T24 PAD
BPM#[4] AR31 XDP_BPM#5 T25 PAD
BPM#[5] AT31 T26 PAD
ESD XDP_BPM#6
BPM#[6] AR32 XDP_BPM#7 T27 PAD
BPM#[7] T28 PAD ESD
3/20 Add (ESD request) TYCO_2013620-2_IVY BRIDGE

+3VALW ME@
+3VALW +3VS
Buffered reset to CPU
2 2
C852 @ @ C853 +1.5V_CPU_VDDQ
0.1U_0402_16V4Z 0.1U_0402_16V4Z +3VS
B 1 1 B
1
R30
U1 200_0402_5% +V1.05S_VCCP
5
1 R161 2 1
P
+3VS B
10K_0402_5% 4 PM_SYS_PWRGD_BUF R32
2 O 75_0402_5%
<16> PM_DRAM_PWRGD A
G
5
74AHC1G09GW_TSSOP5 R34 U2
3
43_0402_1% 1 3V
P
BUF_CPU_RST# 1 2 BUFO_CPU_RST# 4 NC
Y 2 PCH_PLTRST#
A PCH_PLTRST# <18>
G
SN74LVC1G07DCKR_SC70-5 3
A A

PROCESSOR(2/7) PM,XDP,CLK
5 4 3 2 1
5 4 3 2 1
JCPU1C JCPU1D
<13> DDR_B_D[0..63]
AB6 AE2
<12> DDR_A_D[0..63] SA_CLK[0] AA6 M_CLK_DDR0 <12> SB_CLK[0] AD2 M_CLK_DDR2 <13>
DDR_A_D0 C5 SA_CLK#[0] V9 M_CLK_DDR#0 <12> DDR_B_D0 C9 SB_CLK#[0] R9 M_CLK_DDR#2 <13>
DDR_A_D1 D5 SA_DQ[0] SA_CKE[0] DDR_CKE0_DIMMA <12> DDR_B_D1 A7 SB_DQ[0] SB_CKE[0] DDR_CKE2_DIMMB <13>
DDR_A_D2 D3 SA_DQ[1] DDR_B_D2 D10 SB_DQ[1]
DDR_A_D3 D2 SA_DQ[2] DDR_B_D3 C8 SB_DQ[2]
DDR_A_D4 D6 SA_DQ[3] AA5 DDR_B_D4 A9 SB_DQ[3] AE1
C6 SA_DQ[4] SA_CLK[1] AB5 M_CLK_DDR1 <12> A8 SB_DQ[4] SB_CLK[1] AD1 M_CLK_DDR3 <13>
DDR_A_D5 DDR_B_D5
C2 SA_DQ[5] SA_CLK#[1] V10 M_CLK_DDR#1 <12> D9 SB_DQ[5] SB_CLK#[1] R10 M_CLK_DDR#3 <13>
DDR_A_D6 DDR_B_D6
D DDR_A_D7 C3 SA_DQ[6] SA_CKE[1] DDR_CKE1_DIMMA <12> DDR_B_D7 D8 SB_DQ[6] SB_CKE[1] DDR_CKE3_DIMMB <13> D
DDR_A_D8 F10 SA_DQ[7] DDR_B_D8 G4 SB_DQ[7]
DDR_A_D9 F8 SA_DQ[8] DDR_B_D9 F4 SB_DQ[8]
DDR_A_D10 G10 SA_DQ[9] AB4 DDR_B_D10 F1 SB_DQ[9] AB2
DDR_A_D11 G9 SA_DQ[10] RSVD_TP[1] AA4 DDR_B_D11 G1 SB_DQ[10] RSVD_TP[11] AA2
DDR_A_D12 F9 SA_DQ[11] RSVD_TP[2] W9 DDR_B_D12 G5 SB_DQ[11] RSVD_TP[12] T9
DDR_A_D13 F7 SA_DQ[12] RSVD_TP[3] DDR_B_D13 F5 SB_DQ[12] RSVD_TP[13]
DDR_A_D14 G8 SA_DQ[13] DDR_B_D14 F2 SB_DQ[13]
DDR_A_D15 G7 SA_DQ[14] DDR_B_D15 G2 SB_DQ[14]
DDR_A_D16 K4 SA_DQ[15] AB3 DDR_B_D16 J7 SB_DQ[15] AA1
DDR_A_D17 K5 SA_DQ[16] RSVD_TP[4] AA3 DDR_B_D17 J8 SB_DQ[16] RSVD_TP[14] AB1
DDR_A_D18 K1 SA_DQ[17] RSVD_TP[5] W10 DDR_B_D18 K10 SB_DQ[17] RSVD_TP[15] T10
DDR_A_D19 J1 SA_DQ[18] RSVD_TP[6] DDR_B_D19 K9 SB_DQ[18] RSVD_TP[16]
DDR_A_D20 J5 SA_DQ[19] DDR_B_D20 J9 SB_DQ[19]
DDR_A_D21 J4 SA_DQ[20] DDR_B_D21 J10 SB_DQ[20]
DDR_A_D22 J2 SA_DQ[21] AK3 DDR_B_D22 K8 SB_DQ[21] AD3
DDR_A_D23 K2 SA_DQ[22] SA_CS#[0] AL3 DDR_CS0_DIMMA# <12> DDR_B_D23 K7 SB_DQ[22] SB_CS#[0] AE3 DDR_CS2_DIMMB# <13>
DDR_A_D24 M8 SA_DQ[23] SA_CS#[1] AG1 DDR_CS1_DIMMA# <12> DDR_B_D24 M5 SB_DQ[23] SB_CS#[1] AD6 DDR_CS3_DIMMB# <13>
DDR_A_D25 N10 SA_DQ[24] RSVD_TP[7] AH1 DDR_B_D25 N4 SB_DQ[24] RSVD_TP[17] AE6
DDR_A_D26 N8 SA_DQ[25] RSVD_TP[8] DDR_B_D26 N2 SB_DQ[25] RSVD_TP[18]
DDR_A_D27 N7 SA_DQ[26] DDR_B_D27 N1 SB_DQ[26]
DDR_A_D28 M10 SA_DQ[27] DDR_B_D28 M4 SB_DQ[27]
DDR_A_D29 M9 SA_DQ[28] AH3 DDR_B_D29 N5 SB_DQ[28] AE4
DDR_A_D30 N9 SA_DQ[29] SA_ODT[0] AG3 M_ODT0 <12> DDR_B_D30 M2 SB_DQ[29] SB_ODT[0] AD4 M_ODT2 <13>
M_ODT1 <12> M_ODT3 <13>
DDR SYSTEM MEMORY B

DDR_A_D31 M7 SA_DQ[30] SA_ODT[1] AG2 DDR_B_D31 M1 SB_DQ[30] SB_ODT[1] AD5
DDR SYSTEM MEMORY A

DDR_A_D32 AG6 SA_DQ[31] RSVD_TP[9] AH2 DDR_B_D32 AM5 SB_DQ[31] RSVD_TP[19] AE5
DDR_A_D33 AG5 SA_DQ[32] RSVD_TP[10] DDR_B_D33 AM6 SB_DQ[32] RSVD_TP[20]
DDR_A_D34 AK6 SA_DQ[33] DDR_B_D34 AR3 SB_DQ[33]
DDR_A_D35 AK5 SA_DQ[34] DDR_B_D35 AP3 SB_DQ[34]
DDR_A_D36 AH5 SA_DQ[35] DDR_B_D36 AN3 SB_DQ[35]
DDR_A_D37 AH6 SA_DQ[36] C4 DDR_A_DQS#0 DDR_A_DQS#[0..7] <12> DDR_B_D37 AN2 SB_DQ[36] D7 DDR_B_DQS#0 DDR_B_DQS#[0..7] <13>
DDR_A_D38 AJ5 SA_DQ[37] SA_DQS#[0] G6 DDR_A_DQS#1 DDR_B_D38 AN1 SB_DQ[37] SB_DQS#[0] F3 DDR_B_DQS#1
C DDR_A_D39 AJ6 SA_DQ[38] SA_DQS#[1] J3 DDR_A_DQS#2 DDR_B_D39 AP2 SB_DQ[38] SB_DQS#[1] K6 DDR_B_DQS#2 C
DDR_A_D40 AJ8 SA_DQ[39] SA_DQS#[2] M6 DDR_A_DQS#3 DDR_B_D40 AP5 SB_DQ[39] SB_DQS#[2] N3 DDR_B_DQS#3
DDR_A_D41 AK8 SA_DQ[40] SA_DQS#[3] AL6 DDR_A_DQS#4 DDR_B_D41 AN9 SB_DQ[40] SB_DQS#[3] AN5 DDR_B_DQS#4
DDR_A_D42 AJ9 SA_DQ[41] SA_DQS#[4] AM8 DDR_A_DQS#5 DDR_B_D42 AT5 SB_DQ[41] SB_DQS#[4] AP9 DDR_B_DQS#5
DDR_A_D43 AK9 SA_DQ[42] SA_DQS#[5] AR12 DDR_A_DQS#6 DDR_B_D43 AT6 SB_DQ[42] SB_DQS#[5] AK12 DDR_B_DQS#6
DDR_A_D44 AH8 SA_DQ[43] SA_DQS#[6] AM15 DDR_A_DQS#7 DDR_B_D44 AP6 SB_DQ[43] SB_DQS#[6] AP15 DDR_B_DQS#7
DDR_A_D45 AH9 SA_DQ[44] SA_DQS#[7] DDR_B_D45 AN8 SB_DQ[44] SB_DQS#[7]
DDR_A_D46 AL9 SA_DQ[45] DDR_B_D46 AR6 SB_DQ[45]
DDR_A_D48 AP11 SA_DQ[47] DDR_B_D48 AR9 SB_DQ[47]
DDR_A_D49 AN11 SA_DQ[48] D4 DDR_A_DQS0 DDR_A_DQS[0..7] <12> DDR_B_D49 AJ11 SB_DQ[48] C7 DDR_B_DQS0 DDR_B_DQS[0..7] <13>
DDR_A_D50 AL12 SA_DQ[49] SA_DQS[0] F6 DDR_A_DQS1 DDR_B_D50 AT8 SB_DQ[49] SB_DQS[0] G3 DDR_B_DQS1
DDR_A_D51 AM12 SA_DQ[50] SA_DQS[1] K3 DDR_A_DQS2 DDR_B_D51 AT9 SB_DQ[50] SB_DQS[1] J6 DDR_B_DQS2
DDR_A_D52 AM11 SA_DQ[51] SA_DQS[2] N6 DDR_A_DQS3 DDR_B_D52 AH11 SB_DQ[51] SB_DQS[2] M3 DDR_B_DQS3
DDR_A_D53 AL11 SA_DQ[52] SA_DQS[3] AL5 DDR_A_DQS4 DDR_B_D53 AR8 SB_DQ[52] SB_DQS[3] AN6 DDR_B_DQS4
DDR_A_D54 AP12 SA_DQ[53] SA_DQS[4] AM9 DDR_A_DQS5 DDR_B_D54 AJ12 SB_DQ[53] SB_DQS[4] AP8 DDR_B_DQS5
DDR_A_D55 AN12 SA_DQ[54] SA_DQS[5] AR11 DDR_A_DQS6 DDR_B_D55 AH12 SB_DQ[54] SB_DQS[5] AK11 DDR_B_DQS6
DDR_A_D56 AJ14 SA_DQ[55] SA_DQS[6] AM14 DDR_A_DQS7 DDR_B_D56 AT11 SB_DQ[55] SB_DQS[6] AP14 DDR_B_DQS7
DDR_A_D57 AH14 SA_DQ[56] SA_DQS[7] DDR_B_D57 AN14 SB_DQ[56] SB_DQS[7]
DDR_A_D59 AK15 SA_DQ[58] DDR_B_D59 AT14 SB_DQ[58]
DDR_A_D60 AL14 SA_DQ[59] DDR_B_D60 AT12 SB_DQ[59]
DDR_A_D61 AK14 SA_DQ[60] AD10 DDR_A_MA0 DDR_A_MA[0..15] <12> DDR_B_D61 AN15 SB_DQ[60] AA8 DDR_B_MA0 DDR_B_MA[0..15] <13>
DDR_A_D62 AJ15 SA_DQ[61] SA_MA[0] W1 DDR_A_MA1 DDR_B_D62 AR15 SB_DQ[61] SB_MA[0] T7 DDR_B_MA1
DDR_A_D63 AH15 SA_DQ[62] SA_MA[1] W2 DDR_A_MA2 DDR_B_D63 AT15 SB_DQ[62] SB_MA[1] R7 DDR_B_MA2
SA_DQ[63] SA_MA[2] W7 DDR_A_MA3 SB_DQ[63] SB_MA[2] T6 DDR_B_MA3
SA_MA[3] V3 DDR_A_MA4 SB_MA[3] T2 DDR_B_MA4
SA_MA[4] V2 DDR_A_MA5 SB_MA[4] T4 DDR_B_MA5
SA_MA[5] W3 DDR_A_MA6 SB_MA[5] T3 DDR_B_MA6
AE10 SA_MA[6] W6 DDR_A_MA7 AA9 SB_MA[6] R2 DDR_B_MA7
<12> DDR_A_BS0 AF10 SA_BS[0] SA_MA[7] V1 DDR_A_MA8 <13> DDR_B_BS0 AA7 SB_BS[0] SB_MA[7] T5 DDR_B_MA8
<12> DDR_A_BS1 V6 SA_BS[1] SA_MA[8] W5 DDR_A_MA9 <13> DDR_B_BS1 R6 SB_BS[1] SB_MA[8] R3 DDR_B_MA9
B <12> DDR_A_BS2 SA_BS[2] SA_MA[9] AD8 <13> DDR_B_BS2 SB_BS[2] SB_MA[9] AB7 B
DDR_A_MA10 DDR_B_MA10
SA_MA[10] V4 DDR_A_MA11 SB_MA[10] R1 DDR_B_MA11
SA_MA[11] W4 DDR_A_MA12 SB_MA[11] T1 DDR_B_MA12
AE8 SA_MA[12] AF8 DDR_A_MA13 AA10 SB_MA[12] AB10 DDR_B_MA13
<12> DDR_A_CAS# AD9 SA_CAS# SA_MA[13] V5 <13> DDR_B_CAS# AB8 SB_CAS# SB_MA[13] R5
<12> DDR_A_RAS# AF9 SA_RAS# SA_MA[14] V7 <13> DDR_B_RAS# AB9 SB_RAS# SB_MA[14] R4
<12> DDR_A_WE# SA_WE# SA_MA[15] <13> DDR_B_WE# SB_WE# SB_MA[15]
TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE
ME@ +1.5V ME@

1
R37
1K_0402_5%
R38
1K_0402_5%
2
S
H_DRAMRST# 3 1 DDR3_DRAMRST#_R 1 2
<6> H_DRAMRST# DDR3_DRAMRST# <12,13>
2
Q2
R39 LBSS138LT1G_SOT-23-3
G
2
4.99K_0402_1%
1
A R48 1 @ 2 DRAMRST_CNTRL_PCH_R A
<10,15> DRAMRST_CNTRL_PCH
0_0402_5%
1
@
C35
0.047U 16V K X7R 0402
2
PROCESSOR(3/7) DDRIII
Eiffel used 0.01u Size Document Number Rev
Module design used 0.047u DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom VILG1/G2 MB LA9901P Schematic 1.0
5 4 3 2 1
5 4 3 2 1
CFG Straps for Processor
CFG2
1
R41
1K_0402_1%
OPT@
2
D D
Interl request AH26 short GND

JCPU1E check on EVT phase PEG Static Lane Reversal - CFG2 is for the 16x
1: Normal Operation; Lane # definition matches

AH27 PAD T13 CFG2
AK28 VCC_DIE_SENSE AH26 socket pin map definition
AK29 CFG[0] VSS_DIE_SENSE
CFG2 AL26 CFG[1]
0:Lane Reversed
CFG4
CFG5
AL27
AK26
AL29
CFG[2]
CFG[3]
CFG[4] RSVD28
L7
AG7
* CFG4
CFG6 AL30 CFG[5] RSVD29 AE7
CFG[6] RSVD30
1
CFG7 AM31 AK2
AM32 CFG[7] RSVD31
AM30 CFG[8] W8 @ R42
CFG
AM28 CFG[9] RSVD32 1K_0402_1%
AM26 CFG[10]
2
AN28 CFG[11] AT26
AN31 CFG[12] RSVD33 AM33
AN26 CFG[13] RSVD34 AJ27
AM27 CFG[14] RSVD35
AK31 CFG[15]
AN29 CFG[16]
CFG[17]
Display Port Presence Strap
T8
C RSVD37 J16 C
1 : Disabled; No Physical Display Port
T14
T15
PAD
PAD
VCC_AXG_VAL_SENSE
VSS_AXG_VAL_SENSE
AJ31
AH31 VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
RSVD38
RSVD39
RSVD40
H16
G16
CFG4 * attached to Embedded Display Port
VCC_VAL_SENSE AJ33
T16 PAD VSS_VAL_SENSE AH33 VCC_VAL_SENSE
T17 PAD VSS_VAL_SENSE 0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
Need PWR add new circuit on 1.05V(refer CRB) AJ26 AR35
RSVD5 RSVD_NCTF1 AT34
RESERVED
RSVD_NCTF2 AT33 R43 GE@
RSVD_NCTF3 AP35 CFG6
RSVD_NCTF4 AR34
RSVD_NCTF5 CFG5
1
F25
F24 RSVD8 R43 @ R44
F23 RSVD9 1K_0402_1% 1K_0402_1%
D24 RSVD10 B34 @ R43 GV2@
G25 RSVD11 RSVD_NCTF6 A33
2
G24 RSVD12 RSVD_NCTF7 A34
E23 RSVD13 RSVD_NCTF8 B35
D23 RSVD14 RSVD_NCTF9 C35
C30 RSVD15 RSVD_NCTF10
A31 RSVD16
B30 RSVD17
B29 RSVD18
D30 RSVD19 AJ32
B31 RSVD20 RSVD51 AK32
RSVD21 RSVD52 PCIE Port Bifurcation Straps
A30
C29 RSVD22
RSVD23
11: (Default) x16 - Device 1 functions 1 and 2 disabled
AN35
B J20 BCLK_ITP AM35 B
CFG[6:5] 10: x8, x8 - Device 1 function 1 enabled ; function 2
B18 RSVD24
RSVD25
BCLK_ITP#
* disabled
01: Reserved - (Device 1 function 1 disabled ; function
J15 AT2 2 enabled)
RSVD27 RSVD_NCTF11 AT1
RSVD_NCTF12 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
AR1
RSVD_NCTF13
B1 CFG7
KEY
1
@R45
@ R45
1K_0402_1%
2
ME@
PEG DEFER TRAINING
1: (Default) PEG Train immediately following xxRESETB

CFG7 de assertion
A
0: PEG Wait for BIOS for training A

PROCESSOR(4/7) RSVD,CFG
5 4 3 2 1
5 4 3 2 1
JCPU1F POWER +V1.05S_VCCP

+VCC_CORE
QC=94A 8.5A
DC=53A
AG35
AG34 VCC1 AH13
AG33 VCC2 VCCIO1 AH10
AG32 VCC3 VCCIO2 AG10
D AG31 VCC4 VCCIO3 AC10 D
AG30 VCC5 VCCIO4 Y10
AG29 VCC6 VCCIO5 U10
AG28 VCC7 VCCIO6 P10
AG27 VCC8 VCCIO7 L10
AG26 VCC9 VCCIO8 J14
AF35 VCC10 VCCIO9 J13
AF32 VCC13 VCCIO12 H14
AF29 VCC16 VCCIO15 G14
PEG AND DDR

AF26 VCC19 VCCIO18 F14
AD35 VCC20 VCCIO19 F13
AD32 VCC23 VCCIO22 E14
AD31 VCC24 VCCIO23 E12
AD30 VCC25 VCCIO24
AD29 VCC26 E11
AD28 VCC27 VCCIO25 D14
AC35 VCC30 VCCIO28 D11
AC34 VCC31 VCCIO29 C14
AC30 VCC35 VCCIO33 B14
C AC29 VCC36 VCCIO34 B12 C
AC28 VCC37 VCCIO35 A14
AA35 VCC40 VCCIO38 A11
AA34 VCC41 VCCIO39
AA33 VCC42 J23
AA32 VCC43 VCCIO40
AA31 VCC44 +V1.05S_VCCP
AA30 VCC45
AA29 VCC46
AA28 VCC47
AA27 VCC48
AA26 VCC49
Y35 VCC50
CORE SUPPLY
Y34 VCC51
Y33 VCC52
Y32 VCC53
VCC54
1
Y31
Y30 VCC55 R46
Y29 VCC56
VCC57 75_0402_5%
Y28
Y27 VCC58
VR_SVID_CLK series-resistors close to VR
2
Y26 VCC59
V35 VCC60
V34 VCC61 AJ29 H_CPU_SVIDALRT# 1 R47 2 43_0402_5%
SVID
V33 VCC62 VIDALERT# AJ30 VR_SVID_ALRT# <55>

V32 VCC63 VIDSCLK AJ28 VR_SVID_CLK <55>
V31 VCC64 VIDSOUT VR_SVID_DAT <55>
V30 VCC65
V29 VCC66 2 1 130_0402_5%
VCC67
R50 +V1.05S_VCCP 0.1uF on power side
V28
B V27 VCC68 B
V26 VCC69
U35 VCC70
U34 VCC71
U33 VCC72
U32 VCC73
U31 VCC74
U30 VCC75
U29 VCC76
U28 VCC77 VCC_SENCE 100ohm +-1% pull-up to VCC near processor
U27 VCC78
U26 VCC79
R35 VCC80 +VCC_CORE
R34 VCC81
R33 VCC82
VCC83
1
R32
R31
R30
VCC84
VCC85
Trace Impedance =27-33 ohm R51
100_0402_1%
R29
R28
VCC86
VCC87
Trace Length Matc < 25 mils
SENSE LINES
2
R27 VCC88 AJ35
R26 VCC89 VCC_SENSE AJ34 VCCSENSE <55>
P35 VCC90 VSS_SENSE VSSSENSE <55>
P34 VCC91
VCC92
1
P33
P32 VCC93 B10 R54
P31 VCC94 VCCIO_SENSE A10 1 VCCIO_SENSE <53>
VSSIO_SENSE_L R74 2 100_0402_1%
P30 VCC95 VSS_SENSE_VCCIO 10_0402_1%
P29 VCC96
2
P28 VCC97
VCC98 R74 & R79 put together +V1.05S_VCCP
P27
P26 VCC99 R79
A VCC100 2 1 A
VSSIO_SENSE_L <53>
10_0402_1%
VSS_SENCE 100ohm +-1% pull-down to GND near processor
TYCO_2013620-2_IVY BRIDGE Security Classification Compal Secret Data

ME@
PROCESSOR(5/7) PWR,BYPASS
5 4 3 2 1
5 4 3 2 1
+1.5V +1.5V_CPU_VDDQ
Q6
1
D LBSS138LT1G_SOT-23-3
2
+VREF_DQ_DIMMA G DRAMRST_CNTRL_PCH <15,7>
+VREF_DQ_DIMMB S
3
+V_DDR_REFA_R
+V_DDR_REFB_R
U3
DMN3030LSS-13_SOP8L-8
+VSB 8 1 AP4800
1
7 2 D
D 6 3 Id=9.6A DRAMRST_CNTRL_PCH 2 D
1
5 G
R56 S
3
82K_0402_5% Q9
4
LBSS138LT1G_SOT-23-3
2
R885 R02 M3 Circuit (Processor Generated SO-DIMM VREF_DQ)
RUN_ON_CPU1.5VS3 1 2
15K_0402_1% 1
1
D +VCC_GFXCORE_AXG
2 Q4 C97
<46> SUSP G 2N7002_SOT23 0.047U_0603_25V7K
1
S 2
3
R616
10_0402_1%
2
VCC_AXG_SENSE <55>
+VCC_GFXCORE_AXG JCPU1G
POWER
AT24 AK35
SENSE
LINES
AT23 VAXG1 VAXG_SENSE AK34 +1.5V_CPU_VDDQ
VAXG2 VSSAXG_SENSE VSS_AXG_SENSE <55>
AT21
VAXG3
1
AT20
AT18 VAXG4 R626
VAXG5
1
AT17 10_0402_1%
AR24 VAXG6
AR23 VAXG7 R67
+V_SM_VREF should
2
AR21 VAXG8 1K_0402_1%
AR20 VAXG9 have 20 mil trace width
2
AR18 VAXG10 AL1 +V_SM_VREF_CNT
C
AR17 VAXG11 SM_VREF C
VAXG12
1
AP24 1
VREF
AP23 VAXG13
AP21 VAXG14 C98 R78
AP20 VAXG15 B4 +V_DDR_REFA_R 0.1U_0402_10V6K 1K_0402_1%
AP18 VAXG16 SA_DIMM_VREFDQ D1 +V_DDR_REFB_R 2
2
AP17 VAXG17 SB_DIMM_VREFDQ
AN24 VAXG18
AN23 VAXG19
AN21 VAXG20
AN20 VAXG21 +1.5V_CPU_VDDQ
AN18 VAXG22
DDR3 -1.5V RAILS

AN17 VAXG23
AM24 VAXG24 AF7
GRAPHICS
AM23 VAXG25 VDDQ1 AF4
AM21 VAXG26 VDDQ2 AF1
VAXG27 VDDQ3 1 1
AM20 AC7 1 1 1 1
VAXG28 VDDQ4
10U_0603_6.3V6M
C117
10U_0603_6.3V6M
C119
10U_0603_6.3V6M
C120
10U_0603_6.3V6M
C122
AM18 AC4 + C127 + C123
AM17 VAXG29 VDDQ5 AC1 330U_2.5V_M 330U_D2_2V_Y
AL24 VAXG30 VDDQ6 Y7 @
VAXG31 VDDQ7 2 2 2 2 @ 2 2
AL23 Y4
AL21 VAXG32 VDDQ8 Y1
VAXG33 VDDQ9 1/16 Change symbol & value from
AL20 U7
AL18 VAXG34 VDDQ10 U4 SF000002Z00 to SGA20331E10
AL17 VAXG35 VDDQ11 U1
AK24 VAXG36 VDDQ12 P7
AK23 VAXG37 VDDQ13 P4
VAXG38 VDDQ14 1/25 Follow FM-James's comments(Co-lay with C123)
AK21 P1
AK20 VAXG39 VDDQ15
AK18 VAXG40
AK17 VAXG41
AJ24 VAXG42
AJ23 VAXG43
AJ21 VAXG44
B AJ20 VAXG45 +VCCSA B
AJ18 VAXG46
AJ17 VAXG47 M27 +VCCSA
AH24 VAXG48 VCCSA1 M26
SA RAIL
VAXG49 VCCSA2 1 1 1 1
10U_0603_6.3V6M
C124
10U_0603_6.3V6M
C125
10U_0603_6.3V6M
C126
AH23 L26
AH21 VAXG50 VCCSA3 J26 + C128 @
AH20 VAXG51 VCCSA4 J25 330U_D2_2.5VY_R9M
AH18 VAXG52 VCCSA5 J24 2 2 2
AH17 VAXG53 VCCSA6 H26 2
VAXG54 VCCSA7 H25
VCCSA8
1.8V RAIL
H23
+1.8VS VCCSA_SENSE +VCCSA_SENSE <52>
R69 0_0805_5% 1.5A
1 2 +1.8VS_VCCPLL B6
A6 VCCPLL1 C22
MISC
VCCPLL2 VCCSA_VID[0] H_VCCSA_VID0 <52>

10U_0603_6.3V6M
C130
1U_0402_6.3V6K
C132
@ 1 1 A2 C24
VCCPLL3 VCCSA_VID[1] H_VCCSA_VID1 <52>
2 2 A19
VCCIO_SEL
ME@
A IVY Bridge drives VCCIO_SEL low A
VCCP_PWRCTRL:0
Sandy Bridge is NC for A19
VCCP_PWRCTRL:1
Security Classification Compal Secret Data

PROCESSOR(6/7) PWR
Custom 1.0
5 4 3 2 1
5 4 3 2 1
JCPU1H JCPU1I
AT35 AJ22
AT32 VSS1 VSS81 AJ19
AT29 VSS2 VSS82 AJ16 T35 F22
AT27 VSS3 VSS83 AJ13 T34 VSS161 VSS234 F19
AT25 VSS4 VSS84 AJ10 T33 VSS162 VSS235 E30
D D
AT7 VSS10 VSS90 AH35 T27 VSS168 VSS241 E13
AT4 VSS11 VSS91 AH34 T26 VSS169 VSS242 E10
AT3 VSS12 VSS92 AH32 P9 VSS170 VSS243 E9
AR25 VSS13 VSS93 AH30 P8 VSS171 VSS244 E8
AR10 VSS18 VSS99 AH19 N35 VSS176 VSS249 E3
AR2 VSS21 VSS102 AH4 N32 VSS179 VSS252 D35
AP34 VSS22 VSS103 AG9 N31 VSS180 VSS253 D32
AP25 VSS25 VSS106 AF6 N28 VSS183 VSS256 D20
AP22 VSS26 VSS107 AF5 N27 VSS184 VSS257 D17
AP19 VSS27 VSS108 AF3 N26 VSS185 VSS258 C34
AP16 VSS28 VSS109 AF2 M34 VSS186 VSS259 C31
AP13 VSS29 VSS110 AE35 L33 VSS187 VSS260 C28
C
AN30 VSS34 VSS115 AE30 L6 VSS192 VSS265 C1 C
AN27 VSS35 VSS116 AE29 L5 VSS193 VSS266 B22
AN25 VSS36 VSS117 AE28 L4 VSS194 VSS267 B19
AN22
AN19
VSS37
VSS38
VSS39
VSS VSS118
VSS119
VSS120
AE27
AE26
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15
AN16 AE9 L1 B13
AN13 VSS40 VSS121 AD7 K35 VSS198 VSS271 B11
AN10 VSS41 VSS122 AC9 K32 VSS199 VSS272 B9
AM29 VSS44 VSS125 AC5 J34 VSS202 VSS275 B5
AM25 VSS45 VSS126 AC3 J31 VSS203 VSS276 B3
AM22 VSS46 VSS127 AC2 H33 VSS204 VSS277 B2
AM19 VSS47 VSS128 AB35 H30 VSS205 VSS278 A35
AM2 VSS54 VSS135 AB28 H10 VSS212 VSS285
AM1 VSS55 VSS136 AB27 H9 VSS213
AL34 VSS56 VSS137 AB26 H8 VSS214
AL31 VSS57 VSS138 Y9 H7 VSS215
B B
AL13 VSS63 VSS144 W35 H1 VSS221
AL10 VSS64 VSS145 W34 G35 VSS222
AK33 VSS68 VSS149 W30 G23 VSS226
AK22 VSS72 VSS153 W26 F34 VSS230
AK19 VSS73 VSS154 U9 F31 VSS231
AK16 VSS74 VSS155 U8 F29 VSS232
AK13 VSS75 VSS156 U6 VSS233
AK10 VSS76 VSS157 U5
AK7 VSS77 VSS158 U3
AK4 VSS78 VSS159 U2
AJ25 VSS79 VSS160
VSS80
A A
TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE
ME@ ME@
PROCESSOR(7/7) VSS
Custom 1.0
5 4 3 2 1
5 4 3 2 1
+VREF_DQ_DIMMA +1.5V +1.5V

4BA2/6W
<7> DDR_A_D[0..63]
DDR3 SO-DIMM A <7> DDR_A_DQS[0..7]
JDIMM1
<7> DDR_A_DQS#[0..7]
+VREF_DQ_DIMMA 1 2
3 VREF_DQ VSS1 4 DDR_A_D4
0.1U_0402_10V6K VSS2 DQ4 <7> DDR_A_MA[0..15]
DDR_A_D0 5 6 DDR_A_D5
C133
DDR_A_D1 7 DQ0 DQ5 8
1 DQ1 VSS3
9 10 DDR_A_DQS#0
11 VSS4 DQS#0 12 DDR_A_DQS0
13 DM0 DQS0 14
D 2 DDR_A_D2 15 VSS5 VSS6 16 DDR_A_D6 +1.5V D
DDR_A_D3 17 DQ2 DQ6 18 DDR_A_D7
19 DQ3 DQ7 20 RP15
DDR_A_D8 21 VSS7 VSS8 22 DDR_A_D12 8 1
DQ8 DQ12 +VREF_DQ_DIMMA
DDR_A_D9 23 24 DDR_A_D13 7 2
25 DQ9 DQ13 26 6 3
VSS9 VSS10 +VREF_DQ_DIMMB
DDR_A_DQS#1 27 28 5 4
DDR_A_DQS1 29 DQS#1 DM1 30 DDR3_DRAMRST#
DQS1 RESET# DDR3_DRAMRST# <13,7>
31 32 1K_0804_8P4R_1%
DDR_A_D10 33 VSS11 VSS12 34 DDR_A_D14
37 DQ11 DQ15 38
DDR_A_D16 39 VSS13 VSS14 40 DDR_A_D20 +1.5V
43 DQ17 DQ21 44 RP16
DDR_A_DQS#2 45 VSS15 VSS16 46 8 1
DQS#2 DM2 +VREF_CA
DDR_A_DQS2 47 48 7 2
49 DQS2 VSS17 50 DDR_A_D22 6 3
VSS18 DQ22 +VREF_CB
DDR_A_D18 51 52 DDR_A_D23 5 4
DDR_A_D19 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDR_A_D28 1K_0804_8P4R_1%
DDR_A_D24 57 VSS20 DQ28 58 DDR_A_D29
DDR_A_D25 59 DQ24 DQ29 60
61 DQ25 VSS21 62 DDR_A_DQS#3
65 DM3 DQS3 66
71 DQ27 DQ31 72
VSS25 VSS26
C DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA C
<7> DDR_CKE0_DIMMA CKE0 CKE1 DDR_CKE1_DIMMA <7>
75 76
77 VDD1 VDD2 78 DDR_A_MA15
DDR_A_BS2 79 NC1 A15 80 DDR_A_MA14
<7> DDR_A_BS2 BA2 A14
81 82
DDR_A_MA12 83 VDD3 VDD4 84 DDR_A_MA11
DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7
87 A9 A7 88
DDR_A_MA5 91 A8 A6 92 DDR_A_MA4
93 A5 A4 94
DDR_A_MA1 97 A3 A2 98 DDR_A_MA0
99 A1 A0 100
<7> M_CLK_DDR0 M_CLK_DDR0 101 VDD9 VDD10 102 M_CLK_DDR1 OSCAN (220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00)
CK0 CK1 M_CLK_DDR1 <7>
<7> M_CLK_DDR#0 M_CLK_DDR#0 103 104 M_CLK_DDR#1
CK0# CK1# M_CLK_DDR#1 <7>
105 106 Layout Note:
DDR_A_MA10 107 VDD11 VDD12 108 DDR_A_BS1 (10uF_0603_6.3V)*8
A10/AP BA1 DDR_A_BS1 <7>
<7> DDR_A_BS0 DDR_A_BS0 109 110 DDR_A_RAS#
DDR_A_RAS# <7>
Place near DIMM
111 BA0 RAS# 112
<7> DDR_A_WE# DDR_A_WE# 113 VDD13 VDD14 114 DDR_CS0_DIMMA# (0.1uF_402_10V)*4
WE# S0# DDR_CS0_DIMMA# <7>
<7> DDR_A_CAS# DDR_A_CAS# 115 116 M_ODT0
CAS# ODT0 M_ODT0 <7>
117 118
DDR_A_MA13 119 VDD15 VDD16 120 M_ODT1
A13 ODT1 M_ODT1 <7> +VREF_CA
DDR_CS1_DIMMA# 121 122
<7> DDR_CS1_DIMMA# S1# NC2 +1.5V
123 124
125 VDD17 VDD18 126 +VREF_CA
127 NCTEST VREF_CA 128
VSS27 VSS28
0.1U_0402_10V6K
DDR_A_D32 129 130 DDR_A_D36

DQ32 DQ36
C135
DDR_A_D33 131 132 DDR_A_D37 1 1

DQ33 DQ37
10U_0603_6.3V6M
C139
10U_0603_6.3V6M
C140
10U_0603_6.3V6M
C141
10U_0603_6.3V6M
C142
10U_0603_6.3V6M
C143
10U_0603_6.3V6M
C144
0.1U_0402_10V6K
C145
0.1U_0402_10V6K
C146
0.1U_0402_10V6K
C147
0.1U_0402_10V6K
C148
133 134 1 1 1 1 1 1 1 1 1 1
DDR_A_DQS#4 135 VSS29 VSS30 136 + C149 @
B DDR_A_DQS4 137 DQS#4 DM4 138 220U_6.3V_M B
DQS4 VSS31 2 @
139 140 DDR_A_D38
DDR_A_D34 141 VSS32 DQ38 142 DDR_A_D39 2 2 2 2 2 2 2 2 2 2 2
DDR_A_D35 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_A_D44
DDR_A_D41 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_A_DQS#5
155 DM5 DQS5 156
VSS37 VSS38 VDDQ(1.5V) =
DDR_A_D42 157 158 DDR_A_D46
DDR_A_D43 159 DQ42 DQ46 160 DDR_A_D47
DQ43 DQ47 3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)
161 162
DDR_A_D49 165 DQ48 DQ52 166 DDR_A_D53
6*0603 10uf (PER CONNECTOR) Layout Note:
167 DQ49 DQ53 168 Place near DIMM
DDR_A_DQS#6 169 VSS41 VSS42 170
DQS#6 DM6 VTT(0.75V) =
DDR_A_DQS6 171 172
173 DQS6 VSS43 174 DDR_A_D54
VSS44 DQ54 3*0805 10uf 4*0402 1uf
DDR_A_D50 175 176 DDR_A_D55
DDR_A_D51 177 DQ50 DQ55 178 +0.75VS
DQ51 VSS45 VREF =
179 180 DDR_A_D60
DQ56 DQ61 1*0402 0.1uf 1*0402 2.2uf
DDR_A_D57 183 184
+3V_DIMM 185 DQ57 VSS47 186 DDR_A_DQS#7
VSS48 DQS#7 VDDSPD (3.3V)=
1U_0402_6.3V6K
C150
1U_0402_6.3V6K
C152
187 188 DDR_A_DQS7
189 DM7 DQS7 190
VSS49 VSS50 1*0402 0.1uf 1*0402 2.2uf 1 1
DDR_A_D58 191 192 DDR_A_D62
DDR_A_D59 193 DQ58 DQ62 194 DDR_A_D63
195 DQ59 DQ63 196
197 VSS51 VSS52 198 2 2
R136 1 @ 2 0_0402_5% 199 SA0 EVENT# 200 SMB_DATA_S3
+3VS VDDSPD SDA SMB_DATA_S3 <13,15,36>
0.1U_0402_10V6K
A 201 202 SMB_CLK_S3 A

SA1 SCL SMB_CLK_S3 <13,15,36>
C156
1 203 204 +0.75VS

VTT1 VTT2
205 206 1/76BA1/86W
G1 G2
2 LCN_DAN06-K4806-0103
ME@
DDRIII-SODIMM SLOT1
Custom 1.0
5 4 3 2 1
5 4 3 2 1
+VREF_DQ_DIMMB 4BA2/6W
<7> DDR_B_D[0..63]
+1.5V +1.5V
<7> DDR_B_DQS[0..7]
JDIMM2
<7> DDR_B_DQS#[0..7]
+VREF_DQ_DIMMB 1 2
3 VREF_DQ VSS1 4 DDR_B_D4
VSS2 DQ4 <7> DDR_B_MA[0..15]
DDR_B_D0 5 6 DDR_B_D5
DDR_B_D1 7 DQ0 DQ5 8
DQ1 VSS3
0.1U_0402_10V6K 9
VSS4 DQS#0
10 DDR_B_DQS#0
1 11 12 DDR_B_DQS0
13 DM0 DQS0 14
VSS5 VSS6
D
C157 DDR_B_D2 15
DQ2 DQ6
16 DDR_B_D6 D
DDR_B_D3 17 18 DDR_B_D7
2 19 DQ3 DQ7 20
DDR_B_D8 21 VSS7 VSS8 22 DDR_B_D12
DDR_B_D9 23 DQ8 DQ12 24 DDR_B_D13
25 DQ9 DQ13 26
DDR_B_DQS#1 27 VSS9 VSS10 28
DDR_B_DQS1 29 DQS#1 DM1 30 DDR3_DRAMRST#
DQS1 RESET# DDR3_DRAMRST# <12,7>
31 32
37 DQ11 DQ15 38
43 DQ17 DQ21 44
DDR_B_DQS2 47 DQS#2 DM2 48
49 DQS2 VSS17 50 DDR_B_D22
DDR_B_D18 51 VSS18 DQ22 52 DDR_B_D23
DDR_B_D19 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDR_B_D28
DDR_B_D25 59 DQ24 DQ29 60
61 DQ25 VSS21 62 DDR_B_DQS#3
63 VSS22 DQS#3 64 DDR_B_DQS3
65 DM3 DQS3 66
71 DQ27 DQ31 72
VSS25 VSS26
C DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB C
<7> DDR_CKE2_DIMMB CKE0 CKE1 DDR_CKE3_DIMMB <7>
75 76
77 VDD1 VDD2 78 DDR_B_MA15
DDR_B_BS2 79 NC1 A15 80 DDR_B_MA14
<7> DDR_B_BS2 BA2 A14
81 82
DDR_B_MA12 83 VDD3 VDD4 84 DDR_B_MA11
DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7
87 A9 A7 88
DDR_B_MA5 91 A8 A6 92 DDR_B_MA4
93 A5 A4 94
DDR_B_MA1 97 A3 A2 98 DDR_B_MA0
99 A1 A0 100
M_CLK_DDR2 101 VDD9 VDD10 102 M_CLK_DDR3
<7> M_CLK_DDR2 CK0 CK1 M_CLK_DDR3 <7>
<7> M_CLK_DDR#2 M_CLK_DDR#2 103 104 M_CLK_DDR#3
CK0# CK1# M_CLK_DDR#3 <7>
105 106 Layout Note:
DDR_B_MA10 107 VDD11 VDD12 108 DDR_B_BS1 (10uF_0603_6.3V)*8
A10/AP BA1 DDR_B_BS1 <7>
<7> DDR_B_BS0 DDR_B_BS0 109 110 DDR_B_RAS#
DDR_B_RAS# <7>
Place near DIMM
111 BA0 RAS# 112
<7> DDR_B_WE# DDR_B_WE# 113 VDD13 VDD14 114 DDR_CS2_DIMMB# (0.1uF_402_10V)*4
WE# S0# DDR_CS2_DIMMB# <7>
<7> DDR_B_CAS# DDR_B_CAS# 115 116 M_ODT2
CAS# ODT0 M_ODT2 <7>
117 118
DDR_B_MA13 119 VDD15 VDD16 120 M_ODT3
A13 ODT1 M_ODT3 <7> +VREF_CB
DDR_CS3_DIMMB# 121 122
<7> DDR_CS3_DIMMB# S1# NC2 +1.5V
123 124
125 VDD17 VDD18 126 +VREF_CB
NCTEST VREF_CA
0.1U_0402_10V6K
127 128
VSS27 VSS28
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
DDR_B_D32 129 130 DDR_B_D36
DQ32 DQ36
C159
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
DDR_B_D33 131 132 DDR_B_D37 1
DQ33 DQ37
C163
C164
C165
C166
C167
C168
C169
C170
C171
C172
133 134 1 1 1 1 1 1 1 1 1 1
B DDR_B_DQS4 137 DQS#4 DM4 138 B
DQS4 VSS31 2 @
139 140 DDR_B_D38
DDR_B_D34 141 VSS32 DQ38 142 DDR_B_D39 2 2 2 2 2 2 2 2 2 2
DDR_B_D35 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_B_D44
DDR_B_D41 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_B_DQS#5
DM5 DQS5 VDDQ(1.5V) =
155 156
DQ42 DQ46 3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)
DDR_B_D43 159 160 DDR_B_D47
161 DQ43 DQ47 162
6*0603 10uf (PER CONNECTOR) Layout Note:
DDR_B_D49 165 DQ48 DQ52 166 DDR_B_D53 Place near DIMM
167 DQ49 DQ53 168
VSS41 VSS42 VTT(0.75V) =
DDR_B_DQS#6 169 170
DDR_B_DQS6 171 DQS#6 DM6 172
DQS6 VSS43 3*0805 10uf 4*0402 1uf
173 174 DDR_B_D54
DDR_B_D50 175 VSS44 DQ54 176 DDR_B_D55 +0.75VS
DDR_B_D51 177 DQ50 DQ55 178
179 DQ51 VSS45 180 DDR_B_D60
VSS46 DQ60 1*0402 0.1uf 1*0402 2.2uf
DDR_B_D56 181 182 DDR_B_D61
DDR_B_D57 183 DQ56 DQ61 184
DQ57 VSS47 VDDSPD (3.3V)=
1U_0402_6.3V6K
C174
1U_0402_6.3V6K
C176
185 186 DDR_B_DQS#7
DM7 DQS7 1*0402 0.1uf 1*0402 2.2uf 1 1
189 190
DDR_B_D59 193 DQ58 DQ62 194 DDR_B_D63
195 DQ59 DQ63 196 2 2
197 VSS51 VSS52 198
199 SA0 EVENT# 200 SMB_DATA_S3
+3V_DIMM VDDSPD SDA SMB_DATA_S3 <12,15,36>
0.1U_0402_10V6K
A 1 2 201 202 SMB_CLK_S3 A

+3VS SA1 SCL SMB_CLK_S3 <12,15,36>
C178
1 R97 10K_0402_5% 203 204 +0.75VS

VTT1 VTT2 1/76BA1/86W
205 206
G1 G2
2 LCN_DAN06-K4406-0103
ME@
DDRIII-SODIMM SLOT2
1.0
5 4 3 2 1
5 4 3 2 1
PCH_RTCX1
W=20mils W=20mils 1 2 PCH_RTCX2

R98 10M_0402_5%
+RTCVCC +RTCBATT
NOGCLK@
Y1
R99 1 2
1K_0402_5% 32.768KHZ_12.5PF_CM31532768DZFT
1 2 1 1
C180 NOGCLK@ C181
1 12P_0402_50V8J 12P_0402_50V8J
C179 NOGCLK@ NOGCLK@
1U_0603_10V4Z 2 2
2
D D
R187 1 2 GCLK_32K
GCLK_32K <44>
0_0402_5%
@
CMOS U4A
SHORT PADS
CLRP2
+RTCVCC
+RTCVCC PCH_RTCX1 A20 C38 LPC_AD0
1 RTCX1 FWH0 / LAD0 LPC_AD0 <42>
1
R101 1 2 1M_0402_5% SM_INTRUDER# A38 LPC_AD1
FWH1 / LAD1 LPC_AD1 <42>
LPC
C183 PCH_RTCX2 C20 B37 LPC_AD2 EC and Mini card debug port
RTCX2 FWH2 / LAD2 LPC_AD2 <42>
R102 1 2 330K_0402_5% PCH_INTVRMEN 1U_0603_10V4Z C37 LPC_AD3
2
1 2 2 D20 FWH3 / LAD3 LPC_AD3 <42>
PCH_RTCRST#
R103 20K_0402_5% RTCRST# D36 LPC_FRAME#
INTVRMEN FWH4 / LFRAME# LPC_FRAME# <42>
烉Integrated
1 2 PCH_SRTCRST# G22
SRTCRST#
* HL烉 Integrated VRM enable R100 20K_0402_5% 1 LDRQ0#
E36
1
SHORT PADS
CLRP3
K22 K36
RTC
VRM disable SM_INTRUDER#
C182 INTRUDER# LDRQ1# / GPIO23
(INTVRMEN should always be pull high.) 1U_0603_10V4Z PCH_INTVRMEN C17 V5 SERIRQ
SERIRQ <42>
2
2 INTVRMEN SERIRQ
AM3 SATA_DTX_C_IRX_N0
+3VS SATA0RXN SATA_DTX_C_IRX_N0 <40>
HDA_BIT_CLK N34 AM1 SATA_DTX_C_IRX_P0
HDA_BCLK SATA0RXP SATA_DTX_C_IRX_P0 <40>
AP7 SATA_ITX_C_DRX_N0
SATA 6G
SATA0TXN SATA_ITX_C_DRX_N0 <40> HDD
R105 1 @ 2 1K_0402_5% HDA_SPKR HDA_SYNC L34 AP5 SATA_ITX_C_DRX_P0 SATA_ITX_C_DRX_P0 <40>
HDA_SYNC SATA0TXP
HIGH= Enable ( No Reboot ) HDA_SPKR T10 AM10
<41> HDA_SPKR SPKR SATA1RXN AM8
LOW= Disable (Default)
* HDA_RST# K34
HDA_RST#
SATA1RXP
SATA1TXN
AP11
AP10
SATA1TXP
C +3V_PCH HDA_SDIN0 E34 AD7 SATA_DTX_C_IRX_N2 C
<41> HDA_SDIN0 HDA_SDIN0 SATA2RXN SATA_DTX_C_IRX_N2 <40>
AD5 SATA_DTX_C_IRX_P2 ODD
SATA2RXP SATA_DTX_C_IRX_P2 <40>
R106 2 @ 1 1K_0402_5% ME_FLASH G34 AH5 SATA_ITX_C_DRX_N2
HDA_SDIN1 SATA2TXN AH4 SATA_ITX_C_DRX_N2 <40>
SATA_ITX_C_DRX_P2
SATA2TXP SATA_ITX_C_DRX_P2 <40>
Low = Disabled (Default) C34
* HDA_SDIN2 AB8
IHDA
High = Enabled [Flash Descriptor Security Overide] A34 SATA3RXN AB10
HDA_SDIN3 SATA3RXP AF3
SATA3TXN AF1
ME_FLASH A36 SATA3TXP
+3V_PCH <42> ME_FLASH HDA_SDO Y7 11/30 Add(Share ROM)
SATA
SATA4RXN Y5
SATA4RXP Near U5
R108 2 1 1K_0402_5% HDA_SYNC C36 AD3 RP27
HDA_DOCK_EN# / GPIO33 SATA4TXN AD1 EC_SPI_SO 8 1 SPI_SO_L
SATA4TXP <42> EC_SPI_SO
N32 EC_SPI_SI 7 2 SPI_SI_R
HDA_DOCK_RST# / GPIO13 <42> EC_SPI_SI
This signal has a weak internal pull-down Y3 EC_SPI_CLK 6 3 SPI_CLK_PCH_0
SATA5RXN <42> EC_SPI_CLK
On Die PLL VR is supplied by Y1 EC_SPI_CS# 5 4 SPI_SB_CS0#
SATA5RXP <42> EC_SPI_CS#
1.5V when smapled high(For mobile only) AB3
PCH_JTAG_TCK J3 SATA5TXN AB1 0_0804_8P4R_5%
* 1.8V when sampled low (For Desktop only)
Needs to be pulled High for Chief River platfrom
T41 PAD JTAG_TCK SATA5TXP @
PCH_JTAG_TMS H7 Y11 R111 +V1.05S_VCCP
T35 PAD JTAG_TMS SATAICOMPO
JTAG
37.4_0402_1%
PCH_JTAG_TDI K5 Y10 SATA_COMP 1 2
+5VS T36 PAD JTAG_TDI SATAICOMPI
PCH_JTAG_TDO H1
T37 PAD JTAG_TDO +V1.05S_VCCP
SATA3RCOMPO
AB12 R113 8MB SPI ROM FOR ME
For EMI HDA_BIT_CLK @ 49.9_0402_1%
<41> HDA_BITCLK_AUDIO
2
G
Q10 AB13 SATA3_COMP 1 2

RP12 LBSS138LT1G_SOT-23-3 SATA3COMPI & Non-share ROM.
8 1 HDA_SYNC_R 3 1 HDA_SYNC
<41> HDA_SYNC_AUDIO
7 2 SPI_CLK_PCH_R T3 AH1 RBIAS_SATA3 1 2
S
6 3 SPI_CLK SATA3RBIAS R115 +3V_ROM

2
B 5 4 HDA_RST# SPI_SB_CS0# Y14 750_0402_1% B

<41> HDA_RST_AUDIO# SPI_CS0#
R878
33_0804_8P4R_5% 1M_0402_5% R175 SPI_SB_CS1# T1 U6
SPI_CS1#
SPI
ME_FLASH 1 2 P3 SATALED# SPI_SB_CS1# 1 8 0_0402_5%

<41> HDA_SDOUT_AUDIO SATALED# CS# VCC
SPI_SO_R 1 @ 2 SPI_SO1 2 7
SPI_HOLD#1 R198
1
0_0402_5% SPI_SI V4 V14 R188 0_0402_5% SPI_WP#1 3 SO HOLD# SPI_CLK_PCH_1 1

6 @ 2 SPI_CLK_PCH_R
SPI_MOSI SATA0GP / GPIO21 4 WP# SCLK 5
SPI_SI1 1 @ 2 SPI_SI
SPI_SO_R U3 P1 BBS_BIT0_R GND SI R196
check with vender SPI_MISO SATA1GP / GPIO19 For EMI
GPIO19 has internal Pull UP 64M W25Q64FVSSIQ SOIC 8P 0_0402_5%
Del Q10 check with codec @ For EMI
PANTHER-POINT_FCBGA989
VDDIO using 3VALW HM76@ +3V_ROM
U4 HM70@
SPI_CLK_PCH_R R266 1 2 SPI_WP#1
3.3K_0402_5%
U6 Rersver 4M+2M Solution
1
R221 1 2 SPI_HOLD#1 +3V_ROM

R124 3.3K_0402_5%
33_0402_5% SA00005MQ80 R127 1 2 SPI_WP#
@ S IC BD82HM70 SJTNV C1 BGA 989P PCH C38! 3.3K_0402_5%
2
R129 1 2 SPI_HOLD# U5
3.3K_0402_5% SPI_SB_CS0# 1 8 0_0402_5%
C190 SPI_SO_R 1 @ 2 SPI_SO_L 2 CS# VCC 7
SPI_HOLD# R135
DPDG1.1 For EMI SO HOLD#
22P_0402_50V8J R131 0_0402_5% SPI_WP# 3 6
SPI_CLK_PCH_0 1 @ 2 SPI_CLK_PCH_R
@ 4 WP# SCLK 5
SPI_SI_R 1 @ 2 SPI_SI
+3VS GND SI R133
For EMI
RP17 64M W25Q64FVSSIQ SOIC 8P 0_0402_5%
BBS_BIT0_R 8 1 For EMI
R124;c190 close to U4.T3 pin SATALED# 7 2
PCH_GPIO16 6 3
A <19> PCH_GPIO16 SERIRQ 5 4 A
10K_0804_8P4R_5%

PCH (1/9) SATA,HDA,SPI, LPC, XDP
5 4 3 2 1
5 4 3 2 1
U4B
Q60A
2N7002DW-T/R7_SOT363-6
PCIE_PRX_DTX_N1 BG34 6 1 SMB_CLK_S3
<37> PCIE_PRX_DTX_N1 PERN1 SMB_CLK_S3 <12,13,36>
LAN PCIE_PRX_DTX_P1 BJ34 E12 PCH_GPIO11 R134 2 1 10K_0402_5%
<37> PCIE_PRX_DTX_P1 PERP1 SMBALERT# / GPIO11 +3V_PCH
C192 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N1 AV32
<37> PCIE_PTX_C_DRX_N1
C193 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_P1 AU32 PETN1 H14 PCH_SMBCLK DIMM1
2
<37> PCIE_PTX_C_DRX_P1 PETP1 SMBCLK
<36> PCIE_PRX_DTX_N2
PCIE_PRX_DTX_N2 BE34
PERN2 SMBDATA
C9 PCH_SMBDATA
+3VS DIMM2
5
PCIE_PRX_DTX_P2 BF34
WLAN
<36> PCIE_PRX_DTX_P2
<36> PCIE_PTX_C_DRX_N2
C194 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N2 BB32 PERP2
PETN2
MINI CARD
C195 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_P2 AY32 3 4 SMB_DATA_S3
<36> PCIE_PTX_C_DRX_P2 PETP2 SMB_DATA_S3 <12,13,36>
SMBUS
A12 DRAMRST_CNTRL_PCH
BG36 SML0ALERT# / GPIO60 DRAMRST_CNTRL_PCH <10,7>
2N7002DW-T/R7_SOT363-6
BJ36 PERN3 C8 PCH_SML0CLK
PERP3 SML0CLK Q60B
D AV34 2 R139 1 D
PETN3 +3V_PCH
AU34 G12 PCH_SML0DATA 1K_0402_5%
PETP3 SML0DATA Q61A
BF36 2 R140 1 10K_0402_5% 2N7002DW-T/R7_SOT363-6
PERN4 +3V_PCH
BE36 6 1 EC_SMB_CK2
AY34 PERP4 C13 EC_SMB_CK2 <23,39,42>
PCH_HOT#
BB34 PETN4 SML1ALERT# / PCHHOT# / GPIO74
PETP4 E14 SML1CLK VGA
2
SML1CLK / GPIO58
PCI-E*
BG37
BH37 PERN5
PERP5 SML1DATA / GPIO75
M16 SML1DATA
+3VS EC
5
AY36
BB36 PETN5
PETP5
thermal sensor
3 4 EC_SMB_DA2
BJ38 EC_SMB_DA2 <23,39,42>
BG38 PERN6 2N7002DW-T/R7_SOT363-6
AU36 PERP6 M7
Controller
PETN6 CL_CLK1 Q61B
AV36 +3V_PCH
PETP6 +3V_PCH
Link
BG40 T11
PERN7 CL_DATA1
2
BJ40
AY40 PERP7
2
BB40 PETN7 P10 R143
PETP7 CL_RST1# R544 R545
10K_0402_5%
BE38 2.2K_0402_5% 2.2K_0402_5%
1
BC38 PERN8
AW38 PERP8
1
AY38 PETN8 PCH_SML0CLK
PETP8
M10 PCH_SML0DATA
PEG_A_CLKRQ# / GPIO47 CLK_REQ_VGA# <23>
R153 1 @ 2 0_0402_5% CLK_PCIE_LAN#_R Y40
<37> CLK_PCIE_LAN# CLKOUT_PCIE0N
LAN R154 1 @ 2 0_0402_5% CLK_PCIE_LAN_R Y39
<37> CLK_PCIE_LAN CLKOUT_PCIE0P AB37
For EMI CLK_PCIE_VGA#_R R168 1 @ 2 0_0402_5%
C J2 CLKOUT_PEG_A_N AB38 CLK_PCIE_VGA# <23> C
CLK_PCIE_VGA_R R172 1 @ 2 0_0402_5%
CLOCKS
<37> CLKREQ_LAN# 2 1 10K_0402_5% PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P CLK_PCIE_VGA <23>
R152
<36> CLK_PCIE_WLAN1#
+3V_PCH
R156 1 @ 2 0_0402_5% CLK_PCIE_WLAN1#_R AB49
CLKOUT_PCIE1N CLKOUT_DMI_N
AV22 CLK_CPU_DMI# For EMI
CLK_CPU_DMI# <6>
+3V_PCH
+3VS
R165 1 @ 2 0_0402_5% CLK_PCIE_WLAN1_R AB47 AU22 CLK_CPU_DMI
<36> CLK_PCIE_WLAN1 CLKOUT_PCIE1P CLKOUT_DMI_P CLK_CPU_DMI <6>
WLAN For EMI RP23
M1 SML1DATA 8 1
<36> CLKREQ_WLAN# PCIECLKRQ1# / GPIO18
+3VS R158 2 1 10K_0402_5% AM12 EC_SMB_DA2 7 2
CLKOUT_DP_N AM13 SML1CLK 6 3
AA48 CLKOUT_DP_P EC_SMB_CK2 5 4
AA47 CLKOUT_PCIE2N RP8 10K_0804_8P4R_5%
CLKOUT_PCIE2P BF18 CLK_BUF_CPU_DMI# 1 8 2.2K_0804_8P4R_5%
V10 CLKIN_DMI_N BE18 CLK_BUF_CPU_DMI 2 7
PCIECLKRQ2# / GPIO20 CLKIN_DMI_P 3 6 +3V_PCH
4 5
Y37 BJ30 CLKIN_DMI2# +3VS
Y36 CLKOUT_PCIE3N CLKIN_GND1_N BG30 CLKIN_DMI2 RP24
CLKOUT_PCIE3P CLKIN_GND1_P PCH_SMBCLK 8 1
A8 SMB_CLK_S3 7 2
PCIECLKRQ3# / GPIO25 G24 CLK_BUF_DREF_96M# R162 1 2 10K_0402_5% PCH_SMBDATA 6 3
CLKIN_DOT_96N E24 CLK_BUF_DREF_96M R163 1 2 10K_0402_5% SMB_DATA_S3 5 4
Y43 CLKIN_DOT_96P
Y45 CLKOUT_PCIE4N 2.2K_0804_8P4R_5%
CLKOUT_PCIE4P AK7 CLK_BUF_PCIE_SATA# R164 1 2 10K_0402_5%
L12 CLKIN_SATA_N AK5 CLK_BUF_PCIE_SATA R166 1 2 10K_0402_5%
PCIECLKRQ4# / GPIO26 CLKIN_SATA_P
V45 K45 CLK_BUF_ICH_14M R167 1 2 10K_0402_5%

V46 CLKOUT_PCIE5N REFCLK14IN
CLKOUT_PCIE5P
L14 H45 CLK_PCI_LPBACK
PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLK_PCI_LPBACK <18>
B B
AB42 V47 XTAL25_IN 0_0402_5% 2 1 R796 GCLK_PCH_25MHZ
AB40 CLKOUT_PEG_B_N XTAL25_IN V49 XTAL25_OUT GCLK_PCH_25MHZ <44>
@
CLKOUT_PEG_B_P XTAL25_OUT
E6 R171 +V1.05S_VCCP
PEG_B_CLKRQ# / GPIO56 90.9_0402_1%
Y47 XCLK_RCOMP 1 2
For EMI
XCLK_RCOMP
V40
V42 CLKOUT_PCIE6N B Phaes change to GCLK@
CLKOUT_PCIE6P XTAL25_IN
T13 NOGCLK@
PCIECLKRQ6# / GPIO45 27M_SSC XTAL25_OUT 1 2
V38 K43 R169 1M_0402_5%
V37 CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64
FLEX CLOCKS
CLKOUT_PCIE7P F47 3 4
K12 CLKOUTFLEX1 / GPIO65 OSC NC
PCIECLKRQ7# / GPIO46 H47 2 1
AK14 CLKOUTFLEX2 / GPIO66 NC OSC
PCIE_CLK_8N AK13 CLKOUT_ITPXDP_N K49 PCH_GPIO67 Y2
PCIE_CLK_8P CLKOUT_ITPXDP_P CLKOUTFLEX3 / GPIO67 PCH_GPIO67 <19>
1 25MHZ_10PF_7V25000014 1
BIOS Request SKU ID C196 NOGCLK@ C197
PANTHER-POINT_FCBGA989 12P_0402_50V8J 12P_0402_50V8J
HM76@ NOGCLK@ NOGCLK@
2 2
A A

PCH (2/9) PCIE, SMBUS, CLK
5 4 3 2 1
5 4 3 2 1
+RTCVCC
DSWODVREN R179 2 1 330K_0402_5%
D D
U4C * 烉
DSWODVREN - On Die DSW VR Enable
烉
H Enable
L Disable
DMI_CTX_PRX_N0 BC24 BJ14 FDI_CTX_PRX_N0

<5> DMI_CTX_PRX_N0 DMI0RXN FDI_RXN0 FDI_CTX_PRX_N0 <5>
U15 DMI_CTX_PRX_N1 BE20 AY14 FDI_CTX_PRX_N1
MC74VHC1G08DFT2G SC70 5P DMI_CTX_PRX_N2 BG18 BE14 FDI_CTX_PRX_N2
3
@ DMI_CTX_PRX_N3 BG20 BH13 FDI_CTX_PRX_N3

1 BC12 FDI_CTX_PRX_N4
G
<42,55> VGATE A FDI_RXN4 FDI_CTX_PRX_N4 <5>

4 SYS_PWROK DMI_CTX_PRX_P0 BE24 BJ12 FDI_CTX_PRX_N5
Y <5> DMI_CTX_PRX_P0 DMI0RXP FDI_RXN5 FDI_CTX_PRX_N5 <5>
PCH_PWROK 2 DMI_CTX_PRX_P1 BC20 BG10 FDI_CTX_PRX_N6
B <5> DMI_CTX_PRX_P1 DMI1RXP FDI_RXN6 FDI_CTX_PRX_N6 <5>
P
2 DMI_CTX_PRX_P2 BJ18 BG9 FDI_CTX_PRX_N7

<5> DMI_CTX_PRX_P2 DMI2RXP FDI_RXN7 FDI_CTX_PRX_N7 <5>
DMI_CTX_PRX_P3 BJ20
<5> DMI_CTX_PRX_P3
5
C854 @ DMI3RXP BG14 FDI_CTX_PRX_P0

FDI_RXP0 FDI_CTX_PRX_P0 <5>
0.1U_0402_16V4Z DMI_CRX_PTX_N0 AW24 BB14 FDI_CTX_PRX_P1
1 <5> DMI_CRX_PTX_N0 DMI0TXN FDI_RXP1 FDI_CTX_PRX_P1 <5>
DMI_CRX_PTX_N1 AW20 BF14 FDI_CTX_PRX_P2
<5> DMI_CRX_PTX_N1 DMI1TXN FDI_RXP2 FDI_CTX_PRX_P2 <5>
+3VS DMI_CRX_PTX_N2 BB18 BG13 FDI_CTX_PRX_P3
DMI_CRX_PTX_N3 AV18 BE12 FDI_CTX_PRX_P4
DMI
FDI
3/20 Add (ESD request) BG12 FDI_CTX_PRX_P5
FDI_RXP5 FDI_CTX_PRX_P5 <5>
DMI_CRX_PTX_P0 AY24 BJ10 FDI_CTX_PRX_P6
<5> DMI_CRX_PTX_P0 DMI0TXP FDI_RXP6 FDI_CTX_PRX_P6 <5>
DMI_CRX_PTX_P1 AY20 BH9 FDI_CTX_PRX_P7
<5> DMI_CRX_PTX_P1 DMI1TXP FDI_RXP7 FDI_CTX_PRX_P7 <5>
DMI_CRX_PTX_P2 AY18
<5> DMI_CRX_PTX_P2 AU18 DMI2TXP
DMI_CRX_PTX_P3
<5> DMI_CRX_PTX_P3 DMI3TXP AW16 FDI_INT
FDI_INT FDI_INT <5>
+V1.05S_VCCP BJ24 AV12 FDI_FSYNC0
DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 <5>
1 2 DMI_IRCOMP BG25 BC10 FDI_FSYNC1
DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 <5>
R177 49.9_0402_1%
1 2 RBIAS_CPY BH21 AV14 FDI_LSYNC0
C DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 <5> C
R178 750_0402_1%
4mil width and place BB10 FDI_LSYNC1
FDI_LSYNC1 FDI_LSYNC1 <5>
within 500mil of the PCH
A18 DSWODVREN Note:This signal must be always pulled-up to VccRTC.
DSWVRMEN
SUSACK# is only used on platform
that support the Deep Sx state.
System Power Management

C12 E22 EC_RSMRST#
SUSACK# DPWROK
SYS_RST# K3 B9
<19> SYS_RST# SYS_RESET# WAKE# PCIE_WAKE# <36>
R299 10K_0402_5%
SYS_PWROK P12 N3 PM_CLKRUN# 2 1
<42> SYS_PWROK SYS_PWROK CLKRUN# / GPIO32
L22 G8 SUS_STAT#
<42> PCH_PWROK PWROK SUS_STAT# / GPIO61 T38 PAD
PCH_PWROK L10 N14

APWROK SUSCLK / GPIO62 SUSCLK <42>
PM_DRAM_PWRGD B13 D10

<6> PM_DRAM_PWRGD DRAMPWROK SLP_S5# / GPIO63 PM_SLP_S5# <42>
C21 H4
<42> EC_RSMRST# RSMRST# SLP_S4# PM_SLP_S4# <42>
+3V_PCH
SUSWARN# K16 F4
SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# PM_SLP_S3# <42>
2 R192 1 300_0402_5% PM_DRAM_PWRGD
B E20 G10 Can be left NC when IAMT is not support on the platfrom B
<42> PBTN_OUT# PWRBTN# SLP_A#
R194 2 1 10K_0402_5% SUSWARN#
D29 1 2 AC_PRESENT_R H20 G16

<42,47,49> ACIN ACPRESENT / GPIO31 SLP_SUS#
CH751H-40PT_SOD323-2
R197 2 @ 1 10K_0402_5% EC_RSMRST# E10 AP14 H_PM_SYNC
BATLOW# / GPIO72 PMSYNCH H_PM_SYNC <6>
RI# A10 K14 Can be left NC if no use integrated LAN.

RI# SLP_LAN# / GPIO29
HM76@
+3V_PCH
R309 1 2 200K_0402_5% AC_PRESENT_R
+3V_PCH
RP25
8 1 PCIE_WAKE#
A 7 2 RI# A
6 3 EC_SMI#
5 4 EC_SMI# <19,42>
10K_0804_8P4R_5%

PCH (3/9) DMI,FDI,PM,
5 4 3 2 1
5 4 3 2 1
U4D
R438
D 2 1 ENBKL J47 AP43 D
<42> ENBKL L_BKLTEN SDVO_TVCLKINN
M45 AP45
<33> PCH_ENVDD L_VDD_EN SDVO_TVCLKINP
100K_0402_1% P45 AM42
<33> PCH_PWM L_BKLTCTL SDVO_STALLN AM40
EDID_CLK T40 SDVO_STALLP
<33> EDID_CLK K47 L_DDC_CLK AP39
EDID_DATA
<33> EDID_DATA L_DDC_DATA SDVO_INTN AP40
CTRL_CLK T45 SDVO_INTP
CTRL_DATA P39 L_CTRL_CLK
+3VS L_CTRL_DATA
2.37K_0402_1% 2 R206 1 LVDS_IBG AF37 P38 HDMICLK_NB
LVD_IBG SDVO_CTRLCLK HDMICLK_NB <35>
AF36 M39 HDMIDAT_NB
LVD_VBG SDVO_CTRLDATA HDMIDAT_NB <35>
RP14 AE48
8 1 EDID_DATA AE47 LVD_VREFH AT49
7 2 EDID_CLK LVD_VREFL DDPB_AUXN AT47
6 3 CTRL_DATA DDPB_AUXP AT40
DDPB_HPD TMDS_B_HPD# <35>
5 4 CTRL_CLK AK39
<33> LVDS_ACLK# LVDSA_CLK#
LVDS
AK40 AV42 TMDS_B_DATA2#_PCHHDMI@ C200 1 2 0.1U_0402_10V6K
<33> LVDS_ACLK LVDSA_CLK DDPB_0N HDMI_TX2-_CK <35>
2.2K_0804_8P4R_5% AV40 TMDS_B_DATA2_PCH HDMI@ C201 1 2 0.1U_0402_10V6K HDMI D2
AN48 DDPB_0P AV45 TMDS_B_DATA1#_PCHHDMI@ 1 2 HDMI_TX2+_CK <35>
C202 0.1U_0402_10V6K
<33> LVDS_A0# AM47 LVDSA_DATA#0 DDPB_1N AV46 TMDS_B_DATA1_PCH HDMI@ 1 2 HDMI_TX1-_CK <35>
C203 0.1U_0402_10V6K HDMI D1
<33> LVDS_A1# LVDSA_DATA#1 DDPB_1P HDMI_TX1+_CK <35>
Digital Display Interface

AK47 AU48 TMDS_B_DATA0#_PCHHDMI@ C204 1 2 0.1U_0402_10V6K HDMI
C <33> LVDS_A2# AJ48 LVDSA_DATA#2 DDPB_2N AU47 TMDS_B_DATA0_PCH HDMI@ 1 2 HDMI_TX0-_CK <35> C
C205 0.1U_0402_10V6K HDMI D0
LVDSA_DATA#3 DDPB_2P HDMI_TX0+_CK <35>
AV47 TMDS_B_CLK#_PCH HDMI@ C206 1 2 0.1U_0402_10V6K
AN47 DDPB_3N AV49 TMDS_B_CLK_PCH 1 2 HDMI_CLK-_CK <35>
HDMI@ C207 0.1U_0402_10V6K HDMI CLK
<33> LVDS_A0 AM49 LVDSA_DATA0 DDPB_3P HDMI_CLK+_CK <35>
<33> LVDS_A1 LVDSA_DATA1
AK49
<33> LVDS_A2 AJ47 LVDSA_DATA2 P46
LVDSA_DATA3 DDPC_CTRLCLK
CAP move on Conn, side
P42
RP20 DDPC_CTRLDATA
8 1 DAC_BLU AF40
7 2 DAC_GRN AF39 LVDSB_CLK# AP47
6 3 DAC_RED LVDSB_CLK DDPC_AUXN AP49
5 4 AH45 DDPC_AUXP AT38
AH47 LVDSB_DATA#0 DDPC_HPD
150_0804_8P4R_1% AF49 LVDSB_DATA#1 AY47
AF45 LVDSB_DATA#2 DDPC_0N AY49
Max = 800 mils LVDSB_DATA#3 DDPC_0P
DDPC_1N
AY43
AH43 AY45
AH49 LVDSB_DATA0 DDPC_1P BA47
AF47 LVDSB_DATA1 DDPC_2N BA48
AF43 LVDSB_DATA2 DDPC_2P BB47
LVDSB_DATA3 DDPC_3N BB49
DDPC_3P
B DAC_BLU N48 M43 B

<34> DAC_BLU CRT_BLUE DDPD_CTRLCLK
DAC_GRN P49 M36
<34> DAC_GRN T49 CRT_GREEN DDPD_CTRLDATA
DAC_RED
<34> DAC_RED CRT_RED
AT45
DDPD_AUXN
<34> CRT_DDC_CLK
CRT_DDC_CLK
CRT_DDC_DATA
T39
M40 CRT_DDC_CLK CRT DDPD_AUXP
AT43
BH41
<34> CRT_DDC_DATA CRT_DDC_DATA DDPD_HPD
BB43
+3VS M47 DDPD_0N BB45
<34> CRT_HSYNC M49 CRT_HSYNC DDPD_0P BF44
<34> CRT_VSYNC CRT_VSYNC DDPD_1N BE44
DDPD_1P BF42
DDPD_2N
1
CRT_IREF T43 BE42

R559 R524 T42 DAC_IREF DDPD_2P BJ42
CRT_IRTN DDPD_3N
1
2.2K_0402_5% 2.2K_0402_5% BG42

R211 DDPD_3P
1K_0402_1% PANTHER-POINT_FCBGA989
2
HM76@
CRT_DDC_CLK
2
CRT_DDC_DATA
A A

PCH (4/9) LVDS,CRT,DP,HDMI
B 1.0
5 4 3 2 1
5 4 3 2 1
+3VS
RP1
PCI_PIRQA# 1 10
PCI_PIRQD# 2 9 PCH_GPIO2 U4E
PCI_PIRQC# 3 8 DGPU_PWR_EN AY7
PCI_PIRQB# 4 7 PCH_GPIO4 RSVD1 AV7
5 6 PCH_GPIO3 BG26 RSVD2 AU3
+3VS BJ26 TP1 RSVD3 BG4
BH25 TP2 RSVD4
8.2K_1206_10P8R_5% BJ16 TP3 AT10
BG16 TP4 RSVD5 BC8
AH38 TP5 RSVD6
D TP6 D
AH37 AU2
AK43 TP7 RSVD7 AT4
+3VS AK45 TP8 RSVD8 AT3
RP7 C18 TP9 RSVD9 AT1
8 1 DGPU_HOLD_RST# N30 TP10 RSVD10 AY3
7 2 PCH_WL_OFF# H3 TP11 RSVD11 AT5
6 3 PCH_GPIO5 AH12 TP12 RSVD12 AV3
5 4 NVDD_PWR_EN AM4 TP13 RSVD13 AV1
AM5 TP14 RSVD14 BB1
8.2K_0804_8P4R_5% Y13 TP15 RSVD15 BA3
K24 TP16 RSVD16 BB5
Pull-up resistors are not required TP17 RSVD17
L24 BB3
on these signals AB46 TP18 RSVD18 BB7
R292 1 @ 2 8.2K_0402_5% PCH_GPIO51 AB45 TP19 RSVD19 BE8
TP20 RSVD20
RSVD
BD4
R557 1 @ 2 8.2K_0402_5% PCH_GPIO53 RSVD21 BF6
RSVD22
B21 AV5
M20 TP21 RSVD23 AV10
AY16 TP22 RSVD24
BG46 TP23 AT8
TP24 RSVD25
AY5
RSVD26 BA2
USB3_RX1_N BE28 RSVD27
<45> USB3_RX1_N USB3Rn1
<45> USB3_RX2_N USB3_RX2_N BC30 AT12
BE32 USB3Rn2 RSVD28 BF3
C USB3Rn3 RSVD29 C
BJ32
USB3_RX1_P BC28 USB3Rn4
<45> USB3_RX1_P USB3Rp1
<45> USB3_RX2_P USB3_RX2_P BE30 USB DEBUG=PORT1 AND PORT9
BF32 USB3Rp2
BG32 USB3Rp3 C24 USB20_N0
Boot BIOS Strap USB3Rp4 USBP0N USB20_N0 <45>
USB3_TX1_N AV26 A24 USB20_P0 LEFT USB
<45> USB3_TX1_N USB3Tn1 USBP0P USB20_P0 <45>
GPIO51 GPIO19 Boot BIOS USB3_TX2_N BB26 C25 USB20_N1 (USB 3.0)
<45> USB3_TX2_N USB3Tn2 USBP1N USB20_N1 <45>
GNT1#/ AU28 B25 USB20_P1 LEFT USB
Bit11 Bit10 Destination AY30 USB3Tn3 USBP1P C26 USB20_N2
USB20_P1 <45>
GPIO51 USB3_TX1_P AU26 USB3Tn4 USBP2N A26 USB20_P2
USB20_N2 <45>
<45> USB3_TX1_P
USB3_TX2_P AY26 USB3Tp1 USBP2P K28 USB20_N3
USB20_P2 <45> Touch Screen
0 1 Reserved <45> USB3_TX2_P USB3Tp2 USBP3N USB20_N3 <33>
SATA1GP/ AV28 H28 USB20_P3 USB Camera
USB3Tp3 USBP3P USB20_P3 <33>
1 0 PCI AW30 E28
GPIO19 USB3Tp4 USBP4N D28
USBP4P C28
Internal 1 1 SPI (Default) HM76 not support USB2.0 for port 6-7
* USBP5N
USBP5P
A28
PH 0 0 LPC C29 HM70 not support USB2.0 for port 4-7 &12 &13
USBP6N B29
PCI_PIRQA# K40 USBP6P N28
PCI_PIRQB# K38 PIRQA# USBP7N M28
NM70 not support USB2.0 for port 4-7 &12 &13
PIRQB# USBP7P
PCI
PCI_PIRQC# H38 L30
PCI_PIRQD# G38 PIRQC# USBP8N K30
PIRQD# USBP8P G30 USB20_N9
USBP9N USB20_N9 <43>
C46 E30 USB20_P9 USB2.0
<23> DGPU_HOLD_RST# REQ1# / GPIO50 USBP9P USB20_P9 <43>
USB
NVDD_PWR_EN C44 C30 USB20_N10
<27,54> NVDD_PWR_EN REQ2# / GPIO52 USBP10N USB20_N10 <36>
E40 A30 USB20_P10 WLAN
<23,25,42> DGPU_PWR_EN REQ3# / GPIO54 USBP10P USB20_P10 <36>
B L32 USB20_N11 B
USBP11N USB20_N11 <43>
PCH_GPIO51 D47 K32 USB20_P11 CARD READER
GNT1# / GPIO51 USBP11P USB20_P11 <43>
PCH_GPIO53 E42 G32
PCH_WL_OFF# F46 GNT2# / GPIO53 USBP12N E32
<36> PCH_WL_OFF# GNT3# / GPIO55 USBP12P C32
USBP13N A32
PCH_GPIO2 G42 USBP13P
GPIO55 PIRQE# / GPIO2
PCH_GPIO3 G40
PCH_WL_OFF# R215 1 @ 2 1K_0402_5% PCH_GPIO4 C42 PIRQF# / GPIO3 C33 USBRBIAS 1 R218 2
PCH_GPIO5 D44 PIRQG# / GPIO4 USBRBIAS# 22.6_0402_1%
PIRQH# / GPIO5
B33
Within 500 mils
PCI_PME# K10 USBRBIAS
A16 swap overide Strap/Top-Block T39 PAD PME#
Swap Override jumper For LEFT USB3.0 Port
PCH_PLTRST# C6 A14 USB_OC0#
<6> PCH_PLTRST# PLTRST# OC0# / GPIO59 USB_OC0# <45>
Low=A16 swap K20 USB_OC1#
OC1# / GPIO40 B17 USB_OC2#
override/Top-Block For EMI OC2# / GPIO41
PCI_GNT3# Swap Override enabled 22_0402_5% 1 2 R219 CLK_PCI_LPBACK_R H49 C16 USB_OC3#
<15> CLK_PCI_LPBACK CLKOUT_PCI0 OC3# / GPIO42
High=Default 22_0402_5% 1 2 R220 CLK_PCI_EC_R H43 L16 USB_OC4#
* <42> CLK_PCI_EC
J48 CLKOUT_PCI1
CLKOUT_PCI2
OC4# / GPIO43
OC5# / GPIO9
A16 USB_OC5#
USB_OC4# <43>
+3V_PCH
K42 D14 USB_OC6# For RIGHT USB2.0 Port
CLKOUT_PCI3 OC6# / GPIO10 RP18
H40 C14 USB_OC7#
CLKOUT_PCI4 OC7# / GPIO14 USB_OC0# 1 10
USB_OC1# 2 9 USB_OC4#
PANTHER-POINT_FCBGA989 USB_OC2# 3 8 USB_OC5#
HM76@ USB_OC3# 4 7 USB_OC6#
5 6 USB_OC7#
+3V_PCH
A A
R222 10K_1206_10P8R_5%
1 2 PCH_PLTRST#
<23,36,37,42> PLT_RST#
0_0402_5% @
1

R223
100K_0402_5%
PCH (5/9) PCI, USB
2
Custom 1.0
5 4 3 2 1
5 4 3 2 1
+3VS +3VS
+3VS
PCH_GPIO71 Function
2
10K_0402_5%
10K_0402_5%
PCH_GPIO69 PCH_GPIO70 Function
10K_0402_5%
R702 R703
@ HM70@
1 N14M-GE 1000MHz R704
1000M@
- - NM70
1
PCH_GPIO69 PCH_GPIO70
1
PCH_GPIO71
0 N14M-GE 900MH
2
- - Reserved
2
R707 R705
D D
@ HM76@ R706
- 1 HM70 10K_0402_5% 10K_0402_5% 900M@
1
10K_0402_5%
1
- 0 HM76
U4F
T7 C40
BMBUSY# / GPIO0 TACH4 / GPIO68
A42 B41 PCH_GPIO69
GPIO28 TACH1 / GPIO1 TACH5 / GPIO69
On-Die PLL Voltage Regulator H36 C41 PCH_GPIO70 +3VS
TACH2 / GPIO6 TACH6 / GPIO70
This signal has a weak internal pull up
烉烉On-Die <42> EC_SCI#
EC_SCI# E38
TACH3 / GPIO7 TACH7 / GPIO71
A40 PCH_GPIO71
2
H voltage regulator enable
* L On-Die PLL Voltage Regulator disable <16,42> EC_SMI#
EC_SMI# C10
GPIO8
R236
10K_0402_5%
R240 1 @ 2 1K_0402_5% PCH_GPIO28 C4
LAN_PHY_PW R_CTRL / GPIO12
+3V_PCH
1
R230 1 2 1K_0402_5% EC_LID_OUT# G2 P4 +3VS
GPIO15 A20GATE GATEA20 <42>
<42> EC_LID_OUT# AU16
PCH_GPIO16 U2 PECI
<14> PCH_GPIO16 SATA4GP / GPIO16 P5 KBRST# KBRST# R226 1 2 10K_0402_5%
* PCH_GPIO27 (Have internal Pull-High) <26,27,54> DGPU_PWROK
RCIN# KBRST# <42>
GPIO
D40 AY11
High: VCCVRM VR Enable TACH0 / GPIO17 PROCPW RGD H_CPUPWRGD <6>
CPU/MISC
PU on power side
Low: VCCVRM VR Disable PCH_BT_ON# T5 AY10 PCH_THRMTRIP#_R 1 2 H_THRMTRIP#
H_THRMTRIP# <6>
C
SCLOCK / GPIO22 THRMTRIP# R239 390_0402_5% C
1 2 10K_0402_5% <36> PCH_BT_ON# E8 T14
R245 @ PCH_GPIO27 ODD_EN
+3V_PCH <40> ODD_EN GPIO24 INIT3_3V#
PCH_GPIO27 E16 AY1
R241 GPIO27 DF_TVS INIT3_3V
1 2 10K_0402_5% PCH_GPIO28 P8 This signal has weak internal PU,can't pull low
GPIO28 AH8
INTEL_BT_OFF# K1 TS_VSS1
GPIO36, 37 <36> INTEL_BT_OFF# STP_PCI# / GPIO34 +1.8VS
1 R242 2 10K_0402_5% AK11
+3VS When Unused as GPIO or SATA*GP +3VS TS_VSS2
PCH_GPIO35 K4
+3VS GPIO35
Use 8.2K-10K pull-down to ground. TS_VSS3
AH10 DMI Termination Voltage
PCH_GPIO36 V8
SATA2GP / GPIO36
1
1
AK10 Set to Vcc when HIGH
PCH_GPIO37 M5 TS_VSS4
R244 @ R250 @
SATA3GP / GPIO37
NV_CLE
10K_0402_5% 10K_0402_5% Set to Vss when LOW R216
PCH_GPIO38 N2 P37 2.2K_0402_5%
SLOAD / GPIO38 NC_1
2
2
PCH_GPIO37 PCH_GPIO36 PCH_GPIO39 M3 NV_CLE 2 1
SDATAOUT0 / GPIO39 H_SNB_IVB# <6>
R217 1K_0402_5%
1
V13 BG2 Weak internal CLOSE TO THE BRANCHING POINT

SDATAOUT1 / GPIO48 VSS_NCTF_15
1
PU,Do not pull low

R881 V3 BG48
10K_0402_5% R547 @ SATA5GP / GPIO49 / TEMP_ALERT# VSS_NCTF_16
@ 10K_0402_5% D6 BH3
2
GPIO57 VSS_NCTF_17
2
BH47
VSS_NCTF_18
A4 BJ4
VSS_NCTF_1 VSS_NCTF_19
A44 BJ44
B VSS_NCTF_2 VSS_NCTF_20 B
A45 BJ45
NCTF
A46 BJ46
+3VS VSS_NCTF_4 VSS_NCTF_22
BIOS Request SKU ID
A5 BJ5
RP10 VSS_NCTF_5 VSS_NCTF_23
+3VS 8 1 PCH_GPIO39 A6 BJ6
7 2 SYS_RST# VSS_NCTF_6 VSS_NCTF_24
SYS_RST# <16>
6 3 PCH_BT_ON# B3 C2
5 4 PCH_GPIO35 VSS_NCTF_7 VSS_NCTF_25
B47 C48
10K_0804_8P4R_5% VSS_NCTF_8 VSS_NCTF_26
2
1
10K_0402_5%
BD1 D1
R246 VSS_NCTF_9 VSS_NCTF_27
R711 UMA@ BD49 D49
UMA@ 10K_0402_5% VSS_NCTF_10 VSS_NCTF_28
BE1 E1
1
PCH_GPIO38 BE49 E49
PCH_GPIO67 BF1 F1
PCH_GPIO67 <15> VSS_NCTF_13 VSS_NCTF_31
BF49 F49
2
1
10K_0402_5%
R708 R298 PANTHER-POINT_FCBGA989

OPT@ OPT@
10K_0402_5% PCH_GPIO38 PCH_GPIO67 Function HM76@
1
A A
0 0 Optimus
0 1 Reserved Security Classification Compal Secret Data Compal Electronics, Inc.
1 0 DIS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (6/9) GPIO, CPU, MISC
Custom 1.0
1 1 UMA DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5 4 3 2 1
5 4 3 2 1
L1 Change to 1 ohm P/N

S RES 1/10W 1 +-1% 0603
+V1.05S_VCCP U4G POWER +3VS PCH Power Rail Table

Near AA23
1300mA L1 3.3_0603_1% Refer to CPU EDS R1.5
AA23 U48 +VCCADAC 2 1
AC23 VCCCORE[1] 1mA VCCADAC
VCCCORE[2] 1 1 1 1 1 S0 Iccmax
1U_0402_6.3V6K
C210
1U_0402_6.3V6K
C211
1U_0402_6.3V6K
C212
1 1 1 1 AD21 Voltage Rail Voltage Current (A)
CRT
VCCCORE[3]
10U_0603_6.3V6M
C209
AD23 U47 C213 C214 C215 C229 C231
AF21 VCCCORE[4] VSSADAC 0.01U_0402_25V7K 0.1U_0402_10V7K 10U_0603_6.3V6M 10U_0603_6.3V6M 22U_0805_6.3V6M
VCC CORE
AF23 VCCCORE[5] 2 2 2@ 2@ 2
VCCCORE[6]
V_PROC_IO 1.05 0.001
D 2 2 2 2 AG21 +3VS D
AG23 VCCCORE[7]
AG24 VCCCORE[8] AK36
VCCCORE[9] 1mA VCCALVDS V5REF 5 0.001
AG26
AG27 VCCCORE[10] AK37
AG29 VCCCORE[11] VSSALVDS
VCCCORE[12]
V5REF_Sus 5 0.001
AJ23 +1.8VS
VCCCORE[13]
LVDS
AJ26 AM37 L2
AJ27 VCCCORE[14] VCCTX_LVDS[1] 0.1UH_MLF1608DR10KT_10%_1608
VCCCORE[15]
Vcc3_3 3.3 0.228
AJ29 AM38 +VCCTX_LVDS 2 1
AJ31 VCCCORE[16] VCCTX_LVDS[2]
1 1 1 0.1uH inductor, 200mA
+V1.05S_VCCP VCCCORE[17] AP36
60mA VCCTX_LVDS[3] VccADAC 3.3 0.001
C216 C217 C218
AP37 0.01U_0402_25V7K 0.01U_0402_25V7K 22U_0805_6.3V6M
AN19 VCCTX_LVDS[4] 2 2 2
VCCIO[28]
VccADPLLA 1.05 0.075
+VCCAPLLEXP BJ22 +3VS VccADPLLB 1.05 0.075

T29 PAD VCCAPLLEXP Near V33
This pin can be left as no connect in V33
VCC3_3[6]
HVCMOS
AN16 VccCore 1.05 1.3
On-Die VR enabled mode (default). VCCIO[15]
1
AN17
VCCIO[16] V34 C219
VCC3_3[7]
VccDMI 1.05 0.042
0.1U_0402_10V7K
AN21 2
VCCIO[17]
VccIO 1.05 3.709
AN26 +1.5VS
VCCIO[18]
AN27 3711mA AT16 VccASW 1.05 0.903
VCCIO[19] VCCVRM[3]
+V1.05S_VCCP AP21 +V1.05S_VCCP
C
Near AN16 VCCIO[20] Near AT20 C
VccSPI 3.3 0.01
AP23 AT20
VCCIO[21] VCCDMI[1]
1
+V1.05S_VCCP
1U_0402_6.3V6K
C222
1U_0402_6.3V6K
C223
1U_0402_6.3V6K
C224
1U_0402_6.3V6K
C225
DMI
1 1 1 1 1 AP24 Near AB36 VccDSW 3.3 0.001
VCCIO[22]
10U_0603_6.3V6M
C221
VCCIO
C220
AP26 AB36 1U_0402_6.3V6K
VCCIO[23] 20mA VCCCLKDMI 2
1 VccDFTERM 1.8 0.002
2 2 2 2 2 AT24
VCCIO[24] C226
1U_0402_6.3V6K VccRTC 3.3 6 uA
AN33 2
VCCIO[25]
AN34 AG16 VccSus3_3 3.3 0.065
+3VS VCCIO[26] VCCDFTERM[1]
BH29 AG17 +1.8VS VccSusHDA 3.3 / 1.5 0.01

VCC3_3[3] 190mAVCCDFTERM[2]
1
C227
DFT / SPI Near AG16
0.1U_0402_10V7K +1.5VS AJ16 VccVRM 1.8 / 1.5 0.167
VCCDFTERM[3]
2 1
AP16 C228
VCCVRM[2] AJ17 0.1U_0402_10V7K
VCCDFTERM[4]
VccCLKDMI 1.05 0.075
This pin can be left as no connect in +1.05VS_VCCAPLL_FDI BG6 2
T30
On-Die VR enabled mode (default). +V1.05S_VCCP PAD VccAFDIPLL +3V_ROM VccSSC 1.05 0.095
AP17 Near V1
VCCIO[27] V1 VccDIFFCLKN 1.05 0.055
FDI
20mA VCCSPI
1
AU20
+V1.05S_VCCP VCCDMI[2] C230 VccALVDS 3.3 0.001
1U_0402_6.3V6K
B PANTHER-POINT_FCBGA989 2 B
VccTX_LVDS 1.8 0.04
HM76@
11/30 Add(Share ROM)
+3VALW +3V_ROM +3VS
1 R413 2
0_0402_5%
NOSROM@
@
Q21
AO3413_SOT23
+5VALW
D
3 1 1 R419 2
0_0402_5%
.1U_0402_16V7K
C243
1 @ @
Intel recommand VCCVRM==>1.5V FOR MOBILE @
G
2
R418
stuff R265 and unstuff R266 VCCVRM==>1.8V FOR DESKTOP 100K_0402_5%
2
12/20 place @ first
2
VCCVRM = 160mA detal waiting for newest spec
@ Q22
1
R40 D
1 2 PCH_PWR_EN_R 2
<42> PCH_PWR_EN
.1U_0402_16V7K
0_0402_5% G
.1U_0402_16V7K
C237
C252
1 2N7002H_SOT23-3 S 1 @
3
@
@
A A
2 2

PCH (7/9) PWR
5 4 3 2 1
5 4 3 2 1
Have internal VRM

+3VS +V1.05S_VCCP R268 @
0_0603_5%
2 1 +VCCACLK
Near T38
+3V_PCH +3VALW @ +3V_PCH
Near T16 POWER +V1.05S_VCCP PJ1
1 U4J
1U_0402_6.3V6K
C232
2 1
1 AD49 N26
VCCACLK VCCIO[29] JUMP_43X118
2 1
C234 P26
0.1U_0402_10V7K T16 VCCIO[30] C233
D 2 VCCDSW3_3 3mA P28 1U_0402_6.3V6K D
@ VCCIO[31] 2
2 1 +PCH_VCCDSW V12 T27
DCPSUSBYP VCCIO[32]
C235 T29
0.1U_0402_10V7K T38 VCCIO[33] +3V_PCH
烉On-Die PLL voltage regulator enable

+3VS VCC3_3[5]
On-Die PLL Voltage Regulator
H T23
+VCCAPLL_CPY_PCH BH23 119mA VCCSUS3_3[7]
T31 PAD VCCAPLLDMI2
0.1U_0402_10V7K
C236
VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 T24 +3V_PCH
VCCSUS3_3[8] 1 +5VALW +3V_PCH
AL29
,VCCAPLLSATA +V1.05S_VCCP VCCIO[14] V23
VCCSUS3_3[9]
USB
1
2
+VCCSUS1 AL24 V24 2
DCPSUS[3] VCCSUS3_3[10] C238 R275 D1
1
P24 0.1U_0402_10V7K 100_0402_1% CH751H-40PT_SOD323-2
@ C239 VCCSUS3_3[6] 2 +V1.05S_VCCP
1U_0402_6.3V6K AA19
1
2 VCCASW[1] T26 +PCH_V5REF_SUS
+V1.05S_VCCP AA21 VCCIO[34]
Near AA19 VCCASW[2]
1010mA 1
AA24 M26 +PCH_V5REF_SUS C240
VCCASW[3] 1mA V5REF_SUS 0.1U_0603_25V7K
1 1 2
22U_0805_6.3V6M
C241
22U_0805_6.3V6M
C242
AA26
Clock and Miscellaneous

VCCASW[4] AN23 +VCCA_USBSUS
AA27 DCPSUS[4] T33 PAD
2 2 VCCASW[5] AN24
VCCSUS3_3[1] +3V_PCH
AA29
VCCASW[6]
AA31 +5VS +3VS
VCCASW[7]
AC26 P34 +PCH_V5REF_RUN +3V_PCH
VCCASW[8] 1mA V5REF
2
C C
1 1 1
1U_0402_6.3V6K
C244
1U_0402_6.3V6K
C245
1U_0402_6.3V6K
C246
AC27 R279 D2
VCCASW[9] N20 CH751H-40PT_SOD323-2
VCCSUS3_3[2] 1 100_0402_1%
+V1.05S_VCCP AC29
PCI/GPIO/LPC
2 2 2 VCCASW[10] N22 C247
1
AC31 VCCSUS3_3[3] 1U_0402_6.3V +PCH_V5REF_RUN
VCCASW[11] P20 2 +3VS
VCCSUS3_3[4] 1
AD29
VCCASW[12] P22 C248
AD31 VCCSUS3_3[5] 1U_0603_10V6K
VCCASW[13] 1 2
C249
W21 AA16 0.1U_0402_10V7K
VCCASW[14] VCC3_3[1]
L6 W23 W16 2 +3VS
1 2 +1.05VS_VCCA_A_DPL VCCASW[15] VCC3_3[8]
10UH_LB2012T100MR_20% W24 T34
VCCASW[16] VCC3_3[4]
1 1
220U_B2_2.5VM_R35
C250
1U_0402_6.3V6K
C251
1U_0402_6.3V6K
C253
1 1 W26
+ VCCASW[17] C254
@ W29 +3VS 0.1U_0402_10V7K
VCCASW[18] 2
2 2 2 W31 AJ2
VCCASW[19] VCC3_3[2] +V1.05S_VCCP
1
W33
VCCASW[20] AF13
VCCIO[5] C255
2 0.1U_0402_10V7K 1
+VCCRTCEXT N16
+1.5VS DCPRTC AH13 C257
1 VCCIO[12]
C258 1U_0402_6.3V6K
0.1U_0402_10V7K Y49 AH14 2
VCCVRM[4] VCCIO[13]
2
B AF14 B
Near AF17 +1.05VS_VCCA_A_DPL BD47 VCCIO[6]
+V1.05S_VCCP VCCADPLLA 80mA
SATA AK1 +VCCSATAPLL
烉On-Die PLL voltage regulator enable

+1.05VS_VCCA_A_DPL BF47 VCCAPLLSATA T34 PAD
1 VCCADPLLB 80mA
+1.5VS On-Die PLL Voltage Regulator
C256 H
1U_0402_6.3V6K AF11
AF17 VCCVRM[1] +V1.05S_VCCP
2 VCCIO[7] VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2
AF33
AF34 VCCDIFFCLKN[1]
55mA AC16 ,VCCAPLLSATA
Near AF33 AG34 VCCDIFFCLKN[2] VCCIO[2]
+V1.05S_VCCP VCCDIFFCLKN[3]
1 AC17 1
VCCIO[3] C261
C259 AG33 AD17 1U_0402_6.3V6K
1U_0402_6.3V6K VCCSSC 95mA VCCIO[4]
2 2
+VCCSST V16 +V1.05S_VCCP
DCPSST
Near AG33 1
+V1.05S_VCCP C263
1 0.1U_0402_10V7K +1.05VM_VCCSUS T17 T21
T32 PAD V19 DCPSUS[1] VCCASW[22]
C262 2 DCPSUS[2]
MISC
1U_0402_6.3V6K +V1.05S_VCCP V21

2 VCCASW[23]
CPU
Near BJ8 BJ8

V_PROC_IO 1mA T19
VCCASW[21]
1 1
4.7U_0603_6.3V6K
C265
0.1U_0402_10V7K
C266
+RTCVCC +3V_PCH
@ A22 P32
RTC
2 2 @ VCCRTC 10mA VCCSUSHDA

HDA
0.1U_0402_10V7K
C269
1 1
PANTHER-POINT_FCBGA989 C271
A HM76@ 0.1U_0402_16V4Z A
2 2

PCH (8/9) PWR
5 4 3 2 1
5 4 3 2 1
U4I
AY4 H46
AY42 VSS[159] VSS[259] K18
AY46 VSS[160] VSS[260] K26
AY8 VSS[161] VSS[261] K39
B11 VSS[162] VSS[262] K46
D U4H B15 VSS[163] VSS[263] K7 D
H5 B19 VSS[164] VSS[264] L18
VSS[0] B23 VSS[165] VSS[265] L2
AA17 AK38 B27 VSS[166] VSS[266] L20
AA2 VSS[1] VSS[80] AK4 B31 VSS[167] VSS[267] L26
AB11 VSS[5] VSS[84] AL16 F45 VSS[171] VSS[271] M12
AB14 VSS[6] VSS[85] AL17 BB12 VSS[172] VSS[272] P16
AB39 VSS[7] VSS[86] AL19 BB16 VSS[173] VSS[273] M18
AC19 VSS[12] VSS[91] AL27 BB30 VSS[178] VSS[278] M34
AC33 VSS[16] VSS[95] AL48 BC14 VSS[182] VSS[282] M46
AC34 VSS[17] VSS[96] AM11 BC18 VSS[183] VSS[283] M8
AC48 VSS[18] VSS[97] AM14 BC2 VSS[184] VSS[284] N18
AD10 VSS[19] VSS[98] AM36 BC22 VSS[185] VSS[285] P30
AD11 VSS[20] VSS[99] AM39 BC26 VSS[186] VSS[286] N47
AD19 VSS[23] VSS[102] AM46 BC36 VSS[189] VSS[289] T33
AD26 VSS[25] VSS[104] AN2 BC42 VSS[191] VSS[291] P43
AD27 VSS[26] VSS[105] AN29 BC48 VSS[192] VSS[292] P47
AD33 VSS[27] VSS[106] AN3 BD46 VSS[193] VSS[293] P7
AD34 VSS[28] VSS[107] AN31 BD5 VSS[194] VSS[294] R2
C AD36 VSS[29] VSS[108] AP12 BE22 VSS[195] VSS[295] R48 C
AD37 VSS[30] VSS[109] AP19 BE26 VSS[196] VSS[296] T12
AD38 VSS[31] VSS[110] AP28 BE40 VSS[197] VSS[297] T31
AD39 VSS[32] VSS[111] AP30 BF10 VSS[198] VSS[298] T37
AD40 VSS[34] VSS[113] AP38 BF16 VSS[200] VSS[300] W34
AD46 VSS[38] VSS[117] AP8 BF26 VSS[204] VSS[304] V11
AD8 VSS[39] VSS[118] AR2 BF28 VSS[205] VSS[305] V17
AE2 VSS[40] VSS[119] AR48 BD3 VSS[206] VSS[306] V26
AE3 VSS[41] VSS[120] AT11 BF30 VSS[207] VSS[307] V27
AF10 VSS[42] VSS[121] AT13 BF38 VSS[208] VSS[308] V29
AF12 VSS[43] VSS[122] AT18 BF40 VSS[209] VSS[309] V31
AD14 VSS[44] VSS[123] AT22 BF8 VSS[210] VSS[310] V36
AD16 VSS[45] VSS[124] AT26 BG17 VSS[211] VSS[311] V39
AF16 VSS[46] VSS[125] AT28 BG21 VSS[212] VSS[312] V43
AF19 VSS[47] VSS[126] AT30 BG33 VSS[213] VSS[313] V7
AF24 VSS[48] VSS[127] AT32 BG44 VSS[214] VSS[314] W17
AF26 VSS[49] VSS[128] AT34 BG8 VSS[215] VSS[315] W19
AF27 VSS[50] VSS[129] AT39 BH11 VSS[216] VSS[316] W2
AF38 VSS[53] VSS[132] AT7 BH19 VSS[219] VSS[319] Y12
AF4 VSS[54] VSS[133] AU24 H10 VSS[220] VSS[320] Y38
AF42 VSS[55] VSS[134] AU30 BH27 VSS[221] VSS[321] Y4
AF46 VSS[56] VSS[135] AV16 BH31 VSS[222] VSS[322] Y42
AF8 VSS[59] VSS[138] AV30 BH39 VSS[225] VSS[325] BG29
AG19 VSS[60] VSS[139] AV38 BH43 VSS[226] VSS[328] N24
B AG2 VSS[61] VSS[140] AV4 BH7 VSS[227] VSS[329] AJ3 B
AG31 VSS[62] VSS[141] AV43 D3 VSS[228] VSS[330] AD47
AG48 VSS[63] VSS[142] AV8 D12 VSS[229] VSS[331] B43
AH11 VSS[64] VSS[143] AW14 D16 VSS[230] VSS[333] BE10
AH3 VSS[65] VSS[144] AW18 D18 VSS[231] VSS[334] BG41
AH36 VSS[66] VSS[145] AW2 D22 VSS[232] VSS[335] G14
AH39 VSS[67] VSS[146] AW22 D24 VSS[233] VSS[337] H16
AH40 VSS[68] VSS[147] AW26 D26 VSS[234] VSS[338] T36
AH7 VSS[71] VSS[150] AW34 D34 VSS[237] VSS[343] C22
AJ19 VSS[72] VSS[151] AW36 D38 VSS[238] VSS[344] AP13
AJ21 VSS[73] VSS[152] AW40 D42 VSS[239] VSS[345] M14
AJ24 VSS[74] VSS[153] AW48 D8 VSS[240] VSS[346] AP3
AJ33 VSS[75] VSS[154] AV11 E18 VSS[241] VSS[347] AP1
AJ34 VSS[76] VSS[155] AY12 E26 VSS[242] VSS[348] BE16
AK12 VSS[77] VSS[156] AY22 G18 VSS[243] VSS[349] BC16
AK3 VSS[78] VSS[157] AY28 G20 VSS[244] VSS[350] BG28
VSS[79] VSS[158] G26 VSS[245] VSS[351] BJ28
PANTHER-POINT_FCBGA989 G28 VSS[246] VSS[352]
G36 VSS[247]
G48 VSS[248]
HM76@ VSS[249]
H12
H18 VSS[250]
H22 VSS[251]
H24 VSS[252]
H26 VSS[253]
H30 VSS[254]
H32 VSS[255]
H34 VSS[256]
F3 VSS[257]
VSS[258]
A A
HM76@

PCH (9/9) VSS
5 4 3 2 1
5 4 3 2 1
DGPU_PWR_EN
+3VS
QV9 GC6@
2
G
10/29 Add the RV54 pull down 10k to GND by NV. 2N7002_SOT23
U65A GE@ 11/1 Modify the signal name from GC6_FB_CLAMP to GC6_FB_CLAMP_R
3 1 1 GC6@ 2
PCIE_CTX_GRX_N[0..15] PCIE_CTX_GRX_P0 AN12 Part 1 of 7 RV53 10K_0402_5%
D
<5> PCIE_CTX_GRX_N[0..15] PEX_RX0
PCIE_CTX_GRX_N0 AM12 P6 GC6_FB_CLAMP_R 2 GC6@ 1 GC6@
PCIE_CTX_GRX_P[0..15] PCIE_CTX_GRX_P1 AN14 PEX_RX0_N GPIO0 M3 RV54 10K_0402_5% 1 2
<5> PCIE_CTX_GRX_P[0..15] PEX_RX1 GPIO1 0103 Add CV136 0.1uf cap on QV8.2
PCIE_CTX_GRX_N1 AM14 L6 CV136 0.1U_0402_10V7K
PCIE_CRX_GTX_N[0..15] PCIE_CTX_GRX_P2 AP14 PEX_RX1_N GPIO2 P5 for N14P-GS/N14P-GV2 GC6.
<5> PCIE_CRX_GTX_N[0..15] PEX_RX2 GPIO3
2
PCIE_CTX_GRX_N2 AP15 P7 QV8
G
PCIE_CRX_GTX_P[0..15] PCIE_CTX_GRX_P3 AN15 PEX_RX2_N GPIO4 L7
01/22 (GPIO5) Delete Reserve for GPU_STDBY_EN
AO3413_SOT23 GC6@
From EC
<5> PCIE_CRX_GTX_P[0..15] PEX_RX3 GPIO5 10/31 Add the RV5 connect to EC side.
D PCIE_CTX_GRX_N3 AM15 M7 GC6_FB_CLAMP_TGL_REQ#_R 03/12 Change the RV5 from 0 ohm to short pad. GC6_FB_CLAMP_R 1 3 GC6_FB_CLAMP D
PEX_RX3_N GPIO6 GC6_FB_CLAMP <27,42>
PCIE_CTX_GRX_P4 AN17 N8
S
PCIE_CTX_GRX_N4 AM17 PEX_RX4 GPIO7 M1 OVERT# 1 @ 2
01/16 Change U65 from SA00006B500 to SA00006B510 for N14P-GV2-B-A1. PEX_RX4_N GPIO8 OVERT#_R <42> 10/29 Add the QV8 for GC6 circuits.
PCIE_CTX_GRX_P5 AP17 M2 GPU_HOT# RV5 0_0402_5% 1 @ 2
PEX_RX5 GPIO9 GPU_HOT# <54>
03/06 Change U65 from SA00006B510 to SA00006B520 for N14P-GV2-B-A2(R3 part). PCIE_CTX_GRX_N5 AP18 L1 RV132 0_0402_5%
PCIE_CTX_GRX_P6 AN18 PEX_RX5_N GPIO10 M5
Change U65 from SA000068A00 to SA000068A20 for N14M-GE-B-A2(R3 part).
GPIO
PEX_RX6 GPIO11 NVVDD_PWM_VID <54>
PCIE_CTX_GRX_N6 AM18 N3 VGA_AC_DET_R
PCIE_CTX_GRX_P7 AN20 PEX_RX6_N GPIO12 M4 Reserve
PEX_RX7 GPIO13 NVVDD_PSI <54> +3VS
0103 Change QV7.2 control from
U65 U65 PCIE_CTX_GRX_N7 AM20 N4 PLT_RST_VGA#
PCIE_CTX_GRX_P8 AP20 PEX_RX7_N GPIO14 P2 10/30 N14x not support
For GC6 DGPU_PWR_EN to PLT_RST_VGA#
PEX_RX8 GPIO15
2
PCIE_CTX_GRX_N8 AP21 R8 for N14P-GS/N14P-GV2 GC6.
PCIE_CTX_GRX_P9 AN21 PEX_RX8_N GPIO16 M6 RV52
PCIE_CTX_GRX_N9 AM21 PEX_RX9 GPIO17 R1 QV7 GC6@
PEX_RX9_N GPIO18 10K_0402_5%
2
G
PCIE_CTX_GRX_P10 AN23 P3 2N7002_SOT23 GC6@ To EC
PCIE_CTX_GRX_N10 AM23 PEX_RX10 GPIO19 P4
N14P-GV2-B-A1 BGA 908P N14P-GS-A2 BGA 908P
1
SA00006B520 SA000065F00 PCIE_CTX_GRX_P11 AP23 PEX_RX10_N GPIO20 P1 GC6_FB_CLAMP_TGL_REQ#_R 3 1 GC6_FB_CLAMP_TGL_REQ#
PEX_RX11 GPIO21 GC6_FB_CLAMP_TGL_REQ# <42>
GV2@ GS@ PCIE_CTX_GRX_N11 AP24
D
PCIE_CTX_GRX_P12 AN24 PEX_RX11_N
PCIE_CTX_GRX_N12 AM24 PEX_RX12 1 @ 2
PCIE_CTX_GRX_P13 AN26 PEX_RX12_N RV133 0_0402_5%
PCIE_CTX_GRX_N13 AM26 PEX_RX13
PCIE_CTX_GRX_P14 AP26 PEX_RX13_N
PCIE_CTX_GRX_N14 AP27 PEX_RX14
Non-support PCIE port8-15:N14M-GM and N14P-GV2 PCIE_CTX_GRX_P15 AN27 PEX_RX14_N AK9 +3VS_VGA
PCIE_CTX_GRX_N15 AM27 PEX_RX15 DACA_RED AL10
CV6 CV7 CV8 CV9 Support PCIE port8-15:N14P-GS PEX_RX15_N DACA_GREEN AL9
DACA_BLUE 1 GC6@ 2
GC6_FB_CLAMP_TGL_REQ#_R
DACs
PCIE_CRX_GTX_P0 CV6 1 2 GVGS@ 0.22U_0402_10V6K PCIE_CRX_C_GTX_P0 AK14 RV51 10K_0402_5% 10/23 Modify the voltage from +VDD33MISC
PCIE_CRX_GTX_N0 CV7 1 2 GVGS@ 0.22U_0402_10V6K PCIE_CRX_C_GTX_N0 AJ14 PEX_TX0 AM9 +3VS +3VS_VGA
PCIE_CRX_GTX_P1 CV8 1 2 GVGS@ 0.22U_0402_10V6K PCIE_CRX_C_GTX_P1 AH14 PEX_TX0_N DACA_HSYNC AN9 to +3VS_VGA by nvdia suggest.
PEX_TX1 DACA_VSYNC 10/23 Modify the voltage from +VDD33MISC Reserve for
PCIE_CRX_GTX_N1 CV9 1 2 GVGS@ 0.22U_0402_10V6K PCIE_CRX_C_GTX_N1 AG14 +3VS_VGA
/+3VS to +3VS_VGA by nvdia suggest. leakage issue
2
PCIE_CRX_GTX_P2 CV10 1 2 GVGS@ 0.22U_0402_10V6K PCIE_CRX_C_GTX_P2 AK15 PEX_TX1_N 10K_0402_5% N14@
0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K PEX_TX2
C SE102104K00 SE102104K00 SE102104K00 SE102104K00 PCIE_CRX_GTX_N2 CV11 1 2 GVGS@ 0.22U_0402_10V6K PCIE_CRX_C_GTX_N2 AJ15 AG10 +DACA_VDD 2 RV107 1 RV15 RV14 C
PEX_TX2_N DACA_VDD
PCI EXPRESS
GE@ GE@ GE@ GE@ PCIE_CRX_GTX_P3 CV12 1 2 GVGS@ 0.22U_0402_10V6K PCIE_CRX_C_GTX_P3 AL16 AP9 OVERT# 1 N14@ 2 10K_0402_5% 10K_0402_5%
PCIE_CRX_GTX_N3 CV13 1 2 GVGS@ 0.22U_0402_10V6K PCIE_CRX_C_GTX_N3 AK16 PEX_TX3 DACA_VREF AP8 @ RV28 100K_0402_5%
PEX_TX3_N DACA_RSET @
CV10 CV11 CV12 CV13 PCIE_CRX_GTX_P4 CV14 1 2 GVGS@ 0.22U_0402_10V6K PCIE_CRX_C_GTX_P4 AK17 GPU_HOT# 1 N14@ 2
1
PCIE_CRX_GTX_N4 CV15 1 2 GVGS@ 0.22U_0402_10V6K PCIE_CRX_C_GTX_N4 AJ17 PEX_TX4 RV31 100K_0402_5% N14@
PCIE_CRX_GTX_P5 CV16 1 2 GVGS@ 0.22U_0402_10V6K PCIE_CRX_C_GTX_P5 AH17 PEX_TX4_N VGA_EDID_CLK 1 N14@ 2 VGA_AC_DET_R 2 1VGA_AC_DET
PEX_TX5 VGA_AC_DET <42>
PCIE_CRX_GTX_N5 CV17 1 2 GVGS@ 0.22U_0402_10V6K PCIE_CRX_C_GTX_N5 AG17 RV3 2.2K_0402_5% RB751V_SOD323 DV4
PCIE_CRX_GTX_P6 CV18 1 2 GVGS@ 0.22U_0402_10V6K PCIE_CRX_C_GTX_P6 AK18 PEX_TX5_N VGA_EDID_DATA 1 N14@ 2
PCIE_CRX_GTX_N6 CV19 1 2 GVGS@ 0.22U_0402_10V6K PCIE_CRX_C_GTX_N6 AJ18 PEX_TX6 RV4 2.2K_0402_5%
PCIE_CRX_GTX_P7 CV20 1 2 GVGS@ 0.22U_0402_10V6K PCIE_CRX_C_GTX_P7 AL19 PEX_TX6_N VGA_CRT_DATA RP26 1 @ 2
0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K PEX_TX7
SE102104K00 SE102104K00 SE102104K00 SE102104K00 PCIE_CRX_GTX_N7 CV21 1 2 GVGS@ 0.22U_0402_10V6K PCIE_CRX_C_GTX_N7 AK19 R4 VGA_CRT_CLK 8 1 RV126 0_0402_5%
GE@ GE@ GE@ GE@ PCIE_CRX_GTX_P8 CV22 1 2 GS@ 0.22U_0402_10V6K PCIE_CRX_C_GTX_P8 AK20 PEX_TX7_N I2CA_SCL R5 VGA_CRT_DATA VGA_CRT_CLK 7 2 Row resistor
PCIE_CRX_GTX_N8 CV23 1 2 GS@ 0.22U_0402_10V6K PCIE_CRX_C_GTX_N8 AJ20 PEX_TX8 I2CA_SDA 6 3
CV14 CV15 CV16 CV17 PCIE_CRX_GTX_P9 CV24 1 2 GS@ 0.22U_0402_10V6K PCIE_CRX_C_GTX_P9 AH20 PEX_TX8_N R7 I2CB_SCL I2CB_SCL 5 4
PCIE_CRX_GTX_N9 CV25 1 2 GS@ 0.22U_0402_10V6K PCIE_CRX_C_GTX_N9 AG20 PEX_TX9 I2CB_SCL R6 I2CB_SDA
PCIE_CRX_GTX_P10 CV26 1 2 GS@ 0.22U_0402_10V6K PCIE_CRX_C_GTX_P10 AK21 PEX_TX9_N I2CB_SDA I2CB_SDA 2.2K_0804_8P4R_5%
I2C
PCIE_CRX_GTX_N10 CV27 1 2 GS@ 0.22U_0402_10V6K PCIE_CRX_C_GTX_N10 AJ21 PEX_TX10 R2 VGA_EDID_CLK GVGS@
PCIE_CRX_GTX_P11 CV28 1 2 GS@ 0.22U_0402_10V6K PCIE_CRX_C_GTX_P11 AL22 PEX_TX10_N I2CC_SCL R3 VGA_EDID_DATA NVVDD_PSI 1 2
PCIE_CRX_GTX_N11 CV29 1 2 GS@ 0.22U_0402_10V6K PCIE_CRX_C_GTX_N11 AK22 PEX_TX11 I2CC_SDA RV2 N14@ 10K_0402_5%
PCIE_CRX_GTX_P12 CV30 1 2 GS@ 0.22U_0402_10V6K PCIE_CRX_C_GTX_P12 AK23 PEX_TX11_N T4 VGA_SMB_CK2
0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K PEX_TX12 I2CS_SCL
SE102104K00 SE102104K00 SE102104K00 SE102104K00 PCIE_CRX_GTX_N12 CV31 1 2 GS@ 0.22U_0402_10V6K PCIE_CRX_C_GTX_N12 AJ23 T3 VGA_SMB_DA2 +1.05VS_VGA
GE@ GE@ GE@ GE@ PCIE_CRX_GTX_P13 CV32 1 2 GS@ 0.22U_0402_10V6K PCIE_CRX_C_GTX_P13 AH23 PEX_TX12_N I2CS_SDA
PEX_TX13 30 ohms @100MHz 0402 (ESR=0.05) Bead
PCIE_CRX_GTX_N13 CV33 1 2 GS@ 0.22U_0402_10V6K PCIE_CRX_C_GTX_N13 AG23
CV18 CV19 CV20 CV21 PCIE_CRX_GTX_P14 CV34 1 2 GS@ 0.22U_0402_10V6K PCIE_CRX_C_GTX_P14 AK24 PEX_TX13_N
PCIE_CRX_GTX_N14 CV35 1 2 GS@ 0.22U_0402_10V6K PCIE_CRX_C_GTX_N14 AJ24 PEX_TX14 Width: 12~16 mils Under GPU
PCIE_CRX_GTX_P15 CV36 1 2 GS@ 0.22U_0402_10V6K PCIE_CRX_C_GTX_P15 AL25 PEX_TX14_N LV7
PCIE_CRX_GTX_N15 CV41 1 2 GS@ 0.22U_0402_10V6K PCIE_CRX_C_GTX_N15 AK25 PEX_TX15 78mA +PLLVDD 1 2
PEX_TX15_N SBY100505T-300Y-N 0402
22U_0805_6.3V6M
0.1U_0402_10V7K
AD8
CV131
1 1 N14@ 01/28 Change the LV7 from SM01000JE00 to SM01000JN00.
AJ11 PLLVDD
CV40
0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K PEX_WAKE_N 71mA
SE102104K00 SE102104K00 SE102104K00 SE102104K00 AE8
GE@ GE@ GE@ GE@ CLK_PCIE_VGA AL13 SP_PLLVDD Near GPU
B
<15> CLK_PCIE_VGA
CLK_PCIE_VGA# AK13 PEX_REFCLK AD7
41mA +SP_PLLVDD 2 N14@ 2 N14@ B
<15> CLK_PCIE_VGA# PEX_REFCLK_N VID_PLLVDD
CLK_REQ_GPU# AK12
CLK
PEX_CLKREQ_N
Differential signal 1 @ 2 PEX_TSTCLK_OUT AJ26 H3 XTALIN
+3VS_VGA +3VS_VGA RV20 200_0402_1% PEX_TSTCLK_OUT# AK26 PEX_TSTCLK_OUT XTAL_IN H2 XTAL_OUT
PEX_TSTCLK_OUT_N XTAL_OUT
2
@ PLT_RST_VGA# AJ12 J4 XTALOUT 1 2 GCLK_27MHZ

PEX_RST_N XTAL_OUTBUFF GCLK_27MHZ <44>
RV105 PEX_TERMP AP29 H1 XTALSSIN RV233 0_0402_5%
10K_0402_5% PEX_TERMP XTAL_SSIN @
1
5
RV26 RV27 11/8 Modify the BOM structure from GCLK@ to @

1
2 RV22 10K_0402_5% 10K_0402_5% for without external CLK gen.

P
<18,36,37,42> PLT_RST# B 4 2.49K_0402_1%

From PCH 1 Y N14M-GE-B-A2 FCBGA 908P N14@ N14@
<18> DGPU_HOLD_RST#
2
G
A
1
RV18
3
UV2 N14@ 100K_0402_5%

MC74VHC1G08DFT2G SC70 5P N14@
2
1 2
+3VS_VGA +3VS_VGA 10/24 NVIDIA suggest RV23 10M_0402_5% 11/30 Modify the LV1 from SM010019400 to SM010028480
Modify the voltage from +VDD33MISC/+3VS to +3VS_VGA NOGCLK@
Modify the voltage from +VDD33MISC to +3VS_VGA. 180 ohms @100MHz 0603(ESR=0.2) Bead Under GPU(below 150mils)
RV29 10K_0402_5% YV1 150mA
Modify the QV1 from N14MGE@ to always mount.
2
2 1 4 3 XTAL_OUT
<18,25,42> DGPU_PWR_EN Modify the RV130/RV137 from N14PGS@ to @. NC OSC
N14@ RV24 RV25 N14@ +SP_PLLVDD
+3VS_VGA 2.2K_0402_5% 2.2K_0402_5% XTALIN 1 2 1 2
22U_0805_6.3V6M
0.1U_0402_10V7K
0.1U_0402_10V7K
4.7U_0402_6.3V6M
OSC NC +1.05VS_VGA
CV4
CV5
GE@ GE@
CV112
CV113
1 1 1 1 1
5
N14@ 1 27MHZ 10PF +-20PPM X3G027000DA1H 1 LV1 BLM18PG181SN1D_2P

1
CV42 @ QV1B NOGCLK@ CV38

2
0.1U_0402_10V7K VGA_SMB_CK2 4 3 CV37 5P_0402_50V8C

A 2 EC_SMB_CK2 <15,39,42> 2 2 2 2 A
RV30 5P_0402_50V8C NOGCLK@
N14@ 10K_0402_5% 2N7002DW-T/R7_SOT363-6 NOGCLK@ 2 2 Near GPU
2
G
1 2
1
<15> CLK_REQ_VGA# 1 3 CLK_REQ_GPU# RV130 @ 0_0402_5% 11/30 Modify the YV1 from SM010019400 to SM010028480.( Use SM010019400 footprint) N14@ N14@ N14@ N14@
D
Modify CV37/CV38 from 15pF to 5pF.

2
N14@ N14@
2
QV2 QV1A
2N7002H 1N_SOT23-3 @ RV32
10K_0402_5%
VGA_SMB_DA2 1 6
EC_SMB_DA2 <15,39,42>
2N7002DW-T/R7_SOT363-6
1 2 N14X-PCIE/DAC/GPIO
1
RV110 @ 0_0402_5% 1 2 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
RV137 @ 0_0402_5% 0.3
VILG1/G2 MB LA-9901P Schematic
5 4 3 2 1
5 4 3 2 1
U65D
Part 4 of 7
AM6
AN6 IFPA_TXC P8
AP3 IFPA_TXC_N NC AC6
AN3 IFPA_TXD0 NC AJ28
D AN5 IFPA_TXD0_N NC AJ4 D
AM5 IFPA_TXD1 NC AJ5
AL6 IFPA_TXD1_N NC AL11
AK6 IFPA_TXD2 NC C15
IFPA_TXD2_N NC
NC
AJ6 D19
AH6 IFPA_TXD3 NC D20
IFPA_TXD3_N NC D23
NC D26
AJ9 NC H31
AH9 IFPB_TXC NC T8
AP6 IFPB_TXC_N NC V32
AP5 IFPB_TXD4 NC
AM7 IFPB_TXD4_N
AL7 IFPB_TXD5
AN8 IFPB_TXD5_N
AM8 IFPB_TXD6
AK8 IFPB_TXD6_N
AL8 IFPB_TXD7
IFPB_TXD7_N L4 VCCSENSE_VGA
VDD_SENSE VCCSENSE_VGA <54>
AK1
AJ1 IFPC_L0
AJ3 IFPC_L0_N L5 VSSSENSE_VGA
IFPC_L1 GND_SENSE VSSSENSE_VGA <54>
AJ2
AH3 IFPC_L1_N
IFPC_L2 trace width: 16mils
AH4
AG5 IFPC_L2_N differential voltage sensing.
AG4 IFPC_L3
IFPC_L3_N
differential signal routing.
TEST
AM1 AK11 TESTMODE
AM2 IFPD_L0 TESTMODE
C AM3 IFPD_L0_N AM10 JTAG_TCK PAD TV1 C
IFPD_L1 JTAG_TCK
1
AM4 AM11 JTAG_TDI PAD TV2
AL3 IFPD_L1_N JTAG_TDI AP12 JTAG_TDO PAD TV3 N14@
AL4 IFPD_L2 JTAG_TDO AP11 JTAG_TMS PAD TV4 10K_0402_5%
AK4 IFPD_L2_N JTAG_TMS AN11 1 N14@ 2 RV33
AK5 IFPD_L3 JTAG_TRST_N RV34 10K_0402_5%
2
IFPD_L3_N
LVDS/TMDS
AD2
AD3 IFPE_L0
AD1 IFPE_L0_N
AC1 IFPE_L1 SERIAL
AC2 IFPE_L1_N H6 ROM_CS PAD TV5
AC3 IFPE_L2 ROM_CS_N H4 ROM_SCLK
IFPE_L2_N ROM_SCLK ROM_SCLK <32>
AC4 H5 ROM_SI
IFPE_L3 ROM_SI ROM_SI <32>
AC5 H7 ROM_SO
IFPE_L3_N ROM_SO ROM_SO <32>
AE3
AE4 IFPF_L0
AF4 IFPF_L0_N
AF5 IFPF_L1
AD4 IFPF_L1_N GENERAL RV35 10K_0402_5%
AD5 IFPF_L2 L2 2 N14@ 1
AG1 IFPF_L2_N BUFRST_N
AF1 IFPF_L3 L3
IFPF_L3_N CEC GVGS@
J1 1 2
MULTI_STRAP_REF0_GND RV38 40.2K_0402_1%
AG3
AG2 IFPC_AUX_I2CW_SCL
IFPC_AUX_I2CW_SDA_N J2 STRAP0
B STRAP0 STRAP0 <32> B
J7 STRAP1
STRAP1 STRAP1 <32>
AK3 J6 STRAP2
IFPD_AUX_I2CX_SCL STRAP2 STRAP2 <32>
AK2 J5 STRAP3
IFPD_AUX_I2CX_SDA_N STRAP3 STRAP3 <32>
J3 STRAP4
STRAP4 STRAP4 <32>
AB3
AB4 IFPE_AUX_I2CY_SCL
IFPE_AUX_I2CY_SDA_N K3
THERMDP K4
AF3 THERMDN
AF2 IFPF_AUX_I2CZ_SCL
IFPF_AUX_I2CZ_SDA_N
N14M-GE-B-A2 FCBGA 908P
GE@
A A

N14X-LVDS/HDMI/DP/THM
0.3
5 4 3 2 1
5 4 3 2 1
+1.5VS_VGA U65E +1.05VS_VGA
3300mA Under GPU(below 150mils) Near GPU

Near GPU Part 5 of 7
3.5A
AA27 AG19
FBVDDQ_0 PEX_IOVDD_0
22U_0805_6.3V6M
22U_0805_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
AA30 AG21
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
FBVDDQ_1 PEX_IOVDD_1
GS@ CV58
GS@ CV59
N14@ CV271
N14@ CV272
N14@ CV43
N14@ CV44
N14@ CV45
N14@ CV46
N14@ CV47
N14@ CV48
N14@ CV49
N14@ CV50
N14@ CV51
N14@ CV52
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
0128: Change the BOM structure of CV58/CV59/CV278/CV282 1 1 2 2 AB27 AG22 1 1 1 1 1 1 2 2 2 2
AB33 FBVDDQ_2 PEX_IOVDD_2 AG24
from N14@ to GS@. AC27 FBVDDQ_3 PEX_IOVDD_3 AH21
D AD27 FBVDDQ_4 PEX_IOVDD_4 AH25 D
2 2 1 1 AE27 FBVDDQ_5 PEX_IOVDD_5 2 2 2 2 2 2 1 1 1 1
AF27 FBVDDQ_6
+1.5VS_VGA AG27 FBVDDQ_7 AG13
B13 FBVDDQ_8 PEX_IOVDDQ_0 AG15
4.7uF X7R 0402 * 2 FBVDDQ_9 PEX_IOVDDQ_1 +1.05VS_VGA
Close to GPU Ball B16 AG16
FBVDDQ_10 PEX_IOVDDQ_2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
B19 AG18
N14@ CV54
N14@ CV53
N14@ CV56
N14@ CV55
1uF X7R 0402 * 2 0.1uF X7R 0402 * 8 E13 AG25 1 1 1 1
E16 FBVDDQ_12 PEX_IOVDDQ_4 AH15
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
E19 AH18
1U_0603_6.3V6M
1U_0603_6.3V6M
1U_0603_6.3V6M
1U_0603_6.3V6M
N14@ CV267
N14@ CV268
N14@ CV273
N14@ CV274
N14@ CV277
GS@ CV278
GS@ CV282
N14@ CV281
N14@ CV279
N14@ CV280
N14@ CV292
N14@ CV287
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 H10 AH26
H11 FBVDDQ_15 PEX_IOVDDQ_7 AH27 2 2 2 2 +3VS_VGA
H12 FBVDDQ_16 PEX_IOVDDQ_8 AJ27 @
H13 FBVDDQ_17 PEX_IOVDDQ_9 AK27 RV140
2 2 2 2 2 2 2 2 2 2 2 2 H14 FBVDDQ_18 PEX_IOVDDQ_10 AL27 +VDD33MISC 2 1
POWER
H15 FBVDDQ_19 PEX_IOVDDQ_11 AM28
H16 FBVDDQ_20 PEX_IOVDDQ_12 AN28 0_0603_5%
FBVDDQ_21 PEX_IOVDDQ_13 Place near balls
H18 10/24 Delete QV8/CV72/CV105 and mount RV140.
H19 FBVDDQ_22 +3VS_VGA
FBVDDQ_23 RV143
@ 11/29 Modify the RV140 from 0ohm to short pad.
H20
FBVDDQ_24
0.1U_0402_10V7K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
H21 AH12 +PEX_PLLHVDD 2 1
FBVDDQ_25 PEX_PLL_HVDD
N14@ CV70
N14@ CV74
N14@ CV73
H22 1 1 1
H23 FBVDDQ_26 0_0603_5%
rise 1.5v system source voltage to 1.55-1.57V H24 FBVDDQ_27
FBVDDQ_28
210mA
H8 AG12
H9 FBVDDQ_29 PEX_SVDD_3V3 2 2 2
L27 FBVDDQ_30
M27 FBVDDQ_31
N27 FBVDDQ_32 AG26 +PEX_PLLVDD
FBVDDQ_33 PEX_PLLVDD
11/29 Modify the RV138 from 0ohm to short pad.
P27
R27 FBVDDQ_34 +VDD33MISC
T27 FBVDDQ_35
C T30 FBVDDQ_36 J8 +3VS_VGA C
T33 FBVDDQ_37 VDD33_0 K8
FBVDDQ_38 VDD33_1 Place near balls Place near GPU
V27 L8
W27 FBVDDQ_39 VDD33_2 M8
FBVDDQ_40 VDD33_3
0.1U_0402_10V7K
0.1U_0402_10V7K
W30
4.7U_0603_6.3V6K
FBVDDQ_41
N14@ CV109
N14@ CV111
N14@ CV293
N14@ CV75
+1.5VS_VGA
1U_0402_6.3V6K
W33
Y27 FBVDDQ_42
FBVDDQ_43
1 1 1 1
For R-short
1 @ RV48 2 10K_0402_5%
AH8 +IFPAB_PLLVDD LV2 GVGS@
IFPAB_PLLVDD AJ8 1 @ RV40 2 1K_0402_1%
2 RV141 @1 FB_VDDQ_SENSE IFPAB_RSET 2 2 2 2
10_0402_5% AG8 +IFPAB_IOVDD 1 RV65 2 10K_0402_5%
@ IFPA_IOVDD AG9 @
2 RV142 1 FB_VSS_SENSE F1 IFPB_IOVDD
10_0402_5% FB_VDDQ_SENSE
0_0603_5%
AF7 +IFPC_PLLVDD
+1.5VS_VGA F2 IFPC_PLLVDD AF8 RV43 2 @ 1 1K_0402_1%
FB_GND_SENSE IFPC_RSET
AF6 +IFPC_IOVDD 120 ohms @100MHz 0603 (ESR=0.18) Bead 150mA +1.05VS_VGA
1 2 J27 IFPC_IOVDD LV2
RV6 N14@ 40.2_0402_1% FB_CAL_PD_VDDQ +PEX_PLLVDD 1 2
CALIBRATION PIN DDR3
1U_0603_10V6K
0.1U_0402_10V7K
4.7U_0805_25V6-K
AG7 +IFPD_PLLVDD FBMA-L11-160808-121LMT_0603
IFPD_PLLVDD
N14@ CV65
CV3
N14@ CV66
1 2 H27 AN2 RV46 1 @ 2 1K_0402_1% 1 1 1 GE@
RV8 N14@ 42.2_0402_1% FB_CAL_PU_GND IFPD_RSET
FB_CAL_x_PD_VDDQ 40.2Ohm AG6 +IFPD_IOVDD
IFPD_IOVDD
N14@
1 2 H25
RV9 N14@ 51.1_0402_1% FB_CAL_TERM_GND @ 2 2 2
FB_CAL_x_PU_GND 42.2Ohm AB8 +IFPEF_PLLVDD
1 RV72 2 10K_0402_5%
IFPEF_PLVDD AD6 1 RV50 2 1K_0402_1%
IFPEF_RSET @
FB_CAL_xTERM_GND 51.1Ohm Close to GPU Ball AC7 Place
IFPE_IOVDD AC8 +IFPE_IOVDD1 RV73 2 10K_0402_5%
IFPF_IOVDD @ near AG26 Near GPU
B B
RP11
N14M-GE-B-A2 FCBGA
GE@ 908P 8 1 +IFPC_IOVDD +1.5V to +1.5VS_VGA
7 2 +IFPC_PLLVDD +1.5V +1.5VS_VGA
6 3 +IFPD_IOVDD
+3VS to +3VS_VGA Row 5 4 +IFPD_PLLVDD
10K_0804_8P4R_5%
+3VS +3VS_VGA
resistor @
1
CV60 AO4430: Rdson: 5.5mohm @ VGS=10V
4.7U_0603_6.3V6K UV11
@ DMN3030LSS-13_SOP8L-8
+5VALW 2 8 1
7 2
6 3 11/30 Modify the CV63 from 0.01uF to 1uF.
1
+5VALW 5
QV5 N14@ CV57 N14@
01/28 Change the RV41 from 1k to 150k.
LP2301ALT1G_SOT23 10U_0603_6.3V6M RV42 Change the CV63 to SE00000OU00.
4
1
100K_0402_5% 1 RV41 2
+VSB
S
N14@ 3 1 2 1 150K_0402_5%
2
RV242 N14@
1
N14@ D
1U_0402_16V6K
N14@ CV63
100K_0402_5% 1
@ FBVDDQ_PWR_EN# 2 QV3 N14@
G
2
RV205 N14@ QV4 1 G 2N7002_SOT23

DGPU_PWR_EN# 1 2 DTC124EKAT146_SC59-3 S
3
10K_0402_5% 2
OUT
1
D
N14@ CV241
N14@ 1
0.1U_0402_10V7K
2 Q128 N14@
<18,23,42> DGPU_PWR_EN 2
G 2N7002_SOT23 FBVDDQ_PWR_EN
A <27,52> FBVDDQ_PWR_EN IN A
S 11.27 Add the QV4 and RV42.
GND
3
2
For R-short Modify the RV41 from 200k to 1K for EVT test.
1
Modify the QV3 from SB00000QP00 to SB00000EN00.

3
RV243
100K_0402_5% Modify the UV11 from SB00000RV00 to SB548000210.
N14@
2

N14X-POWER
0.3
5 4 3 2 1
5 4 3 2 1
U65G +VGA_CORE
U65F +VGA_CORE
Part 6 of 7 Part 7 of 7 V17

A2 D2 AA12 VDD_56 V18
AA17 GND_0 GND_100 D31 AA14 VDD_0 VDD_57 V20
AA18 GND_1 GND_101 D33 AA16 VDD_1 VDD_58 V22
AA20 GND_2 GND_102 E10 AA19 VDD_2 VDD_59 W12
AA22 GND_3 GND_103 E22 AA21 VDD_3 VDD_60 W14
AB12 GND_4 GND_104 E25 AA23 VDD_4 VDD_61 W16
AB14 GND_5 GND_105 E5 AB13 VDD_5 VDD_62 W19
AB16 GND_6 GND_106 E7 AB15 VDD_6 VDD_63 W21
AB19 GND_7 GND_107 F28 AB17 VDD_7 VDD_64 W23
D AB2 GND_8 GND_108 F7 AB18 VDD_8 VDD_65 Y13 D
AB21 GND_9 GND_109 G10 AB20 VDD_9 VDD_66 Y15
A33 GND_10 GND_110 G13 AB22 VDD_10 VDD_67 Y17
AB23 GND_11 GND_111 G16 AC12 VDD_11 VDD_68 Y18
AB32 GND_14 GND_114 G22 AC19 VDD_14 VDD_71
AB5 GND_15 GND_115 G25 AC21 VDD_15
AB7 GND_16 GND_116 G28 AC23 VDD_16 U1
AC13 GND_17 GND_117 G3 M12 VDD_17 XVDD_1 U2
GND_19 GND_119 VDD_19 XVDD_3
POWER
AC17 G32 M16 U4
AA13 GND_21 GND_121 G5 M21 VDD_21 XVDD_5 U6
AC22 GND_23 GND_123 K2 N13 VDD_23 XVDD_7 U8
AE2 GND_24 GND_124 K28 N15 VDD_24 XVDD_8
AE28 GND_25 GND_125 K30 N17 VDD_25
AE30 GND_26 GND_126 K32 N18 VDD_26 V1
AE32 GND_27 GND_127 K33 N20 VDD_27 XVDD_9 V2
AE33 GND_28 GND_128 K5 N22 VDD_28 XVDD_10 V3
AE5 GND_29 GND_129 K7 P12 VDD_29 XVDD_11 V4
AE7 GND_30 GND_130 M13 P14 VDD_30 XVDD_12 V5
AH10 GND_31 GND_131 M15 P16 VDD_31 XVDD_13 V6
AA15 GND_32 GND_132 M17 P19 VDD_32 XVDD_14 V7
AH13 GND_33 GND_133 M18 P21 VDD_33 XVDD_15 V8
AH16 GND_34 GND_134 M20 P23 VDD_34 XVDD_16
AH19 GND_35 GND_135 M22 R13 VDD_35
AH2 GND_36 GND_136 N12 R15 VDD_36 W2
AH22 GND_37 GND_137 N14 R17 VDD_37 XVDD_17 W3
C AH29 GND_40 GND_140 N2 R22 VDD_40 XVDD_20 W7 C
AH30 GND_41 GND_141 N21 T12 VDD_41 XVDD_21 W8
AH32 GND_42 GND_142 N23 T14 VDD_42 XVDD_22
GND
AH33 GND_43 GND_143 N28 T16 VDD_43

AH5 GND_44 GND_144 N30 T19 VDD_44 Y1
AH7 GND_45 GND_145 N32 T21 VDD_45 XVDD_23 Y2
AJ7 GND_46 GND_146 N33 T23 VDD_46 XVDD_24 Y3
AK10 GND_47 GND_147 N5 U13 VDD_47 XVDD_25 Y4
AK7 GND_48 GND_148 N7 U15 VDD_48 XVDD_26 Y5
AL12 GND_49 GND_149 P13 U17 VDD_49 XVDD_27 Y6
AL17 GND_52 GND_152 P18 U22 VDD_52 XVDD_30
AL18 GND_53 GND_153 P20 V13 VDD_53
AL2 GND_54 GND_154 P22 V15 VDD_54 AA1
AL20 GND_55 GND_155 R12 VDD_55 XVDD_31 AA2
AL21 GND_56 GND_156 R14 XVDD_32 AA3
AL30 GND_61 GND_161 T13 XVDD_37 AA8
AL32 GND_62 GND_162 T15 XVDD_38
AL33 GND_63 GND_163 T17
AL5 GND_64 GND_164 T18
AM13 GND_65 GND_165 T2 N14M-GE-B-A2 FCBGA 908P
AM16 GND_66 GND_166 T20 GE@
AM19 GND_67 GND_167 T22
AM22 GND_68 GND_168 AG11
AM25 GND_69 GND_169 T28
AN1 GND_70 GND_170 T32
AN10 GND_71 GND_171 T5 +V1.05S_VCCP +1.05VS_VGA
B AN13 GND_72 GND_172 T7 B
AN16 GND_73 GND_173 U12
AN19 GND_74 GND_174 U14
AN22 GND_75 GND_175 U16
AN25 GND_76 GND_176 U19 N14@ QV11
AN30 GND_77 GND_177 U21 DMN3030LSS-13_SOP8L-8
AN34 GND_78 GND_178 U23 8 1
AN4 GND_79 GND_179 V12 7 2
AN7 GND_80 GND_180 V14 6 3
AP2 GND_81 GND_181 V16 +5VALW 5
AP33 GND_82 GND_182 V19
GND_83 GND_183
10U_0805_10V6K
1U_0603_10V6K
B1 V21
4
B10 GND_84 GND_184 V23 +5VALW N14@ RV237
N14@RV237
GND_85 GND_185
1
CV307
CV308
B22 W13 20K_0402_1%
B25 GND_86 GND_186 W15 RV241
GND_87 GND_187
1
B28 W17 15K_0402_5%
2
B31 GND_88 GND_188 W18 N14@ 1 2 @ @
B34 GND_89 GND_189 W20 RV44 N14@
GND_90 GND_190 1
B4 W22 100K_0402_5% CV306 N14@
B7 GND_91 GND_191 W28 1U_0603_10V6K
2
C10 GND_92 GND_192 Y12

GND_93 GND_193 1/23 Modify the CV306 from 0.1uF to 1uF.
1
C13 Y14 D 2
C19 GND_94 GND_194 Y16 DGPU_PWROK# 2 QV10 N14@
C22 GND_95 GND_195 Y19 N14@ QV6 G 2N7002_SOT23
GND_96 GND_196
1
C25 Y21 DTC124EKAT146_SC59-3 S

3
C28 GND_97 GND_197 Y23

OUT
C7 GND_98 GND_198 AH11 @

GND_99 GND_199 C16 RV235
GND_OPT W32 2 1 2
GND_OPT <19,27,54> DGPU_PWROK IN 11.29 Add the QV6 and RV44.
GND
0_0603_5% Modify the RV241 from 100k to 15K for EVT test.
A
Modify the QV10 from SB00000QP00 to SB00000EN00. A
Modify the QV11 from SB00000TO00 to SB548000210.
3
N14M-GE-B-A2 FCBGA 908P

11/29 Modify the RV235 from 0ohm to short pad.
GE@

N14X-VGA CORE, GND
0.3
5 4 3 2 1
5 4 3 2 1
FBA_D[0..63] FBA_MA[15..0] <28,29> FBC_D[0..63] FBC_MA[15..0] <30,31>

<28,29> FBA_D[0..63] <30,31> FBC_D[0..63]
FBA_BA[2..0] <28,29> FBC_BA[2..0] <30,31>
U65C
U65B
Part 3 of 7
Part 2 of 7 FBC_D0 G9 D13 FBC_CS0#_L
FBA_D0 L28 U30 FBA_CS0#_L FBC_D1 E9 FBB_D0 FBB_CMD0 E14 FBC_CS0#_L <30>
FBA_D1 M29 FBA_D0 FBA_CMD0 T31 FBA_CS0#_L <28> FBC_D2 G8 FBB_D1 FBB_CMD1 F14 FBC_ODT_L
FBA_D2 L29 FBA_D1 FBA_CMD1 U29 FBA_ODT_L FBC_D3 F9 FBB_D2 FBB_CMD2 A12 FBC_CKE_L FBC_ODT_L <30>
FBA_D3 M28 FBA_D2 FBA_CMD2 R34 FBA_CKE_L FBA_ODT_L <28> FBC_D4 F11 FBB_D3 FBB_CMD3 B12 FBC_MA14 FBC_CKE_L <30>
FBA_D4 N31 FBA_D3 FBA_CMD3 R33 FBA_MA14 FBA_CKE_L <28> FBC_D5 G11 FBB_D4 FBB_CMD4 C14 FBC_RST#
D FBA_D5 P29 FBA_D4 FBA_CMD4 U32 FBA_RST# FBC_D6 F12 FBB_D5 FBB_CMD5 B14 FBC_MA9 FBC_RST# <30,31> D
FBA_D6 R29 FBA_D5 FBA_CMD5 U33 FBA_MA9 FBA_RST# <28,29> FBC_D7 G12 FBB_D6 FBB_CMD6 G15 FBC_MA7
FBA_D7 P28 FBA_D6 FBA_CMD6 U28 FBA_MA7 FBC_D8 G6 FBB_D7 FBB_CMD7 F15 FBC_MA2
FBA_D8 J28 FBA_D7 FBA_CMD7 V28 FBA_MA2 FBC_D9 F5 FBB_D8 FBB_CMD8 E15 FBC_MA0
FBA_D9 H29 FBA_D8 FBA_CMD8 V29 FBA_MA0 FBC_D10 E6 FBB_D9 FBB_CMD9 D15 FBC_MA4
FBA_D10 J29 FBA_D9 FBA_CMD9 V30 FBA_MA4 FBC_D11 F6 FBB_D10 FBB_CMD10 A14 FBC_MA1
FBA_D11 H28 FBA_D10 FBA_CMD10 U34 FBA_MA1 FBC_D12 F4 FBB_D11 FBB_CMD11 D14 FBC_BA0
FBA_D12 G29 FBA_D11 FBA_CMD11 U31 FBA_BA0 FBC_D13 G4 FBB_D12 FBB_CMD12 A15 FBC_WE#
FBA_D13 E31 FBA_D12 FBA_CMD12 V34 FBA_WE# FBC_D14 E2 FBB_D13 FBB_CMD13 B15 FBC_MA15 FBC_WE# <30,31>
FBA_D14 E32 FBA_D13 FBA_CMD13 V33 FBA_MA15 FBA_WE# <28,29> FBC_D15 F3 FBB_D14 FBB_CMD14 C17 FBC_CAS#
FBA_D15 F30 FBA_D14 FBA_CMD14 Y32 FBA_CAS# FBC_D16 C2 FBB_D15 FBB_CMD15 D18 FBC_CS0#_H FBC_CAS# <30,31>
FBA_D16 C34 FBA_D15 FBA_CMD15 AA31 FBA_CS0#_H FBA_CAS# <28,29> FBC_D17 D4 FBB_D16 FBB_CMD16 E18 FBC_CS0#_H <31>
FBA_D17 D32 FBA_D16 FBA_CMD16 AA29 FBA_CS0#_H <29> FBC_D18 D3 FBB_D17 FBB_CMD17 F18 FBC_ODT_H
FBA_D18 B33 FBA_D17 FBA_CMD17 AA28 FBA_ODT_H FBC_D19 C1 FBB_D18 FBB_CMD18 A20 FBC_CKE_H FBC_ODT_H <31>
FBA_D19 C33 FBA_D18 FBA_CMD18 AC34 FBA_CKE_H FBA_ODT_H <29> FBC_D20 B3 FBB_D19 FBB_CMD19 B20 FBC_MA13 FBC_CKE_H <31>
FBA_D20 F33 FBA_D19 FBA_CMD19 AC33 FBA_MA13 FBA_CKE_H <29> FBC_D21 C4 FBB_D20 FBB_CMD20 C18 FBC_MA8
FBA_D21 F32 FBA_D20 FBA_CMD20 AA32 FBA_MA8 FBC_D22 B5 FBB_D21 FBB_CMD21 B18 FBC_MA6
FBA_D22 H33 FBA_D21 FBA_CMD21 AA33 FBA_MA6 FBC_D23 C5 FBB_D22 FBB_CMD22 G18 FBC_MA11
FBA_D23 H32 FBA_D22 FBA_CMD22 Y28 FBA_MA11 FBC_D24 A11 FBB_D23 FBB_CMD23 G17 FBC_MA5
MEMORY INTERFACE
FBA_D24 P34 FBA_D23 FBA_CMD23 Y29 FBA_MA5 FBC_D25 C11 FBB_D24 FBB_CMD24 F17 FBC_MA3
MEMORY INTERFACE B
FBA_D25 P32 FBA_D24 FBA_CMD24 W31 FBA_MA3 FBC_D26 D11 FBB_D25 FBB_CMD25 D16 FBC_BA2
FBA_D26 P31 FBA_D25 FBA_CMD25 Y30 FBA_BA2 FBC_D27 B11 FBB_D26 FBB_CMD26 A18 FBC_BA1
FBA_D27 P33 FBA_D26 FBA_CMD26 AA34 FBA_BA1 FBC_D28 D8 FBB_D27 FBB_CMD27 D17 FBC_MA12
FBA_D27 FBA_CMD27 FBB_D28 FBB_CMD28 DATA Bus
FBA_D28 L31 Y31 FBA_MA12 FBC_D29 A8 A17 FBC_MA10
FBA_D29 L34 FBA_D28 FBA_CMD28 Y34 FBA_MA10 FBC_D30 C8 FBB_D29 FBB_CMD29 B17 FBC_RAS#
FBA_D29 FBA_CMD29 FBB_D30 FBB_CMD30 FBC_RAS# <30,31>
Address 0..31 32..63
FBA_D30 L32 Y33 FBA_RAS# FBC_D31 B8 E17
FBA_D31 L33 FBA_D30 FBA_CMD30 V31 FBA_RAS# <28,29> FBC_D32 F24 FBB_D31 FBB_CMD31
FBA_D31 FBA_CMD31 FBB_D32 FBx_CMD0 CS0#_L
FBA_D32 AG28 FBC_D33 G23
FBA_D33 AF29 FBA_D32 FBC_D34 E24 FBB_D33
FBA_D33 FBB_D34 FBx_CMD1
FBA_D34 AG29 FBC_D35 G24 C12
FBA_D35 AF28 FBA_D34 R32 FBC_D36 D21 FBB_D35 FBB_CMD_RFU0 C20
FBA_D35 FBA_CMD_RFU0 FBB_D36 FBB_CMD_RFU1 FBx_CMD2 ODT_L
FBA_D36 AD30 AC32 FBC_D37 E21
C FBA_D37 AD29 FBA_D36 FBA_CMD_RFU1 +1.5VS_VGA FBC_D38 G21 FBB_D37 +1.5VS_VGA C
FBA_D37 FBB_D38 FBx_CMD3 CKE_L
FBA_D38 AC29 FBC_D39 F21
FBA_D39 AD28 FBA_D38 FBC_D40 G27 FBB_D39 G14 RV60 1 2 60.4_0402_1%
FBA_D39 FBB_D40 FBB_DEBUG0
@ FBx_CMD4 A14 A14
A
FBA_D40 AJ29 R28 RV58 1 @ 2 60.4_0402_1% FBC_D41 D27 G20 RV61 1 @ 2 60.4_0402_1%
FBA_D41 AK29 FBA_D40 FBA_DEBUG0 AC28 1 2 60.4_0402_1% FBC_D42 G26 FBB_D41 FBB_DEBUG1
FBA_D41 FBA_DEBUG1
RV59 @
FBB_D42 can be unstuff by default FBx_CMD5 RST RST
FBA_D42 AJ30 can be unstuff by default FBC_D43 E27
FBA_D43 AK28 FBA_D42 FBC_D44 E29 FBB_D43
FBA_D43 FBB_D44 FBx_CMD6 A9 A9
FBA_D44 AM29 FBC_D45 F29 D12 FBC_CLK0
FBA_D45 AM31 FBA_D44 R30 FBA_CLK0 FBC_D46 E30 FBB_D45 FBB_CLK0 E12 FBC_CLK0# FBC_CLK0 <30>
FBA_D45 FBA_CLK0 FBA_CLK0 <28> FBB_D46 FBB_CLK0_N FBC_CLK0# <30> FBx_CMD7 A7 A7
FBA_D46 AN29 R31 FBA_CLK0# FBC_D47 D30 E20 FBC_CLK1
FBA_D47 AM30 FBA_D46 FBA_CLK0_N AB31 FBA_CLK1 FBA_CLK0# <28> FBC_D48 A32 FBB_D47 FBB_CLK1 F20 FBC_CLK1# FBC_CLK1 <31>
FBA_D47 FBA_CLK1 FBA_CLK1 <29> FBB_D48 FBB_CLK1_N FBC_CLK1# <31> FBx_CMD8 A2 A2
FBA_D48 AN31 AC31 FBA_CLK1# FBC_D49 C31
FBA_D49 AN32 FBA_D48 FBA_CLK1_N FBA_CLK1# <29> FBC_D50 C32 FBB_D49
FBA_D49 FBB_D50 FBx_CMD9 A0 A0
FBA_D50 AP30 FBC_D51 B32
FBA_D51 AP32 FBA_D50 FBC_D52 D29 FBB_D51 F8
FBA_D51 FBB_D52 FBB_WCK01 FBx_CMD10 A4 A4
FBA_D52 AM33 K31 FBC_D53 A29 E8
FBA_D53 AL31 FBA_D52 FBA_WCK01 L30 FBC_D54 C29 FBB_D53 FBB_WCK01_N A5
FBA_D53 FBA_WCK01_N FBB_D54 FBB_WCK23 FBx_CMD11 A1 A1
FBA_D54 AK33 H34 30 ohms @100MHz 0603 (ESR=0.05) Bead FBC_D55 B29 A6
FBA_D55 AK32 FBA_D54 FBA_WCK23 J34 FBC_D56 B21 FBB_D55 FBB_WCK23_N D24
FBA_D55 FBA_WCK23_N +1.05VS_VGA +FB_PLLAVDD FBB_D56 FBB_WCK45 FBx_CMD12 BA0 BA0
FBA_D56 AD34 AG30 FBC_D57 C23 D25
FBA_D57 AD32 FBA_D56 FBA_WCK45 AG31 FBC_D58 A21 FBB_D57 FBB_WCK45_N B27
FBA_D57 FBA_WCK45_N
Place close to BGA FBB_D58 FBB_WCK67 FBx_CMD13 WE# WE#
FBA_D58 AC30 AJ34 200mA FBC_D59 C21 C27
FBA_D59 AD33 FBA_D58 FBA_WCK67 AK34 FBC_D60 B24 FBB_D59 FBB_WCK67_N
FBA_D59 FBA_WCK67_N
BLM18PG330SN1D_0603
FBB_D60 FBx_CMD14 A15 A15
FBA_D60 AF31 1 2 +FB_PLLAVDD FBC_D61 C24
FBA_D61 AG34 FBA_D60 FBC_D62 B26 FBB_D61
FBA_D61
LV3 N14@
FBB_D62 FBx_CMD15 CAS# CAS#
FBA_D62 AG32 FBC_D63 C26 D6
FBA_D63 AG33 FBA_D62 J30 FBB_D63 FBB_WCKB01 D7
FBA_D63 FBA_WCKB01 FBB_WCKB01_N FBx_CMD16 CS0#_H
J31 10/24 Using the materials temporarily for 30ohm FBC_DQM0 E11 C6
FBA_DQM0 P30 FBA_WCKB01_N J32 FBC_DQM1 E3 FBB_DQM0 FBB_WCKB23 B6
FBA_DQM0 FBA_WCKB23 FBB_DQM1 FBB_WCKB23_N FBx_CMD17
FBA_DQM1 F31 J33 FBC_DQM2 A3 F26
FBA_DQM2 F34 FBA_DQM1 FBA_WCKB23_N AH31 FBC_DQM3 C9 FBB_DQM2 FBB_WCKB45 E26
FBA_DQM2 FBA_WCKB45 FBB_DQM3 FBB_WCKB45_N FBx_CMD18 ODT_H
FBA_DQM3 M32 AJ31 10/29 Modify the RV66.2 connect to RV7.2. FBC_DQM4 F23 A26
B FBA_DQM4 AD31 FBA_DQM3 FBA_WCKB45_N AJ32 F27 FBB_DQM4 FBB_WCKB67 A27 B
FBA_DQM5 AL29 FBA_DQM4 FBA_WCKB67 AJ33
11/1 Modify the signal name from GC6_FB_CLAMP_R to GC6_FB_CLAMPFBC_DQM5
FBC_DQM6 C30 FBB_DQM5 FBB_WCKB67_N FBx_CMD19 CKE_H
FBA_DQM6 AM32 FBA_DQM5 FBA_WCKB67_N FBC_DQM7 A24 FBB_DQM6
FBA_DQM6 FBB_DQM7 FBx_CMD20 A13 A13
FBA_DQM7 AF34 RV66 2 N14@ 1 10K_0402_5%
FBA_DQM7 from EC For GC6 FBC_DQS0 D10
GC6@
FBB_DQS_WP0 FBx_CMD21 A8 A8
FBA_DQS0 M31 E1 GC6_EN 1 2 FBC_DQS1 D5
FBA_DQS1 G31 FBA_DQS_WP0 FB_CLAMP GC6_FB_CLAMP <23,42> FBC_DQS2 C3 FBB_DQS_WP1
FBA_DQS_WP1
RV7 0_0402_5%
FBB_DQS_WP2 FBx_CMD22 A6 A6
FBA_DQS2 E33 FBC_DQS3 B9
FBA_DQS_WP2 +FB_PLLAVDD FBB_DQS_WP3
For GC6 FBA_DQS3 M33 FBC_DQS4 E23 H17 FBx_CMD23 A11 A11
FBA_DQS_WP3 FBB_DQS_WP4 FBB_PLL_AVDD +FB_PLLAVDD
0.1U_0402_10V7K
FBA_DQS4 AE31 K27 CV106 1 2 0.1U_0402_10V7K FBC_DQS5 E28
FBA_DQS_WP4 FB_DLL_AVDD FBB_DQS_WP5
GS@ CV108
FBA_DQS5 AK30 N14@ FBC_DQS6 B30 1 FBx_CMD24 A5 A5
FBA_DQS6 AN33 FBA_DQS_WP5 FBC_DQS7 A23 FBB_DQS_WP6
FBA_DQS_WP6
Place close to ball FBB_DQS_WP7
DV2 FBA_DQS7 AF33 FBx_CMD25 A3 A3
GC6@ FBA_DQS_WP7 U27 FBC_DQS#0 D9
FBA_PLL_AVDD +FB_PLLAVDD FBB_DQS_RN0 2
22U_0805_6.3V6M
0.1U_0402_10V7K
DAN202UT106_SC70-3 FBA_DQS#0 M30 FBC_DQS#1 E4 FBx_CMD26 BA2 BA2

FBA_DQS_RN0 FBB_DQS_RN1
N14@ CV107
N14@ CV110
N14@ CV39
1U_0402_6.3V6K
GC6_EN 2 FBA_DQS#1 H30 1 1 1 FBC_DQS#2 B2

1FBVDDQ_PWR_EN FBA_DQS#2 E34 FBA_DQS_RN1 FBC_DQS#3 A9 FBB_DQS_RN2
FBVDDQ_PWR_EN <25,52> FBA_DQS_RN2 FBB_DQS_RN3 FBx_CMD27 BA1 BA1
3 FBA_DQS#3 M34 H26 FBC_DQS#4 D22
FBA_DQS#4 AF30 FBA_DQS_RN3 FB_VREF FBC_DQS#5 D28 FBB_DQS_RN4
Place close to ball FBx_CMD28 A12 A12
1
N14@ GC6@ FBA_DQS#5 AK31 2 2 2 FBC_DQS#6 A30

0.1U_0402_10V7K
1 RV74 2 RV19 FBA_DQS#6 AM34 FBC_DQS#7 B23 FBx_CMD29 A10 A10

<19,26,54> DGPU_PWROK FBA_DQS_RN6 FBB_DQS_RN7
CV115
0_0402_5% 1 200K_0402_5% FBA_DQS#7 AF32

FBA_DQS_RN7
@ FBx_CMD30 RAS# RAS#
1 RV75 2 Place close to ball Place close to BGA
2
<18,54> NVDD_PWR_EN
0_0402_5%
2 N14M-GE-B-A2 FCBGA 908P GE@
@
N14M-GE-B-A2 FCBGA 908P GE@
<28,29> FBA_DQM[7..0]
1 RV81 2 <28,29> FBA_DQS[7..0] <30,31> FBC_DQM[7..0]
<28,29> FBA_DQS#[7..0] <30,31> FBC_DQS[7..0]
0_0402_5%
A <30,31> FBC_DQS#[7..0] A
GE@
Support GC6: N14P-GS/N14P-GV2(Mount RV19/DV2)

Non-support: N14M-GE(Mount RV81)
N14X-MEM Interface
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
0.3
5 4 3 2 1
5 4 3 2 1
Memory Partition A - Lower 32 bits FBA_D[0..63] <27,29>
FBA_MA[15..0] <27,29>
FBA_BA[2..0] <27,29>
FBA_DQM[7..0] <27,29>
FBA_DQS[7..0] <27,29>
FBA_DQS#[7..0] <27,29>
D D
UV3 UV4
+1.5VS_VGA +FBA_VREF0 M8 E3 FBA_D4 +FBA_VREF0 M8 E3 FBA_D19

H1 VREFCA DQL0 F7 FBA_D1 H1 VREFCA DQL0 F7 FBA_D20
VREFDQ DQL1 VREFDQ DQL1 DATA Bus
F2 FBA_D7 F2 FBA_D17
DQL2 DQL2
1
FBA_MA0 N3 F8 FBA_D0 FBA_MA0 N3 F8 FBA_D21 Group2 (IN1) Address 0..31 32..63
N14@ RV79 FBA_MA1 P7 A0 DQL3 H3 FBA_D6 FBA_MA1 P7 A0 DQL3 H3 FBA_D16
A1 DQL4 Group0 (IN3) A1 DQL4
FBA_MA2 P3 H8 FBA_D3 FBA_MA2 P3 H8 FBA_D23 FBx_CMD0 CS0#_L
1.1K_0402_1% FBA_MA3 N2 A2 DQL5 G2 FBA_D5 FBA_MA3 N2 A2 DQL5 G2 FBA_D18
FBA_MA4 P8 A3 DQL6 H7 FBA_D2 FBA_MA4 P8 A3 DQL6 H7 FBA_D22 FBx_CMD1
2
+FBA_VREF0 FBA_MA5 P2 A4 DQL7 FBA_MA5 P2 A4 DQL7

FBA_MA6 R8 A5 FBA_MA6 R8 A5
A6 A6 FBx_CMD2 ODT_L
1
N14@ CV118
0.01U_0402_25V7K
1 FBA_MA7 R2 D7 FBA_D29 FBA_MA7 R2 D7 FBA_D10

FBA_MA8 T8 A7 DQU0 C3 FBA_D25 FBA_MA8 T8 A7 DQU0 C3 FBA_D15
N14@ RV68
A8 DQU1 A8 DQU1 FBx_CMD3 CKE_L
FBA_MA9 R3 C8 FBA_D28 FBA_MA9 R3 C8 FBA_D8
FBA_MA10 L7 A9 DQU2 C2 FBA_D26 FBA_MA10 L7 A9 DQU2 C2 FBA_D13
1.1K_0402_1%
2 A10/AP DQU3 A10/AP DQU3 Group1 (TOP) FBx_CMD4 A14 A14
FBA_MA11 R7 A7 FBA_D31 Group3 (BOT) FBA_MA11 R7 A7 FBA_D9
2
FBA_MA12 N7 A11 DQU4 A2 FBA_D24 FBA_MA12 N7 A11 DQU4 A2 FBA_D12

A12 DQU5 A12 DQU5 FBx_CMD5 RST RST
FBA_MA13 T3 B8 FBA_D30 FBA_MA13 T3 B8 FBA_D11
FBA_MA14 T7 A13 DQU6 A3 FBA_D27 FBA_MA14 T7 A13 DQU6 A3 FBA_D14
A14 DQU7 A14 DQU7 FBx_CMD6 A9 A9
FBA_MA15 M7 FBA_MA15 M7
A15/BA3 +1.5VS_VGA A15/BA3 +1.5VS_VGA FBx_CMD7 A7 A7
FBA_BA0 M2 B2 FBA_BA0 M2 B2 FBx_CMD8 A2 A2
FBA_BA1 N8 BA0 VDD D9 FBA_BA1 N8 BA0 VDD D9
FBA_CLK0 FBA_BA2 M3 BA1 VDD G7 FBA_BA2 M3 BA1 VDD G7
BA2 VDD BA2 VDD FBx_CMD9 A0 A0
K2 K2
VDD K8 VDD K8
VDD VDD FBx_CMD10 A4 A4
2
N1 N1
FBA_CLK0 J7 VDD N9 FBA_CLK0 J7 VDD N9
C
RV80 N14@
<27> FBA_CLK0 CK VDD CK VDD FBx_CMD11 A1 A1 C
160_0402_1% FBA_CLK0# K7 R1 FBA_CLK0# K7 R1
<27> FBA_CLK0# K9 CK VDD R9 CK VDD
FBA_CKE_L FBA_CKE_L K9 R9 FBx_CMD12 BA0 BA0
<27> FBA_CKE_L CKE/CKE0 VDD CKE/CKE0 VDD
1
FBx_CMD13 WE# WE#

FBA_CLK0# FBA_ODT_L K1 A1 FBA_ODT_L K1 A1
<27> FBA_ODT_L FBA_CS0#_L L2 ODT/ODT0 VDDQ A8 FBA_CS0#_L L2 ODT/ODT0 VDDQ A8
<27> FBA_CS0#_L CS/CS0 VDDQ CS/CS0 VDDQ FBx_CMD14 A15 A15
FBA_RAS# J3 C1 FBA_RAS# J3 C1
<27,29> FBA_RAS# K3 RAS VDDQ C9 K3 RAS VDDQ C9
FBA_CAS# FBA_CAS# FBA_ODT_L FBx_CMD15 CAS# CAS#
<27,29> FBA_CAS# L3 CAS VDDQ D2 L3 CAS VDDQ D2
FBA_WE# FBA_WE#
<27,29> FBA_WE# WE VDDQ E9 WE VDDQ E9
VDDQ VDDQ FBx_CMD16 CS0#_H
F1 F1 FBA_CKE_L
FBA_DQS0 F3 VDDQ H2 FBA_DQS2 F3 VDDQ H2
DQSL VDDQ DQSL VDDQ FBx_CMD17
FBA_DQS3 C7 H9 FBA_DQS1 C7 H9
DQSU VDDQ DQSU VDDQ
2
FBx_CMD18 ODT_H
N14@ RV67 RV76 N14@
FBA_DQM0 E7 A9 FBA_DQM2 E7 A9 10K_0402_5% 10K_0402_5% FBx_CMD19 CKE_H
FBA_DQM3 D3 DML VSS B3 FBA_DQM1 D3 DML VSS B3
DMU VSS E1 DMU VSS E1 FBx_CMD20 A13 A13
1
VSS G8 VSS G8
FBA_DQS#0 G3 VSS J2 FBA_DQS#2 G3 VSS J2
DQSL VSS DQSL VSS FBx_CMD21 A8 A8
FBA_DQS#3 B7 J8 FBA_DQS#1 B7 J8
DQSU VSS M1 DQSU VSS M1
VSS VSS FBx_CMD22 A6 A6
M9 M9
VSS P1 VSS P1
FBA_RST# T2 P9 FBA_RST# T2 P9
<27,29> FBA_RST# RESET VSS T1 RESET VSS T1
L8 T9 L8 T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
FBx_CMD25 A3 A3
1
1
J1 B1 J1 B1 FBx_CMD26 BA2 BA2
NC/ODT1 VSSQ NC/ODT1 VSSQ
1
RV78 N14@ RV77 L1 B9 N14@ RV69 L1 B9

J9 NC/CS1 VSSQ D1 J9 NC/CS1 VSSQ D1
B
10K_0402_5% 243_0402_1% NC/CE1 VSSQ 243_0402_1% NC/CE1 VSSQ FBx_CMD27 BA1 BA1 B
L9 D8 L9 D8
NCZQ1 VSSQ E2 NCZQ1 VSSQ E2
N14@ FBx_CMD28 A12 A12
2
2
VSSQ E8 VSSQ E8
2
VSSQ F9 VSSQ F9
VSSQ VSSQ FBx_CMD29 A10 A10
G1 G1
VSSQ G9 VSSQ G9
VSSQ VSSQ FBx_CMD30 RAS# RAS#
UV3 X76_M2G@ UV3 X76_M1G@ UV3 X76_S1G@ UV3 X76_H1G@
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3
K4W4G1646B-HC11 FBGA 96P K4W4G1646B-HC11 FBGA 96P
X76_S2G@ X76_S2G@
MT41K256M16HA-107G:E H5TC2G63FFR-11C 96P

MT41J128M16JT-093G:K FBGA K4W2G1646E-BC1A FBGA 96P
SA000065D20 SA000067510 SA000068U10 SA00006H410 03/18 Change UV3/UV4/UV5/UV6 from SA000068R00 to SA000068R10 for SAM 2G VRAM(R3 part).
Change UV3/UV4/UV5/UV6 from SA000065D00 to SA000065D20 for MIC 2G VRAM(R3 part).
UV4 X76_M2G@ UV4 X76_M1G@ UV4 X76_S1G@ UV4 X76_H1G@ Change UV3/UV4/UV5/UV6 from SA000068U00 to SA000068U10 for SAM 1G VRAM(R3 part).
Change UV3/UV4/UV5/UV6 from SA000067500 to SA000067510 for MIC 1G VRAM(R3 part).
Change UV3/UV4/UV5/UV6 from SA00006H400 to SA00006H410 for HYN 1G VRAM(R3 part).
+1.5VS_VGA UV4 SIDE
MT41K256M16HA-107G:E MT41J128M16JT-093G:K FBGA K4W2G1646E-BC1A FBGA 96PH5TC2G63FFR-11C 96P +1.5VS_VGA UV3 SIDE
SA000065D20 SA000067510 SA000068U10 SA00006H410
0.1U_0402_10V7K
N14@ CV164
N14@ CV163
N14@ CV137
N14@ CV135
N14@ CV142
N14@ CV158
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1
0111 Change UV3/UV4/UV5/UV6
N14@ CV119
N14@ CV120
N14@ CV159
N14@ CV134
N14@ CV121
N14@ CV123
N14@ CV162
N14@ CV129
N14@ CV160
N14@ CV133
N14@ CV132
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1
from SA000065300 to SA00006H400 for Hynix VRAM 2 2 2 2 2 2
UV3 GV2_M2G@ UV3 GV2_M1G@ UV3 GV2_S1G@ UV3 GV2_H1G@ UV3 GV2_S2G@ 2 2 2 2 2 2 2 2 2 2 2
A A

MT41J128M16JT-093G:K FBGA K4W2G1646E-BC1A FBGA 96P K4W4G1646B-HC11 FBGA 96P
SA000065D20 SA000067510 SA000068U10 SA00006H410 SA000068R10
UV4 GV2_M2G@ UV4 GV2_M1G@ UV4 GV2_S1G@ UV4 GV2_H1G@ UV4 GV2_S2G@
N14X-VRAM A Lower
MT41K256M16HA-107G:E MT41J128M16JT-093G:K FBGA K4W2G1646E-BC1A FBGA 96PH5TC2G63FFR-11C 96P K4W4G1646B-HC11 FBGA 96P Size Document Number Rev
SA000065D20 SA000067510 SA000068U10 0.3
SA00006H410 SA000068R10 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS VILG1/G2 MB LA-9901P Schematic
0206 Add UV3/UV4/UV5/UV6 BOM structure for N14P-GV2. MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2 1
5 4 3 2 1
Memory Partition A - Upper 32 bits
FBA_D[0..63] <27,28>
FBA_MA[15..0] <27,28>
UV5 UV6
D +1.5VS_VGA D
+FBA_VREF1 M8 E3 FBA_D36 +FBA_VREF1 M8 E3 FBA_D63 FBA_BA[2..0] <27,28>
H1 VREFCA DQL0 F7 FBA_D34 H1 VREFCA DQL0 F7 FBA_D58
VREFDQ DQL1 VREFDQ DQL1 FBA_DQM[7..0] <27,28>
1
F2 FBA_D37 F2 FBA_D60
N14@ RV70 FBA_MA0 N3 DQL2 F8 FBA_D35 FBA_MA0 N3 DQL2 F8 FBA_D59
P7 A0 DQL3 H3 P7 A0 DQL3 H3 FBA_DQS[7..0] <27,28>
FBA_MA1 FBA_D39 Group4 (IN1) FBA_MA1 FBA_D61 Group7 (IN3)
1.1K_0402_1% FBA_MA2 P3 A1 DQL4 H8 FBA_D32 FBA_MA2 P3 A1 DQL4 H8 FBA_D56
FBA_MA3 N2 A2 DQL5 G2 FBA_D38 FBA_MA3 N2 A2 DQL5 G2 FBA_D62 FBA_DQS#[7..0] <27,28>
2
+FBA_VREF1 FBA_MA4 P8 A3 DQL6 H7 FBA_D33 FBA_MA4 P8 A3 DQL6 H7 FBA_D57

FBA_MA5 P2 A4 DQL7 FBA_MA5 P2 A4 DQL7
A5 A5
1
N14@ CV178
0.01U_0402_25V7K
1 FBA_MA6 R8 FBA_MA6 R8
N14@ RV82 FBA_MA7 R2 A6 D7 FBA_D45 FBA_MA7 R2 A6 D7 FBA_D55
FBA_MA8 T8 A7 DQU0 C3 FBA_D42 FBA_MA8 T8 A7 DQU0 C3 FBA_D51
FBA_MA9 R3 A8 DQU1 C8 FBA_D46 FBA_MA9 R3 A8 DQU1 C8 FBA_D54
1.1K_0402_1%
2 A9 DQU2 A9 DQU2 DATA Bus
FBA_MA10 L7 C2 FBA_D41 Group5 (TOP) FBA_MA10 L7 C2 FBA_D49
2
FBA_MA11 R7 A10/AP DQU3 A7 FBA_D47 FBA_MA11 R7 A10/AP DQU3 A7 FBA_D52 Group6 (BOT) Address 0..31 32..63
FBA_MA12 N7 A11 DQU4 A2 FBA_D43 FBA_MA12 N7 A11 DQU4 A2 FBA_D50
FBA_MA13 T3 A12 DQU5 B8 FBA_D44 FBA_MA13 T3 A12 DQU5 B8 FBA_D53
A13 DQU6 A13 DQU6 FBx_CMD0 CS0#_L
FBA_MA14 T7 A3 FBA_D40 FBA_MA14 T7 A3 FBA_D48
FBA_MA15 M7 A14 DQU7 FBA_MA15 M7 A14 DQU7
A15/BA3 +1.5VS_VGA A15/BA3 +1.5VS_VGA
FBx_CMD1
FBx_CMD2 ODT_L
FBA_BA0 M2 B2 FBA_BA0 M2 B2
FBA_BA1 N8 BA0 VDD D9 FBA_BA1 N8 BA0 VDD D9
BA1 VDD BA1 VDD FBx_CMD3 CKE_L
FBA_CLK1 FBA_BA2 M3 G7 FBA_BA2 M3 G7
BA2 VDD K2 BA2 VDD K2
K8 K8
VDD VDD
2
N1 FBA_CKE_H N1 FBx_CMD5 RST RST

RV83 N14@ FBA_CLK1 J7 VDD N9 FBA_CLK1 J7 VDD N9
<27> FBA_CLK1 K7 CK VDD R1 CK VDD
160_0402_1% FBA_CLK1# FBA_CLK1# K7 R1 FBx_CMD6 A9 A9
<27> FBA_CLK1# K9 CK VDD R9 CK VDD
FBA_CKE_H FBA_ODT_H FBA_CKE_H K9 R9
<27> FBA_CKE_H CKE/CKE0 VDD CKE/CKE0 VDD
FBx_CMD7 A7 A7
1
C C
FBA_CLK1# FBA_ODT_H K1 A1 FBA_ODT_H K1 A1 FBx_CMD8 A2 A2
<27> FBA_ODT_H ODT/ODT0 VDDQ ODT/ODT0 VDDQ
1
FBA_CS0#_H L2 A8 N14@ RV84 RV87 N14@ FBA_CS0#_H L2 A8
<27> FBA_CS0#_H J3 CS/CS0 VDDQ C1 J3 CS/CS0 VDDQ C1
FBA_RAS# 10K_0402_5% 10K_0402_5% FBA_RAS# FBx_CMD9 A0 A0
<27,28> FBA_RAS# FBA_CAS# K3 RAS VDDQ C9 FBA_CAS# K3 RAS VDDQ C9
<27,28> FBA_CAS# FBA_WE# L3 CAS VDDQ D2 FBA_WE# L3 CAS VDDQ D2
<27,28> FBA_WE# WE VDDQ WE VDDQ FBx_CMD10 A4 A4
E9 E9
2
VDDQ F1 VDDQ F1
VDDQ VDDQ FBx_CMD11 A1 A1
FBA_DQS4 F3 H2 FBA_DQS7 F3 H2
FBA_DQS5 C7 DQSL VDDQ H9 FBA_DQS6 C7 DQSL VDDQ H9
DQSU VDDQ DQSU VDDQ FBx_CMD12 BA0 BA0
FBx_CMD13 WE# WE#
FBA_DQM4 E7 A9 FBA_DQM7 E7 A9
FBA_DQM5 D3 DML VSS B3 FBA_DQM6 D3 DML VSS B3
DMU VSS DMU VSS FBx_CMD14 A15 A15
E1 E1
VSS G8 VSS G8
VSS VSS FBx_CMD15 CAS# CAS#
FBA_DQS#4 G3 J2 FBA_DQS#7 G3 J2
FBA_DQS#5 B7 DQSL VSS J8 FBA_DQS#6 B7 DQSL VSS J8
DQSU VSS DQSU VSS FBx_CMD16 CS0#_H
M1 M1
VSS M9 VSS M9
VSS VSS FBx_CMD17
P1 P1
FBA_RST# T2 VSS P9 FBA_RST# T2 VSS P9
<27,28> FBA_RST# RESET VSS RESET VSS FBx_CMD18 ODT_H
T1 T1
L8 VSS T9 L8 VSS T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS FBx_CMD19 CKE_H
FBx_CMD20 A13 A13
1
1
J1 B1 J1 B1
L1 NC/ODT1 VSSQ B9 L1 NC/ODT1 VSSQ B9
N14@ RV86
NC/CS1 VSSQ
N14@ RV85
NC/CS1 VSSQ FBx_CMD21 A8 A8
243_0402_1% J9 D1 243_0402_1% J9 D1
L9 NC/CE1 VSSQ D8 L9 NC/CE1 VSSQ D8
NCZQ1 VSSQ NCZQ1 VSSQ FBx_CMD22 A6 A6
E2 E2
2
2
VSSQ E8 VSSQ E8
B VSSQ VSSQ FBx_CMD23 A11 A11 B
F9 F9
VSSQ G1 VSSQ G1
G9 G9
VSSQ VSSQ
FBx_CMD25 A3 A3
96-BALL 96-BALL
UV5 X76_M2G@ UV5 X76_M1G@ UV5 X76_S1G@ UV5 X76_H1G@ SDRAM DDR3 SDRAM DDR3 FBx_CMD26 BA2 BA2
K4W4G1646B-HC11 FBGA 96P K4W4G1646B-HC11 FBGA 96P
X76_S2G@ X76_S2G@ FBx_CMD27 BA1 BA1
FBx_CMD28 A12 A12
MT41J128M16JT-093G:K FBGA K4W2G1646E-BC1A FBGA 96P FBx_CMD29 A10 A10
SA000065D20 SA000067510 SA000068U10 SA00006H410
FBx_CMD30 RAS# RAS#
UV6 X76_M2G@ UV6 X76_M1G@ UV6 X76_S1G@ UV6 X76_H1G@
MT41K256M16HA-107G:E MT41J128M16JT-093G:K FBGA K4W2G1646E-BC1A FBGA 96PH5TC2G63FFR-11C 96P +1.5VS_VGA UV5 SIDE +1.5VS_VGA UV6 SIDE
SA000065D20 SA000067510 SA000068U10 SA00006H410
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0111 Change UV3/UV4/UV5/UV6
N14@ CV145
N14@ CV174
N14@ CV299
N14@ CV290
N14@CV296
N14@CV301
N14@CV291
N14@CV302
N14@CV300
N14@CV297
N14@CV298
N14@CV165
N14@ CV177
N14@ CV166
N14@ CV172
N14@ CV167
N14@ CV171
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
from SA000065300 to SA00006H400 for Hynix VRAM
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
A A

MT41J128M16JT-093G:K FBGA K4W2G1646E-BC1A FBGA 96P K4W4G1646B-HC11 FBGA 96P
SA000065D20 SA000067510 SA000068U10 SA00006H410 SA000068R10
N14X-VRAM A Upper
MT41K256M16HA-107G:E MT41J128M16JT-093G:K FBGA K4W2G1646E-BC1A FBGA 96PH5TC2G63FFR-11C 96P K4W4G1646B-HC11 FBGA 96P Size Document Number Rev
SA000065D20 SA000067510 SA000068U10 0.3
SA00006H410 SA000068R10 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS VILG1/G2 MB LA-9901P Schematic
0206 Add UV3/UV4/UV5/UV6 BOM structure for N14P-GV2. MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2 1
5 4 3 2 1
Memory Partition C - Lower 32 bits FBC_D[0..63] <27,31>
FBC_MA[15..0] <27,31>
FBC_BA[2..0] <27,31>
FBC_DQM[7..0] <27,31>
FBC_DQS[7..0] <27,31>
FBC_DQS#[7..0] <27,31>
D +1.5VS_VGA D
1
GS@
UV7 UV8
RV111
+FBB_VREF0 M8 E3 FBC_D1 +FBB_VREF0 M8 E3 FBC_D9
1.1K_0402_1% H1 VREFCA DQL0 F7 FBC_D4 H1 VREFCA DQL0 F7 FBC_D15
VREFDQ DQL1 F2 FBC_D2 VREFDQ DQL1 F2 FBC_D10
2
+FBB_VREF0 FBC_MA0 N3 DQL2 F8 FBC_D5 FBC_MA0 N3 DQL2 F8 FBC_D14
A0 DQL3 Group0 (IN3) A0 DQL3
FBC_MA1 P7 H3 FBC_D0 FBC_MA1 P7 H3 FBC_D12 Group1 (TOP)
1 A1 DQL4 A1 DQL4
GS@
GS@
1 CV202 FBC_MA2 P3 H8 FBC_D6 FBC_MA2 P3 H8 FBC_D8
RV115 FBC_MA3 N2 A2 DQL5 G2 FBC_D3 FBC_MA3 N2 A2 DQL5 G2 FBC_D11
FBC_MA4 P8 A3 DQL6 H7 FBC_D7 FBC_MA4 P8 A3 DQL6 H7 FBC_D13
A4 DQL7 A4 DQL7 DATA Bus
1.1K_0402_1% 0.01U_0402_25V7K FBC_MA5 P2 FBC_MA5 P2
2 FBC_MA6 R8 A5 FBC_MA6 R8 A5
Address 0..31 32..63
2
FBC_MA7 R2 A6 D7 FBC_D24 FBC_MA7 R2 A6 D7 FBC_D16

FBC_MA8 T8 A7 DQU0 C3 FBC_D29 FBC_MA8 T8 A7 DQU0 C3 FBC_D20
A8 DQU1 A8 DQU1 FBx_CMD0 CS0#_L
FBC_MA9 R3 C8 FBC_D26 FBC_MA9 R3 C8 FBC_D18
FBC_MA10 L7 A9 DQU2 C2 FBC_D31 FBC_MA10 L7 A9 DQU2 C2 FBC_D17
A10/AP DQU3 A10/AP DQU3 FBx_CMD1
FBC_MA11 R7 A7 FBC_D27 Group3 (BOT) FBC_MA11 R7 A7 FBC_D21 Group2 (IN1)
FBC_MA12 N7 A11 DQU4 A2 FBC_D28 FBC_MA12 N7 A11 DQU4 A2 FBC_D23
A12 DQU5 A12 DQU5 FBx_CMD2 ODT_L
FBC_MA13 T3 B8 FBC_D25 FBC_MA13 T3 B8 FBC_D19
FBC_MA14 T7 A13 DQU6 A3 FBC_D30 FBC_MA14 T7 A13 DQU6 A3 FBC_D22
A14 DQU7 A14 DQU7 FBx_CMD3 CKE_L
FBC_MA15 M7 FBC_MA15 M7
A15/BA3 A15/BA3
+1.5VS_VGA +1.5VS_VGA FBx_CMD4 A14 A14
FBC_BA0 M2 B2 FBC_BA0 M2 B2 FBx_CMD5 RST RST
FBC_BA1 N8 BA0 VDD D9 FBC_ODT_L FBC_BA1 N8 BA0 VDD D9
FBC_BA2 M3 BA1 VDD G7 FBC_BA2 M3 BA1 VDD G7
BA2 VDD BA2 VDD FBx_CMD6 A9 A9
FBC_CLK0 K2 FBC_CKE_L K2
VDD K8 VDD K8
N1 N1
310mA VDD VDD
2
1
GS@
GS@
GS@
C FBC_CLK0 J7 N9 FBC_CLK0 J7 N9 C
<27> FBC_CLK0 CK VDD
RV117 RV116
CK VDD FBx_CMD8 A2 A2
RV89 FBC_CLK0# K7 R1 10K_0402_5% 10K_0402_5% FBC_CLK0# K7 R1
<27> FBC_CLK0# K9 CK VDD R9 CK VDD
160_0402_1% FBC_CKE_L FBC_CKE_L K9 R9 FBx_CMD9 A0 A0
<27> FBC_CKE_L CKE/CKE0 VDD CKE/CKE0 VDD
FBx_CMD10 A4 A4
1
2
FBC_ODT_L K1 A1 FBC_ODT_L K1 A1
<27> FBC_ODT_L L2 ODT/ODT0 VDDQ A8 L2 ODT/ODT0 VDDQ A8
FBC_CLK0# FBC_CS0#_L FBC_CS0#_L FBx_CMD11 A1 A1
<27> FBC_CS0#_L J3 CS/CS0 VDDQ C1 J3 CS/CS0 VDDQ C1
FBC_RAS# FBC_RAS#
<27,31> FBC_RAS# K3 RAS VDDQ C9 K3 RAS VDDQ C9
FBC_CAS# FBC_CAS# FBx_CMD12 BA0 BA0
<27,31> FBC_CAS# FBC_WE# L3 CAS VDDQ D2 FBC_WE# L3 CAS VDDQ D2
<27,31> FBC_WE# WE VDDQ E9 WE VDDQ E9
VDDQ VDDQ FBx_CMD13 WE# WE#
F1 F1
FBC_DQS0 F3 VDDQ H2 FBC_DQS1 F3 VDDQ H2
DQSL VDDQ DQSL VDDQ FBx_CMD14 A15 A15
FBC_DQS3 C7 H9 FBC_DQS2 C7 H9
DQSU VDDQ DQSU VDDQ
FBx_CMD15 CAS# CAS#
FBC_DQM0 E7 A9 FBC_DQM1 E7 A9 FBx_CMD16 CS0#_H
FBC_DQM3 D3 DML VSS B3 FBC_DQM2 D3 DML VSS B3
DMU VSS E1 DMU VSS E1
VSS VSS FBx_CMD17
G8 G8
FBC_DQS#0 G3 VSS J2 FBC_DQS#1 G3 VSS J2
DQSL VSS DQSL VSS FBx_CMD18 ODT_H
FBC_DQS#3 B7 J8 FBC_DQS#2 B7 J8
DQSU VSS M1 DQSU VSS M1
VSS VSS FBx_CMD19 CKE_H
M9 M9
VSS P1 VSS P1
FBC_RST# T2 P9 FBC_RST# T2 P9
<27,31> FBC_RST# RESET VSS T1 RESET VSS T1
L8 T9 L8 T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
10K_0402_5%
FBx_CMD22 A6 A6
243_0402_1%
1
1
GS@
GS@
J1 B1 J1 B1 FBx_CMD23 A11 A11
NC/ODT1 VSSQ NC/ODT1 VSSQ
1
GS@
L1 B9 RV88 L1 B9
B J9 NC/CS1 VSSQ D1 J9 NC/CS1 VSSQ D1 B
NC/CE1 VSSQ 243_0402_1% NC/CE1 VSSQ FBx_CMD24 A5 A5
L9 D8 L9 D8
NCZQ1 VSSQ E2 NCZQ1 VSSQ E2 FBx_CMD25 A3 A3
2
2
VSSQ VSSQ
RV91
E8 E8
2
VSSQ VSSQ
RV90
F9 F9 FBx_CMD26 BA2 BA2

VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9
VSSQ VSSQ FBx_CMD27 BA1 BA1
96-BALL 96-BALL FBx_CMD28 A12 A12
SDRAM DDR3 SDRAM DDR3
K4W4G1646B-HC11 FBGA 96P K4W4G1646B-HC11 FBGA 96P FBx_CMD29 A10 A10
@ @
FBx_CMD30 RAS# RAS#
+1.5VS_VGA +1.5VS_VGA UV8 SIDE

UV7 SIDE
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
GS@ CV192
GS@ CV203
GS@ CV187
GS@ CV198
GS@ CV184
GS@ CV197
GS@ CV186
GS@ CV195
GS@ CV200
GS@ CV201
GS@ CV204
GS@ CV193
0.1U_0402_10V7K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1
GS@ CV206
GS@ CV189
GS@ CV205
GS@ CV199
GS@ CV182
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2
2 2 2 2 2
A A

N14X-VRAM C Lower
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom VILG1/G2 MB LA-9901P Schematic 0.3
5 4 3 2 1
5 4 3 2 1
Memory Partition C - Upper 32 bits

FBC_D[0..63] <27,30>
FBC_MA[15..0] <27,30>
FBC_BA[2..0] <27,30>
+1.5VS_VGA FBC_DQM[7..0] <27,30>

D D
FBC_DQS[7..0] <27,30>
UV9
1
GS@
M8 E3 FBC_DQS#[7..0] <27,30>
RV120 +FBB_VREF1 FBC_D39 UV10
H1 VREFCA DQL0 F7 FBC_D33
1.1K_0402_1% VREFDQ DQL1 F2 FBC_D38 +FBB_VREF1 M8 E3 FBC_D60
FBC_MA0 N3 DQL2 F8 FBC_D32 H1 VREFCA DQL0 F7 FBC_D56
2
+FBB_VREF1 FBC_MA1 P7 A0 DQL3 H3 FBC_D36 VREFDQ DQL1 F2 FBC_D63

A1 DQL4 Group4 (IN1) DQL2
FBC_MA2 P3 H8 FBC_D35 FBC_MA0 N3 F8 FBC_D58
A2 DQL5 A0 DQL3
1
GS@
GS@ CV229
0.01U_0402_25V7K
1 FBC_MA3 N2 G2 FBC_D37 FBC_MA1 P7 H3 FBC_D61 Group7 (IN3)

RV127 FBC_MA4 P8 A3 DQL6 H7 FBC_D34 FBC_MA2 P3 A1 DQL4 H8 FBC_D57
FBC_MA5 P2 A4 DQL7 FBC_MA3 N2 A2 DQL5 G2 FBC_D62
1.1K_0402_1% FBC_MA6 R8 A5 FBC_MA4 P8 A3 DQL6 H7 FBC_D59
2 FBC_MA7 R2 A6 D7 FBC_D45 FBC_MA5 P2 A4 DQL7
2
FBC_MA8 T8 A7 DQU0 C3 FBC_D41 FBC_MA6 R8 A5

FBC_MA9 R3 A8 DQU1 C8 FBC_D47 FBC_MA7 R2 A6 D7 FBC_D52
FBC_MA10 L7 A9 DQU2 C2 FBC_D42 FBC_MA8 T8 A7 DQU0 C3 FBC_D51
FBC_MA11 R7 A10/AP DQU3 A7 FBC_D44 FBC_MA9 R3 A8 DQU1 C8 FBC_D55
A11 DQU4 Group5 (TOP) A9 DQU2
FBC_MA12 N7 A2 FBC_D40 FBC_MA10 L7 C2 FBC_D49
FBC_MA13 T3 A12 DQU5 B8 FBC_D46 FBC_MA11 R7 A10/AP DQU3 A7 FBC_D54
A13 DQU6 A11 DQU4 Group6 (BOT)
FBC_MA14 T7 A3 FBC_D43 FBC_MA12 N7 A2 FBC_D50
FBC_MA15 M7 A14 DQU7 FBC_MA13 T3 A12 DQU5 B8 FBC_D53
A15/BA3 +1.5VS_VGA FBC_MA14 T7 A13 DQU6 A3 FBC_D48
FBC_MA15 M7 A14 DQU7
FBC_BA0 M2 B2 A15/BA3
BA0 VDD
+1.5VS_VGA DATA Bus
FBC_BA1 N8 D9
FBC_BA2 M3 BA1 VDD G7 FBC_ODT_H FBC_BA0 M2 B2
BA2 VDD BA0 VDD
Address 0..31 32..63
K2 FBC_BA1 N8 D9
VDD K8 FBC_BA2 M3 BA1 VDD G7
VDD BA2 VDD FBx_CMD0 CS0#_L
N1 FBC_CKE_H K2
FBC_CLK1 FBC_CLK1 J7 VDD N9 VDD K8
<27> FBC_CLK1 CK VDD VDD FBx_CMD1
FBC_CLK1# K7 R1 N1
<27> FBC_CLK1# CK VDD VDD
GS@1
GS@
C FBC_CKE_H K9 R9 FBC_CLK1 J7 N9 C
<27> FBC_CKE_H CKE/CKE0 VDD
RV118 RV119
CK VDD FBx_CMD2 ODT_L
2
GS@
10K_0402_5% 10K_0402_5% FBC_CLK1# K7 R1

FBC_CKE_H K9 CK VDD R9
RV129
CKE/CKE0 VDD FBx_CMD3 CKE_L
160_0402_1% FBC_ODT_H K1 A1
<27> FBC_ODT_H FBC_CS0#_H L2 ODT/ODT0 VDDQ A8 FBx_CMD4 A14 A14
2
<27> FBC_CS0#_H FBC_RAS# J3 CS/CS0 VDDQ C1 FBC_ODT_H K1 A1
1
<27,30> FBC_RAS# K3 RAS VDDQ C9 L2 ODT/ODT0 VDDQ A8

FBC_CAS# FBC_CS0#_H FBx_CMD5 RST RST
<27,30> FBC_CAS# L3 CAS VDDQ D2 J3 CS/CS0 VDDQ C1
FBC_CLK1# FBC_WE# FBC_RAS#
<27,30> FBC_WE# WE VDDQ E9 K3 RAS VDDQ C9
FBC_CAS# FBx_CMD6 A9 A9
VDDQ F1 FBC_WE# L3 CAS VDDQ D2
FBC_DQS4 F3 VDDQ H2 WE VDDQ E9
DQSL VDDQ VDDQ FBx_CMD7 A7 A7
FBC_DQS5 C7 H9 F1
DQSU VDDQ FBC_DQS7 F3 VDDQ H2
DQSL VDDQ FBx_CMD8 A2 A2
FBC_DQS6 C7 H9
FBC_DQM4 E7 A9 DQSU VDDQ
DML VSS FBx_CMD9 A0 A0
FBC_DQM5 D3 B3
DMU VSS E1 FBC_DQM7 E7 A9
VSS DML VSS FBx_CMD10 A4 A4
G8 FBC_DQM6 D3 B3
FBC_DQS#4 G3 VSS J2 DMU VSS E1
DQSL VSS VSS FBx_CMD11 A1 A1
FBC_DQS#5 B7 J8 G8
DQSU VSS M1 FBC_DQS#7 G3 VSS J2
VSS DQSL VSS FBx_CMD12 BA0 BA0
M9 FBC_DQS#6 B7 J8
VSS P1 DQSU VSS M1
VSS VSS FBx_CMD13 WE# WE#
FBC_RST# T2 P9 M9
<27,30> FBC_RST# RESET VSS T1 VSS P1
L8 T9 FBC_RST# T2 P9
ZQ/ZQ0 VSS RESET VSS T1
VSS FBx_CMD15 CAS# CAS#
L8 T9
ZQ/ZQ0 VSS
1
J1 B1 FBx_CMD16 CS0#_H
NC/ODT1 VSSQ
GS@
RV123 L1 B9
NC/CS1 VSSQ
1
GS@
243_0402_1% J9 D1 J1 B1 FBx_CMD17
L9 NC/CE1 VSSQ D8 RV128 L1 NC/ODT1 VSSQ B9
B NCZQ1 VSSQ E2 J9 NC/CS1 VSSQ D1 B
243_0402_1% FBx_CMD18 ODT_H
2
VSSQ E8 L9 NC/CE1 VSSQ D8

VSSQ F9 NCZQ1 VSSQ E2 FBx_CMD19 CKE_H
2
VSSQ G1 VSSQ E8
VSSQ G9 VSSQ F9
G1
VSSQ G9
96-BALL
VSSQ FBx_CMD21 A8 A8
SDRAM DDR3
K4W4G1646B-HC11 FBGA 96P 96-BALL FBx_CMD22 A6 A6
@ SDRAM DDR3
K4W4G1646B-HC11 FBGA 96P FBx_CMD23 A11 A11
@
FBx_CMD24 A5 A5
FBx_CMD25 A3 A3
+1.5VS_VGA UV9 SIDE
+1.5VS_VGA UV10 SIDE FBx_CMD26 BA2 BA2
FBx_CMD27 BA1 BA1
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
FBx_CMD28 A12 A12

GS@ CV209
GS@ CV220
GS@ CV221
GS@ CV233
GS@ CV226
GS@ CV207
GS@ CV213
GS@ CV225
GS@ CV210
GS@ CV224
GS@ CV223
GS@ CV214
GS@ CV212
GS@ CV215
GS@ CV217
GS@ CV218
GS@ CV232
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
FBx_CMD29 A10 A10
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
FBx_CMD30 RAS# RAS#
A A

N14X-VRAM C Upper
5 4 3 2 1
5 4 3 2 1
+3VS_VGA
N14M-GE X76 Multi-Level Mode
X7647138L01:X76_M2G@ Physical Logical Logical Logical Logical
2
Power Rail
X7647138L02:X76_S1G@ RV92 RV93 RV94 RV121 RV122
Strapping pin Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
ROM_SCLK +3VS_VGA PCI_DEVID[4] SUB_VENDOR SLOT_CLK_CFG PEX_PLL_EN_TERM
X7647138L03:X76_M1G@ 10K_0402_1%
X76_S2G@
10K_0402_1%
X76_S2G@
10K_0402_1%
X76_M2G@
10K_0402_1%
X76_S2G@
10K_0402_1%
@
ROM_SI +3VS_VGA RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
X7647138L04:X76_S2G@
1
STRAP0
<24> STRAP0
STRAP1 ROM_SO +3VS_VGA FB[1] FB[0] SMB_ALT_ADDR VGA_DEVICE
X7647138L05:X76_H1G@ <24>
<24>
STRAP1
STRAP2
STRAP2
STRAP3 STRAP0 +3VS_VGA USER[3] USER[2] USER[1] USER[0]
<24> STRAP3
STRAP4
<24> STRAP4
STRAP1 +3VS_VGA 3GIO_PADCFG[3] 3GIO_PADCFG[2] 3GIO_PADCFG[1] 3GIO_PADCFG[0]
2
D RV92 X76_M1G@ RV135 X76_M1G@ RV97 X76_M1G@ D
RV95 RV96 RV135 RV124 RV97 STRAP2 +3VS_VGA PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
10K_0402_1% 10K_0402_1% 10K_0402_1% 10K_0402_1% 10K_0402_1%
X76_H1G@ X76_M1G@ X76_S2G@ X76_M1G@ X76_S2G@ STRAP3 +3VS_VGA SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
1
STRAP4 +3VS_VGA RESERVED PCIE_SPEED_ PCIE_MAX_SPEED DP_PLL_VDD33V
10K_0402_1% 10K_0402_1% 10K_0402_1% CHANGE_GEN3
SD034100280 SD034100280 SD034100280
RV92 X76_S1G@ RV96 X76_S1G@ RV94 X76_S1G@ RV124 X76_S1G@ RV97 X76_S1G@ RV136 X76_M2G@ RV139 X76_M2G@ RV103 X76_M2G@
Binary-Level Mode
Resistor Pull-up to Physical Strapping
Values +3VS_VGA Pull-down to Gnd Strapping pin Mapping Resistance Polarity
4.99K 1000 0000 ROM_SCLK SMB_ALT_ADDR 10K PD
10K_0402_1% 10K_0402_1% 10K_0402_1% 10K_0402_1% 10K_0402_1% 10K_0402_1% 10K_0402_1% 10K_0402_1%
SD034100280 SD034100280 SD034100280 SD034100280 SD034100280 SD034100280 SD034100280 SD034100280 10.0K 1001 0001 ROM_SI SUB_VENDOR 10K PU(VBIOS ROM)
PD(Non-VBIOS ROM)
RV92 X76_M2G@ RV96 X76_M2G@ RV121 X76_M2G@ RV97 X76_M2G@ RV136 X76_S1G@ RV139 X76_S1G@ RV103 X76_S1G@ 15.0K 1010 0010
N14P-GV2 X76 ROM_SO VGA_DEVICE 10K PD(No display)
X7647138L06:GV2_M2G@ 20.0K 1011 0011
STRAP0 RAM_CFG[0] 10K
X7647138L07:GV2_S1G@ 24.9K 1100 0100
STRAP1 RAM_CFG[1] 10K PU (Binary=1)
10K_0402_1% 10K_0402_1% 10K_0402_1% 10K_0402_1% 10K_0402_1% 10K_0402_1% 10K_0402_1%
X7647138L08:GV2_M1G@ 30.1K 1101 0101 PD (Binary=0)
SD034100280 SD034100280 SD034100280 SD034100280 SD034100280 SD034100280 SD034100280 STRAP2 RAM_CFG[2] 10K
RV136 X76_M1G@ RV139 X76_M1G@ RV103 X76_M1G@
X7647138L09:GV2_S2G@ 34.8K 1110 0110
RV96 X76_H1G@ RV94 X76_H1G@ RV121 X76_H1G@ RV97 X76_H1G@ STRAP3 RAM_CFG[3] 10K
X7647138L10:GV2_H1G@ 45.3K 1111 0111
STRAP4 PCIE_MAX_SPEED 10K PD
10K_0402_1% 10K_0402_1% 10K_0402_1% RV96 GV2_M2G@ RV96 GV2_S1G@ RV96 GV2_M1G@ RV96 GV2_S2G@ RV96 GV2_H1G@ RV124 GV2_M2G@ RV124 GV2_S1G@ RV124 GV2_M1G@ RV124 GV2_S2G@ RV124 GV2_H1G@
C SD034100280 SD034100280 SD034100280 C
10K_0402_1% 10K_0402_1% 10K_0402_1% 10K_0402_1%
SD034100280 SD034100280 SD034100280 SD034100280 RV136 X76_H1G@ RV139 X76_H1G@ RV103 X76_H1G@
+3VS_VGA
2
45.3K_0402_1% 45.3K_0402_1% 45.3K_0402_1% 45.3K_0402_1% 45.3K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
RV98 RV134 RV100 SD034453280 SD034453280 SD034453280 SD034453280 SD034453280 SD034499180 SD034499180 SD034499180 SD034499180 SD034499180
10K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 10K_0402_1% 10K_0402_1% 10K_0402_1% RV97 GV2_M2G@ RV97 GV2_S1G@ RV97 GV2_M1G@ RV97 GV2_S2G@ RV97 GV2_H1G@ RV92 GV2_M2G@ RV92 GV2_S1G@ RV92 GV2_M1G@ RV92 GV2_S2G@ RV92 GV2_H1G@
@ GV2_S2G@ GV2_S2G@ SD034100280 SD034100280 SD034100280
RV134 GV2_M2G@ RV134 GV2_S1G@ RV134 GV2_M1G@ RV134 GV2_H1G@
1
ROM_SI
<24> ROM_SI
ROM_SO
<24> ROM_SO
ROM_SCLK
<24> ROM_SCLK
45.3K_0402_1% 45.3K_0402_1% 45.3K_0402_1% 45.3K_0402_1% 45.3K_0402_1% 45.3K_0402_1% 45.3K_0402_1% 45.3K_0402_1% 45.3K_0402_1% 45.3K_0402_1%
2
SD034453280 SD034453280 SD034453280 SD034453280 SD034453280 SD034453280 SD034453280 SD034453280 SD034453280 SD034453280
RV136 RV139 RV103 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
10K_0402_1% 10K_0402_1% 10K_0402_1% SD034499180 SD034499180 SD034499180 SD034499180
X76_S2G@ X76_S2G@ X76_S2G@ RV100 GV2_M2G@ RV100 GV2_S1G@ RV100 GV2_M1G@ RV100 GV2_H1G@
SUB_VENDOR PEX_PLL_EN_TERM XCLK_417
1
RV136 GV2_S1G@ RV136 GV2_M2G@

0 No VBIOS ROM 0 Disable (Default) 0 277MHz (Default)
For N14P-GV2 strap table X76 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 1 BIOS ROM is present (Default) 1 Enable 1 Reserved
SD034499180 SD034499180 SD034499180 SD034499180
45.3K_0402_1% 10K_0402_1%
Frenq. Memory Size Memory Config strap0 strap1 strap2 strap3 strap4 ROM_SI ROM_SO ROM_SCLK SD034453280 SD034100280
GPU
RV136 GV2_M1G@ RV136 GV2_S2G@ RV136 GV2_H1G@ FB_0_BAR_SIZE SLOT_CLK_CFG
N14P-GV2 128M* 16* 4 Samsung R R R R R R R R
1 GHz
1GB K4W2G1646E-BC1A PU 45K PD 45K PD 15K PD 5K PD 45K PD 45K PU 5K PU 5K 0 Reserved 0 GPU and MCH don't share a common reference clock
N14P-GV2 128M* 16* 4 Micron R R R R R R R R
1 GHz
1GB MT41J128M16JT-093G:K PU 45K PD 45K PD 15K PD 5K PD 45K PD 30K PU 5K PU 5K
B 128M* 16* 4 Hynix R R R R R R R R 1 Reserved 1 GPU and MCH share a common reference clock (Default) B
N14P-GV2 1 GHz
1GB H5TC2G63FFR-11C PU 45K PD 45K PD 15K PD 5K PD 45K PD 25K PU 5K PU 5K 30.1K_0402_1% 20K_0402_1% 24.9K_0402_1%
N14P-GV2 256M* 16* 4 Samsung R R R R R R R R SD034301280 SD034200280 SD034249280
900 MHz
2GB K4W4G1646B-HC11 PU 45K PD 45K PD 15K PD 5K PD 45K PD 20K PU 5K PU 5K 2 256MB (Default)
N14P-GV2 900 MHz
256M* 16* 4 Micron R R R R R R R R SMBUS_ALT_ADDR VGA_DEVICE
2GB MT41K256M16HA-107G:E PU 45K PD 45K PD 15K PD 5K PD 45K PD 10K PU 5K PU 5K 0206 Change R136 from SD034200200 to Non-Primary 3D Acceleration Device
SD034200280 for GV2_S2G. 3 Reserved 0 0x9E (Default) 0
(Class Code 302h)
For N14P-GS strap table X76 0206 Change R136 from SD034249200 to
Primary Display or VGA Device
SD034249280 for GV2_H1G. 1 0x9C (Multi-GPU usage) 1
GPU Frenq. Memory Size Memory Config strap0 strap1 strap2 strap3 strap4 ROM_SI ROM_SO ROM_SCLK USER Straps (Class Code 300h)
128M* 16* 8 Samsung R R R R R R R R User[3:0]
N14P-GS 1 GHz
2GB K4W2G1646E-BC1A PU 45K PD 5K PD 20K PD 5K PD 45K PD 45K PU 5K PD 15K
PCI_DEVID
128M* 16* 8 Micron R R R R R R R R RV135 GV2_S1G@ RV135 GV2_M2G@
N14P-GS 1 GHz
2GB MT41J128M16JT-093G:K GPU Type DEVID[5] DEVID[4] DEVID[3] DEVID[2] DEVID[1] DEVID[0]
Hynix
PU 45K PD 5K PD 20K PD 5K PD 45K PD 30K PU 5K PD 15K 1000-1100 Customer defined
128M* 16* 8 R R R R R R R R 0 1 0
N14P-GS 1 GHz
2GB H5TC2G63FFR-11C N14P-GV2 0 1 0
PU 45K PD 5K PD 20K PD 5K PD 45K PD 25K PU 5K PD 15K
256M* 16* 8 Samsung R R R R R R R R 0 1 1
N14P-GS 900 MHz
4GB K4W4G1646B-HC11 PU 45K PD 5K PD 20K PD 5K PD 45K PD 20K PU 5K PD 15K
3GIO_PADCFG N14P-GS 1 0 0
N14P-GS 256M* 16* 8 Micron R R R R R R R R 15K_0402_1% 15K_0402_1% [3:0]
900 MHz Description
4GB MT41K256M16HA-107G:E PU 45K PD 5K PD 20K PD 5K PD 45K PD 10K PU 5K PD 15K SD034150280 SD034150280
PCIE_SPEED_CHANGE_GEN3 PCIE_MAX_SPEED
For N14M-GE strap table X76 RV135 GV2_M1G@ RV135 GV2_S2G@ RV135 GV2_H1G@ 0110 Gen 1 / Gen 2 Support only N14P-GV2 1 1
N14P-GS 1 1
GPU Frenq. Memory Size Memory Config strap0 strap1 strap2 strap3 strap4 ROM_SI ROM_SO ROM_SCLK 0000 Gen 3 Support
0: Disable PCIE Gen3 operation 0: Limit to PCIE Gen1
N14M-GE 1 GHz NV update PUN doc for the definition of 3GIO_CONFIG. 1: Enable PCIE Gen3 operation 1: PCIE Gen 2/3 Capable
1GB K4W2G1646E-BC1A PU 10K PD 10K PU 10K PD 10K PD 10K PD 10K PD 10K PD 10K 15K_0402_1% 15K_0402_1% 15K_0402_1%
128M* 16* 4 Micron R R R R R R R R SD034150280 SD034150280 SD034150280
N14M-GE 1 GHz
1GB MT41J128M16JT-093G:K PU 10K PD 10K PD 10K PD 10K PD 10K PD 10K PD 10K PD 10K 3GIO_PADCFG[3:0]
A 128M* 16* 4 Hynix R R R R R R R R A
N14M-GE 1 GHz Strap1 3GIO_PADCFG[3] 3GIO_PADCFG[2] 3GIO_PADCFG[2] 3GIO_PADCFG[1]
1GB H5TC2G63FFR-11C PD 10K PD 10K PU 10K PU 10K PD 10K PD 10K PD 10K PD 10K
N14M-GE 900 MHz
2GB K4W4G1646B-HC11 PU 10K PU 10K PD 10K PU 10K PD 10K PD 10K PD 10K PD 10K
N14P-GV2 0 1 1 1
N14M-GE 900 MHz
2GB MT41K256M16HA-107G:E PU 10K PD 10K PU 10K PU 10K PD 10K PD 10K PD 10K PD 10K
N14P-GS 0 0 0 0
VRAM Part Number Security Classification Compal Secret Data Compal Electronics, Inc.
Samsung Micron Hynix Samsung Micron 2011/06/15 2012/07/11 Title
Frenq. Memory Size
K4W2G1646E-BC1A MT41J128M16JT-093G:K H5TC2G63FFR-11C K4W4G1646B-HC11 MT41K256M16HA-107G:E
Issued Date Deciphered Date
1 GHz
128M* 16* 8
SA000068U10 SA000067510 SA00006H410 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N14X-MISC
2GB Size Document Number Rev
900 MHz 256M* 16* 8 SA000068R10 SA000065D20 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom VILG1/G2 MB LA-9901P Schematic 0.3
4GB MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2 1
5 4 3 2 1
LCD POWER CIRCUIT CMOS Camera

+3VS
W=60mils
+3VS +LCDVDD_CONN CMOS@ +3VS_CMOS
W=60mils U72 Q83
D 1 +LCDVDD_CONN PMV65XP_SOT23-3~D D
5 VOUT
(20 MIL)
4.7U_0603_6.3V6K
VIN
D
3 1
C516
2 1 1 1
4 GND CMOS@
SS C518 C519 @
G
2
1 3 0.1U_0402_16V4Z R02 10U_0603_6.3V6M
EN 2 R435CMOS@ 2 2
C4 APL3512ABI-TRG_SOT23-5 150K_0402_5%
1500P_0402_50V7K 4.7V
2 <42> CMOS_ON#
<17> PCH_ENVDD 1
C520 CMOS@
0.1U_0402_16V4Z
2
C
VGA LCD/PANEL BD. Conn. C
12/12 Mount C539/C541 of 680pF,Chanage R813

to 220 ohm bead.(For EMI request)
+LEDVDD B+
R813
FBMA-L11-201209-221LMA30T_0805
1 2
BKOFF#
<42> BKOFF#
1
C539 C541
1
680P_0402_50V7K 680P_0402_50V7K
2
R716
10K_0402_5%
2
JLVDS1
1 2
1 2 PCH_PWM <17>
3 4
5 3 4 6 USB20_N3_R
BKOFF# 7 5 6 8 USB20_P3_R
B B
9 7 8 10
11 9 10 12
<17> LVDS_ACLK 11 12 LVDS_A1 <17>
13 14
<17> LVDS_ACLK# 13 14 LVDS_A1# <17>
15 16
17 15 16 18
<17> LVDS_A2 17 18 LVDS_A0 <17>
19 20
For EMI <17>
<17>
LVDS_A2#
EDID_DATA
21
23
25
19
21
23
20
22
24
22
24
26 (60 MIL)
LVDS_A0# <17>
<17> EDID_CLK 25 26 +LCDVDD_CONN

27 28 +3VS
USB20_P3 2 R688 1 0_0402_5% USB20_P3_R 29 27 28 30
<18> USB20_P3 +3VS 29 30 +3VS_CMOS
<18> USB20_N3 USB20_N3 2 R684 1 0_0402_5% USB20_N3_R
31 32
L58 @ GNDGND
USB20_P3 1 2 USB20_P3_R ACES_87142-3041-BS
1 2 ME@
USB20_N3 4 3 USB20_N3_R
4 3
WCM-2012-900T_4P
A A

LVDS/CAMERA
Custom 1.0
5 4 3 2 1
A B C D E
1 1
FCM1608CF-121T03 0603
1 2 RED
<17> DAC_RED
L30
FCM1608CF-121T03 0603
1 2 GREEN
<17> DAC_GRN
L31
FCM1608CF-121T03 0603
1 2 BLUE
<17> DAC_BLU
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
C522
C523
C524
C525
C526
C527
L32
1 1 1 1 1 1
RP22
8 1 DAC_BLU 2 2 2 2 2 2 +5V_DISPLAY
7 2 DAC_GRN
6 3 DAC_RED
5 4
150_0804_8P4R_1% @ @ @ @ @ @ JCRT1
6
PAD T66 NC11 11
For EMI RED
CRT_DDC_DAT_CONN
1
7
12
GREEN 2
8 G 16
2 JVGA_HS_R 13 17 2
BLUE 3 G
9
JVGA_VS_R 14
4
10
CRT_DDC_CLK_CONN 15
5
SUYIN_070546FR015S251ZR
ME@
+5VS
1 1
C529 C531
U10
0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 @ 1 8 1 2
VCC_SYNC BYP C6 0.22U_0402_10V6K +5V_DISPLAY
2 3 RED
+3VS VCC_VIDEO VIDEO1
1
7 4 GREEN
VCC_DDC VIDEO2 R31 R33
1 4.7K_0402_5% 4.7K_0402_5%
<17> CRT_DDC_DATA 10 5 BLUE
C537 DDC_IN1 VIDEO3
2
0.1U_0402_16V4Z
3 2 11 9 CRT_DDC_DAT_CONN 3
<17> CRT_DDC_CLK DDC_IN2 DDC_OUT1
13 12 CRT_DDC_CLK_CONN
<17> CRT_VSYNC SYNC_IN1 DDC_OUT2
15 14 JVGA_VS 1 @ 2 JVGA_VS_R
<17> CRT_HSYNC SYNC_IN2 SYNC_OUT1 R411 0_0402_5%
6 16 JVGA_HS 1 @ 2 JVGA_HS_R
GND SYNC_OUT2 R412 0_0402_5%
10P_0402_50V8J
10P_0402_50V8J
TPD7S019-15DBQR_SSOP16 1 1
C411
C412
@ @
2 2
4 4

CRT Connector
Custom 1.0
A B C D E
5 4 3 2 1
+5V_DISPLAY
For EMI +5VS

U73
3
W=40mils
OUT
1
L35 HDMI@ 1
HDMI_CLK+_CK 1 2 HDMI_CLK+_CONN +3VS IN C543
<17> HDMI_CLK+_CK 1 2 1
2
C544 GND 0.1U_0402_16V4Z 2
<17> HDMI_CLK-_CK HDMI_CLK-_CK 4 3 HDMI_CLK-_CONN 0.1U_0402_16V4Z
4 3
2
2 AP2330W-7_SC59-3
D WCM-2012HS-900T R485 ZZZ3 45@ D
1M_0402_5% Q93
L36 HDMI@ HDMI@ HDMI@
2
G
<17> HDMI_TX0+_CK HDMI_TX0+_CK 1 2 HDMI_TX0+_CONN 2N7002H_SOT23-3
1
1 2
TMDS_B_HPD# 3 1
4 3 <17> TMDS_B_HPD#
HDMI_TX0-_CK HDMI_TX0-_CONN
D
<17> HDMI_TX0-_CK 4 3 HDMI Logo
WCM-2012HS-900T RO0000003HM
2
L37 HDMI@ R488
HDMI_TX1+_CK 1 2 HDMI_TX1+_CONN 20K_0402_5%
<17> HDMI_TX1+_CK 1 2 HDMI@
JHDMI1
1
HDMI_TX1-_CK 4 3 HDMI_TX1-_CONN HDMI_DET 19
<17> HDMI_TX1-_CK 4 3 HP_DET
+5V_DISPLAY 18
WCM-2012HS-900T 17 +5V
HDMIDAT_R 16 DDC/CEC_GND
L38 HDMI@ HDMICLK_R 15 SDA
HDMI_TX2+_CK 1 2 HDMI_TX2+_CONN 14 SCL
<17> HDMI_TX2+_CK 1 2 Reserved
13
HDMI_CLK-_CONN 12 CEC 20
HDMI_TX2-_CK 4 3 HDMI_TX2-_CONN 11 CK- GND 21
<17> HDMI_TX2-_CK 4 3 CK_shield GND
HDMI_CLK+_CONN 10 22
C CK+ GND C
WCM-2012HS-900T HDMI_TX0-_CONN 9 23
8 D0- GND For LAN
HDMI_TX0+_CONN 7 D0_shield CHASSIS1_GND
+3VS HDMI_TX1-_CONN 6 D0+
5 D1-
HDMI_TX1+_CONN 4 D1_shield
HDMI_TX2-_CONN 3 D1+
2 D2-
HDMI_TX2+_CONN 1 D2_shield
D2+
CONCR_099ATAC19NBLCNF
ME@
+3VS Q63A
HDMI@
2
+5V_DISPLAY RP21 2N7002DW-T/R7_SOT363-6

8 1 HDMIDAT_NB
7 2 HDMIDAT_R <17> HDMICLK_NB 1 6 HDMICLK_R
6 3 HDMICLK_NB
5
5 4 HDMICLK_R
4 3 RP19
2.2K_0804_8P4R_5% <17> HDMIDAT_NB HDMIDAT_R
HDMI@ HDMI_CLK-_CONN 1 10
Q63B HDMI_CLK+_CONN 2 9 HDMI_TX0-_CONN
B HDMI@ HDMI_TX1-_CONN 3 8 HDMI_TX0+_CONN B
2N7002DW-T/R7_SOT363-6 HDMI_TX1+_CONN 4 7 HDMI_TX2+_CONN
5 6 HDMI_TX2-_CONN
680_1206_10P8R_5%
ESD HDMI@
@ D32 @ D28 @ D33

HDMIDAT_R 9 1 HDMIDAT_R HDMI_CLK-_CONN 9 1 HDMI_CLK-_CONN HDMI_TX0-_CONN 9 1 HDMI_TX0-_CONN
HDMICLK_R 8 2 HDMICLK_R HDMI_CLK+_CONN 8 2 HDMI_CLK+_CONN HDMI_TX0+_CONN 8 2 HDMI_TX0+_CONN

+3VS
HDMI_DET 7 4 HDMI_DET HDMI_TX1-_CONN 7 4 HDMI_TX1-_CONN HDMI_TX2-_CONN 7 4 HDMI_TX2-_CONN
1
D
6 5 HDMI_TX1+_CONN 6 5 HDMI_TX1+_CONN HDMI_TX2+_CONN 6 5 HDMI_TX2+_CONN 2
G
3 3 3 S Q95
3
HDMI@
8 8 8 2N7002H_SOT23-3
YSCLAMP0524P_SLP2510P8-10-9 YSCLAMP0524P_SLP2510P8-10-9 YSCLAMP0524P_SLP2510P8-10-9

A A

HDMI CONN
B 1.0
5 4 3 2 1
A B C D E
Mini-Express Card for WLAN/WiMAX(Half)
1 1
+3VS 80mil +3VS_WLAN

J6
@
1 2
1 2 +1.5VS
JUMP_43X79
JWLN1
1 R508 2 @ PCIE_WAKE#_WLAN 1 2
<16> PCIE_WAKE# 1 2
0_0402_5% 3 4
5 3 4 6
<19> PCH_BT_ON# 5 6
<15> CLKREQ_WLAN# 7 8
9 7 8 10
11 9 10 12
<15> CLK_PCIE_WLAN1# 11 12
13 14
<15> CLK_PCIE_WLAN1 15 13 14 16
17 15 16 18
19 17 18 20
21 19 20 22 PCH_WL_OFF# <18>
21 22 PLT_RST# <18,23,37,42>
23 24 +3VS_WLAN
2 <15> PCIE_PRX_DTX_N2 25 23 24 26
2
<15> PCIE_PRX_DTX_P2 25 26
27 28
29 27 28 30 1 R501 2 @ 0_0402_5%
29 30 SMB_CLK_S3 <12,13,15>
31 32 1 R502 2 @ 0_0402_5%
<15> PCIE_PTX_C_DRX_N2 31 32 SMB_DATA_S3 <12,13,15>
33 34
<15> PCIE_PTX_C_DRX_P2 35 33 34 36
+3VS_WLAN 35 36 USB20_N10 <18>
37 38
39 37 38 40 USB20_P10 <18>
41 39 40 42
43 41 42 44
100_0402_1% 45 43 44 46
R505 47 45 46 48
1 2 49 47 48 50
<42> EC_TX 1 2 EC_RX_R 51 49 50 52
<42> EC_RX 51 52
R506
100_0402_1% 53 54
R801 2 1 1K_0402_5% GND1 GND2
<19> INTEL_BT_OFF#
LOTES_AAA-PCI-046-K01
2
For EC to detect ME@

R507
debug card insert. 100K_0402_5%
3 3
1
Reserve for SW mini-pcie debug card.

Series resistors closed to KBC side.
4 4

Mini-Card/NEW Card/SIM
1.0
A B C D E
5 4 3 2 1
For LAN & Green CLK +3VALW +3V_LAN

+LX
Close together
J12
@ LL2 LL3 SWR@
1 2 LL1 SWR@
1 2 +LX_R 1 2 +LX FBMA-L11160808601LMA10T_2P FBMA-L11160808601LMA10T_2P
1000P_0402_50V7K
1 2 1 2
10U_0603_6.3V6M
4.7UH_SIA4012-4R7M_20% +1.1_AVDDL_L +1.1_AVDDL +LX_R
0.1U_0402_16V4Z
JUMP_43X79
CL1
CL2
0.1U_0402_16V4Z
1U_0402_6.3V4Z
4.7U_0603_6.3V6K
1 1
CL4
CL5
CL6
D
Note: Place Close to LAN chip 1 1 1 D
3 1
D
2 2 LL1 DCR< 0.15 ohm
CL3
@ Rate current > 1A
RL3 2 2 2
QL1
G
2
@
LAN_PWR_ON# 2 1 LP2301ALT1G-SOT23-3
<42> LAN_PWR_ON# 10U
2
@
10K_0402_5% CL7 SWR@SWR@SWR@
1
0.1U_0402_16V7K Place close to Pin34
Close to
Pin40
Vendor recommand reseve the

PU resistor close LAN chip
RL4 1 2 4.7K_0402_5% UL1 8172@ +3V_LAN

+3V_LAN
@
PLT_RST#
<18,23,36,42> PLT_RST#
QCA8172-BL3A-R
0.1U_0402_16V4Z
1U_0402_6.3V4Z
Pin Configure signal Description
CL10
CL8
1 Switch mode regulator(SWR) mode 1 1
LED[1] Regulator select
@
C
Place Close to Chip UL1
0 Linear regulator (LDO) mode
* 2 2
C
CL9 1 2 0.1U_0402_16V7K PCIE_PRX_C_DTX_N1 29 38 RL12 10K_0402_5%

<15> PCIE_PRX_DTX_N1 TX_N LED_0 39 2 LDO@ 1 mount RL12 if use LDO modue
CL11 1 2 0.1U_0402_16V7K PCIE_PRX_C_DTX_P1 30
Atheros LED_1 23
<15> PCIE_PRX_DTX_P1 TX_P LED_2
AR8151/AR8161 Place close to Pin16
36
<15> PCIE_PTX_C_DRX_N1 RX_N 12 MDI0-
35 TRXN0 11 MDI0- <38>
MDI0+
<15> PCIE_PTX_C_DRX_P1 RX_P TRXP0 MDI0+ <38>
15 MDI1-
TRXN1 MDI1- <38>
32 14 MDI1+
<15> CLK_PCIE_LAN# 33 REFCLK_N TRXP1 18 MDI1+ <38>
<15> CLK_PCIE_LAN REFCLK_P TRXN2 17
PLT_RST# 2 TRXP2 21
PERST# TRXN3 20
PCIE_WAKE#_R 3 TRXP3 Place Close to PIN1
RL7 1 @ 2 0_0402_5% W AKE#
<42> LAN_WAKE# +3V_LAN
25 10 LAN_RBIAS 1 2
RL9 1 2 4.7K_0402_5% 26 SMCLK RBIAS RL8 2.37K_0402_1%
+3V_LAN SMDATA
@ Place Close to PIN1
28 1 +3V_LAN
NC VDD33
CL12
CL13
CL14
CL15
CL16
1000P_0402_50V7K
27
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V4Z
Vendor recommand reseve the
0.1U_0402_16V4Z
TESTMODE 1 1 1 1
2
PU resistor close LAN chip 40 +LX
LX +LX
LAN_XTALO 7 @
don't @ (could be B C cost done)
1
LAN_XTALI 8 XTLO RL10 30K_0402_5% 2 2 2 2
RL11 1 @ 2 4.7K_0402_5% XTLI 5 +1.7_VDDCT 1 2
+3V_LAN VDDCT/ISOLAN +3V_LAN
4
<15> CLKREQ_LAN# CLKREQ# 24 @ @
B DVDDL/PPS 37 +LX_R B
+1.1_AVDDL 13 DVDDL_REG/DVDDL
+1.1_AVDDL 19 AVDDL +2.7_AVDDH
+1.1_AVDDL 31 AVDDL 16 +3V_LAN
+1.1_AVDDL_L 34 AVDDL AVDDH/AVDD33 22 +2.7_AVDDH
+1.1_AVDDL 6 AVDDL AVDDH 9 +2.7_AVDDH
AVDDL_REG/AVDDL AVDDH_REG
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
CL17
CL18
CL19
CL20
CL21
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 1 1 1 1
CL22
CL23
CL24
CL25
CL26
41 1 1 1 1 1
GND
AR8162-BL3A-R_QFN40_5X5 @ @
2 2 2 Near 2 2 8162@
2 2 2 2 2
Pin6
@
For EMI
B Phaes change to GCLK@
Near
Near Near Near Pin9 Near Near
@
Pin13 Pin19 Pin31 RL13 1 2 0_0402_5% Pin22 Pin37
<44> GCLK_LAN_25MHZ
1
CL27
value shoud be discuss 5P_0402_50V8C
2 @
ORB 5P LAN_XTALI
A YL1 LAN_XTALO A
4 3
NC OSC
1 2
OSC NC
1 25MHZ_10PF_7V25000014 1
CL28 CL29
15P_0402_50V8J 15P_0402_50V8J
NOGCLK@
NOGCLK@ 2 NOGCLK@ 2
LAN-AR8162/8172
Custom
VILG1/G2 MB LA9901P Schematic 1.0
5 4 3 2 1
5 4 3 2 1
ESD
@
DL1
Place Close to TL1 AZC099-04S.R7G_SOT23-6 Reserve gas tube for EMI go rural solution
MDI1+ 1 4 MDI0+
I/O1 I/O3
D D
DL1 2 5
1'S PN:SC300001G00
GND VDD
For EMI
MDI0- 3 6 MDI1-
2'S PN:SC300002E00 I/O2 I/O4
RL14 CL30
1 2 1 2
CHASSIS1_GND
75_0805_5% 10P_0603_50V
2 1
TL1
DLL1
MDI0+ 1 16 MDO0+ BS4200N-C-LV_SMB-F2
<37> MDI0+ 2 TD+ TX+ 15
MDI0- MDO0- GAS@
<37> MDI0- TD- TX-
3 14 MCT
4 CT CT 13
5 NC NC 12
NC NC Place Close to TL1
6 11 MCT
C
For EMI 1
CL31
<37>
<37>
MDI1+
MDI1-
MDI1+
MDI1-
7
8
CT
RD+
RD-
CT
RX+
RX-
10
9
MDO1+
MDO1-
C
12/12 Change BOM Structure of CL31 from @ to

mount(EMI request) 2
0.01U_0402_16V7K
MHPC_NS681612A For EMI
CL63 1 2 0.1U_0603_50V7K
CHASSIS1_GND
JLAN1
MCT 8
PR4-
MCT 7
PR4+
B B
MDO1- 6
PR2-
MCT 5
PR3-
MCT 4
PR3+
MDO1+ 3
PR2+
MDO0- 2
PR1-
MDO0+ 1
PR1+
10
SHLD1
9
SHLD2
PS_HPKR0125-08A1A0R
ME@
CHASSIS1_GND
A A

LAN_Transformer
B
VILG1/G2 MB LA9901P Schematic 1.0
5 4 3 2 1
5 4 3 2 1
2 Channel
D D
SMSC thermal sensor

placed near VRAM
+3VS
U9
1 8 EC_SMB_CK2
VDD SCLK EC_SMB_CK2 <15,23,42>
REMOTE1+ 2 7 EC_SMB_DA2
D+ SDATA EC_SMB_DA2 <15,23,42>
REMOTE1- 3 6
D- ALERT#
C +3VS 1 R335 2 4 5 C
THERM# GND
4.7K_0402_5% REMOTE1+
@ EMC1402-2-ACZL-TR MSOP 8P
1
1
Address is 1001100xb C
C587 2 Q11
2200P_0402_50V7K B MMST3904-7-F_SOT323-3
OPT@ 2 E OPT@
3
REMOTE1-
REMOTE1,2+/-:
Trace width/space:10/10 mil
Trace length:<8"
B B
MINI WLAN VGA CPU

H1 H2 H3 H4 H5 H6 H7
H_3P3 H_3P3 H_3P3 H_3P3 H_3P8 H_3P8 H_3P8 FD1 FD2 FD3 FD4
1
1
FAN1 Conn
+5VS
@
R581 11/20 Change symbol of JFAN1 to SP020008X00
JFAN1
2 1 1
2 1 H14 H15 H19 H20 H21 H22 H23
0_0603_5%
<42> EC_TACH
<42> EC_FAN_PWM
3 2
3
H_2P8 H_2P8 H_2P8 H_2P8 H_4P6 H_2P8 H_2P8 R
4 H16 H17 H24 H25
5 4 H_3P0X4P0N H_7P0N H_3P0N H_3P0N
2 G5
6
1
1
C591 G6
10U_0603_6.3V6M ACES_85205-04001
1
1 ME@
SP020008X00
M/B
E
㨊⚻⫼ M/B ⚻⫼ A

Fintek-Thermal IC/FAN/screw
Custom 1.0
5 4 3 2 1
A B C D E F G H
SATA HDD Conn.

Near Connector
JHDD1
1
0.01U_0402_25V7K 2 1 C184 SATA_ITX_DRX_P0 2 GND
<14> SATA_ITX_C_DRX_P0 RX+
<14> SATA_ITX_C_DRX_N0 0.01U_0402_25V7K 2 1 C185 SATA_ITX_DRX_N0 3
4 RX-
SATA_DTX_C_IRX_N0 C596 1 2 0.01U_0402_25V7K SATA_DTX_IRX_N0 5 GND
<14> SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_P0 C597 1 2 0.01U_0402_25V7K SATA_DTX_IRX_P0 6 TX-
<14> SATA_DTX_C_IRX_P0 7 TX+
GND
1 1
R551 0_0805_5% 8
1 2 +3VS_HDD 9 3.3V 26
+3VS 3.3V boss
10 25
@ 11 3.3V boss
12 GND 24
13 GND GND 23
R550 0_0805_5% 14 GND GND
1 2 +5VS_HDD 15 5V
+5VS 5V
16
@ 17 5V
18 GND
19 Rsv
20 GND
21 12V
+5VS_HDD 22 12V
12V
Near HDD LCN_ASF98-2231S10-0002
1 1 1 ME@
@
C598 C599 C602
1000P_0402_50V7K 0.1U_0402_16V4Z 10U_0603_6.3V6M
2 2 2
ODD Power Control 1/16 Change footprint of JHDD1 from SANTA_191501-1_22P to

LCN_ASF98-2231S10-0002_22P (DC010005W00 toDC010009C00)
2 2
@ J9
1 2
1 2 +5V_ODD FOR 15"
+5VALW +5VS JUMP_43X79
SATA ODD FFC Conn.
Near Connector
S
3 1 JODD2
1
1
1
Q99 <14> SATA_ITX_C_DRX_P2 SATA_ITX_C_DRX_P2 15@C605 1

15@C605 2 0.01U_0402_25V7K SATA_ITX_DRX_P2_15 2
R552 @ PMV65XP_SOT23-3~D SATA_ITX_C_DRX_N2 15@C606 1
15@C606 2 0.01U_0402_25V7K SATA_ITX_DRX_N2_15 3 2
G
<14> SATA_ITX_C_DRX_N2
2
R568 10K_0402_5% @ 4 3
10K_0402_5% R675 SATA_DTX_C_IRX_N2 R403 1 15@ 2 0_0402_5% SATA_DTX_IRX_N2_15 5 4
@ 100K_0402_5% <14> SATA_DTX_C_IRX_N2 SATA_DTX_C_IRX_P2 R404 1 15@ 2 0_0402_5% SATA_DTX_IRX_P2_15 6 5
1
2
1 2 <14> SATA_DTX_C_IRX_P2 1 2 ODD_DETECT# 7 6

@ C608 R710 @ 0_0402_5% +5V_ODD 8 7
8
1
1 10U_0603_6.3V6M 9
2 ODD_DA# 10 9
OUT
@ C607 <42> ODD_DA# 10 11

GND 12
0.01U_0402_25V7K GND
2 2 1 R555 2
<19> ODD_EN IN +3VS
10K_0402_5% ACES_88058-100N
GND
@ ME@
Q100 SP010016C00
DTC124EKAT146_SC59-3
3
@ 11/20 Change symbol of JODD2 to SP010016C00
3 3
Co-lay
FOR 14"
SATA ODD Conn.
Near Connector JODD1
1
SATA_ITX_C_DRX_P2 14@C616 1
14@C616 2 0.01U_0402_25V7K SATA_ITX_DRX_P2_14 2 GND
SATA_ITX_C_DRX_N2 14@C615 1
14@C615 2 0.01U_0402_25V7K SATA_ITX_DRX_N2_14 3 A+
4 A-
SATA_DTX_C_IRX_N2 14@C614 1
14@C614 2 0.01U_0402_25V7K SATA_DTX_IRX_N2_14 5 GND
SATA_DTX_C_IRX_P2 14@C613 1
14@C613 2 0.01U_0402_25V7K SATA_DTX_IRX_P2_14 6 B-
7 B+
GND
ODD_DETECT# 8
+5V_ODD 9 DP
10 +5V 14
ODD_DA# 11 +5V GND 15
12 MD GND 16
13 GND GND 17
GND GND
4 SANTA_202801-1 4
ME@

HDD/ODD/BT Connector
Custom 1.0
A B C D E F G H
5 4 3 2 1
CX20757 Sense resistors must be

connected same power
High Definition Audio Codec SoC that is used for VAUX_3.3
With Integrated Class-D Stereo
RA5 1 2 5.11K_0402_1% +3VS
Amplifier.
An integrated 5 V to 3.3 V Low-dropout RA6 10K_0402_1%
mount RA6 on the Jack Sense circuit
voltage regulator (LDO). 1 2 to configure Port-C for mono MIC.
An integrated 3.3 V to 1.8V Low-dropout JSENSE RA7 1 2 20K_0402_1%

voltage regulator (LDO). RA8 1 2 39.2K_0402_1% PLUG_IN
PLUG_IN <43>
+VREF_1V65 CA3 vendor suggest
For no Speaker Hum Noise feature
For Universal jack
D change to 2.2U Don't support LINE_IN function D
+LDO_OUT_3.3V
RA7 could be @
RA11 1 @ 2 0_0402_5% +3V_AVDD_HP
1U_0603_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+3VLP
2.2U_0603_6.3V4Z
1 1 2 1 AVDD_3.3 pinis output of
CA1
CA2
CA4
RA10 1 @ 2 0_0402_5%
internal LDO. NOT connect
0.1U_0402_16V4Z
4.7U_0603_6.3V6K
+3V_PCH
CA3
1 1 to external supply.
CA5
CA6
2 2 1 2
2 @ 2
+3VS
+3VS
1U_0603_10V4Z
1U_0603_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 1
CA8
CA9
1 1
CA15
CA10
@
Should be same supply rail as used for @
2 2 Layout Note:Path from +5VS to LPWR_5.0
PCH HDA bus controller section 2 2
RPWR_5.0 must be very low
resistance (<0.01 ohms)
RA3
+3VS
1 @ 2 0_0402_5% +VDDIO_HDA
4.7U_0603_6.3V6K
0.1U_0402_16V4Z +LDO_1.8V +5VS

+3V_PCH RA4 1 @ 2 0_0402_5% 1 1
CA16
CA17
0.1U_0402_16V4Z
4.7U_0603_6.3V6K
+5VS
1 1
CA18
CA19
10 mils
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
@ 2 2
1 1 1 1
CA20
CA21
CA22
CA23
@
4.7U_0603_6.3V6K
0.1U_0402_16V4Z
2 2
CA24 1 1
CA25
@
For EMI 2 2 2 2
0.1U_0402_16V4Z
@ 2 2 For Layout
18
29
27
28
24
C 1 C
3
7
2
CA26
CA7 @ UA1
1 RA21 2 For Layout
FILT_1.8
VDDO_3.3
DVDD_3.3
AVDD_3.3
VDD_IO
VREF_1.65V
AVDD_5V
AVDD_HP
Please bypass caps very close to device.
22P_0402_50V8J 33_0402_5% 13 2
LPWR_5.0 16
HDA_RST_AUDIO# 9 RPWR_5.0 11
<14> HDA_RST_AUDIO# RESET# CLASS-D_REF
HDA_BITCLK_AUDIO 5
<14> HDA_BITCLK_AUDIO BIT_CLK
HDA_SYNC_AUDIO 8 38 JSENSE
<14> HDA_SYNC_AUDIO SYNC JSENSE
RA9 1 2 33_0402_5% HDA_SDIN0_R 6
<14>
<14> HDA_SDIN0
HDA_SDOUT_AUDIO
HDA_SDOUT_AUDIO 4 SDATA_IN
SDATA_OUT MICBIASB
MICBIASC
34
35
+MICBIASB
+MICBIASC
For EMI HGNDA, HGNDB 80mils
PC_BEEP 10 32 MICB_L
39 PC_BEEP PORTB_L_LINE 33 MICB_R APPLE_MIC RA16 1 2 100_0402_1% CA28 1 2 2.2U_0402_6.3V6M HGNDB
<42> EC_MUTE# SPKR_MUTE# PORTB_R_LINE Universal Jack NOKIA_MIC RA12 1 2 100_0402_1% CA27 1 2 2.2U_0402_6.3V6M HGNDA
HGNDB <43>
HGNDA <43>
30 APPLE_MIC External MIC HP_L RA13 1 2 15_0402_5% HPOUT_L
PORTD_A_MIC HPOUT_L <43>
31 NOKIA_MIC HP_R RA14 1 2 15_0402_5% HPOUT_R
PORTD_B_MIC HPOUT_R <43>
1 25 HGNDA
40 DMIC_DAT/GPIO1 HGNDA 26 HGNDB
For EMI MIC_IN 36
DMIC_CLK / MUSIC_REQ/GPIO0 HGNDB
22 HP_L
Internal analog MIC 37 MUSIC_REQ/GPIO0/PORTC_L_MIC PORTA_L 23 HP_R
For Universal jack
GPIO1/PORTC_R_MIC PORTA_R Headphone
CA64 1 2 0.1U_0402_16V7K
SPK_L2+ 12
CA65 1 2 0.1U_0402_16V7K SPK_L1- 14 LEFT+ CA36
LEFT- MICB_L RA17 1 2 100_0402_1% 1 2 HP_L
Internal SPEAKER 21 2.2U_0402_6.3V6M
CA66 1 2 0.1U_0402_16V7K SPK_R2+ 17 AVEE 19 CA46
SPK_R1- 15 RIGHT+ FLY_P 20 1 2 MICB_R RA18 1 2 100_0402_1% 1 2 HP_R
0.1U_0402_16V4Z
2.2U_0603_6.3V4Z
RIGHT- FLY_N CA29 1U_0603_10V4Z 2.2U_0402_6.3V6M
1 2
RA20 1 2 3K_0402_5%
CA35
CA30
GND
12/12 Change BOM Structure of CA64~CA66 from @ to +MICBIASB RA19 1 2 3K_0402_5%

B 2 1 B
CX20751-11Z_QFN40
mount(EMI request)
41
follow vendor suggest

& reserver default design
LA1 LA2
0_0603_5% 0_0603_5% 11/20 Change symbol of JSPK1 to SP02000H700
@ @
LA3 LA4
0_0603_5% 0_0603_5%
PC Beep @ @ JSPK1
EC Beep
wide 40MIL 6
5 GND2
GND1
<42> BEEP# 1 2 RA492
CA37 0.1U_0402_16V4Z 1 2 PC_BEEP SPK_R1- LA1 1 2
FBMA-L11-160808-121LMT_0603 SPK_R1-_CONN 4
1 2 33_0402_5% SPK_R2+ LA2 1 2
FBMA-L11-160808-121LMT_0603 SPK_R2+_CONN 3 4
<14> HDA_SPKR 3
CA45 0.1U_0402_16V4Z SPK_L1- LA3 1 2
FBMA-L11-160808-121LMT_0603 SPK_L1-_CONN 2
ICH Beep Place colose to Codec chip SPK_L2+ LA4 1 2
FBMA-L11-160808-121LMT_0603 SPK_L2+_CONN 1 2
1
1
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
RA22
10K_0402_5%
+MICBIASC For EMI 1 1 1 1 +5VS
SP02000H700
ME@
CA38
CA39
CA40
CA43
ESD ACES_88231-04001
@
2
DA3
RA23 2 2 2 2 SPK_R1-_CONN 6 3 SPK_L2+_CONN
2.2K_0402_5% For EMI I/O4 I/O2
2
MIC1 CA41 1U_0603_10V4Z 5 2

A 1 EXT_MIC 1 2 MIC_IN VDD GND A
2 GNDA
1 1
WM-64PCY_2P SPK_R2+_CONN 4 1 SPK_L1-_CONN
0.1U_0402_16V4Z
0.1U_0402_16V4Z
MIC@ I/O3 I/O1

AZC099-04S.R7G_SOT23-6
2 2
CA42
CA44
@ @
CX20757-11Z Codec
Custom
VILG1/G2 MB LA9901P Schematic1.0
5 4 3 2 1
+3VALW
+3VLP
@
R304 R416
2 1 +3V_EC 1 2
0_0603_5% 1
@ 0_0603_5% C535
100P_0402_50V8J
@ 3.3V
L44 2 Vcc
FBM-11-160808-601-T_0603 100K +/- 1%
1 1 1 1
+EC_VCCA R694
0.1U_0402_16V4Z
C653
0.1U_0402_16V4Z
C654
1000P_0402_50V7K
C657
1000P_0402_50V7K
C658
1 2
+3V_EC +EC_VCCA
@ @ Board ID min typ
1 R695 VAD_BID V AD_BID VAD_BID max EC AD
C656 2 2 2 2
0 0 0 V 0 V 0.300 V 0x00 - 0x0B MP
111
125
0.1U_0402_16V4Z U31
22
33
96
67
9
1 2 2 ECAGND
1 12K +/- 1% 0.347 V 0.354 V 0.360 V 0x0C - 0x1C PVT
L45
EC_VDD0
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/AVCC
FBM-11-160808-601-T_0603 15K +/- 1%
2 0.423 V 0.430 V 0.438 V 0x1D - 0x26 DVT
ECAGND 20K +/- 1%
1 21 ADP_65
3 0.541 V 0.550 V 0.559 V 0x27 - 0x30 EVT
<19> GATEA20 GATEA20/GPIO00 GPIO0F ADP_65 <48>
2 23 BEEP#
<19> KBRST# KBRST#/GPIO01 BEEP#/GPIO10 BEEP# <41>
3 26 EC_FAN_PWM +3VALW
<14> SERIRQ SERIRQ GPIO12 EC_FAN_PWM <39>
4 27 ACOFF
<14> LPC_FRAME# LPC_FRAME# ACOFF/GPIO13 ACOFF <49>
LPC_AD3 5
<14> LPC_AD3
2
LPC_AD2 7 LPC_AD3
<14> LPC_AD2 LPC_AD2 PWM Output
LPC_AD1 8 63 BATT_TEMP
<14> LPC_AD1 LPC_AD1 BATT_TEMP/GPIO38 BATT_TEMP <47,48>
LPC_AD0 10 LPC & MISC 64 GPU_IMON R694
<14> LPC_AD0 LPC_AD0 GPIO39 GPU_IMON <55>
2 1 2 1 65 ADP_I +5VALW 100K_0402_1%
ADP_I/GPIO3A ADP_I <48,49>
@ C660 22P_0402_50V8J @ R589 10_0402_5% 12 AD Input 66 ADP_ID
<18> CLK_PCI_EC ADP_ID <47>
1
13 CLK_PCI_EC GPIO3B 75 BRDID BRDID
<18,23,36,37> PLT_RST# PCIRST#/GPIO05 GPIO42
1 2 EC_RST# 37 76
+3V_EC ENBKL <17>
2
R590 47K_0402_5% EC_SCI# 20 EC_RST# IMON/GPIO43
<19> EC_SCI# EC_SCII#/GPIO0E
2 BATT_LEN# 38 R594 @
<48> BATT_LEN# GPIO1D
1 68 ADP_90 USB_ON# 1 2 R695
DAC_BRIG/GPIO3C ADP_90 <48>
C661 C47 70 12K_0402_1%
0.1U_0402_16V4Z EN_DFAN1/GPIO3D 71 GC6_FB_CLAMP 10K_0402_5%
DA Output GC6_FB_CLAMP <23,27>
1
1 100P_0402_50V8J KSI0 55 IREF/GPIO3E 72 +3VALW
2 KSI0/GPIO30 CHGVADJ/GPIO3F GC6_FB_CLAMP_TGL_REQ# <23>
KSI1 56
KSI2 57 KSI1/GPIO31 EC_MUTE# 1 R593 2 10K_0402_5%
KSO[0..17] KSI3 58 KSI2/GPIO32 83
<43> KSO[0..17] KSI4 59 KSI3/GPIO33 EC_MUTE#/GPIO4A 84 USB_ON#
EC_MUTE# <41> 3/20 Add (ESD request)
KSI[0..7] KSI4/GPIO34 USB_EN#/GPIO4B USB_ON# <43,45>
ESD KSI5 60 85 ADP_135
<43> KSI[0..7] KSI5/GPIO35 CAP_INT#/GPIO4C ADP_135 <48>
KSI6 61 PS2 Interface 86 SYS_PWROK_R R417 1 @ 2 0_0402_5%
KSI6/GPIO36 EAPD/GPIO4D SYS_PWROK <16> +5VS
KSI7 62 87 TP_CLK
KSI7/GPIO37 TP_CLK/GPIO4E TP_CLK <43> +5VS
KSO0 39 88 TP_DATA
KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA <43>
KSO1 40 2
KSO2 41 KSO1/GPIO21 TP_CLK R603 1 2 4.7K_0402_5%
KSO3 42 KSO2/GPIO22 97 EC_TS_ON# C851 @ TP_DATA R598 1 2 4.7K_0402_5%
KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 EC_TS_ON# <45>
KSO4 43 98 VGA_AC_DET 0.1U_0402_16V4Z
KSO4/GPIO24 WOL_EN/GPXIOA01 VGA_AC_DET <23> 1
KSO5 44 99 ME_FLASH
KSO6 45 KSO5/GPIO25 Int. K/B HDA_SDO/GPXIOA02 109
ME_FLASH <14>
KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 NTC_V <48>
+3V_EC KSO7/GPIO27 SPI Device Interface
KSO8 47
R600 KSO9 48 KSO8/GPIO28 119 EC_SPI_SO BATT_TEMP 1 2
KSO9/GPIO29 SPIDI/GPIO5B EC_SPI_SO <14>
1 2 EC_SMB_CK1 KSO10 49 120 EC_SPI_SI C663 100P_0402_50V8J
KSO10/GPIO2A SPIDO/GPIO5C EC_SPI_SI <14>
2.2K_0402_5% KSO11 50 SPI Flash ROM 126 EC_SPI_CLK 10/26 Add(Reserve for SPI ROM Interface share) ACIN 1 2
KSO11/GPIO2B SPICLK/GPIO58 EC_SPI_CLK <14>
R604 KSO12 51 128 EC_SPI_CS# C664 100P_0402_50V8J
KSO12/GPIO2C SPICS#/GPIO5A EC_SPI_CS# <14>
1 2 EC_SMB_DA1 KSO13 52
2.2K_0402_5% KSO14 53 KSO13/GPIO2D 1 R522 2
KSO15 54 KSO14/GPIO2E 73 4.7K_0402_5%
KSO15/GPIO2F ENBKL/GPIO40 IMVP_IMON <55>
KSO16 81 74 VGATE @
KSO16/GPIO48 PECI_KB930/GPIO41 VGATE <16,55>
KSO17 82 89
KSO17/GPIO49 FSTCHG/GPIO50 LAN_PWR_ON# <37>
90 BATT_CHG_LED#
BATT_CHG_LED#/GPIO52 BATT_CHG_LED# <43>
91 CAPS_LED#
CAPS_LED#/GPIO53 CAPS_LED# <43>
EC_SMB_CK1 77 GPIO 92
<48,49> EC_SMB_CK1 EC_SMB_CK1/GPIO44 PWR_LED#/GPIO54 PWR_LED# <43>
+3VALW EC_SMB_DA1 78 93 BATT_LOW_LED#
<48,49> EC_SMB_DA1 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 BATT_LOW_LED# <43>
EC_SMB_CK2 79 SM Bus 95 SYSON
<15,23,39> EC_SMB_CK2 EC_SMB_CK2/GPIO46 SYSON/GPIO56 SYSON <51>
EC_SMB_DA2 80 121
<15,23,39> EC_SMB_DA2 EC_SMB_DA2/GPIO47 VR_ON/GPIO57 VR_ON <55>
127 PM_SLP_S4# <16>
1 2 LAN_WAKE# PM_SLP_S4#/GPIO59
R606 10K_0402_5% H_PROCHOT# <47,55,6>
6 100
<16> PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 EC_RSMRST# <16>
14 101 EC_LID_OUT#
<16> PM_SLP_S5# EC_LID_OUT# <19>
1
EC_SMI# 15 PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 102 Turbo_V D
<16,19> EC_SMI# EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 Turbo_V <48> 1
16 103 PROCHOT 2
<33> CMOS_ON# GPIO0A H_PROCHOT#_EC/GPXIOA06 PROCHOT <48>
+3VS OVERT#_R 17 104 MAINPWON_R R738 1 2 0_0402_5% G C493
<23> OVERT#_R GPIO0B VCOUT0_PH/GPXIOA07 MAINPWON <50>
18 GPO 105 BKOFF# @ Q37 S 47P_0402_50V8J
<54> EC_VGA_EN BKOFF# <33>
3
ODD_DA# 19 GPIO0C BKOFF#/GPXIOA08 106 PBTN_OUT# 2N7002H_SOT23-3 2
<40> ODD_DA# GPIO0D GPIO PBTN_OUT#/GPXIOA09 PBTN_OUT# <16>
ADP_ID_CLOSE 25 107 PCH_PWR_EN
<47> ADP_ID_CLOSE EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10 PCH_PWR_EN <20>
1 2 EC_TACH EC_TACH 28 108 SA_PGOOD <52>
<39> EC_TACH FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11
R605 10K_0402_5% LAN_WAKE# 29
<37> LAN_WAKE# EC_PME#/GPIO15
EC_TX 30 +3VALW
<36> EC_TX EC_TX/GPIO16
EC_RX 31 110 ACIN
<36> EC_RX EC_RX/GPIO17 AC_IN/GPXIOD01 ACIN <16,47,49>
PCH_PWROK 32 112 EC_ON
<16> PCH_PWROK PCH_PWROK/GPIO18 EC_ON/GPXIOD02 EC_ON <50>
NOVO# 34 114 ON/OFF <43>
<43> NOVO# SUSP_LED#/GPIO19 ON/OFF/GPXIOD03
2 1 NUM_LED# 36 GPI 115 LID_SW# LID_SW# 1 R618 2
<43> NUM_LED# NUM_LED#/GPIO1A LID_SW#/GPXIOD04 LID_SW# <43>
@ R608 116 SUSP# 100K_0402_5%
SUSP#/GPXIOD05 SUSP# <46,51,53> +V1.05S_VCCP
10K_0402_5% 117 NUVOTON_VTT
GPXIOD06 118 PECI_KB9012 1 2
PECI_KB9012/GPXIOD07 H_PECI <6>
AGND/AGND
122 R669 43_0402_1% NUVOTON_VTT R410 1 @ 2 0_0402_5%

<16> SUSCLK XCLKI/GPIO5D
GND/GND
GND/GND
GND/GND
GND/GND
DGPU_PWR_EN 123 124 +V18R

<18,23,25> DGPU_PWR_EN XCLKO/GPIO5E V18R
C667
4.7U_0603_6.3V6K
1
1
GND0
1
R740 C93
100K_0402_5% 20P_0402_50V8 KB9012QF A4 LQFP 128P_14X14 2
2
11
24
35
94
113
69
@ @
2
ECAGND
EMC Request
SYSON
C492
PN : SA00004OB20 S IC KB9012QF A3 LQFP 128P KB CONTROLLER
0.1U_0402_10V6K
1
@
2

BIOS & EC I/O Port
Custom 1.0
PWR Button For Debug Key Board Conn. KSI[0..7]
KSO[0..17]
KSI[0..7] <42>
KSO[0..17] <42>
For 15" For 14"

+3VLP
JKB1
KSI1 1 JKB2
KSI7 2 1 KSI1 1
2 1
2
KSI6 3 KSI7 2
R415 KSO9 4 3 KSI6 3 2
100K_0402_5% KSI4 5 4 KSO9 4 3
@ KSI5 6 5 KSI4 5 4
@ 6 5
KSO0 7 KSI5 6
1
+3VLP 1 R414 2 KSI2 8 7 KSO0 7 6
0_0402_5% KSI3 9 8 KSI2 8 7
KSO5 10 9 KSI3 9 8
10 9
2
KSO1 11 KSO5 10
+3VALW KSI0 12 11 KSO1 11 10
R701 +3VS KSO2 13 12 KSI0 12 11
100K_0402_5% KSO4 14 13 KSO2 13 12
2
KSO7 15 14 KSO4 14 13
1
R642 KSO8 16 15 KSO7 15 14

100K_0402_5% KSO6 17 16 KSO8 16 15
17 16
1
KSO3 18 KSO6 17
R745 R744 KSO12 19 18 KSO3 18 17
1
ON/OFF D26 KSO13 20 19 KSO12 19 18
ON/OFF <42> 300_0402_5% 300_0402_5% 20 19
NOVO# 2 15@ KSO14 21 KSO13 20
<42> NOVO# 1 22 21 21 20
NOVO_BTN# KSO11 KSO14
2
ON/OFF 3 KSO10 23 22 KSO11 22 21
KSO15 24 23 KSO10 23 22
KB1 25 24 KSO16 R747 1 15@ 2 0_0402_5% KSO15 24 23
DAN202UT106_SC70-3 KB2 26 25 KB_LED_PWR R746 1 14@ 2 0_0402_5% KB1 25 24
KB_LED_PWR 27 26 KSO17 R748 1 15@ 2 0_0402_5% KB2 26 25
28 27 CAPS_LED# R749 1 14@ 2 0_0402_5% 26 27
<42> CAPS_LED# 28 GND2
KB_LED_PWR_2 29 31 28
30 29 GND 32 GND1
<42> NUM_LED# 30 GND
ACES_88514-3001 ACES_88514-02601-071
ME@ ME@
SP010011A00
11/20 Change symbol of
JKB1 to SP010011A00
IO/B Conn.
For EMI
Ext. USB2.0 R868 2 @ 1 0_0402_5%
+3VS
JIO1
14 16
L66 USB20_N11 13 14 G2 15
4 3 <18> USB20_N11 12 13 G1
USB20_N9 USB20_N9_R USB20_P11
<18> USB20_N9 4 3 +USB_VCCB <18> USB20_P11 12
W=80mils 11
USB20_N9_R 10 11
USB20_P9 1 2 USB20_P9_R USB20_P9_R 9 10
<18> USB20_P9 1 2 9
+USB_VCCB 8
2
+5VALW +USB_VCCB WCM-2012-900T_4P @ @ 7 8
1 7
R503 R504 C714 1 6
U36 + HPOUT_L 5 6
10_0402_5% 10_0402_5% <41> HPOUT_L 5
1 8 R869 2 @ 1 0_0402_5% 220U_6.3V_M C715 HPOUT_R 4
GND VOUT <41> HPOUT_R 4
2 7 470P_0402_50V7K HGNDA 3
1
3 VIN VOUT 6 2 2 <41> HGNDA 2 3
HGNDB
VIN VOUT <41> HGNDB 2
4 5 1 1 PLUG_IN 1
<42,45> USB_ON# EN FLG USB_OC4# <18> 6.3ĭ * 5.9 <41> PLUG_IN 1
@ @
G547I2P81U_MSOP8 C701 C702 SF000001500 ACES_85202-1405N
1.2P_0402_50V8C 1.2P_0402_50V8C ME@
2 2
11/30 Change U36 symbol & PN from SA00003XM00 to SA00003TV00
TP Switch & TP Conn. LED PWR/B Conn.

+5VS LED1 14@
JPWRB1
<42> PWR_LED# PWR_LED# 1 2 2 R623 1 +3VALW 1
300_0402_5% 2 1
NOVO_BTN# 3 2
14@ 3
JTP1 19-213A-T1D-CP2Q2HY-3T_WHITE ON/OFF 4
8 5 4
7 GND LED2 14@ 6 5
2
GND 6
6 BATT_LOW_LED# 1 2 2 R764 1 @ 7
6 <42> BATT_LOW_LED# +3VALW GND
TP_CLK 5 470_0402_5% 8
<42> TP_CLK 4 5 GND
TP_DATA 14@ D24
<42> TP_DATA 4
TP_3 3 19-217-S2C-FM2P1VY-3T_ORANGE ACES_88058-060N
TP_2 2 3 PJSOT24C 3P C/A SOT-23 ME@
1
TP_1 1 2 LED5 14@
1 SP010010T00
ACES_88058-060N BATT_CHG_LED# 1 2 2 R765 1 11/20 Change symbol of
<42> BATT_CHG_LED# +3VALW
C490
C491
ME@ 300_0402_5%
JPWRB1 to SP010010T00
0.1U_0402_10V6K
0.1U_0402_10V6K
1 1 SP010010T00 14@ ESD

15@ 19-213A-T1D-CP2Q2HY-3T_WHITE
2 R627 1 TP_3
0_0402_5% @ @
2 R619 1 14@ TP_1

0_0402_5%
2 2
Lid SW(For 14") +3VALW
JTP1 to SP010010T00
L R LED/B Conn.
2
1
VDD
SW4 14@ SW5 14@ JLED1 14@
SMT1-05_4P SMT1-05_4P
15" 14" 1 C551
+3VALW 1
5
6
5
6
LID_SW# 2 LID_SW# 3 0.1U_0402_16V4Z

4 2 4 2 3 2 <42> LID_SW# OUTPUT 2
TP_3 TP_2
1 VCC 1 VCC PWR_LED# 4 3
GND
3 1 3 1 BATT_LOW_LED# 5 4
5 2
BATT_CHG_LED# 6 C550
2 CLK 2 CLK 6 14@
1
7 10P_0402_50V8J
8 GND 1
3 DAT 3 DAT GND
ACES_88058-060N 11/30 Change PN of U40 from
ME@ 14@ U40
SW6 15@ SW7 15@
4 GND 4 L SA000031C00 to SA00005LN00
S-5712ACDL2-M3T1U_SOT23-3
SMT1-05_4P SMT1-05_4P
SP010010T00
For 15"
5
6
5
6
4 2 4 2
5 L 5 R JLED1 to SP010010T00
TP_2 TP_1
3 1 3 1
GND
6 R 6 2011/06/15 2012/07/11 Title
Issued Date Deciphered Date ROM/KBD/PWR/CR/LED/TP Conn.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
A B C D E
For UMA Every power trace need:

U71 GCLK244@
W=20mils
1 1
SLG3NB244VTR_TQFN16_2X3
For GreenCLK generate CLK:
+CHGRTC_R Mount: All parts in this page except
+RTCBATT
Swing Level RES (Marked "*")
1
+3VLP RG12
NA: PD108,
2
390_0402_5%
GCLK@ RG10 @
0_0402_5% Y1,R98,C180,C181,
2
+V1.05S_VCCP +3V_LAN +3VS_VGA +3V_LAN
1 Y2,R169,C196,C197,
1
CG3 GCLK@
1
22U_0805_6.3V6M Y6,C968,C969
+GCLK_VBAT
0_0402_5%
@ 1 1
1
2
GCLK304@
GCLK@ RG8
CG2
For DIS
RG9
0.1U_0402_16V7K
CG4
0_0402_5%
2.2U_0402_6.3V6M
2
1
2 U71 2 GCLK@
RG11
2
0_0402_5% 1 10 14
2
GCLK@ CG6 VBAT VDD_RTC_OUT
For EMI 2
0.1U_0402_16V7K
@ 1 15
2
CG5 @ @ +V3.3A
2
0.1U_0402_16V7K
2 1 +3VS_GCLK 2
@ CG1 VDD 9 GCLK_32K_R RG1 1 2 0_0402_5% GCLK_32K
CG7
1 2 0.1U_0402_16V7K 32kHz GCLK@
GCLK_32K <14> PCH_32.768K
0.1U_0402_16V7K
2
VGA_GCLK 11
VDDIO_27M 27MHz
12 GCLK_27MHZ_R RG2 1
GCLK304@
2 0_0402_5% GCLK_27MHZ
GCLK_27MHZ <23> NV_GPU
<37> LAN
8 6 GCLK_LAN_25MHZ_R RG3 1 2 0_0402_5% GCLK_LAN_25MHZ
VDDIO_25M_A 25MHz_A GCLK_LAN_25MHZ
GCLK@
<15> PCH_25M
PCH_GCLK 3 5 GCLK_PCH_25MHZ_R RG4 1 2 0_0402_5% GCLK_PCH_25MHZ
VDDIO_25M_B 25MHz_B GCLK_PCH_25MHZ
GCLK@
GREENCLK_XTALI 1
Y8 GREENCLK_XTALO 16 XTAL_IN
XTAL_OUT
Close to GCLK
GND1
GND2
GND3
GND4
4 3
NC OSC
1 2
OSC NC
SLG3NB304VTR_TQFN16_2X3
4
7
13
17
1 GCLK@ 1
GCLK@ CG8 25MHZ_10PF_7V25000014 GCLK@ CG9 GCLK304@
15P_0402_50V8J 15P_0402_50V8J
2 2
3 3
Reserved for Swing Level adjustment

( Close GCLK side )
@
GCLK_27MHZ RG5 *1 2 0_0402_5%
@
GCLK_LAN_25MHZ RG6 *1 2 0_0402_5%
@
GCLK_PCH_25MHZ RG7 *1 2 0_0402_5%
4
For EMI 4

USB ext. ports
B 1.0
A B C D E
5 4 3 2 1
Touch Screen
+3VS +3VS_TS
1 TS@ 2
R799 0_0402_5% +3VS_TS
JTS1
D
1 D
3 1
S
D
1 2
3 2
<18> USB20_N2 3
4
<18> USB20_P2 4
R798 @ Q156 5
G
2
100K_0402_5% PMV65XP_SOT23-3 EC_TS_ON# R726 1 TS@ 2 0_0402_5% TS_RST# 6 5
6
0.1U_0402_16V7K
1 2 @ 7
<42> EC_TS_ON# GND
1 2 8
GND
C669 @ C668 ACES_50208-00601-P01
0.1U_0402_16V7K TS@ ME@
2 1
SP010013W10
JTS1 to SP010013W10
USB3.0
2A/Active Low ESD
+5VALW +USB3_VCCA
D27 D30 D22 D31
@ @ @ @
U35 W=80mils U3RXDN1 9 1U3RXDN1 U3RXDN2 9 1 U3RXDN2 U2DN1 3 6 U2DP2 3 6
1 8 I/O2 I/O4 I/O2 I/O4
2 GND VOUT 7 U3RXDP1 8 2U3RXDP1 U3RXDP2 8 2 U3RXDP2

3 VIN VOUT 6
4 VIN VOUT 5 U3TXDN1 7 4U3TXDN1 U3TXDN2 7 4 U3TXDN2 2 5 2 5
<42,43> USB_ON# USB_OC0# <18> +5VALW +5VALW
EN FLG GND VDD GND VDD
C C
G547I2P81U_MSOP8 U3TXDP1 6 5U3TXDP1 U3TXDP2 6 5 U3TXDP2
11/30 Change U35 symbol & PN from 3 3 1 4 U2DP1 1 4 U2DN2

I/O1 I/O3 I/O1 I/O3
SA00003XM00 to SA00003TV00 1
1 C735 8 8
AZC099-04S.R7G_SOT23-6 AZC099-04S.R7G_SOT23-6
+
C736 470P_0402_50V7K
220U_6.3V_M @ YSCLAMP0524P_SLP2510P8-10-9 YSCLAMP0524P_SLP2510P8-10-9
SF000002Y00 2 2
For EMI
For EMI
Intel_PCH_USB2.0 Intel_PCH_USB2.0
B B
WCM-2012-900T_4P WCM-2012-900T_4P
1 2 U2DN1 1 2 U2DN2
<18> USB20_N0 1 2 <18> USB20_N1 1 2
4 3 U2DP1 4 3 U2DP2
<18> USB20_P0 4 3 <18> USB20_P1 4
USB2@ USB2@ 3
L51 L55
Left Ext.USB Conn. 1

Intel_PCH_USB3.0 Left Ext.USB Conn. 2
WCM-2012-900T_4P +USB3_VCCA
Intel_PCH_USB3.0 WCM-2012-900T_4P +USB3_VCCA
1 2 U3RXDN1
<18> USB3_RX1_N 1 2
W=80mils 1 2 U3RXDN2
<18> USB3_RX2_N 1 2
4 3 U3RXDP1 JUSB1
W=80mils
<18> USB3_RX1_P 4 3
USB3@ U3TXDP1 9 4 3 U3RXDP2 JUSB2
SSTX+ <18> USB3_RX2_P 4
L50 1 USB3@ 3 U3TXDP2 9
U3TXDN1 8 VBUS L54 1 SSTX+
U2DP1 3 SSTX- U3TXDN2 8 VBUS
7 D+ U2DP2 3 SSTX-
U2DN1 2 GND_D 10 7 D+
U3RXDP1 6 D- GND1 11 U2DN2 2 GND_D 10
C849 4 SSRX+ GND2 12 U3RXDP2 6 D- GND1 11
.1U_0402_16V7K WCM-2012-900T_4P U3RXDN1 5 GND GND3 13 C850 4 SSRX+ GND2 12
1 2 U3TXDN1_L 1 2 U3TXDN1 SSRX- GND4 .1U_0402_16V7K WCM-2012-900T_4P U3RXDN2 5 GND GND3 13
<18> USB3_TX1_N 1 2 SSRX- GND4
USB3@ OCTEK_USB-09EAAB 1 2 U3TXDN2_L 1 2 U3TXDN2
<18> USB3_TX2_N USB3@ 1 2
ME@ OCTEK_USB-09EAAB
1 2 U3TXDP1_L 4 3 U3TXDP1 ME@
<18> USB3_TX1_P 4 USB3@ 3
USB3@ 1 2 U3TXDP2_L 4 3 U3TXDP2
<18> USB3_TX2_P 4
C847 L49 USB3@ USB3@ 3
.1U_0402_16V7K C848 L53
.1U_0402_16V7K
A A
Place TX AC coupling Cap (C843~C850). Close to connector

2011/06/15 2012/07/11 Title
USB3.0/Left USB Ports
Custom 1.0
5 4 3 2 1
A B C D E
+5VALW to +5VS
+3VALW to +3VS
+5VALW +5VS +3VALW +3VS
U38
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
U39
DMN3030LSS-13_SOP8L-8 DMN3030LSS-13_SOP8L-8
8 1 8 1
C720
C721
C723
C724
1 1 7 2 1 1 1 7 2 1 1 1
6 3 @ 6 3 @
5 C722 5 C725
@ 1U_0603_10V4Z 1U_0603_10V4Z
2 @ 2 2 2@ 2 @ 2
4
+VSB +VSB +3VALW
100U_1206_6.3V6M
1
1
R646 1 1 1
150K_0402_5% R647
470K_0402_1% C737 C738 C739
100U_1206_6.3V6M @ 100U_1206_6.3V6M
2
2
5VS_GATE2 R649 15VS_GATE_R @ 2 2 2
@
1 1
1
1
D D
SUSP 2 Q110 82K_0402_5% C726 SUSP 2 Q111 C727
G 2N7002_SOT23 0.01U_0402_25V7K G 2N7002_SOT23 0.01U_0402_25V7K
S 2 S 2
3
3
1/28 Add
2 2
+1.5V to +1.5VS
+0.75VS
+1.5V Q8 +1.5VS
1
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
PMV65XP_SOT23-3~D
D
R658 3 1
C717
C718
22_0603_5% 1 1 1
@
1 2
@ C719
G
2
D @ 1U_0603_10V4Z
2 SUSP 2 2 2
G
S Q115
3
2N7002_SOT23
+3VALW
1
For Intel S3 Power Reduction. 100K_0402_5%
R648
R651
0.1U_0402_10V7K
2 @ 1 1.5VS_GATE
+RTCVCC +3VLP
C729
Q112 0_0402_5% 1
1
D
3 3
SUSP# 2
2
G
R652 @ 2N7002_SOT23 S 2
3
220K_0402_5% R653
100K_0402_5%
1
SUSP
<10> SUSP
Q117
1
DTC124EKAT146_SC59-3
OUT
2
<42,51,53> SUSP# IN
GND
1
R795 @
100K_0402_5%
2
4 4

DC Interface
Custom 1.0
A B C D E
5 4 3 2 1
ADP_ID
JDCIN1
VIN AC Adapter 90W 65W
1 APDIN EMI@ PL101
1 2 1 2 APDIN1 1 2 R(K ohm) open 10
2 3
3 4 PF101 FBCA-K5B-302540-L1-T_2P ADP_ID(V) 3.3 1.65
4
1000P_0402_50V7K
1000P_0402_50V7K
100P_0402_50V8J
100P_0402_50V8J
5 7A_24VDC_429007.WRML
5 Detection voltage >2.64 1.32~1.98
ACES_88299-0510
1
EMI@ PC101
EMI@ PC102
EMI@ PC103
EMI@ PC104
CONN@
2
D D
PQ102A
2N7002KDW-2N_SOT363-6
680P_0603_50V7K
1 2 6 1
+3VALW ADP_ID <42>
0.1U_0402_16V7K
PR102
750_0402_1%
A/D
1
PC108
PC109
2
PR111
2
2N7002KDW-2N_SOT363-6
100K_0402_5%
1 2
VIN
3
1
PQ102B
PR112
5 ADP_ID_CLOSE <42>
100K_0402_5%
4
+CHGRTC
PR103
1K_0603_5%
1 2
PD101
+3VLP
S SCH DIO BAS40CW SOT-323
2 +CHGRTC_R
+RTCBATT 1
C 3 PR101 C
1K_0603_5% JRTC1 @ JRTC2 @
1 2 1 1
2 1 2 1
3 2 3 2
4 GND 4 GND
GND GND
ACES_50271-0020N-001 ACES_50271-0020N-001
RTC Battery +5VS
+3VALW
47K_0402_1%
<42,55,6> H_PROCHOT#
@
PR106
@
10K_0402_1%
2N7002KDW-2N_SOT363-6
PU101A
6
PR108
AS393MTR-E1 SO 8P OP
8
@
@ PC105 3 BATT_TEMP <42,48>
P
+
PQ101A
2 2 1 1
1N4148WS-7-F_SOD323-2
1
O 2
-
G
1.5M_0402_5%
0.022U_0402_16V7K
1
100K_0402_1%
100P_0402_50V8J
4
1
PR104
@ @
PD105
PR109
@
PC107
2
@
2
1
B @ +5VS B
H_PROCHOT#
2
47K_0402_1%
@
PR107
2N7002KDW-2N_SOT363-6
3
@
1
PC106 5
P
+
PQ101B
5 2 1 7
O 6 ACIN <16,42,49>
1N4148WS-7-F_SOD323-2
-
G
0.022U_0402_16V7K
4
1.5M_0402_5%
@ PU101B
4
@ AS393MTR-E1 SO 8P OP
PD104
PR105
@
2
A A

PWR DCIN / RTC Battery
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Gx00 1.0
5 4 3 2 1
5 4 3 2 1
VMB2 VMB
CONN@ PF201 EMI@ PL201
JBAT1 12A_65V_451012MRL FBCA-K5B-302540-L1-T_2P
SUYIN_200082GR007M229ZR
1 1 2 1 2
1 2 BATT+
2 3 EC_SMCA
3 4 EC_SMDA
4 5
5 6
6
1
7
7
1
100_0402_1%
100_0402_1%
D 8 D
GND 9 EMI@ PC201 EMI@ PC203
GND 1000P_0402_50V7K 0.01U_0402_25V7K
2
PR201
PR204
2
2
EC_SMB_CK1 <42,49>
EC_SMB_DA1 <42,49> 90W(DIS) : 6.65K 100W active 90W recovery

PH201 under CPU botten side :
1 2
65W(UMA): 1.65K 70W active 65W recovery
@ PR209
+3VLP CPU thermal protection at 93 +-3 degree C 20120314
6.49K_0402_1%
CONN@ 1 2 Recovery at 56 +-3 degree C Change to +EC_VCCA from +3VLP
+3VALW
JBAT2 PR206
SUYIN_200082GR007M229ZR
6.49K_0402_1%
1 1 2
1 BATT_TEMP <42,47,48> A/D
2
2
3
PR207
10K_0402_5%
+EC_VCCA
3 4 <42,49> ADP_I
4
12.7K_0402_1%
5
5
1
6 <42> PROCHOT
6
10K_0402_1%
PR226
7
7
2
6.65K_0402_1%
8
GND
PR975
9
GND
PR221
2
<42> NTC_V
1
C C
1
<42> Turbo_V
PH201
2
100K_0402_1%_TSM0B104F4251RZ
5.9K_0402_1%
PR222
2
25.5K_0402_1%
10K_0402_1%
1
9.31K_0402_1%
PR974
1
1
PR972
PR973
VL +3VALW
2
2
2N7002KDW-2N_SOT363-6
2N7002KDW-2N_SOT363-6
2 ECAGND
3
VL PR214
2
1
D
PC202 PR211 100K_0402_1% 2 PQ207
1
PQ206A
PQ206B
2 5 G 2N7002KW_SOT323-3
6 1
1
0.01U_0402_25V7K 100K_0402_1% S
3
BATT_OUT <49>
PR202 PR210
2
4
2
75K_0402_1% 47K_0402_1%
PQ202A
2 2N7002KDW-2N_SOT363-6
2
PC208
1
1
8
0.068U_0402_16V7K~N
<42,47,48> BATT_TEMP 3 PQ202B <42> ADP_65 <42> ADP_90 <42> ADP_135
P
+ 1 1 2 5 2N7002KDW-2N_SOT363-6 ECAGND ECAGND ECAGND

2 O
-
G
PU201A
4
1
B B
1N4148WS-7-F_SOD323-2
AS393MTR-E1 SO 8P OP PJ202
4
2
PD201
@ JUMP_43X39
PR213 PR205 1 2
B+ 1 2 +VSB
1
100K_0402_1%
1
PC207 1.5M_0402_5%
2
100P_0402_50V8J
1
VL +3VLP
100K_0402_1%
+3V_LDO
2
VMB
1
PR220
75K_0402_1%
@ PR212
2
47K_0402_1%
@ PR203
<42> BATT_LEN#
8
@ PC209 D
2
5 0.068U_0402_16V7K~N D 2 PQ205
P
+ 7 1 2 2 @ PQ208 G 2N7002KW_SOT323-3
1
6 O G 2N7002KW_SOT323-3 S
3
-
G
S
3
2
1
100K_0402_1%
1.5M_0402_5%
100P_0402_50V8J
1N4148WS-7-F_SOD323-2
4
1
@ PR208
@ PD202
PU201B
@ PR215
AS393MTR-E1 SO 8P OP
@ PC210
2
1
+5VALW
22U_0603_6.3V6M
@ PU202
1
@ PC212
1 5
A IN OUT +3V_LDO A
4.7U_0402_6.3V6M
1
2
2
GND
@ PC213
3 4
2
SHDN# BYP
G9191-330T1U_SOT23-5
1

2
PC211
P C211 2011/06/15 2012/07/11 Title
1U_0402_16V6K
PWR-BATTERY CONN/OTP
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Gx00-CR 1.0
5 4 3 2 1
5 4 3 2 1
P3
B+
P2
PQ301 PQ302
AO4407AL_SO8 AO4423L_SO8
8 1 1 8 PR301
VIN 7 2 2 7 0.01_1206_1% CHG_B+
6 3 3 6
5 5 1 4 1 2 PQ312
EMI@ PL301 AO4407AL_SO8
2 3 1UH_NRS4018T1R0NDGJ_3.2A_30% 1 8
4
2 7
3 6
2200P_0402_50V7K
PQ304 5
470P_0402_50V8J
10U_0805_25V6K
10U_0805_25V6K
D D
47K_0402_5%
1
2
200K_0402_1%
0.1U_0603_25V7K
EMI@ PC319
4
1
PR302
PC315
PC316
EMI@ PC318
DTA144EUA_SC70-3 DISCHG_G
3
PC302
PR304
1
1 2 PR322
200K_0402_1%
2
2
2 PC301 1 2
2
5600P_0402_25V7K ACN VIN
2ACOFF-1
1SS355_SOD323-2
2
1
ACP PR321
1DISCHG_G-1
47K_0402_1%
1
2
PD302
P2-1 PR325
0.1U_0402_25V6
1
2 200K_0402_1%
PQ303 PQ311
1
PC307 PC311 DTC115EUA_SC70-3
1
DTC115EUA_SC70-3
PR306 1 2 2 1
3
20K_0402_1%
0.1U_0402_25V6 2 1 2
1 2
6
PQ306 DIS19W @ PU301

1
D
150K_0402_1%
2N7002KW _SOT323-3 S IC BQ24737RGRR VQFN 20P CHARGER PC308 PD303 PQ313

PR305
PQ307A 2 1SS355_SOD323-2
2 BATT_OUT <48,49>
2N7002KDW -2N_SOT363-6 G 0.1U_0402_25V6 P2 2N7002KW _SOT323-3
1
D
0.1U_0402_25V6
S
3
2 1 2 PACIN
1
1
PC324
VIN G
S
3
392K_0402_1% ACPRN
2
1
P2-2
10_1206_5%
ACON
5
C C
PR309
2N7002KDW-2N_SOT363-6
PR319
PQ309
3
PQ307B
ACOK
CMPIN
CMPOUT
ACP
ACN
PR303 PR308
2
47K_0402_1% 64.9K_0402_1% 21
1
PACIN 1 2 5 1 2 6 TP 2 1 4
<42,48> ADP_I ACDET PC314
PC303 20 BQ24737VCC 1 2 PR326
4
1 2 1 2 7 VCC 2.2_0402_5%
IOUT AON7408L_DFN8-5 PL302 PR324
3
2
1
1U_0603_25V6K
1
PQ305 0.1U_0402_25V6 PC304 100P_0402_50V8J 19 4.7UH_PCMC063T-4R7MN_5.5A_20% 0.01_1206_1%

PHASE
DTC115EUA_SC70-3
<42,48> EC_SMB_DA1
8
SDA
DIS25W @ PU301
1 2 1 4
BATT+
BQ24727RGRR_VQFN20_3P5X3P5 LX_CHG CHG
PR328 18 DH_CHG
HIDRV
5
1 2ACOFF-1 2 9 2 3
<42> ACOFF SCL
1
10K_0402_5% <42,48> EC_SMB_CK1 PR315 PR320 PC317 PQ310
4.7_1206_5%
EMI@ PR323
316K_0402_1% 2.2_0603_5% 0.047U_0603_16V7K
1 2 10 17 BST_CHG 1 2 2 1 SRP SRN
10U_0805_25V6K
10U_0805_25V6K
124737_SN
ILIM BTST
1
+3VALW
3
PD301 4
PR316
LODRV
1
PC322
PC323
100K_0402_1% 16 2 1
GND
SRN
SRP
REGN
PQ314 BM
2N7002KW_SOT323-3
2
RB751V-40_SOD323-2 AON7408L_DFN8-5
680P_0603_50V7K
11
12
13
14
15
3
2
1
1
1
D
EMI@ PC320
2
2 PC312
6.8_0402_5%
<48,49> BATT_OUT BQ24737VDD

1
10_0402_5%
G 1U_0603_25V6K
2
PR317
PR318
S
3
PC306 DL_CHG
2
B 0.1U_0402_25V6 B
2 1
1
PC305 PC309
0.1U_0402_25V6 0.1U_0402_25V6
2
BQ24737VDD
PR314
10K_0402_1%
1
1 2
ACIN <16,42,47>
PR310
PR307 10K_0402_1%
47K_0402_1%
PACIN
2
1 2
PR312
ACPRN 2
12K_0402_1%
2
PQ308
A DTC115EUA_SC70-3 A
3

CHARGER
1.0
Gx00-CR
Date: W ednesday, March 20, 2013 Sheet 49 of 63
5 4 3 2 1
A B C D E
1 1
PR402
499K_0402_1%
ENLDO_3V5V 2 1
B+ EMI@ PL401
B+
1
150K_0402_1%
HCB1608KF-121T30_0603 PU401
PR403
1 2 3V_VIN 7 1 3V5V_EN PC405 PR409
2200P_0402_50V7K IN EN1 0.01U_0402_25V4Z 1K_0402_5%
10U_0805_25V6K
0.1U_0402_25V6
8 3 3V_FB 1 2 1 2
IN EN2 PR401 PC402
2
@EMI@ PC403
6 BST_3V 1 2 1 2
1
1
BS
EMI@ PC404
PC406
2.2_0603_5%
0.1U_0603_25V7K
PL402
2
10 LX_3V 1 2
LX +3VALWP
9 4 1.5UH_PCMC063T-1R5MN_9A_20%
GND OUT
470P_0805_50V8
470P_0805_50V8
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
1
4.7_1206_5%
2 5
PG LDO +3VLP
EMI@ PC415 EMI@ PR404
PC408
PC409
PC410
PC411
EMI@ PC412
EMI@ PC413
1
SY8208BQNC_QFN10_3X3
2
PC414
1 3V_SN
4.7U_0603_6.3V6M
680P_0603_50V7K
2
2 2
B+ EMI@ PL403 PC407 PR410

HCB2012KF-121T50_0805 PU402 6800P_0402_25V7K 1K_0402_5%
1 2 5V_VIN 8 1 3V5V_EN 5V_FB 1 2 1 2
IN EN1
2200P_0402_50V7K
0.1U_0402_25V6
4.7U_0805_25V6-K
4.7U_0805_25V6-K
3 PR405 PC421
EN2 2.2_0603_5% 0.1U_0603_25V7K
1
1
PC420
PC427
EMI@ PC417
@EMI@ PC418
6 BST_5V 1 2 1 2
BS
2
PL404 @ PJ401
9 10 LX_5V 1 2 +5VALWP +3VALWP 1 2 +3VALW
GND LX 1 2
EMI@ PR406
5V_VCC 5 4 1.5UH_PCMC063T-1R5MN_9A_20% JUMP_43X118

VCC OUT
1
470P_0805_50V8
470P_0805_50V8
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
680P_0603_50V7K 4.7_1206_5%
1
2 7
PG LDO VL
1
PC422
PC423
PC424
PC425
PC426
EMI@ PC416
EMI@ PC419
4.7U_0603_6.3V6M
SY8208CQNC_QFN10_3X3
2
1 5V_SN
@ PJ402
2
2
1
PC430
4.7U_0603_6.3V6M
+5VALWP 1 2 +5VALW
3 1 2 3
JUMP_43X118
2
EMI@ PC429
2
PR407
2.2K_0402_5%
2 1
<42> EC_ON
@ PR408
1 2
<42> MAINPWON
0_0402_5%
3V5V_EN
4.7U_0402_6.3V6M
1
1M_0402_5%
1
@ PR411
@ PC431
2
2
4 4

+3VALW/+5VALW
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Gx00-CR 1.0
A B C D E
A B C D
EMI@ PL502
1.5V_B+ 1 2 B+
HCB2012KF-121T50_0805
2200P_0402_50V7K
10U_0805_25V6K
STATE S3 S5 1.5VP VTT_REFP 0.75VSP
0.1U_0402_25V6
4.7U_0805_25V6-K
1
1
PC501
PC520
@EMI@ PC509
EMI@ PC513
S0 Hi Hi On On On
5
Off
2
@
S3 Lo Hi On On (Hi-Z) +1.5VP
UG_1.5V 4 PQ501
S4/S5 Lo Lo Off Off Off MDV1525URH_PDFN33-8-5
1
1 1
LX_1.5V
3
2
1
@ PR503
Note: S3 - sleep ; S5 - power off 0_0603_5%
PR501 PC512 PL501 Vo=1.518V
2
2.2_0603_5% 0.1U_0603_25V7K 1UH_PCMB104T-1R0MH_18A_20%
BST_1.5V 1 2 BST_1.5V-11 2 2 1
+0.75VSP +1.5VP
10U_0805_25V6K
10U_0805_25V6K
1
MDU1511RH_POWERDFN56-8-5
1
5
PC504
@EMI@
20
19
18
17
16
1
PC505
PU501 PR515
4.7_1206_5%
VTT
VLDOIN
BOOT
UGATE
PHASE
2
21 1
2
PAD
PQ502
1 15 LG_1.5V 4 +
VTTGND LGATE PC521
1
2 14 @EMI@ 2 330U_2.5V_M
VTTSNS PGND PR511 PC517
3
2
1
6.65K_0402_1% 680P_0603_50V7K
2
3 13 2 1
GND RT8207MZQW _W QFN20_3X3 CS
4 12
+VTT_REFP Set)po*>3/8n.4/4n!pin!
VTTREF VDDP
5 11 2 1
+1.5VP VDDQ VDD
+5VALW
1
PGOOD
PR514
PC506 +3VALW 5.1_0603_5%
1U_0603_10V6K
TON
0.033U_0402_16V7K
FB
S3
S5
2
2 2
1
PC510
10K_0402_5%
PC511
10
PR510
1U_0603_10V6K
S3_1.5V
2
PR502
S5_1.5V
49.9K_0402_5% @
2
<42,46,51,53> SUSP# 1 2 PGOOD_1.5V
PR509
@ PR505 887K_0402_1%
<42> SYSON 1 2 2 1 1.5V_B+
@
PJ504
0_0402_5% PR507
1
PC503 @ PC508 5.9K_0402_1% 1 2

0.1U_0402_16V6K 0.1U_0402_16V7K 2 1 1 2
2
@ JUMP_43X118
FB=Vref=0.75V PJ505
1
+1.5VP Ipeak=14A ; Imax=9.8A

+1.5VP 1 2 +1.5V
PR506 Delta I=4.8476A=>1/2Delta I=2.4238A 1 2
5.76K_0402_1% Rton= 887K ohm,F= 285K Hz JUMP_43X118
Rds(on)=3.3m ohm(max) ; Rds(on)=2.7m ohm(typical)
2
PR511=6.65K ohm
Ilimit_min=(6.65K*10uA)/(10*3.3m*1.2)=16.793A @
PJ506
Ilimit_max=(6.65K*10uA)/(10*2.7m*1.2)=20.525A +0.75VSP
1 2
+0.75VS
1 2
Iocp=Ilimit+1/2Delta I=19.217 ~ 22.948A
JUMP_43X39
3 3
PU502
SY8033BDBC_DFN10_3X3
@ PL503 Vo=1.8V
PJ502
4
1UH_PH041H-1R0MS_3.8A_20%
1 2 1.8VSP_VIN 10 2 1.8VSP_LX 1 2
+3VALW
PG
1 2 PVIN LX +1.8VSP
@EMI@ PR508
9 3
4.7_0603_5%
JUMP_43X79 PVIN LX
1
1
PC502 8
22U_0805_6.3VAM SVIN
68P_0402_50V8J
1
6 FB=0.6Volt
2
FB 1
PC525
22U_0805_6.3VAM
22U_0805_6.3VAM
1 2
EN
1
NC
NC
PR512 @
TP
PJ507
PC514
PC515
20K_0402_1%
680P_0603_50V7K
<42,46,51,53> SUSP#
@EMI@ PC523
@ PR516 +1.8VSP 1 2 +1.8VS

11
2
1 2 EN_1.8VSP 1 2
2
0_0402_5% JUMP_43X79
0.1U_0402_10V7K
1
PC507 @
1
1M_0402_5%
PR504 1.8VSP_FB
2
2
PR513
10K_0402_1%
4 4
2

+1.5VP/+1.8VSP
Custom 1.0
Gx00-CR
A B C D
5 4 3 2 1
NONCR@ PR603
0.001_1206_1%
+V1.05S_VCCP 1 2 +VCCSA
D
VID [0] VID[1] VCCSA Vout @CR@ PJ601
D
+VCC_SAP +VCCSA
0 0 0.9V TDC 4.2A +VCCSAP 2
2 1
1
JUMP_43X118
0 1 0.8V Peak Current 6A
1 0 0.725V OCP current 7.2A
OVP 1.06V
1 1 0.675V
output voltage adjustable network
CR@ PU601
SY8037BDCC_DFN12_3X3 CR@ PL601
@CR@ PJ602 0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
+3VALW 1
1 2
2 +VCCSA_PWR_SRC 12
PVIN LX
1 +VCCSA_PHASE 1 2 +VCCSAP
22U_0805_6.3V6M
1
11 2 @EMI@
JUMP_43X79 PVIN LX SA_PGOOD <42>
PR602
22U_0805_6.3V6M
22U_0805_6.3V6M
2
CR@ PC602 10 3 PR601 4.7_0603_5%
CR@ PC601
2
68P_0402_50V8J SVIN LX 100K_0402_5%
CR@ PC603
CR@ PC604
2 1 FB_VCCSA_IC9 4 1 2
+3VS
2
FB PG
1
8 5 +VCCSA_EN 1 2 @EMI@
VOUT EN
1
NONCR@ PR608 PC605
GND
7 6 0_0402_5% 680P_0402_50V7K
VID1 VID0
+V1.05S_VCCP_PWRGOOD <53>
2
13
2
@CR@ PC606
.1U_0402_16V7K
1
C H_VCCSA_VID0 <10> C
FB_VCCSA
PR604
1K_0402_5%
2 1 The 1k PD on the VCCSA VIDs are empty.
PR605 These should be stuffed to ensure that
1K_0402_5% VCCSA VID is 00 prior to VCCIO stability.
2 1
H_VCCSA_VID1 <10> CR@ PR606

100_0402_1%
2 1
@ PR607
1 2
+VCCSA_SENSE <10>
0_0402_5%
B B
PR615
200K_0402_1%
2 1
FBVDDQ_PWR_EN <25,27>
2
PR610 PC632
1M_0402_1% 0.01UF_0402_25V7K
2
1
@EMI@ PR617 @EMI@ PC624

4.7_1206_5% 680P_0603_50V7K
EMI@ PL603 1 2SNB_1.5V_VRAM 1 2 +1.5VSP PJ603
HCB2012KF-121T50_0805 PU602 2 1
+1.5VS_VGA
н 1 2 B+_1.5V_VRAM 8 1 PR618 PC627 2 1
IN EN 0_0603_5% 0.1U_0603_25V7K @ JUMP_43X118
10U_0805_25V6K
1
6BST_1.5V_VRAM 2 1 2 PL602 Vo=1.503V
0.1U_0402_25V6
2200P_0402_50V7K
1
BS 1UH_PCMB063T-1R0MS_12A_20%
PC628
нϯs^ 9 10 LX_1.5V_VRAM 1 2
нϭ͘ϱs^W
EMI@ PC629
PC631
GND LX
2
30.1K_0402_1%
47U_0805_6.3V6M
47U_0805_6.3V6M
22U_0805_6.3VAM
22U_0805_6.3VAM
1
330P_0402_50V7K
1
1
4
@EMI@
PR616
@ PR609 FB
PC626
PC622
PC630
PC621
@ PC620
0_0402_5% 3 7 FB=0.6V
+3VALW
2
2
ILMT BYP
ILMT_1.5V_VRAM
4.7U_0603_6.3V6K
2
ILMT_1.5V_VRAM 2 5
4.7U_0603_6.3V6K
1
PG LDO
PC623
1
SY8208DQNC_QFN10_3X3
PC625
@ PR611
2
0_0402_5%
2
PR612
2
20K_0402_1%
A A
2

+VCCSAP/+1.5VSP(VRAM)
C 1.0
Gx00-CR
5 4 3 2 1
5 4 3 2 1
D D
+1.05VS_VCCPP Ipeak=15.2A ; Imax=10.64A

PJ701
PR701 Delta I=2.48=>1/2Delta I=1.24A (F=400K Hz) D-CAP 2 2 1
<42,46,51> SUSP# 60.4K_0402_1% Rds(on)=3.3m ohm(max) ; Rds(on)=2.7m ohm(typical) 2 1
1 2 @ JUMP_43X118
PR711=47K ohm +1.05VS_VCCPP PJ703 +V1.05S_VCCP
@ 10K_0402_1%
2
Vtrip=(Rtrip*10uA)/8= 58.75mV 2 1
.1U_0402_16V7K
+3VS 2 1
1
PR706
Iocp=19.043~22.999A @ JUMP_43X118
PC701
100K_0402_1%
2
1
2
PR710
100K_0402_1%
EMI@ PL702
2
HCB2012KF-121T50_0805
PR712
<52> +V1.05S_VCCP_PW RGOOD 1.05VS_B+ 2 1
B+
2200P_0402_50V7K
10U_0805_25V6K
4.7U_0805_25V6-K
0.1U_0402_25V6
1
1
PR713 PC707
PC712
PC713
@EMI@ PC715
EMI@
2.2_0603_5% 0.1U_0603_25V7K
PC711
1
BST_1.05VS_VCCP 2 1 2
2
@
10.7K_0402_1%~N
17
16
15
14
13
C PU701 4 PQ701 C
PAD
PGOOD
EN
MODE
BST
2
MDV1525URH_PDFN33-8-5
PR704
1 12 LX_1.05VS_VCCP PL701
0.1U_0402_25V6
3
2
1
VREF SW 1UH_PCMB104T-1R0MH_18A_20%
+1.05VS_VCCPP
1
2 1
12K_0402_1%
1
PC702
2 11 DH_1.05VS_VCCP
2
REFIN DH
2
1
PR705
1000P_0603_50V7K 4.7_1206_5%
5
PC703
TPS51219RTER_QFN16_3X3
@EMI@ PR714
0.01UF_0402_25V7K
1
@ PR702 3 10 DL_1.05VS_VCCP PC714 1

1 2 GSNS DL
1
2
+
0_0402_5% 4
S TR MDU1511RH 1N POWERDFN56-8
4 9 330U_2.5V_M
VSNS V5 +5VALW 2
COMP
1
PGND
PQ702
TRIP
GND
3
2
1
<9> VSSIO_SENSE_L
@EMI@ PC709
2
PC706
5
8
<9> VCCIO_SENSE
1
1 2
PR703
PC708
47K_0402_1%
1
1 2 0.01UF_0402_25V7K 1U_0603_10V6K
2
10_0402_1%
Set)po*>3/8n.4/4n!pin!
PR711
2
B B
2
PC704
1000P_0402_50V7K
1
PR709
1 2
10_0402_1%
2
PC705
1000P_0402_50V7K
1
A A

+1.05VS_VCCP
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
5 4 3 2 1
A B C D
GSGV2(25W) GE(19W)
PR842 20 39 (kohm)
+VGA_B+ EMI@ PL801
PR845 20 30 (kohm) HCB4532KF-800T90_1812
1 2 B+
PR831 2 3 (kohm)
PR816 18 24 (kohm)
680P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
2200P_0402_50V7K
PR832 0 3 (kohm)
1
EMI@ PC801
PC803
PC804
EMI@ PC802
1 1
PC863 2.7 1.8 (nF)
2
U2_UGATE1
PR817 PC806 PQ801
1
2.2_0603_5% 0.22U_0603_10V7K CSD87351Q5D_SON8-7
+3VS_VGA U2_BOOT1 2 1 U2_BOOT1_VGA 1 2 2
PL802 +VGA_CORE
1
7 0.22UH_PCMB104T-R22MS_35A_20%
PR801 @ PR823 U2_PHASE1 3 6 SW1_VGA 1 2
0_0402_5% 1 2 NVVDD_PWM_VID <23> 5
U2_LGATE1 4 DCR: 0.98m ±5% ohm
@
0_0402_5% 1 1 1 1
47P_0402_50V8J
330U_D2_2V_Y
330U_D2_2V_Y
330U_D2_2V_Y
330U_D2_2V_Y
2
1
PC866
4.7_1206_5%
1
+3VS + + + +
PC807
PC808
PC809
PC810
DISGE@ PR845
EMI@ PR826
8
30K_0402_1% @
2
PR838 2 2 2 2
If fix to one phase, PR838 and PR836 must mount.
2
2
10K_0402_5%
SNUB1_VGA
@ PR837
1phase CCM=>1.2V<PSI<1.8V
1
DISGE@ PR831 0_0402_5%
1
3K_0402_1% 1 2 NVVDD_PSI <23>

DISGSGV2@ PR845
1
PC850 DISGE@ PR816 DISGE@ PR842

20K_0402_1%
680P_0402_50V7K
1U_0402_6.3V6K 24K_0402_1% 39K_0402_1%
2
1
EMI@ PC811
2
2
2
DISGSGV2@ PR831 @ PR854

+VGA_CORE Under VGA Core 2
2K_0402_5% 0_0402_5%
GPU_REFIN 1 2 1 2 1 2 EC_VGA_EN <42>
DISGSGV2@ PR816
2700P_0402_50V7K
2700P_0402_50V7K
DISGSGV2@ PR842
DISGSGV2@ PC863
18K_0402_1%
20K_0402_1% @ PR847
2
NVDD_PWR_EN <18,27>
1 2 +VGA_CORE
PC861
Near VGA Core
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
2
1
0_0402_5%
PC813
PC815
PC817
PC814
PC816
PC820
PC836
PC818
DISGE@ PC863
1800P_0402_50V7K
2 1
2
GPU_REFADJ
U2_BOOT1
U2_UGATE1
DISGE@ PR832
0_0402_5%
DISGSGV2@
47U_0805_4V6
22U_0805_6.3V6M
22U_0805_6.3V6M
4.7U_0805_6.3V6K
GPU_VID
3K_0402_1%
GPU_PSI
GPU_EN
1
1
1
@ PC812
PR832
PC819
PC824
PC821
PC822
0.1U_0402_25V6
1
2
2
PR853=18K ohm,OCP=103A
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
GPU_FBRTN
1
PR853=15K ohm,OCP=83A
PC825
PC826
PC827
PC828
PC829
PC830
PC831
6
PU801 PR853=12K ohm,OCP=63A

PSI
UGATE1
BOOT1
VID
EN
REFADJ
2
+VGA_B+
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
<24>
VSSSENSE_VGA
2 PR822 1
1
360K_0402_5% GPU_REFIN 7 24 U2_PHASE1
PC832
PC833
PC834
PC835
.01U_0402_16V7K
PR853
1
REFIN PHASE1
@ PR806 GPU_VREF 8 23 U2_LGATE1 2 1
2
1 2 @ PC847 VREF LGATE1
2
GPU_TON 9 22
0_0402_5% TON GND/PWM3 15K_0402_1%
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
@0.1U_0402_10V7K
@0.1U_0402_10V7K
@0.1U_0402_10V7K
1 2 GPU_FBRTN 10 21 @
RGND PVCC
1
PR813
PC839
PC840
PC841
PC842
PC843
PC844
PC845
PC846
<24>
1
VCCSENSE_VGA
TALERT/ISEN2
100_0402_1% GPU_FB 11 20 U2_LGATE2

VSNS LAGTE2
TSNS/ISEN3
@ PC871
VCC/ISNE1
2
0.1U_0402_25V6 @ PC860 GPU_COMP 12 19 U2_PHASE2
2
SS PHASE2
UGATE2
PGOOD
@ PR818 33P_0402_50V8J
BOOT2
1 2 1 2 1 2
GND
3
@ PR812 +VGA_B+ 3
0_0402_5% 0_0402_5%
@ PR824 RT8813AGQW_WQFN24_4X4
25
13
14
15
16
17
18
1 2 1 2
+VGA_CORE
PR811 0_0402_5%
10U_0805_25V6K
10U_0805_25V6K
GPU_DSBL/ISEN1
GPU_TSNS/ISEN3
GPU_TALERT/ISEN2
100_0402_1%
1
PC880
PC881
2
2
U2_UGATE2
1 2 U2_UGATE2
U2_BOOT2
@ PC848 PQ802
47P_0402_50V8J PR852 PC858 CSD87351Q5D_SON8-7
1
2.2_0603_5% 0.22U_0603_10V7K
GPU_VREF 2
U2_BOOT2 1 U2_BOOT2_VGA 1 2 2
PR822=499K ohm,F=300Khz +3VS PL803
PR822=360K ohm,F=450Khz
1
7 0.22UH_PCMB104T-R22MS_35A_20%
10K_0402_1%
PR844 U2_PHASE2 3 6 SW2_VGA 1 2

+VGA_CORE
1
5
PR843
25.5K_0402_1%
4 DCR: 0.98m ±5% ohm
2
1
470K_0402_5%_TSM0B474J4702RE
4.7_1206_5%
470K_0402_1%
DGPU_PWROK <19,26,27>
8
2
EMI@ PR855
1
U2_LGATE2
PH801
PR820
1U_0402_6.3V6K
1
+5VS
PC823
2
1
1 SNUB2_VGA
2
PR834
2.2_0603_5%
1 2
680P_0402_50V7K
4 4
EMI@ PC865
.1U_0603_25V7K
1
PC859
2
2
<23> GPU_HOT#

VGA_CORE
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C Gx00-CR 1.0
A B C D
5 4 3 2 1
PC902
1 2
.1U_0402_16V7K
1 PR904 2
2P: 24K 24.9K_0402_1%

1P: 24.9K PR915,PR946=200K(setting 113 degreeC)
PR915,PR946=8.25K(setting 93 degreeC)
PC901
<42> GPU_IMON
1200P_0402_50V7K
680P_0402_50V7K
1 PR901 2 FBA3 1 2
D PUT COLSE D
75K_0402_1%
10_0402_1% 0.033U_0402_16V7K
TO GT
1
PR903
PC903
PC904
PR905
TRBSTA# 1 PR902 2 FBA1 1 2 PH901 Inductor
PR906 PC906
1
1
1.21K_0402_1% 10.7K_0402_1% 220K_0402_5%_ERTJ0EV224J CSCOMPA 1 2 DROOPA 1 2 CSREFA
PC905
2
PR908 PC907 PC908 2 PR907 1 NTC_PH203 1K_0402_1% 1000P_0402_50V7K
2
0.033U_0402_16V7K 1 2 FBA2 1 2 1 2 165K_0402_1%
10_0402_1% 2P: 1.65K
680P_0402_50V7K PR910 10P_0402_50V8J PC909
1P: 1K
15.8K_0402_1%
1 PR909 2 1 2 COMPA11 2 TSENSEA
1K_0402_1% 6.04K_0402_1% 2200P_0402_50V7K CSREFA
1
PC910
2
1 PR912 2 SWN1A 0.047U_0402_16V7K @ PR916
0_0402_5%
2P: 21.5K 63.4K_0603_1% PR913 6.98K_0402_1%
1
CSP1A 1 2
SWN1A <56>
2
1P: 15.8K
2
@ PR937
CSCOMPA
1 2 PC911
<10> VCC_AXG_SENSE
1PR914
1000P_0402_50V7K @
1
0_0402_5% PC912
2
200K_0402_1%
@ PR954 1000P_0402_50V7K
CSREFA <56>
1
1 2 PH904
<10> VSS_AXG_SENSE
PR915
PC914
CSP2A
CSP1A
0_0402_5% 1 2 100K_0402_1%_TSM0B104F4251RZ
TRBSTA#
DROOPA
CSSUMA
TSENSEA
COMPA
1
FBA
.1U_0402_16V7K
DIFFA
ILIMA
+V1.05S_VCCP
PR927=95.3K ohm,F=300Khz PR918 2P: 36K

1 2
PR927=63.4K ohm,F=450Khz 26.1K_0402_1% 1P: 26.1K
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
6132_PWMA
+5VS 1 PR919 2 PU901 PUT COLSE
C C
2_0603_5%
VSNA
VSPA
DIFFA
FBA
COMPA
IOUTA
ILIMA
DROOPA
CSCOMPA
CSSUMA
CSREFA
CSP2A
CSP1A
TSNSA
PAD
TRBSTA#
PC915 TO V_GT
1 2 6132_VCC HOT SPOT
.1U_0402_16V7K
1 45 PR921 PC918
2 2.2U_0603_10V7K VCC PWMA 44 BSTA1 1 2 BSTA1_11 2
VDDBP BSTA +5VS
130_0402_1%
54.9_0402_1%
3 43 2.2_0603_5% 0.22U_0603_25V7K
VRDYA HGA HG1A <56>
PR922 2
4 42
<42> VR_ON EN SWA SW1A <56>
PR923
PC917 VR_SVID_DAT1 5 41 PC919

SDIO LGA LG1A <56>
VR_SVID_ALRT# 6 40 BST2 1 PR924 2 BST2_1 1 2 2Phase: @
2
PR927 PR925 VR_SVID_CLK 7 ALERT# BST2 39 2.2_0603_5% 0.22U_0603_25V7K

SCLK HG2 HG2 <56> 1Phase: install
1
0_0402_5% 95.3K_0402_1% 1 2 VBOOT 8 38 Option for
SW2 <56>
1
1@ PR926 2 VR_SVID_DAT1 1 2 10K_0402_1% ROSC_CPU 9 VBOOT NCP6132AMNR2G_QFN60_7X7 SW2 37 PC920

<9> VR_SVID_DAT ROSC LG2 LG2 <56> 1 phase GFX 0_0402_5%
<9> VR_SVID_ALRT# CPU_B+ 1 2 VRMP 10
VRMP PVCC
36 6132P_VCCP 1 @ PR930 2 1 2
H_PROCHOT# 11 35 0_0402_5% 2.2U_0603_10V7K @ PR928
<9> VR_SVID_CLK <42,47,6> H_PROCHOT# VRHOT# PGND
0.01U_0402_25V7K
PR929 1K_0402_1% VGATE 12 34

LG1 <56> +5VS
2
VRDY LG1
1
13 33 CSP2A
VSN SW1 SW1 <56>
PC921 14 32 PC922
+3VS VSP HG1 HG1 <56>
DIFF_CPU 15 31 BST1 1 PR931 2 BST1_1 1 2
CSCOMP
2
DIFF BST1
TRBST#
2.2_0603_5% 0.22U_0603_25V7K
DROOP
CSSUM
DRVEN
CSREF
COMP
TSNS
CSP3
CSP2
CSP1
PWM
IOUT
ILIM
1
FB
PR933 +5VS
10K_0402_5%
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
2
COMP_CPU
1
VGATE Option for
FB_CPU
3Phase: @
TRBST#
<16,42> VGATE
@ PR936 3P: 73.2K 2 phase CPU
DROOP
TSENSE
ILIM_CPU
1 2 VSN 3P: 22p 6132_PWM 1 PR9342 0_0402_5% 2Phase: install
<9> VSSSENSE 2P: 41.2K
1
41.2K_0402_1% @ PR935
0_0402_5% PC923 2P: 10p
2
@ PR938 1000P_0402_50V7K CSP3
2
1 2 VSP PC924
<9> VCCSENSE
2
PR939 12.4K_0402_1% 1 2
0_0402_5% .1U_0402_16V7K
IMVP_IMON
B B
PC926 CSP1
3P: 330p 1 PR940 2 2 1 CSP2 CSP2 1 PR941 2
SWN2 <56>
1
2
1K_0402_1% CSP3 PC927 6.98K_0402_1% TSENSE
2P: 1000p
1
10P_0402_50V8J 0.047U_0402_16V7K
@
1
PR942 PC928 PR943 PC929 3P: 21K PR960
2
1 2FB_CPU1 1 2 2 1COMP_CPU1 2 1 CSREF 6.98K_0402_1% @ PR917
1
PR944 PC930 49.9_0402_1% 4.32K_0402_1% 2P: 12.4K 0_0402_5%
1 2FB_CPU3 1 2 1000P_0402_50V7K 3300P_0402_50V7K CSP1 1 PR9452
SWN1 <56>
2
10_0402_1% 3P: 6.04K 6.98K_0402_1%
CSREF <56>
CSCOMP
2
2
1
0.033U_0402_16V7K PC931
PR947 PR948 2P: 4.32K PC932 @ PR961
TRBST# 1 2 FB_CPU2 1 2 1000P_0402_50V7K 3P: 1500p0.047U_0402_16V7K 6.98K_0402_1%
1
2
0.033U_0402_16V7K
CSREF
1
2P: 1200p
1
8.06K_0402_1% 806_0402_1% 3P: 2200p

PC933 @
2P: 3300p
200K_0402_1%
CSSUM
2
PR946 1
2
3P: 348 3P: 3.65K PC934
1 2 PH902
2P: 1.21K 2P: 9.53K 1000P_0402_50V7K 1 PR949 2 SWN1
24.9K_0402_1%
124K_0603_1% 100K_0402_1%_TSM0B104F4251RZ
2
.1U_0402_16V7K
1
PC935
3P: 23.7K 1 2 PC936 1 PR951 2 SWN2

PR950
820P_0402_25V7 124K_0603_1%
1
2P: 24.9K
1 PR952 2NTC_PH201 1 PR953 2 PR949.PR951 need link SD014124380.
1
75K_0402_1%
PR955 PC937 165K_0402_1%
CSCOMP 1 2 DROOP 1 2 CSREF PH903 PUT COLSE
PUT COLSE TO VCORE
1K_0402_1% 1000P_0402_50V7K 2 1
3P: 806 TO VCORE HOT SPOT
Phase 1 220K_0402_5%_ERTJ0EV224J
2P: 1K
A Inductor A
<42> IMVP_IMON
Security Classification
2011/06/15
Compal Secret Data
2012/07/11 Title
Compal Electronics, Inc.
PWR-CPU_CORE
Custom Gx00-CR 1.0
5 4 3 2 1
5 4 3 2 1
CPU_B+ CPU_B+
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
B+
0.1U_0402_25V6
0.1U_0402_25V6
2200P_0402_25V7K
2200P_0402_25V7K
5
5
EMI@ PL901
EMI@ PC944
EMI@ PC945
HCB4532KF-800T90_1812
1
1 2
PC938
PC939
EMI@ PC940
EMI@ PC941
PC942
PC943
CPU_B+
PR962 1 1 PR963
2
1 2 4 1 2 4
<55> HG1 + + <55> HG2
0_0402_5% PQ901 PC970 PC969 0_0402_5%
+VCC_CORE 68U_25V_M 68U_25V_M PQ902 +VCC_CORE
PL902 2 2 PL903
S TR MDU1516URH 1N POWERDFN56-8 S TR MDU1516URH 1N POWERDFN56-8
3
2
1
3
2
1
D D
0.36UH_PCMB104T-R36MH1R105_30A_20% 0.36UH_PCMB104T-R36MH1R105_30A_20%
1 4 1 4
<55> SW1 <55> SW2
1
2 3 DCR: 1.10m ±5% ohm 2 3 DCR: 1.10m ±5% ohm
5
EMI@ PR956 EMI@ PR957
4.7_1206_5% 4.7_1206_5%
2
PR958
4 V1N_CPU 2 1 4 V2N_CPU 2 PR959 1 CSREF
<55> LG1 CSREF <55> <55> LG2
1SNUB_CPU1
SNUB_CPU2
10_0402_1%
10_0402_1%
PQ903
PQ904
SWN1 <55> SWN2 <55>
3
2
1
3
2
1
EMI@ PC948 S TR MDU1511RH 1N POWERDFN56-8
1
680P_0603_50V7K EMI@ PC949
Set)po*>3/8n.4/4n!pin! Set)po*>3/8n.4/4n!pin!
2
680P_0603_50V7K
2
C C
QC 45W CPU DC 35W CPU

VID1=0.9V VID1=1.05V
IccMax=94A IccMax=53A
Icc_Dyn=66A Icc_Dyn=43A
Icc_TDC=52A Icc_TDC=36A
R_LL=1.9m ohm R_LL=1.9m ohm
OCP~110A OCP~65A
CPU_B+
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
2200P_0402_25V7K
B B
EMI@ PC946
EMI@ PC947
1
1
PC957
PC958
2
2
5
PR964
1 2 4
<55> HG1A
0_0402_5%
PQ907
S TR MDU1516URH 1N POWERDFN56-8 PL905 +VCC_GFXCORE_AXG
3
2
1
0.36UH_PCMB104T-R36MH1R105_30A_20%
1 4
<55> SW1A
1
2 3 DCR: 1.10m ±5% ohm

5
EMI@ PR967
V1N_GFX
4.7_1206_5%
2
4
<55> LG1A
1SNUB_GFX1
PQ909
2 PR971 1
CSREFA <55>
3
2
1
10_0402_1%
EMI@ PC968
Set)po*>3/8n.4/4n!pin! 680P_0603_50V7K
SWN1A <55>
2
A A
QC 45W GT2 DC 35W GT2

VID1=1.23V VID1=1.23V
IccMax=46A IccMax=33A
Icc_Dyn=37A Icc_Dyn=20.2A Security Classification Compal Secret Data Compal Electronics, Inc.
Icc_TDC=38A Icc_TDC=21.5A Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title
R_LL=3.9m ohm R_LL=3.9m ohm THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-CPU_CORE
OCP~55A OCP~40A AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Gx00-CR
5 4 3 2 1
5 4 3 2 1
+VCC_CORE Below is 458544_CRV_PDDG_0.5 Table 5-8.

+VCC_CORE +VCC_GFXCORE_AXG
1 1 1 1 1
5 x 22 ȝF (0805)
PC1
PC2 PC3 PC4 PC5
Socket Bottom 5 x (0805) no-stuff
2
10U_0805_6.3VAM
2
10U_0805_6.3VAM
2
10U_0805_6.3VAM
2
10U_0805_6.3VAM
2
10U_0805_6.3VAM +VCC_GFXCORE_AXG sites
D
7 x 22 ȝF (0805) D
Socket Top 2 x (0805) no-stuff
sites
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1 1 1 1 1 1 1 1 1 1
PC13
PC15
PC17
PC18
PC19
PC6 PC7 PC8 PC9 PC10
10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM
2 2 2 2 2 2 2 2 2 2
+V1.05S_VCCP
+VCC_CORE +V1.05S_VCCP
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1 1 1 1 1 1 1 1 1 1 1 1
PC27
PC28
PC29
PC30
PC31
PC32
PC33
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2
PC36
PC38
PC39
PC40
PC41
PC42
PC43
2 2 2 2 2 2 2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1 1 1 1 1
1 1 1 1 1
PC50
PC51
PC52
PC53
PC56
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 2 2 2 2 2
2 2 2 2 2
470U_D2_2VM_R4.5M
390U_2.5V_M
1 1
PC58
PC59
+ +
C C
2 2
330U_D2_2V_Y
330U_D2_2V_Y
1 1
1 1 1 1
QD69!FTS>!5/6n!pin!
PC66
PC67
+ +
PC61 PC62 PC63 PC64
2
22U_0805_6.3V6M
2
22U_0805_6.3V6M
2
22U_0805_6.3V6M
2
22U_0805_6.3V6M QD6:!FTS>!:n!pin! FTS>!:n!pin! 2 2
1 1
PC71 PC72
22U_0805_6.3V6M 22U_0805_6.3V6M
2 2
+VCC_CORE
1 1 1
330U_D2_2V_Y
330U_D2_2V_Y
330U_D2_2V_Y
+ + +
PC73
PC74
PC76
B 2 2 2 B
1 1
330U_D2_2V_Y
330U_D2_2V_Y
+ +
PC77
PC78
FTS>!:n!pin!
2 2
A A

PWR - PROCESSOR DECOUPLING
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-9631P 1.0
5 4 3 2 1
5 4 3 2 1
9HUVLRQFKDQJHOLVW3,5/LVW 3DJHRI

IRU3:5
,WHP 5HDVRQIRUFKDQJH 3* 0RGLI\/LVW 'DWH 3KDVH
Design Change of IC Package. 50 Change PU401 to SA000061M00(S IC SY8208BQNC QFN 10P PWM) 2012/11/22 DVT

D D
Design Change of IC Package. 50 Change PU402 to SA000061N00(S IC SY8208CQNC QFN 10P PWM) 2012/11/22 DVT
Design Change of IC Package. 52 Change PU602 to SA000061Q00(S IC SY8208DQNC QFN 10P PWM) 2012/11/22 DVT
Add PQ102 to SB00000EO10(S TR 2N7002KDW 2N SOT-363-6 PANJIT)

Add ADP_ID Circuit. 47 2012/12/03 DVT
Add PR111.PR112 to SD028100380(S RES 1/16W 100K +-5% 0402)
Factory lack of material. 52 Change PC521 to SF000003H00(S_A-P_CAP 330U 2.5V M 6.3X4.2 LESR16M SL) 2012/12/06 DVT
Factory lack of material. 56 Change PL902.PL903.PL905 to SH00000N900(S COIL .36U PCMB104T-R36MH1R105 30A GLUE) 2012/12/06 DVT

EMI request adjust +3VALWP/+5VALWP snubber function. 50 Change @PR404.@PC415.@PR406.@PC429 to PR404.PC415.PR406.PC429. 2012/12/06 DVT
C C
EMI request adjust +3VALWP/+5VALWP boost resistor. 50 Change PR401.PR405 to SD013220B80(S RES 1/10W 2.2 +-5% 0603). 2012/12/06 DVT

EMI request add bypass capacitor. 50 Add PC412.PC413.PC416.PC419 to SE001471J80(S CER CAP 470P 50V J NPO 0805 H0.6) 2012/12/06 DVT

EMI request adjust CPU/GFX CORE snubber function. 56 Change @PR956.@PC948.@PR957.@PC949.@PR967.@PC968 to PR956.PC948.PR957.PC949.PR967.PC968. 2012/12/06 DVT

EMI request adjust bypass capacitor. 56 Change @PC940 to PC940. 2012/12/06 DVT

Add PC944.PC946 to SE00000G880(S CER CAP 0.1U 25V K X5R 0402)
EMI request add bypass capacitor. 56 Add PC945.PC947 to SE075222K80(S CER CAP 2200P 25V K X7R 0402) 2012/12/06 DVT
Change PC420 to SE00000OF80(S CER CAP 4.7U 25V K X6S 0805 H1.25)
Design Change of input capacitor. 50 Add PC427 to SE00000OF80(S CER CAP 4.7U 25V K X6S 0805 H1.25) 2012/12/07 DVT
Add @PR409.@PR410 to SD028100180(S RES 1/16W 1K +-5% 0402)

Add @PC405 to SE075472K80(S CER CAP 4700P 25V K X7R 0402)
Design Change of IC Application. 50 2012/12/10 DVT
Add
Add
@PC407 to SE075472K80(S CER CAP 0.047U 25V K X7R 0402)
PR411 to SD028000080(S RES 1/16W 0 +-5% 0402)
B B
Change PC936 to SE000008980(S CER CAP 820P 25V K X7R 0402)

Change PC929 to SE074332K80(S CER CAP 3300P 50V K X7R 0402)
55
Change
Change
PC926 to SE071100J80(S CER CAP 10P 50V J NPO 0402)
PC928 to SE074102K80(S CER CAP 1000P 50V K X7R 0402) 2012/12/17 DVT
Design Change of IC Application. Change PR943 to SD00000J280(S RES 1/16W 4.32K +-1% 0402)
Change PR949.PR951 to SD014124380(S RES 1/10W 124K +-1% 0603 YAGEO)
Design Change of CPU/GFX CORE Choke. 56 Change PL902.PL903.PL905 to SH00000NM00(S COIL 0.22UH +-20% PCMB104T-R22MS 35A) 2012/12/21 DVT

Design Change of VGA CORE(Standby mode Circuit). 54 Delete PC864.PQ810.PR802.PR803.PR805 2012/12/21 DVT

Reduction Part Count. 47 Delete PR110. 2013/01/18 PVT


Reduction Part Count. 54 Delete PR814.PC849.PR825.PR835.PR850.PD802.PD801. 2013/01/18 PVT
A A

PIR (PWR)
Custom
C38-G series Chief River Schematic1.0
5 4 3 2 1
5 4 3 2 1
9HUVLRQFKDQJHOLVW3,5/LVW 3DJHRI

IRU3:5
Reduction Part Count. 55 Delete PC916. 2013/01/18 PVT

D D
Design Change of IC Application. 50 Change @PC405.@PR490.@PC407.@PR410 to PC405.PR490.PC407.PR410.
Change PR411 to SD028000080(S RES 1/16W 0 +-5% 0402) 2013/01/18 PVT
Change PR505.PR516 to SD028000080(S RES 1/16W 0 +-5% 0402) 2013/01/18 PVT

Reduction Part Count. 51 Change PR503 to SD013000080(S RES 1/10W 0 +-5% 0603)
Design Change of Thermal Application. 51 Change PC521 to SGA20331E10(S POLY C 330U 2V Y D2 LESR9M EEFSX H1.9) 2013/01/18 PVT

Reduction Part Count. 52 Change PR611 to SD028000080(S RES 1/16W 0 +-5% 0402) 2013/01/18 PVT

Reduction Part Count. 53 Change PR702 to SD028000080(S RES 1/16W 0 +-5% 0402) 2013/01/18 PVT

Reduction Part Count. 54 Change PR823.PR824 to SD028000080(S RES 1/16W 0 +-5% 0402) 2013/01/18 PVT

Reduction Part Count. 55 Change PR926.PR916.PR917 to SD028000080(S RES 1/16W 0 +-5% 0402) 2013/01/18 PVT

Design Change of CPU/GFX CORE Choke. 56 Change PL902.PL903.PL905 to SH00000N900(S COIL .36U PCMB104T-R36MH1R105 30A GLUE) 2013/01/18 PVT
C
C
Design Change of CPU/GFX CORE Frequence. 55 Change PR927 to SD034953280(S RES 1/16W 95.3K +-1% 0402) 2013/01/18 PVT

Factory lack of material. 50 Change PC420.PC427 to SE000006R80(S CER CAP 4.7U 25V K X5R 0805 H1.25) 2013/01/18 PVT


Design Change of Power Circuit Application. 48 Change PC208 to SE000003J80(S CER CAP 0.068U 16V K X7R 0402) 2013/01/23 PVT

Add PR328 to SD028100280(S RES 1/16W 0 +-5% 0402)
Design Change of Power Circuit Application. 49 2013/01/23 PVT

Add PR327 to SD028000080(S RES 1/16W 0 +-5% 0402)
Add PQ314 to SB000009Q80(S TR 2N7002KW 1N SOT323-3)
Change PC405 to SE072103Z80(S CER CAP .01U 25V Z Y5V 0402)

Design Change of Power Circuit Application. 50 2013/03/04 PVT

Change PC407 to SE075682K80(S CER CAP 6800P 25V K X7R 0402)
B B
A A

PIR (PWR)
Custom
C38-G series Chief River Schematic1.0
5 4 3 2 1
5 4 3 2 1
COMPAL CONFIDENTIAL
MODEL NAME: Power Sequence Block Diagram
PCB NAME: LA-9901P
D REVISION: 0.2 JUMP
D
DATE: 2013/01/14 6 +3V_PCH
A1 PCH_PWROK 14
AC
VIN
MODE 7 EC_RSMRST#
B+ PU401 +3VALW
PU301 6 8 PBTN_OUT# SYS_PWROK 19
2 PU402 +5VALW
DGPU_PWROK
BATT PM_SLP_S3#
BATT+ 16
MODE EC_ON 5 PM_SLP_S4#
B1 3 ACIN PM_SLP_S5# 9 PCH 15 PM_DRAM_PWRGD
ON/OFF EC 16 H_CPUPWRGD
4 SW3 GC6_FB_CLAMP_TGL_REQ#
GC6_FB_CLAMP
20 PLT_RST# CPU
C
12 SA_PGOOD 14 SVID C
11 SUSP# DGPU_PWR_EN 11 17
-->UMA 11 SYS_PWROK
SYSON 10 -->DIS 11 VGATE 18
10 SVID
B+
NVDD_PWR_EN
DGPU_PWROK
SW1,SW2
+VCC_CORE NVDD_PWR_EN 16
VR_ON 13 PU901 B+
SW1A +VCC_GFXCORE_AXG PU801 +VGA_CORE
EC_VGA_EN
SYSON +1.5VP
JUMP
+1.5V 15
B+ PU501 JUMP
16
+0.75VSP +0.75VS
FBVDDQ_PWR_EN
DV2 GC6_EN
SUSP# JUMP UV11 +1.5V
DGPU_PWROK
+1.05VS_VCCP
+3VALW PU502 +1.8VSP +1.8VS 17
B+
SUSP +5VS PU602
B
+5VALW U38 U73 +5VS_DISPLAY 16 B
18
+3VS +1.5VS_VGA JUMP
QV11
SUSP JUMP
+3VALW U39 +3VS_WLAN
12QV5 +3VS_VGA 13
VRAM 19
DGPU_PWR_EN
SUSP# 20 PLT_RST# 22 +1.05VS_VGA

+1.5V Q8 +1.5VS
PLT_RST_VGA#
DGPU_HOLD_RST# UV2
SUSP PCH
21
+1.5V U3 +1.5V_CPU_VDDQ
VGA
JUMP
SUSP# +1.05VS_VCCP JUMP
B+ PU701 +3VALW +VCCSA
+1.05VS_VCCP_PWRGD +VCCSA_EN PU601
SA_PGOOD
A A
GC6_FB_CLAMP
GC6_FB_CLAMP_TGL_REQ#

Power sequence
5 4 3 2 1
5 4 3 2 1
VILG1/G2 HW PIR List

Jufn Qbhf NPEJGJDBUJPO!MJTU QVSQPTF
FWU!UP!EWU
2 Q/622 Dibohf!gppuqsjou!pg!KDQV2 Gps!Mfopwp!svmf
D
3 Q/25 Bee!S517-!S518-!S519-!S51: Sftfswf!gps!jnqspwfnfou!gbdupsz!qspdfttft D
4 Q/53 Bee!FD`TQJ`TP-!FD`TQJ`TJ-!FD`TQJ`DML-!FD`TQJ`DT$!up!FD Sftfswf!gps!jnqspwfnfou!gbdupsz!qspdfttft

5 Q/53 Bee!QDI`QXS`FO!up!FD!Qjo/218 Sftfswf!gps!jnqspwfnfou!gbdupsz!qspdfttft
6 Q/53 Sftfswf!S521 Sftfswf!Qvmm.ijhi!gps!HQJP!vtf
7 Q/53 Dibohf!FD`GBO`QXN!gspn!FD!Qjo/45!up!FD!Qjo/37 Gps!dpnnpo!eftjho
8 Q/53 Dibohf!OPWP$!gspn!FD!Qjo/37!up!FD!Qjo/45 Gps!dpnnpo!eftjho
9 Q/53 Dibohf!FOCLM!gspn!FD!Qjo/84!up!FD!Qjo/87 Gps!dpnnpo!eftjho
: Q/53 Dibohf!JNWQ`JNPO!gspn!FD!Qjo/87!up!FD!Qjo/84 Gps!dpnnpo!eftjho
21 Q/53 Dibohf!EHQV`QXS`FO!gspn!FD!Qjo/218!up!FD!Qjo/234 Gps!dpnnpo!eftjho
22 Q/53 Dibohf!PWFSU$`S!gspn!FD!Qjo/228!up!FD!Qjo/28 Gps!dpnnpo!eftjho
23 Q/45 Bee!S522-!S523-!D522-!D523 Sftfswf!gps!FNJ
C C
24 Q/31 Bee!R32-!S51-!D348-!R33-S529-!D354-D363-S524 Sftfswf!gps!qpxfs!dpotvnqujpo

25 Q/36 Dibohf!SW52!up!2L!pin-!DW74!up!2vG Gps!WHB!Tfrvfodf
26 Q/36 Bee!RW50SW53 Gps!WHB!Tfrvfodf
27 Q/36 Dibohf!RW40VW22 Gps!WHB!Tfrvfodf
28 Q/37 Dibohf!SW352!up!26L!pin Gps!WHB!Tfrvfodf
29 Q/37 Bee!RW7!boe!SW55/ Gps!WHB!Tfrvfodf
2: Q/37 Dibohf!RW210RW22 Gps!WHB!Tfrvfodf
31 Q/54 Efm!R230S917 Gps!Dibohf!Bvejp!Kbdl!uzqf!gspn!Opsnbm!dmptf!up!Opsnbm!pqfo
B B
A A

HW-PIR1
5 4 3 2 1
5 4 3 2 1
VILG1/G2 HW PIR List

Jufn Qbhf NPEJGJDBUJPO!MJTU QVSQPTF
EWU!UP!QWU
2 Q/47 Sftfswf!S619 Gps!mfblbhf!dvssfou!jttvf!pg!Buifspt!XMBO
D 3 Q/52 Dibohf!SB33!up!sftfswf Gps!QD!Cffq!jttvf)dbo(u!ifbse!tpvoe!pg!#ej#!po!CJPT!tfuvq!nfov* D
4 Q/52 Sftfswf!SB210SB22 Gps!tpmwf!Dpefd!tqfblfs!Ivn!opjtf!jttvf)[j{j*

5 Q/53 Sftfswf!S527 Sftfswf!,4WMQ!qpxfs!sbjm!up!FD
6 Q/53 Dibohf!FD`STU$!qpxfs!sbjm!up!,4W`FD Vtjoh!qpxfs!sbjm!xijdi!uif!tbnf!xjui!FD
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G400S/G500S DIS M/B Schematics Document

Security Classification Compal Secret Data Compal Electronics, Inc.

NVIDIA GB4-128 29 x 29 mm PEG 8x Intel Memory Bus 204pin DDRIII-SO-DIMM X2

2 LVDS Conn. Left USB3.0 x2 Right USB2.0 Int. Camera

HDMI Conn. USB20 x6 Touch Screen Card Reader

Int. MIC Conn. Int. Speaker Conn. Audio Combo Jacks

Power/B Thermal Sensor Touch Pad Int. KBD

Board ID PCB Revision Full ON HIGH HIGH HIGH HIGH ON ON ON ON

+5VALW +1.5V +VCC_CORE

S5 S4/AC BTO Item BOM Structure

For N14P-GV2 strap table X76

DGPU_PWR_EN T2>0 T4>0

GC6 Entry/Exit Sequence Timing Diagram

PEG_ICOMPI and RCOMPO signals should be

PCI EXPRESS* - GRAPHICS

PEG_TX#[14] E25 PCIE_CTX_GRX_C_N0 C18 GVGS@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N0

PEG_TX[6] J29 PCIE_CTX_GRX_C_P8 C26 GS@ 1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P8

0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K

0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K

Security Classification Compal Secret Data Compal Electronics, Inc.

T48 H_CATERR# AL33

JTAG & BPM

R29 AL35 XDP_DBRESET# R28 2 1 1K_0402_5%

2 BPM#[1] AR30 T22 PAD 0.047U_0402_16V7K

3/20 Add (ESD request) TYCO_2013620-2_IVY BRIDGE

Security Classification Compal Secret Data Compal Electronics, Inc.

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY A

TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE

ME@ +1.5V ME@

CFG Straps for Processor

Interl request AH26 short GND

1: Normal Operation; Lane # definition matches

PEG DEFER TRAINING

1: (Default) PEG Train immediately following xxRESETB

Security Classification Compal Secret Data Compal Electronics, Inc.

JCPU1F POWER +V1.05S_VCCP

PEG AND DDR

V33 VCC62 VIDALERT# AJ30 VR_SVID_ALRT# <55>

VSS_SENCE 100ohm +-1% pull-down to GND near processor

TYCO_2013620-2_IVY BRIDGE Security Classification Compal Secret Data

DDR3 -1.5V RAILS

VCCPLL2 VCCSA_VID[0] H_VCCSA_VID0 <52>

A IVY Bridge drives VCCIO_SEL low A

Security Classification Compal Secret Data

+VREF_DQ_DIMMA +1.5V +1.5V

DDR_A_D32 129 130 DDR_A_D36

DDR_A_D33 131 132 DDR_A_D37 1 1

A 201 202 SMB_CLK_S3 A

1 203 204 +0.75VS

A 1 2 201 202 SMB_CLK_S3 A

1 R97 10K_0402_5% 203 204 +0.75VS

W=20mils W=20mils 1 2 PCH_RTCX2

Q10 AB13 SATA3_COMP 1 2

6 3 SPI_CLK SATA3RBIAS R115 +3V_ROM

B 5 4 HDA_RST# SPI_SB_CS0# Y14 750_0402_1% B

ME_FLASH 1 2 P3 SATALED# SPI_SB_CS1# 1 8 0_0402_5%

0_0402_5% SPI_SI V4 V14 R188 0_0402_5% SPI_WP#1 3 SO HOLD# SPI_CLK_PCH_1 1

R221 1 2 SPI_HOLD#1 +3V_ROM

Security Classification Compal Secret Data Compal Electronics, Inc.

V45 K45 CLK_BUF_ICH_14M R167 1 2 10K_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.