Power Management Texas Instruments Incorporated

Designing DC/DC converters based on

ZETA topology
By Jeff Falin
Senior Applications Engineer
Introduction Figure 1. Simple circuit diagram of
Similar to the SEPIC DC/DC converter topology, the ZETA ZETA converter
converter topology provides a positive output voltage from
an input voltage that varies above and below the output L1b
voltage. The ZETA converter also needs two inductors CC
and a series capacitor, sometimes called a flying capacitor. VIN VOUT
Unlike the SEPIC converter, which is configured with a Q1
standard boost converter, the ZETA converter is config-
C IN L1a D1 COUT
ured from a buck controller that drives a high-side PMOS
FET. The ZETA converter is another option for regulating
an un­regulated input-power supply, like a low-cost wall
wart. To minimize board space, a coupled inductor can be
used. This article explains how to design a ZETA converter
running in continuous-conduction mode (CCM) with a
coupled inductor.
Basic operation Figure 2. ZETA converter during CCM operation
Figure 1 shows a simple circuit diagram of a
ZETA converter, consisting of an input capac­
Q1 is On
itor, CIN; an output capacitor, COUT; coupled
inductors L1a and L1b; an AC coupling
capac­itor, CC; a power PMOS FET, Q1; and a – VOUT + + VIN –
diode, D1. Figure 2 shows the ZETA con- IL1a
CC L1b
verter operating in CCM when Q1 is on and VIN VOUT
when Q1 is off. +
To understand the voltages at the various IL1b
C IN VIN L1a COUT
circuit nodes, it is important to analyze the
–
circuit at DC when both switches are off and
GND
not switching. Capacitor CC will be in parallel
with COUT, so CC is charged to the output
voltage, VOUT, during steady-state CCM.
(a) When Q1 is on
Figure 2 shows the volt­ages across L1a and
L1b during CCM operation.
Q1 is Off
When Q1 is off, the voltage across L1b
must be VOUT since it is in parallel with COUT.
C IN
Since COUT is charged to VOUT, the voltage – VOUT + – VOUT +
across Q1 when Q1 is off is VIN + VOUT; CC L1b
there­fore the voltage across L1a is –VOUT VIN VOUT
relative to the drain of Q1. When Q1 is on, –
IL1a IL1b
capacitor CC, charged to VOUT, is connected VOUT L1a COUT
in series with L1b; so the voltage across L1b
+
is +VIN, and diode D1 sees VIN + VOUT. GND

(b) When Q1 is off

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The currents flowing through various

Figure 3. ZETA converter’s component currents during CCM
circuit components are shown in Figure 3.
When Q1 is on, energy from the input supply
is being stored in L1a, L1b, and CC. L1b also
TS
provides IOUT. When Q1 turns off, L1a’s cur-
VIN + VOUT
rent continues to flow from current provided
by CC, and L1b again provides IOUT. VQ1 D × TS (1 – D) × TS
Duty cycle
Assuming 100% efficiency, the duty cycle, D, I Q1(Peak)
for a ZETA converter operating in CCM is I IN + lOUT
given by l Q1

VOUT
D= . (1)
VIN + VOUT
I IN + lOUT
This can be rewritten as l D1
D I V
= IN = OUT . (2)
1 − D IOUT VIN
I IN
Dmax occurs at VIN(min), and Dmin occurs at
l*CC
VIN(max).
–I OUT
Selecting passive components
One of the first steps in designing any PWM I IN
switching regulator is to decide how much l L1a
inductor ripple current, ∆IL(PP), to allow. Too
much increases EMI, while too little may
result in unstable PWM operation. A rule of
I OUT
thumb is to assign a value for K between 0.2 I L1b
and 0.4 of the average input current. A desired
ripple current can be calculated as follows:
*Measured flowing into CC from Q1’s drain.
Desired ∆I L(PP) = K × IIN
(3)
D
= K × IOUT × .
1− D
In an ideal, tightly coupled inductor, with each inductor Like a buck converter, the output of a ZETA converter
having the same number of windings on a single core, the has very low ripple. Equation 6 computes the component
coupling forces the ripple current to be split equally of the output ripple voltage that is due solely to the capac-
between the two coupled inductors. In a real coupled itance value:
inductor, the inductors do not have equal inductance and ∆I L1b(PP) [at VIN(max) ]
the ripple currents will not be exactly equal. Regard­less, ∆VC (PP) = , (6)
OUT 8 × COUT × fSW(min)
for a desired ripple-current value, the inductance required
in a coupled inductor is estimated to be half of what would where fSW(min) is the minimum switching frequency.
be needed if there were two separate inductors, as shown Equation 7 computes the component of the output ripple
in Equation 4: voltage that is due solely to the output capacitor’s ESR:
1 VIN × D ∆VESR _C (PP) = ∆I L1b(PP) [at VIN(max) ] × ESRC (7)
L1a min = L1bmin = × (4) OUT OUT
2 ∆I L(PP) × fSW(min)
Note that these two ripple-voltage components are phase-
To account for load transients, the coupled inductor’s shifted and do not directly add together. For low-ESR
saturation current rating needs to be at least 1.2 times the (e.g., ceramic) capacitors, the ESR component can be
steady-state peak current in the high-side inductor, as ignored. A minimum capacitance limit may be necessary
computed in Equation 5: to meet the application’s load-transient requirement.
D ∆I The output capacitor must have an RMS current rating
I L1a(PK) = IOUT × + L (5) greater than the capacitor’s RMS current, as computed in
1− D 2
Equation 8:
Note that IL1b(PK) = IOUT + ∆IL /2, which is less than IL1a(PK).
∆I L1b(PP) [at VIN(max) ]
IC (RMS) = (8)
OUT
3

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 Power Management Texas Instruments Incorporated

The input capacitor and the coupling capacitor source where QGD is the gate-to-drain charge, QG is the total gate
and sink the same current levels, but on opposite switching charge of the FET, IGate is the maximum drive current, and
cycles. Similar to a buck converter, the input capacitor VGate is the maximum gate drive from the controller. Q1’s
and the coupling capacitor need the RMS current rating, RMS current is
VOUT IQ1( RMS ) = (I IN(max) + IOUT ) × Dmax
IC = IC = IOUT . (9)
IN (RMS) C (RMS) VIN(min) IOUT × VOUT (14)
= .
Equations 10a and 10b compute the component of the VIN(min) × Dmax

output ripple voltage that is due solely to the capacitance
value of the respective capacitors: The output diode must be able to handle the same peak
current as Q1, IQ1(PK). The diode must also be able to with­
Dmax × IOUT stand a reverse voltage greater than Q1’s maximum voltage
∆VC = (10a)
IN (PP) CIN × fSW(min)
(VIN(max) + VOUT) to account for transients and ringing.
Since the average diode current is the output current,
Dmax × IOUT the diode’s package must be capable of dissipating up to
∆VC = (10b)
IOUT × VFWD, where VFWD is the Schottky diode’s forward
C (PP) CC × fSW(min)
voltage at IOUT.
Equations 11a and 11b compute the component of the
output ripple voltage that is due solely to the ESR value of
Loop design
the respective capacitors: The ZETA converter is a fourth-order converter with
multi­ple real and complex poles and zeroes. Unlike the
∆VESR _C = (IIN(max) + IOUT ) × ESRC SEPIC converter, the ZETA converter does not have a
IN (PP) IN

I (11a) right-half-plane zero and can be more easily compensated

= OUT × ESRC to achieve a wider loop bandwidth and better load-
1 − Dmax IN
transient results with smaller output-capacitance values.
Reference 1 provides a good mathematical model based on
∆VESR _C = (I IN(max) + IOUT ) × ESRC state-space averaging. The model excludes inductor DC
C (PP) C
(11b) resistance (DCR) but includes capacitor ESR. Even though
I
= OUT × ESRC the converter in Reference 1 uses ceramic capacitors, for
1 − Dmax C
the following design example, the inductor DCR was sub­
Again, the two ripple-voltage components are phase-shifted sti­tuted for the capacitor ESR so that the model would
and do not directly add together; and, for low-ESR capaci- more closely match measured values. The open-loop gain
tors, the ESR component can again be ignored. A typical bandwidth (i.e., the frequency where the gain crosses zero
ripple value is less than 0.05 times the input voltage for with an acceptable phase margin of typically 45º), should
the input capacitor and less than 0.02 times the output be greater than the resonant frequency of L1b and CC so
voltage for the coupling capacitor. that the feedback loop can dampen the nonsinusoidal
ripple on the output with fundamental frequency at that
Selecting active components resonant frequency.
The power MOSFET, Q1, must be carefully selected so
that it can handle the peak voltage and currents while Design example
minimizing power-dissipation losses. The power FET’s For this example, the requirements are for a 12-V, 1-W
current rating will determine the ZETA converter’s maxi- supply with η = 0.9 peak efficiency. The load is steady-
mum output current. state, so few load transients are expected. The 2-A input
As shown in Figure 3, Q1 sees a maximum voltage of supply is 9 to 15 V. A nonsynchronous voltage-mode con-
VIN(max) + VOUT. Q1 must have a peak-current rating of troller, the Texas Instruments TPS40200, was selected,
IQ1(PK) = I L1a(PK) + I L1b(PK) = IIN + IOUT + ∆I L . (12) running with a switching frequency between 340 and
460 kHz. The maximum allowed ripple at the input and
At the ambient temperature of interest, the FET’s power- flying capacitor is respectively 1% of the maximum voltage
dissipation rating must be greater than the sum of the across each. The maximum output ripple is 25 mV, and
conductive losses (a function of the FET’s rDS(on)) and the the maximum ambient temperature is 55ºC. Because EMI
switching losses (a function of the FET’s gate charge) as is not a concern, an inductor with a lower inductance
given in Equation 13: value was selected by using the minimum input voltage.
PD _ Q1 = Pr + PSWG + PGate Table 1 on the next page summarizes the design calcula-
DS(on )
tions given earlier. Equations 7 through 9 and Equation 11
2
= IQ1(RMS) × rDS(on) were ignored because low-ESR ceramic capacitors with
(13)
+(VIN(max) + VOUT ) × IQ1(PK) × QGD / IGate × fSW(max) high RMS current ratings were used.
+ VGate × QG × fSW(max),
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Texas Instruments Incorporated Power Management

Table 1. Computations for example ZETA-converter design

BASED ON COMPUTATION
ADJUSTED FOR η = 0.9 SELECTED COMPONENT/RATING
DESIGN EQUATION (ASSUMING η = 1)
Passive Components
12 V
(1) Dmax = = 0 .57 N/A N/A
12 V + 9 V

12 V
(1) Dmin = = 0 .44 N/A N/A
12 V + 15 V

0 .57 1 .33 A
(2) IIN(max) = 1A × = 1 .33 A = 1 .48 A N/A
1 − 0 .57 0 .9

Desired ∆IL(PP) [at VIN(min) ] = 0 .3 × 1 .33 A = 0 .4 A 0 .4 A

(3) = 0 .44 A N/A
0 .9

1 9 V × 0 .57 Coilcraft MSD1260: 22 µH – IRMS =

(4) using VIN(min) L1a = L1b = × = 18 .9 µH 18 .9 µH × 0 .9 = 17 .0 µF 1.76 A in each winding simultane-
2 0 .40 A × 340 kHz ously, ISAT = 5 A
1 9 V × 0 .57
(4) at VIN(min) Actual ∆IL(PP) = × = 0 .34 A N/A
2 22 µH × 340 kHz

0 .34 A 0 .34 A
(5) IL1a(PK) = 1 .33 A + = 1 .50 A 1 .48 A + = 1 .65 A
2 2

1 15 V × 0 .44
(4) at VIN(max) Actual ∆IL(PP) = × = 0 .45 A N/A N/A
2 22 µH × 340 kHz

Two 10-µF, 25-V X5R ceramics and

0 .44 A one 4.7-µF, 25-V X5R ceramic to pro­
(6) COUT(min) = = 6 .5 µF N/A vide good load-transient response
8 × 0 .025 V × 340 kHz and to accommodate ceramic
capacitor derating
Two 10-µF, 25-V X5R ceramics and
0 .57 × 1A 11 .2 µF one 4.7-µF, 25-V X5R ceramic to
(10a) for CIN C IN(min) = = 11 .2 µF = 12 .4 µF
0 .01× 15 V × 340 kHz 0 .9 accommodate ceramic capacitor
derating

0 .57 × 1A 14 µF Three 10-µF, 25-V X5R ceramics to

(10b) for CC CC(min) = = 14 µF = 15 .6 µF accommodate ceramic capacitor
0 .01× 12 V × 340 kHz 0 .9 derating
Active Components

(12) IQ1(PK) = 1 .33 A + 1A + 0 .34 A = 2 .67 A 1 .48 A + 1A + 0 .34 A = 2 .82 A N/A

1A × 12 V 1 .77 A Fairchild FDC365P: –35-V, –4.3-A,

(14) IQ1(RMS) = = 1 .77 A = 1 .96 A
9 V × 0 .57 0 .9 55-mΩ PFET

PD_Q1 = (1 .96 A)2 × 55 mΩ

(13) + (15 V + 12 V) × 2 .82 A × 2 .2 nC / 0 .3 A × 460 kHz Included
+ 8 V × 15 nC × 460 kHz = 0 .54 W

— PD_D1 = 1A × 0 .5 V = 0 .5 W N/A MBRS340: 40 V, 3 A, SMC

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 Power Management Texas Instruments Incorporated

Figure 4. ZETA-converter design with 9- to 15-V VIN and 12-V VOUT at 1 A

VIN
(9 to 15 V )
R1 C1 C2
R2
2 2 x 10 µF 4.7 µF
0.01 
25 V 25 V

R3 U1 1000 pF
68.1 k R4
TPS40200D C3
2.0 k
1 RC VDD 8
2 SS ISNS 7
3 6
COMP DRV FDC365P
4 5
FB GND Q1
R5
7.15 k
L1 MSD1260
C5 R6 22 µH
390 pF 2 4
1 M C4 VOUT
3 x 10 µF (12 V at up
25 V 1 3 to 1 A )
C6 C10 C11 C7
150 pF 12 nF 0.47 µF 1 µF C8
2 x 10 µF
25 V C9
D1 4.7 µF
MBRS340 25 V

C12 R7
330 pF 7.5 k

R8
R9 178 k
11 k

Figure 4 shows the schematic and Figure 5 the

efficiency of the ZETA converter. On the next page, Figure 5. Efficiency of example ZETA-converter design
Figure 6 shows the converter’s operation in deep
CCM, and Figure 7 shows the loop response.
VIN = 9 V
0.9
Conclusion
Like the SEPIC converter, the ZETA converter is VIN = 15 V
another converter topology to provide a regulated 0.8
Efficiency (%)

output voltage from an input voltage that varies

above and below the output voltage. The benefits of
0.7
the ZETA converter over the SEPIC converter
include lower output-voltage ripple and easier com-
pensation. The drawbacks are the requirements for a 0.6
higher input-voltage ripple, a much larger flying
capac­itor, and a buck controller (like the TPS40200)
0.5
capable of driving a high-side PMOS. 0 200 400 600 800 1000
Ouput Current, IOUT (mA)

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Reference Related Web sites

1. Eng Vuthchhay and Chanin Bunlaksananusorn, power.ti.com
“Dynamic modeling of a zeta converter with state-space www.ti.com/sc/device/TPS40200
averaging technique,” Proc. 5th Int. Conf. Electrical
Engineering/Electronics, Computer, Telecommu­ni­
ca­tions and Information Technology (ECTI-CON)
2008, Vol. 2, pp. 969–972.

Figure 6. Operation at VIN = 9 V and IOUT = 1 A

IL1a (500 mA/div)

IL1b (500 mA/div)

32 1
VIN (200 mV/div)

4
VOUT (50 mV/div)

Time (5 µs/div)

Figure 7. Loop response at VIN = 9 V and 15 V, and IOUT = 1 A

60 180
3 4

Phase
(VIN = 15 V)
30 Gain 90
Phase
(VIN = 9 V) (VIN = 9 V)
Phase (degrees)
Gain (dB)

Gain
0 (VIN = 15 V) 0

Gain Crossover Point

3 VIN = 15 V
–30 Phase = +59° –90

4 VIN = 9 V
Phase = +41°

–60 –180
100 1k 10 k 100 k
Frequency (Hz)

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