Control Systems

LAB REPORT # 01

Submitted By:
Talha Tahir (FA17-EEE-028)
Soban Zamir (FA17-EEE-028)
Raja Muhammad Badar Naeem (FA17-EEE-028)

Submitted To:

Dated:
11-02-2020

Electrical and Computer Engineering Department, COMSTAS University,

Islamabad.
Objectives:
 To understand the basics of PLC (Programmable Logic Controller).
 Programming of PLC using ladder logic.
 Introduction to software TRiLOGI.
 Implementation of different logical gates and decoders on TRiLOGI.

Task 1:

Figure 1: ladder diagram of Single bulb controlled through single switch

Figure 2: Output

In this task, a circuit having a voltage source, a switch and a bulb is implemented on
TRiLOGI using ladder logic. i1 is representing the input i.e. switch ,in this case, and o1 is
representing bulb, which is, ultimately, representing the state of bulb.

Task 2:
In this task, output o1 which represents bulb, in this case, is controlled using a relay r1. When
input, i1, is supplied but relay is open, then output obtained will be zero. Similarly, when
input is supplied and relay is closed, then output will be obtained i.e. bulb will turn on. In
short, output depends on the state of relay.

Task 3(a):

In this task, AND gate with three inputs is implemented using ladder diagram. All three
inputs are connected in series to satisfy the truth table of AND gate which tells that for o1=1
all inputs should be equal to 1. Truth table of AND gate is given by:

I1 I2
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
I3 O1
0 0
1 0
0 0
1 0
0 0
1 0
0 0
1 1
Task 3(b):

In this task, three input OR gate is implemented in TRiLOGI. For operating the circuit
according to the truth table of OR gate, all inputs are connected in parallel so that switching
any one input or all the inputs on will cause o1=1. Truth table is given by:

I1 I2
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
I3 O1
0 0
1 1
0 1
1 1
0 1
1 1
0 1
1 1

Task 3(c):

In this task, NOT gate is implemented. For satisfying the truth table of NOT gate, input i1
used is called “normally closed”, which works in reverse manner i.e. o1=1 when i1=0 and
vice versa.
 Task 3(d):

In this task, XOR gate is implemented. The equation of XOR gate is given by:

Y=A’B + AB’

Firstly, I implemented the AND gate circuit i.e. series connection between i1 and i2, then OR
gate is implemented by connecting two series inputs in parallel to the series connection done
at the beginning. The complemented terms in the above equation are represented using
normally closed switch.

Task 4:
INPUT OUTPUT

I1 I2 I3 O1 O2 O3 O4 O5 O6 O7 O8
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
In this task, 3-8 line decoder is implemented. 3-8 line decoder means represents 3 inputs and
8 outputs. From the truth table given in in-lab, the terms were written according to their given
parallel binary number and are implemented using ladder diagram. As mentioned earlier,
complemented terms are represented using normally closed contacts.
 Task 5:

In this task, NOR gate is implemented in the similar fashion as above gates were
implemented. NOR gate is inverted form of OR gate. Ladder diagram and output is shown.

Task 6:

In this task, NAND gate is implemented in the similar fashion as above gates were
implemented. NAND gate is inverted form of AND gate. Ladder diagram and output is
shown.

Task 7:

Equation of XNOR gate is given by:

 Y=A’B’+AB.

Complemented terms are represented by normally closed switches and the rest of the circuit
is composed using AND and OR logic i.e. series and parallel placement of contacts.

Task 8:
A B C D O1 O2 O3 O4 O5 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15 O16
0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
0 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Similar to 3-8 line decoder, 4-16 line decoder is implemented. 4-16 line decoder has 4 inputs
and 16 outputs. Terms corresponding to the binary number is written and implemented using
AND logic.

e.g. 0000 is written as A’B’C’D’.

0001 is written as A’B’C’D.

Post Lab:

Task 1

Using NOR gate:

Flip flop is implemented using NOR gate. Ladder diagram along with output is shown. The
output obtained is reversed i.e. in my case, the truth table is satisfied if positions of Q and Q’
are interchanged.
 Using NAND gate:

Flip flop is implemented using NAND gate. Ladder diagram along with output is shown. The
output obtained is reversed i.e. in my case, the truth table is satisfied if positions of Q and Q’
are interchanged.

Task 2:

A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Half bit adder is implemented via ladder diagram. Half adder adds two one bit binary
numbers and sum and carry are generated.

It can be observed through the truth table that Sum column is similar to XOR gate and Carry
column is representing AND gate in disguise.
So, we can say that:

Sum= A’B+AB’

Carry=AB

Task 3:

A simple Lounge circuit’s ladder diagram is implemented.

Task 4:

X Y Z F
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 0
Simply, the equation was written by observing the circuit diagram given in post lab and then,
it was implemented via a ladder diagram and output is shown.

The equation obtained is:

F= X’Y’Z+X’YZ+XY’

Post Lab Task:

Mechanical Switch: Mechanical Switch is a switch in which two metal plates make contact
with each other to allow current flow through them and separate to stop the current flow e.g.
a simple switch as shown is an example of mechanical switch. They are
operated by a human and cannot change its state by itself i.e. activated Figure: Mechanical switch
physically by pressing etc.

Electrical Switch: They do not require any physical contact to turn them on. They are
activated by semiconductor action. They control the operation of a switch by themselves e.g.
diode.

When voltage is applied to diode, it will remain in its cut off region until the supplied voltage
crosses the amount of threshold voltage. As soon as input voltage becomes greater than
threshold voltage, circuit becomes operational, otherwise, will remain in off state.

Figure: Diode
Critical Analysis:
In this lab, we were given the introduction about the course and the software,
TRiLOGI, which is to be used in this lab. Then, we implemented different Logic gates
(AND, OR, NOT, XOR, XNOR, NAND, NOR) and some other assigned tasks like 3-
8 & 4-16 line decoders on software using Ladder diagram. Some new terms were
introduced in this lab e.g. the “normally open” and “normally closed” contacts.
Normally open is similar to an ordinary switch, that turns on and turn off by toggling
or pressing the switch, whereas, normally closed shows reverse behavior. It gives
output when it is open i.e. off state and vice versa. Flip flops using NAND and NOR
gate along with some other assigned tasks, as a post lab, are implemented as well
using the same software and ladder logic. In short, any desired logical circuit can be
implemented in this software.