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IN5240

Fundamentals of RF Circuit Design


Part 1

Sumit Bagga* and Dag T. Wisland**


*Staff IC Design Engineer, Novelda AS
**CTO, Novelda AS

Institutt for Informatikk


Outline

• Wireless communication systems


• Performance metrics of a wireless receiver
• RF building blocks

IN5240: Design of CMOS RF-Integrated Circuits,


Dag T. Wisland and Sumit Bagga Institutt for Informatikk
Wireless Communications System

• A communication system comprises a transmitter,


a channel and a receiver
– Analog building blocks in the receiver front-end
operate at RF frequencies and interface the channel to
the receiver
– Digital circuitry is responsible for demodulation, and
decoding

IN5240: Design of CMOS RF-Integrated Circuits,


Dag T. Wisland and Sumit Bagga Institutt for Informatikk
RF Channel
RF Band

In-band blockers Out of band blocker

Wanted signal Frequency

• Standards share spectrum resources


– e.g., wideband transmissions (UWB) overlapping WLAN
• Blockers are sources of interference
– Adjacent channel or standard in the receiver band à in-band
– Out of band à blockers outside of standard

IN5240: Design of CMOS RF-Integrated Circuits,


Dag T. Wisland and Sumit Bagga Institutt for Informatikk
Channel or Band Selection at RF?

• Quality factor, ! ≝ $%& ⁄', where $%& is the carrier


frequency and B is the bandwidth
• GSM standard with RF carriers at 935-960 MHz
– If channel select à ' is 200 kHz,
• ! is 950 MHz⁄200 KHz = 4750
– If band select à ' is 25 MHz
• ! is 950 MHz⁄25 MHz = 380
• Narrowband filter characteristics
– Very high ! (' << $%& ) and tunability to select channels

IN5240: Design of CMOS RF-Integrated Circuits,


Dag T. Wisland and Sumit Bagga Institutt for Informatikk
Receiver Goals

RF Signal conditioning
• Filter in-and out-of band blockers
• Amplify the wanted signal
• Frequency translation
– Down-convert with low-IF, zero-IF, sub-sampling
receivers
• Direct-RF sampling

IN5240: Design of CMOS RF-Integrated Circuits,


Dag T. Wisland and Sumit Bagga Institutt for Informatikk
Receiver Blocks

RF signal conditioning is realized with active and


passive blocks
• Passives include switches, circulators, filters,
mixers, resonators
• Actives include low-noise amplifiers (LNA),
mixers, local oscillator (LO), variable gain
amplifier (VGA), channel select filter, analog-to-
digital converter (ADC), and a digital signal
processor (DSP)

IN5240: Design of CMOS RF-Integrated Circuits,


Dag T. Wisland and Sumit Bagga Institutt for Informatikk
Filter or LNA as 1st Receiver Block?

Interference rejection vs noise figure (NF)


• Option 1: Passive filter
– ↑ Interferer rejection, but with ↑ insertion loss à ↑ NF
• Option 2: Low-noise amplifier
– ↓ Noise figure, but receiver risks desensitization from
interferers

IN5240: Design of CMOS RF-Integrated Circuits,


Dag T. Wisland and Sumit Bagga Institutt for Informatikk
SAW Filter à Out of Band Blockers

• A non-tunable surface acoustic wave (SAW) filter


with very high ! (in the hundreds) is generally the
first (off-chip) block in the receiver chain
– Electrical signal à acoustic wave by interdigital
transducers (IDT) on a piezoelectric substrate (e.g., quartz)
à electrical signal
• Low form factor, low insertion loss, and high-
frequency operation (typically 50 MHz to 5 GHz)

IN5240: Design of CMOS RF-Integrated Circuits,


Dag T. Wisland and Sumit Bagga Institutt for Informatikk
[Liscidini, ISSCC, 2015]

Modern RF Receiver

• Heterodyne: signal to low intermediate frequency (low-IF)


• Homodyne : signal to dc (direct conversion or zero-IF)

IN5240: Design of CMOS RF-Integrated Circuits,


Dag T. Wisland and Sumit Bagga Institutt for Informatikk
Receiver Architecture Trade-Offs
Architecture J L
Direct Conversion No off-chip IF filter LO leakage
Single synthesizer LO pulling
DC offset
0/90º LO
Superheterodyne Low LO leakage Off-chip IF filter
Weak LO pulling Two synthesizers
No 0/90º LO

IN5240: Design of CMOS RF-Integrated Circuits,


Dag T. Wisland and Sumit Bagga Institutt for Informatikk
Performance Metrics of RF Receiver

• Gain
• Matching
• Noise
• Distortion
• Dynamic Range

IN5240: Design of CMOS RF-Integrated Circuits,


Dag T. Wisland and Sumit Bagga Institutt for Informatikk
Noise Factor (F) and Noise Figure (NF)
SNRout
SNRin Nout
Nin GNin

• Noise factor, ! & noise figure (is ! in dB) à


noise added by the receiver, and is:
$%&'( $'( ⁄%'( $'( %)*+ %)*+
– != =$ = =
$%&)*+ )*+ ⁄%)*+ -$'( %'( -%'(

• Power, . in dBm is 10 log (.⁄1 mW)

IN5240: Design of CMOS RF-Integrated Circuits,


Dag T. Wisland and Sumit Bagga Institutt for Informatikk
Noise, SNRmin and Sensitivity
[Power] Psens = SNRmin + Nfloor
SNRmin
[Power] Nfloor
[PSD] Nin
B
• Minimum input signal (!"#$" ) to generate an output
signal with a specified signal-to-noise ratio (SNR)
• Product of SNRmin and mean noise power or noise
floor (%&'(() )
– Minimum achievable noise at the input of the receiver

IN5240: Design of CMOS RF-Integrated Circuits,


Dag T. Wisland and Sumit Bagga Institutt for Informatikk
Receiver Sensitivity Equations

• "#$%# = '()*+% (-./ 0 1 2)


• Power spectral density (PSD), (+% is:
– 456 (-174 dBm/Hz at 290 oK)
• Mean noise power of ‘ideal’ receiver is:
– 456 8 and is typically -94 dBm for pulsed radar
• Mean noise power of ‘real’ receiver input, (9:;;< is:
– 456 8 1 =

IN5240: Design of CMOS RF-Integrated Circuits,


Dag T. Wisland and Sumit Bagga Institutt for Informatikk
[Direct RF conversion: From vision to reality, TI, 2005]

Low-IF to Direct-RF Receiver

• "# = 2&'( (Nyquist)


• Direct-RF sampling provides a higher level of integration
with fewer active chain components à lower power

IN5240: Design of CMOS RF-Integrated Circuits,


Dag T. Wisland and Sumit Bagga Institutt for Informatikk
Cascaded Noise Factor

Equivalent noise factor for IF-sampling and RF-sampling ADCs


• Cascaded noise factor is:
()$* +, ( +, ()01 +,
– " = "$%& + + .*( +
-$%& -$%& /-)$* -$%& /-)$* /-.*(
• " of ADC is
,888/9:: ; (I
– 10log + 174 dBm − FGH)01 − 10log
</=>? ;
Even with a higher conversion rate, lower FGH)01 and "F
requriements, an RF-sampling ADC vs IF-sampling ADC
requires additional FE gain (in LNA) approximately equal to
JKLM + JNKO + JPO" dB!

IN5240: Design of CMOS RF-Integrated Circuits,


Dag T. Wisland and Sumit Bagga Institutt for Informatikk
Fig. 2. UWB radar waveform example, Z L = 100 !, VTX = 0.6 V, f c = 7.25 GHz, BW = 1.5 GHz, and PRF = 14 MHz. (a) Frequency-shifted Gaussian

Swept Threshold Principle


in time domain, both polarities. (b) Corresponding frequency spectrum after PRN pattern coding, with ETSI UWB regulatory mask, assuming 6-dBi antenna
gain.

The input signal is compared with a threshold, and the


Fig. 3. ST sampling principle.

resulting
reflectors close 1-bit quantized
to the targets. The ST samplingvalue
introduces is summed
where at gain,
G is the antenna each range
λ is the bin
wavelength, k isto B
a tradeoff where the input range can be traded for sweep Boltzmann’s constant, T is the temperature in Kelvin, F is
incrementally build
times and/or processing gain thethemulti-bit
by adjusting sweep limits. theframe.
0
RX noise factor, P is the transmitted pulse power, and t
t p
The sweep time is given by the total number of pulses n pulses is the pulse duration. The transmitted pulse is approximated
and the PRF as a rectangular windowed pulse with length t p , such that the
IN5240: Design of CMOS RF-Integrated n pulses energy of the pulse E p equals
tsweep = Circuits,
Dag T. Wisland and Sumit Bagga PRF
. (3)
InstituttVfor
2 Informatikk
TX
The SNR for an ideal pulse-based radar RX from a target E p = Pt · t p = · tp . (5)
2Z L
Direct-RF Wideband Receiver

• Differential RF-FE comprises HPF, LNA and 12x time-


interleaved 1-bit quantization & sampling circuit
• DAC sets the quantization threshold
[Andersen, JSSC, 2017]

IN5240: Design of CMOS RF-Integrated Circuits,


Dag T. Wisland and Sumit Bagga Institutt for Informatikk
Sub-Sampling Receiver
FS ≥ 2B fIF

RF

Vin Vout FS (N)FS (N+1)FS

IF
DC fIF FS/2 Frequency

• For !" ≥ 2% à down-convert RF to low-IF signal


– '()**+ increases by 2' (' is the sub-sampling factor)
and phase noise increases by ' C (output of sampler)
• (2FGH +%)⁄(' + 1) ≤ !" ≤ (2FGH −%)⁄', where
' = 1,2,3, …
IN5240: Design of CMOS RF-Integrated Circuits,
Dag T. Wisland and Sumit Bagga Institutt for Informatikk
Receiver Overview

• One or more IF stages to relax the requirements of


the ‘image’ rejection filter
• Image reject mixers with I&Q LO signals to
eliminate band-pass filters (BPFs)
• Compromise à mixing with image filtering and
image reject mixing

IN5240: Design of CMOS RF-Integrated Circuits,


Dag T. Wisland and Sumit Bagga Institutt for Informatikk
Baseband to RF Wideband Transmitter
Z0
Modulator PG

• Pulse generator (PG) generates a baseband pulse


à up-converted “around” a carrier frequency with
a local oscillator
• Pulse position modulation is applied to each pulse
[Bagga, MTT, 2005]

IN5240: Design of CMOS RF-Integrated Circuits,


Dag T. Wisland and Sumit Bagga Institutt for Informatikk
[Joo, ISSCC, 2010]

Digital RRC Pulse-to-RF Upconversion TX

• DAC derived RRC pulses are filtered w/ a 400 MHz 5th-order Gm-C filter
• Passive mixer for upconversion and SE-DE class-A cascoded PA w/
resistive FB
• Classical upconversion TX consumes 36.4 mW with swing of 0.72 Vpp

IN5240: Design of CMOS RF-Integrated Circuits,


Dag T. Wisland and Sumit Bagga Institutt for Informatikk
Direct-RF Transmitter

Modulator PG PA

• Short time-duration and low peak power


requirements of the waveform makes direct-RF a
good candidate
• A time-domain, digital-intensive pulse generator is
preferred à “digital-RF” for dynamic power

IN5240: Design of CMOS RF-Integrated Circuits,


Dag T. Wisland and Sumit Bagga Institutt for Informatikk
[Mercier, RFIC 2008]
All-Digital TX w/ Capacitively
Coupled PAs

• 3-stage DCO output is modulated via dual digital PAs


comprising parallel drivers for dynamically switching signal up
to 0.7 Vpp maximum drive strength
• 4-levels of pulse shaping for 15—20 dB of sidelobe rejection
plus additional 12 dB of low frequency sidelobe rejection

IN5240: Design of CMOS RF-Integrated Circuits,


Dag T. Wisland and Sumit Bagga Institutt for Informatikk
[Andersen, JSSC, 2017]

Direct-RF Synthesis Transmitter

• 7.29/8.748 GHz dual-band BPSK pseudo-differential DPG plus PA (switching)


• Programmable PRI and 3 power levels with max. 6.4 dBm peak transmit
power

IN5240: Design of CMOS RF-Integrated Circuits,


Dag T. Wisland and Sumit Bagga Institutt for Informatikk
Impedance Matching

Z0=(L/C)-1/2
LNA Antenna
On/Off-Chip

ZLNA=RS ZANT=RS

• LNA interacts with the antenna via a transmission


line with a characteristic impedance, !"
• Maximum power absorption à antenna’s radiation
resistance, #$ is matched to the !%& of the LNA
IN5240: Design of CMOS RF-Integrated Circuits,
Dag T. Wisland and Sumit Bagga Institutt for Informatikk
[Niknejad, EECS 242]

Scattering Parameters

• Difficult to measure voltages/currents at RF à


S-parameters w/ ‘power’ flow
– "# = "%&,( − "*
• "%&,( = ,(- /801

• Signal flow and Mason’s rule to calculate input


reflection, transducer gain of a two-port network
IN5240: Design of CMOS RF-Integrated
Circuits, Dag T. Wisland and Sumit Bagga Institutt for Informatikk
Return Loss and Mismatch Loss

• Absolute impedance ! " + $ "


('()* ), -.,
• Reflection coefficient, Γ is
('-)* ), -.,

– 01 is the source impedance


234
• Voltage standing wave ratio (VSWR) is 254
• Return loss (S11) is −20log(Γ)
• Mismatch loss is −10(1 − Γ " )

IN5240: Design of CMOS RF-Integrated Circuits,


Dag T. Wisland and Sumit Bagga Institutt for Informatikk
Smith Chart − * is +11 !
Constant reactance

Constant resistance

Minimum requirement |+11| < -10 dB (90% power transfer) and


preferably -20 dB (99% power transfer)
IN5240: Design of CMOS RF-Integrated Circuits,
Dag T. Wisland and Sumit Bagga Institutt for Informatikk
L’s and C’s

IN5240: Design of CMOS RF-Integrated


Circuits, Dag T. Wisland and Sumit Bagga Institutt for Informatikk
Amplifier Noise Factor
Rs v2eq

Noiseless
Vs
2-port

• Equivalent noise voltage, !"# = !% + '( )%


*
• For uncorrelated noise sources, !"# = !%* + |'( |* )%*
7
456
./,12
• Noise factor, , = 1 + =1+
.3 437

IN5240: Design of CMOS RF-Integrated Circuits,


Dag T. Wisland and Sumit Bagga Institutt for Informatikk
Minimum Noise Factor –
Noise Matching
• For the minimum noise factor, !"#$
(
– ! = !"#$ + *) |-. − -012 | 3
+

• Source impedance, -. ≠ -012 à ! ↑ with 2 factors


– Minimizing 6$ à ↓ noise match sensitivity

IN5240: Design of CMOS RF-Integrated Circuits,


Dag T. Wisland and Sumit Bagga Institutt for Informatikk
Passive Input Termination
• Low-complexity and cheap
• Neglecting the noise of the RL
transistor, the ! due to the input
termination resistor, "# is:
+
()* Rs
– ! >1+
(,+
-.01 ⁄23 2, R1
– !> 1 + -.0 ⁄2 = 1+2 =2
1 , 3

– ∵ "7 ≈ "#, i.e., 3 dB in 9!

IN5240: Design of CMOS RF-Integrated Circuits,


Dag T. Wisland and Sumit Bagga Institutt for Informatikk
Active Input Termination
• Impedance seen at source of
CG-stage is "!#
RL
!
• Assume "#
≈ %& , thus,
. 4
,- 123 6#
5
• ( >1+ =1+ =
,/. 1237/
8
1+ ≈2
9
8
– ∵ for short channel device, ≈2 Rs
9

IN5240: Design of CMOS RF-Integrated Circuits,


Dag T. Wisland and Sumit Bagga Institutt for Informatikk
Noise Figure Common-Source Stage
• Noise at the output
– "#$ = "&$ + "($ + (*+$ + *,$)./
$

• Noise factor
234 674 8694 ;3 =⁄> ?
– 0 =1+ + =1+ ;5
+; + + ; +4 ;
254 254 +:
4 5 : 5 : 9

• If ./ ↑ gate resistance, A+ ↓
– Two components à physical gate resistance (poly) and
induced channel resistance
– Multi-finger layout à ↓ {A+ and junction capacitance}

IN5240: Design of CMOS RF-Integrated Circuits,


Dag T. Wisland and Sumit Bagga Institutt for Informatikk
Intermodulation Distortion (IMD)

f2
G f1,f2+IMD
f1

• Distortion à harmonic(s) generation


• Blockers à intermodulation products (IMD) à ↓SNR
2 signals (!" , !# ) at input à !" , !# + IMD products
– Second order: !" − !# , !# − !" , 2!" , 2!#
– Third order: 2!" − !# , 2!# − !" , 3!" , 3!#

IN5240: Design of CMOS RF-Integrated


Circuits, Dag T. Wisland and Sumit Bagga Institutt for Informatikk
IIP/OIP, IMD Products and P1dB
∆(
• nth order intercept point, IP# = % + )*+
((1 *(234 )
– OIP3 = %/ +
6
– IIP3 = OIP3 − G
((1 *(234 )
– IIP3 = %9 + 6
• e.g., two 10 dBm tones à -20 dBm 3rd order IMD
+<* *6<
products à IP3 = 10 + = 25 dBm
=*+
• 1 dB compression point (P1dB) is where the
fundamental drops by 1 dB
IN5240: Design of CMOS RF-Integrated
Circuits, Dag T. Wisland and Sumit Bagga Institutt for Informatikk
IP3 for Cascaded Stages

• 3rd-order intercept point is:


" " " "
– #$%&
=( +( + #$%
) (* #$%* , #$%) ,

– IIP3 = OIP3/(3"343&)
• 2nd-order intercept point is:
" " " "
– = + +
#$%4 () (* #$%* (, #$%) #$%,
– IIP2 = OIP2/(3"343&)

IN5240: Design of CMOS RF-Integrated


Circuits, Dag T. Wisland and Sumit Bagga Institutt for Informatikk
Spurious Free Dynamic Range (SFDR)

• SFDR is difference in dB à power of the blocker


(!" ) to sensitivity (!#$%# ), when !" à IM3 = *+,--.
– !#$%# = 0*123% + *+,--.
– IM3 = 3!" − 2IIP3 = *+,--.
D EEFGH=IJKKL
• 09:1|<=>?@ABC = G
D EEFGH(HRST UVWXYZ[ \]\RC^_`("))
• SFDR = − 0*123%
G

IN5240: Design of CMOS RF-Integrated


Circuits, Dag T. Wisland and Sumit Bagga Institutt for Informatikk
Summary

• Receiver topologies and trade-offs


• Impedance matching à reflection coefficient, !""
• Interdependencies of noise figure, sensitivity
(minimum detectable signal), SNR and SFDR
• Metrics P1dB, IIP2, IIP3 (TOI) to characterize
linearity

IN5240: Design of CMOS RF-Integrated


Circuits, Dag T. Wisland and Sumit Bagga Institutt for Informatikk
Key References

1. A. M. Niknejad, EECS 142 and 242


2. A. Liscidini, “Fundamentals of Modern RF
Receivers,” ISSCC 2015
3. N. Andersen, “A 118-mW Pulse-Based Radar
SoC in 55-nm CMOS for Non-Contact Human
Vital Signs Detection,” JSSC, 2017

IN5240: Design of CMOS RF-Integrated


Circuits, Dag T. Wisland and Sumit Bagga Institutt for Informatikk
Homework L
1. For each block in a receiver chain (i.e., RF filter,
LNA, mixer, channel select filter), find values for G,
NF, and IIP3, such that the front-end realizes:
– G > 90 dB, NF ≤ 3 dB, IIP3 > -15 dBm referred to 50 Ω
– https://www.mathworks.com/help/rf/examples/finding-
cascaded-gain-noise-figure-and-ip3.html
2. A pre-amplifier with an input impedance of 100 Ω is
placed after the 50 Ω input matched LNA. What is
the noise figure of the pre-amplifier? Hint: calculate
input referred noise power.

IN5240: Design of CMOS RF-Integrated


Circuits, Dag T. Wisland and Sumit Bagga Institutt for Informatikk

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