17BEC0085

RVR Abhiram
Slot: C1
1. a. Draw the clear Block Diagram of the Microprocessor /
Microcontroller/ IP core selected. b. Give the internal
Diagram of each and every block.
2. Provide the Instruction set of the Micro Processing
element (Microprocessor/ Microcontroller/ IP core) with clock
cycle required/Machine cycle required, memory required,
flags affected, type of instruction based on addressing
modes, operation, etc.
3. Explain Micro processing element (Microprocessor/
Microcontroller/ IP core) Architecture.
The microcontrollers of tlcs-900 series are mostly based on CISC
architecture with a few systems based on RISC architecture.
The MCUs are the industry's first 32-bit microcontrollers based on
a CISC architecture with that level of memory on chip, according
to Toshiba.
The TMP92CW53F and 92CW10F contains a new 32-bit central
processing unit core, called the TLCS-900/H1. Toshiba said the
CPU core has been designed for lower power consumption and
enhanced processor performance compared to other solutions,
including MCUs based on reduced instruction set computing
(RISC).
4. Correlate the Microprocessing element
(Microprocessor/controller/IP core) architecture with
architectures discussed in Module 1.
8051- If the user wants a controller with basic functions then 8051
will suffice. It will be of great use in your low-cost college projects.
• TLCS 900 has a 8and/or 16 and/or 32-bit architecture. The 8051
is byte (8-bit) architecture.
• 8051 has limited stack space – limited to 128 bytes for the
8051. Writing a C compiler for these architectures must have
been challenging, and compiler choice is limited
. • 8051 and TLCS 900 can directly address all available RAM.
• Both 8051 and TLCS 900 use CISC Architecture.
• 8051 has a bus width of 8 bit in size and TLCS 900h has a bus
width of 16 bits.
5. Elaborate Register organisation of Micro processing
element.

 Register bank system One of the follwing mode can be

selected.
• Minimum mode: eight 16-bit register banks
• Maximum mode: four 32-bit register banks
 Minimum mode: 64-Kbyte program area/16-Mbyte data area
 Four 16-bit general-purpose registers × 8 banks
+ Four 32-bit general-purpose registers + 16-bit program
counter
 Maximum mode: 16-Mbyte program area/16-Mbyte data
area Four 32-bit general-purpose registers × 4 banks + Four
32-bit general-purpose registers + 32-bit program counter
 Stack Pointer
 The stack pointer is provided for only System mode (XSP).
The System stack pointer (XSP) is set to 100H by resetting.



 General-purpose bank registers
 The TLCS-900 series has two register formats. Which of the
register formats is used depends on whether the mode is
minimum or maximum. In either way, the register sets and
registers in each bank are used exactly the same.
 General-purpose Bank Registers in Minimum Mode In
minimum mode, the following four 16-bit general-purpose
registers consisting of 8 banks can be used. The register
format in a bank is shown below.
 Four 16-bit registers (WA, BC, DE and HL) are general-
purpose registers and can be used as accumulators, index
registers, and displacement registers. They can also be used
as 8-bit registers (W, A, B, C, D, E, H and L) to function for
example as accumulators.

 General-purpose Bank Registers in Maximum Mode
 In maximum mode, the following four 32-bit general-purpose
registers consisting of 4 banks can be used. The register
format in a bank is shown below.
 Four 32-bit registers (XWA, XBC, XDE and XHL) are
general-purpose registers and can be used as an
accumulators and index registers. They can also be used as
16-bit registers (WA, BC, DE and HL), in which case, the
lower 16 bits of the 32-bit registers are assigned
 16-bit registers can be used as accumulators, index registers
in index addressing mode, and displacement registers. They
can also be used as two 8-bit general-purpose registers (W,
A, B, C, D, E, H and L) to function for example as
accumulators.


 32-bit General-purpose Registers
 The TLCS-900 series has four 32-bit general-purpose
registers (XIX, XIY, XIZ and XSP). They are fixed,
independent of maximum or minimum mode. The register
format is shown below.
 These registers can also be used as accumulators, index
registers, and displacement registers. They can be used
either as 16-bit, or 8-bit registers. Names when registers are
used as 8-bit registers are listed later.


 Stack Pointer
 The XSP register is utilized for stack pointer. It is used when
the interrupt is occured or “CALL”, “RET” instruction are
executed. The stack pointer (XSP) is set to 100H by
resetting.
 Status Register (SR)
 The status register contains flags indicating the status
(operating mode, register format, etc.) of the CPU and
operation results. This register consists of two parts. The
upper byte of the status register (bits 8 to 15) indicates the
CPU status. The lower byte (bits 0 to 7) are referred to as
the flag register (F). This indicates the status of the operation
result. The TLCS-900 series has two flag registers (F and
F´). They can be switched using the EX instruction.
 (1) Upper Byte of Status Register


 1. SYSM (System Mode)
 2. IFF2 to IFF0 (Interrupt mask Flip-Flop2 to 0)


 3. MAX ( MINimum / MAXimum)


 Flag Register, F


 1. S (Sign flag) “1” is set when the operation result is
negative, “0” when positive. (The value of the most
significant bit of the operation result is copied.)
 2. Z (Zero flag) “1” is set when the operation result is zero,
otherwise “0”.
 3. H (Half carry flag) “1” is set when a carry or borrow from
bit 3 to bit 4 occurs as a result of the operation, otherwise
“0”. With a 32-bit operation instruction, an undefined value is
set.
 4. V (Parity/over-flow flag) Indicates either parity or
overflow, depending on the operation type. Parity (P): “0” is
 set when the number of bits set to 1 is odd, “1” when even.
An undefined value is set with a 32-bit operation instruction.
Overflow (V): “0” is set if no overflow, if overflow “1”.
 5. N (Negative) ADD/SUB flag “0” is set after an addition
instruction such as ADD is executed, “1” after a subtraction
instruction such as SUB. Used when executing the DAA
(decimal addition adjust accumulator) instruction.
 6. C (Carry flag) “1” is set when a carry or borrow occurs,
otherwise “0”.


6. Explain the type of algorithm used for signed/unsigned

Calculations (Addition, Multiplication, etc.).
7. Find what type of control logic unit used and correlate its
performance with the type of control unit in Module 3 in the
COA syllabus.
The TMP92FD54AI is a high-performance 32-bit microcontroller
incorporating a Toshibaproprietary CPU, the TLCS-900/H1 core.
The TMP92FD54AI is developed for various automotive
equipments which require high-speed data processing. Housed in
a 100-pin mini-flat package, the TMP92FD54AI is best suited for
high-density implementation of user systems.
Toshiba-proprietary high-speed 32-bit CPU (TLCS-900/H1 CPU)
Fully-compatible with the instruction codes of the TLCS-900,
TLCS-900/L, ELCS-900/L1, TLCS-900/H and TLCS-900/H2
16 Mbytes of linear address space General-purpose registers and
register banks Micro DMA:
8 channels (250 ns/4 bytes at fc = 20 MHz)
Minimum instruction execution time: 50 ns (at fc = 20 MHz)
Control Unit (8051)
• The Control unit consists of a microcontroller which receives
signals from the sensors and decides what operations to be
performs by the system. The microcontroller used in the module 4
of COA was 8051 cores.
• We can interface it with a DC motor whose motion can be
controlled with the received signals from the sensors.
• It’s a low power, high performance CMOS 8-bit microcontroller
with 4K bytes of In-System Programmable Flash memory, 128
bytes of RAM, 32 I/O lines, Watchgod timer, two data pointers,
two 16 bit timer/counters, a five-vector twolevel interrupt
architecture, a full duplex serial port, on-chip oscillator and clock
circuitry.
8. Explain the memory management system in the
processing element selected. List its Addressing capabilities,
Memory mapping technique followed. Find the advantage of
memory design and management techniques over the
concepts given in Module 4 in the COA syllabus.
Memory Map

Mask programmable, one time programmable, flash

memory or EEPROM type of ROM.
Flash Memory
Features
1) Memory Capacity The TMP92FD54AI has a 4-Mbit (512-Kbyte)
flash memory, which is divided into a total of ten blocks (64
Kbytes × 6 blocks, 56 Kbytes × 2 blocks, 8 Kbytes × 2 blocks) to
allow for independent protection from program and erase for each
block. When the CPU attempts to access the internal flash
memory, it uses the 32-bit data bus.
2) Flash Memory Access Interleaved access (2-1-1-1 clock
access)
3) Program/Erase Time Chip programming time: 6 seconds
(typ.), including program verify operations [30 µs / long word
(typ.)] Chip erase time: 12 seconds (typ.), including program verify
operations
8051 Memory Organization The 8051 microcontroller's memory is
divided into Program Memory and Data Memory. Program
Memory (ROM) is used for permanent saving program being
executed, while Data Memory (RAM) is used for temporarily
storing and keeping intermediate results and variables. Program
Memory (ROM) Program Memory (ROM) is used for permanent
saving program (CODE) being executed. The memory is read
only. Depending on the settings made in compiler, program
memory may also used to store a constant variables. The 8051
executes programs stored in program memory only. code memory
type specifier is used to refer to program memory. 8051 memory
organization alows external program memory to be added. How
does the microcontroller handle external memory depends on the
pin EA logical state.
9. Elaborate the pipeline and parallel processing capabilities
of the unit and hazard management technique.
• Pipeline system with 4-byte instruction queue buffer
Instruction pipelining is a technique for implementing instruction-
level parallelism within a single processor. Pipelining attempts to
keep every part of the processor busy with some instruction by
dividing incoming instructions into a series of sequential steps
If the processor has the 5 steps listed in the initial illustration,
instruction 1 would be fetched at time t1 and its execution would
be complete at t5. Instruction 2 would be fetched at t2 and would
be complete at t6. The first instruction might deposit the
incremented number into R5 as its fifth step (register write back)
at t5. But the second instruction might get the number from R5 (to
copy to R6) in its second step (instruction decode and register
fetch) at time t3.
• IF: Fetches the instruction into the instruction register.
• ID: Instruction Decode, decodes the instruction for the opcode.
• AG: Address Generator, generates the address.
• DF: Data Fetch, fetches the operands into the data register.
• EX: Execution, executes the specified operation.
• WB: Write back, writes back the result to the register.
Pipelining Hazards
In a typical computer program besides simple instructions, there
are branch instructions, interrupt operations, read and write
instructions. Pipelining is not suitable for all kinds of instructions.
In most of the computer programs, the result from one instruction
is used as an operand by the other instruction. When such
instructions are executed in pipelining, break down occurs as the
result of the first instruction is not available when instruction two
starts collecting operands. So, instruction two must stall till
instruction one is executed and the result is generated. This type
of hazard is called Read –after-write pipelining hazard.
10. Find whether processor level parallelism is available in
the element selected. Illustrate cache coherence and
protocol used for handling memory HIT or MISS.
Cache coherency is an important concept to understand when
sharing data. Disabling caches can impact performance; software
coherency adds overheads and complexity; and hardware
coherency manages sharing automatically which can simplify
software. The AMBA 4 ACE bus interface extends hardware
cache coherency outside of the processor cluster and into the
system.
There are three mechanisms to maintain coherency:
• Disable caching is the simplest mechanism but may cost
significant CPU performance. To get the highest performance
processors are pipe-lined to run at high frequency, and to run
from caches which offer a very low latency. Caching of data that
is accessed multiple times increases performance significantly
and reduces DRAM accesses and power. Marking data as “non-
cached” could impact performance and power.
• Software managed coherency is the traditional solution to the
data sharing problem. Here the software, usually device drivers,
must clean or flush dirty data from caches, and invalidate old data
to enable sharing with other processors or masters in the system.
This takes processor cycles, bus bandwidth, and power.
• Hardware managed coherency offers an alternative to simplify
software. With this solution any cached data marked ‘shared’ will
always be up to date, automatically. All processors and bus
masters in that sharing domain see the exact same value.
Software managed coherency manages cache contents with two
key mechanisms:
• Cache Cleaning (flushing):
• If any data stored in a cache is modified, it is marked as ‘dirty’
and must be written back to DRAM at some point in the future.
The process of cleaning or flushing caches will force dirty data to
be written to external memory.
• Cache Invalidation:
 • If a processor has a local copy of data, but an external agent
updates main memory then the cache contents are out of date, or
‘stale’. Before reading this data, the processor must remove the
stale data from caches, this is known as ‘invalidation’ (a cache
line is marked invalid). An example is a region of memory used as
a shared buffer for network traffic which may be updated by a
network interface DMA hardware; a processor wishing to access
this data must invalidate any old stale copy before reading the
new data.
• An access to an item which is in the cache is called a hit, and an
access to an item which is not in the cache is a miss.