IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO.

1, JANUARY 2005 293

A 0.18-m 3.0-V 64-Mb Nonvolatile Phase-Transition

Random Access Memory (PRAM)
Woo Yeong Cho, Beak-Hyung Cho, Byung-Gil Choi, Hyung-Rok Oh, Sangbeom Kang, Ki-Sung Kim,
Kyung-Hee Kim, Du-Eung Kim, Choong-Keun Kwak, Hyun-Geun Byun, Youngnam Hwang, SuJin Ahn,
Gwan-Hyeob Koh, Gitae Jeong, Hongsik Jeong, and Kinam Kim, Fellow, IEEE

Abstract—A nonvolatile 64-Mb 1T1R phase-transition random

access memory (PRAM) has been developed by fully integrating
chalcogenied storage material (GST: Ge2 Sb2 Te5 ) into 0.18- m
CMOS technology. To optimize SET/RESET distribution, 512-kb
sub-array core architecture was proposed, featuring meshed
ground line and separated SET/RESET control schemes. Random
read access time, random SET and RESET write access times
were measured to be 60 ns, 120 ns, and 50 ns, respectively, at 3.0-V
supply voltage with 30 C.
Index Terms—Phase change, phase-transition random access
memory (PRAM), RESET, SET. Fig. 1. Basic structure of PRAM unit-cell.

I. INTRODUCTION

A PHASE-TRANSITION random access memory (PRAM)

which uses chalcogenide alloy (GST: Ge Sb Te ), is pro-
grammed by resistive heating with current pulses that drive the
cell into high or low resistance state (RESET or SET state)
[1]–[4]. Stored data is read out from its resistance difference [5],
[6]. As shown in Fig. 1, PRAM cell is composed of a standard
access transistor plus a storage element of GST alloy which has
been used for rewritable compact disk (CD) or DVD disk. The
top of GST is connected to the bit-line (B/L) through top-elec-
trode-contact (TEC) and the bottom of GST is connected to
Fig. 2. RESET current as a function of BEC size.
the drain of access transistor through bottom-electrode-contact
(BEC) and bottom-electrode (BE). Using this simple cell struc-
ture, it is easy to integrate GST cells into a conventional CMOS
process. BEC works as a heater tip to make GST transition
between SET and RESET state. The size of BEC is about 45
nm and the entire cell size is 0.504 m , which corresponds
to 16 F . Fig. 2 shows the reduction of RESET current with
BEC size. For a BEC size of 45 nm, RESET current is about
1 mA. To reduce RESET write current, many researches were Fig. 3. Basic operational characteristics of PRAM cell.
tried such as a development of storage material [7] and a modi-
fication of PRAM cell structure [8]. Fig. 3 shows a basic opera- for read operation by forcing read bias current and typical re-
tional characteristic of PRAM cell. SET state means crystalline sistance difference ratio is more than . Write operation is
low-resistance state with logic “L” state and RESET state means performed by heating the GST cell by injecting write current.
amorphous high-resistance state with logic “H” state. The re- RESET state of GST cell is obtained by heating GST cell above
sistance difference between SET and RESET state is sensed melting temperature with fast quenching. SET state of GST
cell is obtained by heating above crystallization temperature
Manuscript received April 15, 2004; revised May 10, 2004. and below melting temperature with gradual quenching process.
W. Y. Cho, B.-H. Cho, B.-G. Choi, H.-R. Oh, S. Kang, K.-S. Kim, K.-H. Kim, With its nonvolatile byte write in either direction, the writing
D.-E. Kim, C.-K. Kwak, and H.-G. Byun are with the SRAM team, Memory
Division, Samsung Electronics Company, Ltd., Hwasung-City, Gyeonggi-Do, speed of PRAM is much faster than that of Flash memory and
Korea 445-701 (e-mail: solarmac.cho@samsung.com). cell size is smaller than SRAM due to its simple structure. Due
Y. Hwang, S. Ahn, G.-H. Koh, G. Jeong, H. Jeong, and K. Kim are with to these promising characteristics of nonvolatile random acces-
the Technology Development Team, Memory Division, Samsung Electronics
Company, Ltd., Yongin-City, Gyeonggi-Do, Korea. sibility with high density, PRAM is one of the candidates for
Digital Object Identifier 10.1109/JSSC.2004.837974 future memory technology. Currently, as shown in Fig. 4, the
0018-9200/$20.00 © 2005 IEEE

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294
Fig. 4. Example of the advantage of random accessibility of PRAM. (a) Flash
Flash memory plus RAM buffer solution is widely used for mo-
bile applications. With the added complexity of buffering with
SRAM, complex four steps are required to change one-byte data
in Flash memory for nonvolatile retention. At the first step, the
entire corresponding block is dumped to DRAM. Next within
DRAM, the new one-byte of data is changed. Next within Flash,
the corresponding block is erased, and finally, the changed block
is programmed from DRAM to Flash memory. However, by
using a PRAM solution, random access byte write is possible
and needs only one step that reduces write time by times.
The potential performance of PRAM features notably higher
write speed than Flash, smaller cell size than SRAM, but also
simpler circuitries than Flash and DRAM because PRAM does
not need high-voltage boosting and refresh/restore operations.
Thus, PRAM can merge advantageous aspects of conventional
mobile memory technologies. In this work, we describe a de-
veloped 64-Mb PRAM featuring 512-kb sub-array core archi-
tecture with full integration of GST into 0.18- m CMOS tech-
nology. On-chip circuits fully control SET/RESET resistance
states stably with minimal stand-by power consumption and
nonvolatile random read/write operation. The SRAM interface
was employed to confirm the feasibility of PRAM use in low-
power mobile applications.
II. CORE ARCHITECTURE
64-Mb density PRAM core is constructed with 128 sub-array
blocks of 512 kb, by collating 16 blocks in the direction of
row and 8 blocks in the direction of column. As depicted in
Fig. 5, a sub-array core consists of 512-kb cell array organized
as 1024 word-line drivers (SWD), 512 column select/precharge
circuits, 8 I/O sense-amplifiers and
8 write drivers . For read and write operation, each
top and bottom circuit connects 4 B/L to
S/A for reading, and W/D for writing. Sharing the SWD, S/A,
W/D and circuitries with adjacent 512-kb
sub-array cores make chip layout more efficient and simpler.
Since I/O S/A and W/D are included in every 512-kb sub-array
core, read and write related operational margins do not degrade
with combining sub-blocks to obtain higher cell density (64 Mb
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 1, JANUARY 2005
+ RAM solution case. (b) PRAM case.
or higher). In the case of write operation, the amount of write
current which flows from W/D to cell ground line through
circuit, B/L, GST and access NMOS
transistor, is very important to guarantee uniform SET/RESET
resistance states. Tungsten (W) ground lines within a cell array
causes considerable rise of ground level due to its relatively
high resistivity. Meshed ground strapping lines of Aluminum
(Al) with resistivity almost 7 times lower than W, attach every
16 cells along the column and 64 cells along the row. This
technique restricts the ground voltage variation in the cell array
to less than 50 mV during SET/RESET write operation.
III. SET WINDOW
Fig. 6 shows the change of GST resistance with applied
voltage for all GST cells under same test condition. The resis-
tance of SET and RESET state show Gaussian like distribution
with target minimum and maximum values. These distributions
are intrinsic and may come from process variations such as
BEC size variation and local uniformity variation of GST
composition. The SET window can be defined as ,
where as shown in
the R–V curve. This SET window and its distribution are very
important factors for designing cell array size, S/A and W/D. In
addition to the SET window defined from R–V characteristics,
the influence of B/L, needs to be considered to obtain the
real SET window. A typical I–V curve for GST based cell and
B/L configuration are shown in Fig. 7. The B/L resistance for
the cell located far from the W/D is larger. The B/L voltage for
far cell, which is defined as , is lower than that of the near
cell defined as . To transit GST cell to SET state, the voltage
applied across the GST layer should be controlled between
and . is the threshold voltage
( , typically 1.0 V) for phase transition of GST.
is the RESET voltage at which GST material starts to melt.
Thus, to obtain reliable SET operation, the voltage difference
between and , defined as , should be within the
. Especially the B/L voltage far from the W/D
defined as must be larger than to guarantee
entering minimum SET operation. From the statistical distri-
bution analysis of the intrinsic defined from the
CHO et al.: NONVOLATILE PHASE-TRANSITION RANDOM ACCESS MEMORY (PRAM) 295

Fig. 5. 512-kb sub-array core architecture having common shared SWD, S/A, and W/D.

R–V curve in Fig. 6, the mean and standard deviation of the far cell, , becomes lower than injected into the near
are essential design parameters to construct cell cell. This contributes to further reduction of . In our design
array, since small with wide distribution make it with B/L with Al, 1024 cells per bit-line (CPB) architecture
very challenging to aim the SET-voltage range to appropriate has of 0.5 k with of 250 mV that corresponds to
level. In this work, as depicted in Fig. 8(a), and values are of . The SET fail probability of far cells is
1.53 V and 380 mV, respectively. The minimum SET window statistically only 0.04%. If is about 1.5 k , the voltage
which is far from the value by is 390 mV. This corresponds drop from to is 770 mV. In this case, several percent
to statistical SET fail probability of 0.13% for far cells. Another of far cells cannot be changed from the previous resistance
factor that needs to be considered is that varies with the states during SET operation. As a result, 512-kb sub-array core
distance between W/D and PRAM cells. When the PRAM having 1024 CPB architecture is suitable for stable read and
cells selected for writing are far from the W/D, makes the write operation of PRAM.
voltage difference of . Fig. 8(b) is a simulation result of
as a function of which shows the increasing IV. DEVICE CHARACTERISTICS
with increased . The intrinsic minimum SET window of
390 mV which is defined from the distribution characteristic A. S/A and W/D Schematics
of SET window implies an equivalent of 0.8 k , which Fig. 9 shows a simplified schematic for read and write op-
corresponds to the maximum allowed for acceptable SET eration consisting of current mirror type W/D, S/A,
operation of far cells. Since the W/D is a nonideal current and PRAM cell. When cells are not selected or
source for B/L voltage variations, the performance of the W/D in stand-by mode, all the B/L are precharged to ground level by
is degraded with larger such that SET current injected into enabling PREBL signal so that current consumption in sub-cell

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296
Fig. 6. Typical GST R–V curve having SET voltage window.
Fig. 7. Typical GST I–V curve and BL configuration.
array is near zero. During read operation, to prevent uninten-
tional write, the selected B/L is clamped below 0.5 V, which
is sufficiently lower than the threshold voltage of GST cell.
The S/A is a single ended voltage type with reference voltage
. Also, read bias current is adjustable to allow extracting
the distributions of GST-resistance state after various write op-
eration. For SET and RESET operations, two separated current
W/D sources are used respectively to control the height and du-
ration of applied pulses, independently.
B. Read/Write Operation
Fig. 10 shows the simulation results for read operation,
showing voltage levels at input and output nodes of S/A, B/L
clamping behaviors, and DQ results with SET resistance of 1
k and RESET resistance of 100 k cases. The S/A read bias
current is supplied form the S/A input node. With W/L and
enabled, BL is clamped below of GST. The S/A
input node drop to the B/L level for reading SET state and S/A
input node maintains its precharged level (nearly Vcc level)
for reading the RESET state. Even though the timing margin
for S/A enable and other read-related control signals are not
tight, the random access time is 60 ns both by simulation
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 1, JANUARY 2005
Fig. 8. (a) SET voltage window distribution characteristic and (b) BL voltage
versus BL resistance characteristics.
Fig. 9. Simplified S/A, W/D, and BL schematics.
and actual measurement at 3.0-V supply voltage with 30 C.
This access time is fast enough for mobile applications. For
reduction of active power consumption, address-transition-de-
tectors (ATD) are used to activate a pulsed W/L scheme. In
this scheme, W/L is activated only when external addresses are
changed.
During write operation referring to Fig. 9, SET and RESET
current are delivered by W/D which is included within each
sub-array core block. To verify SET and RESET write character-
istics, W/L is statically activated during write operation. Using
separate SET and RESET control logic for independent pulse
height and duration, various write conditions could be tried for
verification. Fig. 11 shows voltage level at BL during SET and
RESET operations. For stable write operation, the required min-
imum write pulse widths of SET and RESET were 80 and
20 ns, respectively, with a pulse height ratio of 0.8. The pulse
durations for random access write time are 120 ns for
SET state and 50 ns for RESET state at 3.0-V supply voltage
with 30 C.
CHO et al.: NONVOLATILE PHASE-TRANSITION RANDOM ACCESS MEMORY (PRAM) 297

Fig. 10. Simulation waveforms of read operation.

Fig. 11. Simulation waveforms of SET/RESET write operation.

C. On Chip Resistance Distribution

The distribution characteristics of SET and RESET resis-

tances are shown in Fig. 12. The SET and RESET resistances
are extracted by counting pass/fail bits while varying read
bias current as shown in Fig. 9. For the as-fabricated
chip, before any write operation, the initial distribution of GST
resistance ranged from 1 k to 1 M . After optimum SET
and RESET operations, the typical SET and RESET resistance
values were 2 k and 200 k , respectively. Thus, the resistance
difference between SET and RESET is large enough for the
S/A to determine data state using a reference voltage only,
without reference cells.

D. Design Summary

Fig. 13 shows the microphotograph of the fabricated 64-Mb

PRAM chip in which GST storage materials were fully inte-
grated into 0.18- m CMOS technology. External pads include
power pins, address pins, and control pins, located at top and
bottom. For two-byte (x16) operation, the left-half 32 Mb is
used for the lower-byte (LB) and the right-half 32 Mb is used for
the upper-byte (UB). 128 sub-core arrays are placed above and
below the periphery circuits. Design feature and device perfor-
mance of the test chip are summarized in Table I. In this work, a
64-Mb PRAM was successfully developed for the first time with
the highest reported density. As an access device, NMOS was
Fig. 12. Resistance distribution of GST cell before/after initial write.
used instead of bipolar transistor (BJT) or diode, because scala-
bility of PRAM cell using NMOS transistor as an access device
is better than a BJT or diode beyond sub-100-nm technology
to satisfy the high write current requirement. Using dual gate
polysilicon, Co-salicidation, and triple metal process with de-
sign rule of 0.18- m, the unit cell size is 0.504 m and the chip
size is 70 mm . Read, SET and RESET random access times are

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298 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 1, JANUARY 2005

TABLE I
SUMMARY OF CHIP PERFORMANCES AND PROCESS TECHNOLOGY

cell is less than 0.5 k . So the statistical SET fail probability

of far cells was only 0.04%. The typical on-chip SET and
RESET resistances were 2 k and 200 k , respectively. The
device was fully functional at 3.0 V. Random read access
time of 60 ns, random SET write time of 120 ns and random
RESET write times of 50 ns were achieved. Operating current
is 30 mA at 70-ns cycle time and stand-by current is 5 A
at 3.0-V supply voltage with 30 C.

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[4] A. Pirovano, A. L. Lacaita, A. Benvenuti, F. Pellizzer, and R. Bez, “Elec-
tronic switching in phase-change memories,” IEEE Trans. Electron De-
vices, vol. 51, no. 3, pp. 452–459, Mar. 2004.
[5] M. Gill, T. Lowrey, and J. Park, “Ovonic unified memory—A high-per-
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Papers, 2002, pp. 202–203.
[6] Y. N. Hwang et al., “Full integration and reliability evaluation of phase-
change RAM based on 0.24 m-CMOS technologies,” in Symp. VLSI
Technology Dig. Tech. Papers, Jun. 2003, pp. 173–174.
[7] H. Horii, J. H. Yi, J. H. Park, Y. H. Ha, I. G. Baek, S. O. Park, Y. N.
Hwang, S. H. Lee, Y. T. Kim, K. H. Lee, U.-I. Chung, and J. T. Moon,
“A novel cell technology using n-doped GeSbTe films for phase change
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[8] Y. H. Ha, J. H. Yi, H. Horii, J. H. Park, S. H. Joo, S. O. Park, U.-I. Chung,
and J. T. Moon, “An edge contact type cell for phase change RAM fea-
60 ns, 120 ns, and 50 ns, respectively at 3.0-V supply voltage turing very low power consumption,” in Symp. VLSI Technology Dig.
with 30 C. Tech. Papers, 2003, pp. 175–176.

V. CONCLUSION

A GST alloy with an NMOS transistor PRAM cell configura- Woo Yeong Cho received the B.S., M.S., and Ph.D.
tion is very convenient for integration with conventional CMOS degrees in electrical engineering from Korea Ad-
vanced Science and Technology (KAIST), Taejon,
process. Through built-in S/A and W/D within sub-array core Korea, in 1992, 1994, and 1999, respectively.
architecture and a meshed Al ground plane, read and write In 1999, he joined Samsung Electronics, where he
related margin was secured. The distribution characteristic of has been involved in low-power SRAM, UtRAM and
is working on the circuit design for next-generation
intrinsic SET window that is introduced from process variation memories such as PRAM, MRAM, and STTM (Scal-
has a mean value of 1.53 V with standard deviation of 380 mV. able Two Transistor Memory).
By using 1024 CPB configuration, the BL resistance to a far

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CHO et al.: NONVOLATILE PHASE-TRANSITION RANDOM ACCESS MEMORY (PRAM)
Beak-Hyung Cho received the B.S. degree in
electrical engineering from Ajou University, Suwon,
Korea, in 1994.
In 1995, he joined Samsung Electronics Company,
Yong-In, Korea, and has been working on design of
low-power SRAM. His interests are in analog circuits
and new memory development including MRAM and
PRAM.
Byung-Gil Choi was born in Po-Hang, Korea,
on May 3, 1971. He received the B.S. degree in
semiconductor science from Dong-guk University,
Korea, in 1999.
He joined the Memory Division, Samsung Elec-
tronics Corporation, Kiheung, Korea, in 1989, where
he was involved in the circuit design of SRAM,
UtRAM, and PRAM. At present, he has been
working on circuit design of new memory PRAM.
Hyung-Rok Oh received the B.S. and M.S. degrees
in electrical engineering from Yonsei University,
Seoul, Korea, in 1994 and 1999, respectively.
In 2000, he joined Samsung Electronics Company,
Yong-In, Korea, and has been working on design of
low-power SRAM. His interests are in analog circuits
and new memory development including MRAM and
PRAM.
cation.
Sangbeom Kang received the B.S. degree in elec-
trical engineering from Korea University, Seoul,
Korea, in 1993, and the M.S.E.E. and Ph.D. de-
grees from the Georgia Institute of Technology,
Atlanta, in 1997 and 2002, respectively. While
in the master’s degree track, he joined a research
project of designing a voltage comparator operating
at low-power supply voltages. His Ph.D. research
topic was the heteroepitaxy of GaN and AlGaN/GaN
structures using MBE (molecular beam epitaxy) for
high-power HFET applications.
In 2003, he joined Samsung Electronics Company, Ltd., where he has been
involved in the development of 64-Mb PRAM.
Ki-Sung Kim was born in Seoul, Korea, in 1974.
He received the B.S. degree in electrical engineering
from Dankook University, Seoul, Korea, in 2000.
In 2000, he joined Samsung Electronics Company,
Yong-In, Korea and has been working on device
evaluation programming development and analysis
of low-power SRAM, UtRAM. His interests are in
next-generation mobile solution memory verification
and including low-power sync-SRAM, MRAM, and
PRAM.
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299
Kyung-Hee Kim was born in Busan, Korea, in 1974.
She joined Samsung Electronics Company, Ltd.,
Yongin, Kyunggi-Do, Korea in 1993, where she has
been working on the layout of high-speed SRAM,
low-power SRAM, UtRAM, and PRAM.
Du-Eung Kim was born in Hong-Sung, Korea, in
1964. He received the B.S. degree in electrical en-
gineering from In-Ha university, Korea, in 1990.
He joined the Memory Division, Samsung Elec-
tronics Corporation, Kiheung, Korea, in 1990, where
he was involved in the circuit design of SRAM. Cur-
rently, he is involved in developing the next-genera-
tion memory (PRAM).
Choong-Keun Kwak was born on November 17,
1959, in Kyungbook, Korea. He received the B.S.
and M.S. degrees in electrical engineering from
Dankook University, Seoul, Korea, in 1982 and
1985, respectively.
He joined the Memory Development Division,
Samsung Electronics, Korea, in 1985, where he was
engaged in the development of low-power SRAM
and high-speed SRAM. Currently, he is involved
in developing new memory (PRAM/MRAM) and
next-generation low-power SRAM for mobile appli-
Hyun-Geun Byun was born on October 17, 1957,
in Kyungbook, Korea. He received the B.S. degree
in electronic engineering from Kyungbook National
University, Taegu, Korea, in 1993.
He joined the Memory Development Division,
Samsung Electronics, Korea, in 1983, where he was
engaged in the development of low-power SRAM
and high-speed SRAM.
Youngnam Hwang received the B.S., M.S., and
Ph.D. degrees in physics from Yonsei University,
Seoul, Korea, in 1991, 1993, and 1998, respectively.
In 1998, he studied the carrier dynamics of
quantum dots as a Postdoctorate with Kriss, Taejon,
Korea. He joined Samsung Electronics Company,
Ltd., Yongin, Korea, in 2000, where he has been
involved in the development of PRAM.
300
Sujin Ahn received the M.S. and Ph.D. degrees in
electronics and electrical engineering from Pohang
University of Science and Technology, Pohang,
Korea, in 1996, and 1999, respectively.
In 1999, she joined Samsung Electronics Com-
pany, Ltd., Yongin, Kyunggi-Do, Korea. Since then,
she was engaged in the research and development of
CMOS process and device technologies in DRAM
process integration. She took part in 4-Gb DRAM
development and currently involved in the develop-
ment of next-generation memory devices.
Gwan-Hyeob Koh was born in Korea in 1966. He
received the B.S., M.S., and Ph.D. degrees in physics
from Seoul National University, Seoul, Korea, in
1989, 1991, and 1996, respectively.
In 1997, he joined Samsung Electronics Company,
Ltd., where he worked on the development of 4-Gb
DRAM. Since 2002, he has been working on the de-
velopment of new memories including MRAM and
PRAM.
Gitae Jeong received the B.S., M.S., and Ph.D.
degrees in physics from Seoul National University,
Seoul, Korea, in 1989, 1991, and 1995, respectively.
He has been with Samsung Electronics Company,
Ltd., since 1995, where he has been involved in the
development of 512-Mb DRAM and 1-Gb DRAM.
Currently, he is involved in the development of
next-generation new memories such as PRAM and
MRAM.
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 1, JANUARY 2005
Hongsik Jeong was born in Seoul, Korea, on May
27, 1962. He received the B.S., M.S., and Ph.D. de-
grees in department of physics from Yonsei Univer-
sity, Korea, in 1985, 1987, and 1992, respectively.
In 1992, he studied the carrier dynamics of
GaAs/AlGaAs quantum structure as a Postdoctorate
at the Laser Spectroscopy Lab, Kriss, Taejon, Korea.
In the same year, he joined the Samsung Electronics
Company, Ltd., Kyunggi-Do, Korea, where he is
involved in dry etching process for device fabrication
such as 64-Mb and 256-Mb DRAM. Since 1997, he
has been engaged in the development of process integration. He participated in
development of cutting-edge technologies of 1-Gb and 4-Gb DRAM. Recently,
he is in charge of developing new memories such as FRAM, MRAM, and
PRAM as a project leader.
Kinam Kim (S’90–M’97–SM’01–F’03) received
the Ph.D. degree in electrical engineering from the
University of California at Los Angeles in 1994. He
received the B.Sc. degree in electronic engineering in
1981 from Seoul National University, South Korea.
In 1983, he received the M.S. degree in electrical
engineering from the Korea Advanced Institute of
Science and Technology.
In 1983, he joined Samsung Electronics Company,
Ltd., where he has been involved in the development
of DRAMs, ranging from 64-kb to 4-Gb densities.
Currently, he is a Senior Vice President responsible for the research and
development of next-generation memory technologies for DRAM, nonvolatile
memory, SRAM, and emerging new memories such as FRAM, PRAM, and
MRAM. He was a program director for 0.13-m DRAM technology generation
from its development at the R&D center to transferring to manufacturing lines
during 1999–2001. He was a Technical Director for 4-Gb DRAM development
for 1998–1999. He has been a Project Leader for the development of the
first 1-Gb DRAM using 0.18-m CMOS technologies during 1994–1996.
His current major activity is focused on the development of technologies for
low-power and high-performance multigigabit density DRAMs and high-den-
sity nonvolatile memories. His research interests are memory device reliability,
yield modeling on memory device, memory cell technology, and multilevel
metallization for high-performance of multigigabit memory devices. He has
published more than 260 technical papers on the field of memory technology.
He holds 70 patents related to memory technology. He plays an active part in
advancing future memory technology through participating panel discussions
of prime conferences such as VLSI technology symposium.
Dr. Kim twice received the grand prize of the Samsung group, for the suc-
cessful developments of 1-Mb DRAM and 1-Gb DRAM in 1986 and 1996, re-
spectively. He is a recipient of ISI’s citation award for highly cited paper. He
served as a committee member of the International Electron Device Meeting
(IEDM), and he is a member of editorial advisory board of Microelectronics
Reliability. He is a Samsung fellow.