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1FEATURES
• 2.5 A Maximum Peak Output Current • Wide VCC1 Range: 3 V to 5.5 V
• Drives IGBTs up to IC = 150 A, VCE = 1200 V • Wide VCC2 Range: 15 V to 30 V
• Capacitive Isolated Fault Feedback • Operating Temperature: –40°C to 125°C
• CMOS/TTL Compatible Inputs • Wide-body SO-16 Package
• 300 ns Maximum Propagation Delay • ±50 kV/us Transient Immunity Typical
• Soft IGBT Turn-off • 6000 VPeak Isolation
• Integrated Fail-safe IGBT Protection • Regulatory Approvals: UL1577 Approved;
– High VCE (DESAT) Detection CSA, DIN EN 60747-5-2, IEC 60950-1 and
– Under-Voltage Lockout (UVLO) Protection 61010-1 Pending
with Hysteresis
APPLICATIONS
• User Configurable Functions
• Isolated IGBT and MOSFET Drives in
– Inverting, Non-inverting Inputs
– Motor Control
– Auto-Reset
– Motion Control
– Auto-Shutdown
– Industrial Inverters
– Switched-Mode Power Supplies
DESCRIPTION
The ISO5500 is an isolated gate driver for IGBTs and MOSFETs with power ratings of up to IC = 150 A and
VCE = 1200 V. Input TTL logic and output power stage are separated by a capacitive, silicon dioxide (SiO2),
isolation barrier. When used in conjunction with isolated power supplies, the device blocks high voltage, isolates
ground, and prevents noise currents from entering the local ground and interfering with or damaging sensitive
circuitry.
The device provides over-current protection (DESAT) to an IGBT or MOSFET while an Undervoltage Lockout
circuit (UVLO) monitors the output power supply to ensure sufficient gate drive voltage. If the output supply drops
below 12 V, the UVLO turns the power transistor off by driving the gate drive output to a logic low state.
For a DESAT fault, the ISO5500 initiates a soft shutdown procedure that slowly reduces the IGBT/MOSFET
current to zero while preventing large di/dt induced voltage spikes. A fault signal is then transmitted across the
isolation barrier, actively driving the open-drain FAULT output low and disabling the device inputs. The inputs are
blocked as long as the FAULT-pin is low. FAULT remains low until the inputs are configured for an output low
state, followed by a logic low input on the RESET pin.
The ISO5500 is available in a 16-pin SOIC package and is specified for operating temperatures from –40°C to
125°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2011–2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
ISO5500
SLLSE64A – SEPTEMBER 2011 – REVISED JULY 2012 www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
VCC1
VREG ISO5500
- VCC2
VIN+ UVLO
+ VC
V IN- + DESAT
Gate DESAT 12 .3V
Drive -
ISO - Barri er
DELAY
and
7.2 V Q1b Q1a
Fault Q4
Logic VOUT
FAULT
Q S
VE
R
RESET Q3
Q2b Q2a
VEE-P
GND1
VEE-L
VIN+ 1 16 VE
VIN- 2 15 VEE-L
VCC1 3 14 DESAT
ISOLATION
GND1 4 13 VCC2
RESET 5 12 VC
FAULT 6 11 VOUT
NC 7 10 VEE-L
GND1 8 9 VEE-P
PIN FUNCTIONS
PIN
DESCRIPTION
NO. NAME
1 VIN+ Non-inverting gate drive voltage control input
2 VIN– Inverting gate drive voltage control input
3 VCC1 Positive input supply (3 V to 5.5 V)
4,8 GND1 Input ground
5 RESET FAULT reset input
6 FAULT Open-drain output. Connect to 3.3k pull-up resistor
7 NC Not connected
9 VEE-P Most negative output-supply potential of the power output. Connect externally to pin 10.
Most negative output-supply potential of the logic circuitry. Pin 10 and 15 are internally connected. Connect at least
10, 15 VEE-L
pin 10 externally to pin 9. Pin 15 can be floating.
11 VOUT Gate drive output voltage
12 VC Gate driver supply. Connect to VCC2.
13 VCC2 Most positive output supply potential
14 DESAT Desaturation voltage input
16 VE Gate drive common. Connect to IGBT Emitter.
ELECTRICAL CHARACTERISTICS
All typical values are at TA = 25°C, VCC1 = 5 V, VCC2 – VE = 30 V, VE – VEE-P = 0 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Quiescent VI = VCC1 or 0 V, No load, See Figure 1, 5.5 8.5
ICC1 Supply current mA
300 kHz Figure 2, Figure 28, and Figure 29 5.7 8.7
Quiescent VI = VCC1 or 0 V, No load, See Figure 3 8.4 12
ICC2 Supply current mA
300 kHz through Figure 5, Figure 30, and Figure 31 9 14
IOUT = 0, See Figure 27 and Figure 30 1.3
ICH High-level collector current mA
IOUT = –650 μA, See Figure 27 and Figure 30 1.9
ICL Low-level collector current See Figure 27 and Figure 31 0.4 mA
IEH VE High-level supply current See Figure 6 and Figure 40 –0.5 –0.3 mA
IEL VE Low-level supply current See Figure 6 and Figure 41 –0.8 –0.53 mA
IIH High-level input leakage 10
IN from 0 to VCC μA
IIL Low-level input leakage –10
VFAULT = VCC1, no pull-up,
IFH High-level FAULT pin output current –10 10 μA
See Figure 33
IFL Low-level FAULT pin output current VFAULT = 0.4 V, no pull-up, See Figure 34 5 12 mA
VIT+(UVLO) Positive-going UVLO threshold voltage 11.6 12.3 13.5
VIT–(UVLO) Negative-going UVLO threshold voltage See Figure 32 11.1 12.4 V
VHYS (UVLO) UVLO Hysteresis voltage (VIT+ – VIT–) 0.7 1.2
VOUT = VCC2 – 4 V (1), See Figure 7 and
–1 –1.6
Figure 35
IOH High-level output current (2)
A
VOUT = VCC2 – 15 V , See Figure 7 and
–2.5
Figure 35
VOUT = VEE-P + 2.5 V (1), See Figure 8 and
1 1.8
Figure 36
IOL Low-level output current (2)
A
VOUT = VEE-P + 15 V , See Figure 8 and
2.5
Figure 36
VOUT – VEE-P = 14 V, See Figure 9 and
IOF Output-low fault current 90 140 230 mA
Figure 37
IOUT = –100 mA, See Figure 10, Figure 11
VC-1.5 VC-0.8
and Figure 38
VOH High-level output voltage V
IOUT = –650 μA, See Figure 10, Figure 11 and
VC-0.15 VC-0.05
Figure 38
IOUT = 100 mA, See Figure 12, Figure 13 and
VOL Low-level output voltage 0.2 0.5 V
Figure 39
VDESAT = 0 V to 6 V, See Figure 14 and
ICHG Blanking capacitor charging current –180 –270 –380 μA
Figure 42
IDSCHG Blanking capacitor discharge current VDESAT = 8 V, See Figure 42 20 45 mA
(VCC2 – VE) > VTH-(UVLO), See Figure 15 and
VDSTH DESAT threshold voltage 6.7 7.2 7.7 V
Figure 42
VI = VCC1 or 0 V, VCM at 1500 V,
CMTI Common mode transient immunity 25 50 kV/μS
See Figure 43 though Figure 46
SWITCHING CHARACTERISTICS
All typical values are at TA = 25°C, VCC1 = 5 V, VCC2 – VE = 30 V, VE – VEE-P = 0 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation Delay 150 200 300 ns
RG = 10 Ω, CG = 10 nF,
tsk-p Pulse Skew |tPHL – tPLH| 50 % duty cycle, 10 kHz input, 1.7 10 ns
tsk-pp Part-to-part skew (1) VCC2 – VEE = 30 V, 45 ns
VE – VEE = 0 V, See Figure 16
tsk2-pp Part-to-part skew (2) –50 50 ns
through Figure 19, Figure 26,
tr Output signal rise time Figure 47, Figure 49, and 55 ns
Figure 50
tf Output signal fall time 10 ns
tDESAT (90%) DESAT sense to 90% VOUT delay 300 550 ns
tDESAT (10%) DESAT sense to 10% VOUT delay RG = 10 Ω, CG = 10 nF, 1.8 2.3 μs
VCC2 – VEE-P = 30 V,
tDESAT (FAULT) DESAT sense to FAULT low output delay 290 550 ns
VE – VEE-P = 0 V, See Figure 20
DESAT sense to DESAT low propagation through Figure 25, Figure 48 and
tDESAT (LOW) 180 ns
delay Figure 51
tRESET (FAULT) RESET to high-level FAULT signal delay 3 8.2 13 μs
tUVLO (ON) UVLO to VOUT high delay 1ms ramp from 0 V to 30 V 4 μs
tUVLO (OFF) UVLO to VOUT low delay 1ms ramp from 30 V to 0 V 6 μs
Failsafe output delay time from input power
tFS 2.8 μs
loss
(1) tsk-pp is the maximum difference in same edge propagation delay times (either VIN+ to VOUT or VIN– to VOUT) between two devices
operating at the same supply voltage, same temperature, and having identical packages and test circuits.
ìé (
ï ëtP HL-ma x VCC1, VCC2, TA )- ( )
tPHL -m in VCC1, VCC2,TA ûù,ïü
i.e. max í ý
(
ï ëétP LH-ma x VCC1, VCC2, TA
î )- ( )
tPL H-m in VCC1, VCC2,TA ûù ï
þ
(2) tsk2-pp is the propagation delay difference in high-to-low to low-to-high transition ( any of the combinations VIN+ to VOUT or VIN– to VOUT)
between two devices operating at the same supply voltage, same temperature, and having identical packages and test circuits.
i.e. min = tPHL-min (VCC1, VCC2,TA ) - tPLH-max (VCC1 ,VCC2 ,TA )
max = tP HL -ma x (VCC1, VCC2,TA ) - tPL H-min (VCC1, VCC2,TA )
TYPICAL CHARACTERISTICS
VCC1 SUPPLY CURRENT vs. TEMPERATURE VCC1 SUPPLY CURRENT vs. FREQUENCY
8 7
7
6
ICC1 - Supply Current (mA)
4 4
3
3
2
VCC1 = 3 V VCC1 = 4.5 V
1 2 VCC1 = 3.3 V
VCC1 = 3.3 V VCC1 = 5 V
VCC1 = 3.6 V VCC1 = 5.5 V VCC1 = 5 V
0 1
-40 -20 0 20 40 60 80 100 120 140 0 50 100 150 200 250 300
o
Ambient Temperature ( C) Input Frequency (KHz)
Figure 1. Figure 2.
VCC2 SUPPLY CURRENT vs. TEMPERATURE VCC2 SUPPLY CURRENT vs. FREQUENCY
12 12
No Load
11
11
ICC2 - Supply Current (mA)
8 9
7
8
6
VCC2 = 15 V VCC2 = 15 V
7
5 VCC2 = 20 V VCC2 = 20 V
VCC2 = 30 V VCC2 = 30 V
4 6
-40 -20 0 20 40 60 80 100 120 140 0 50 100 150 200 250 300
o
Ambient Temperature ( C) Input Frequency (KHz)
Figure 3. Figure 4.
VCC2 SUPPLY CURRENT vs. LOAD CAPACITANCE VE SUPPLY CURRENT vs. TEMPERATURE
70 0
RG = 10 W
fINP = 20 kHz -0.1
IEH, IEL - Supply Current (mA)
60
ICC2 - Supply Current (mA)
50 -0.2
-0.3
40
-0.4
30
-0.5
20
-0.6 IEH, VE - VEE = 0 V
IEH, VE - VEE = 15 V
10 VCC2 = 15 V -0.7 IEL, VE - VEE = 0 V
VCC2 = 30 V IEL, VE - VEE = 15 V
0 -0.8
0 20 40 60 80 100 -40 -20 0 20 40 60 80 100 120 140
o
Load Capacitance (nF) Ambient Temperature ( C)
Figure 5. Figure 6.
-2.5 4
-3
3
-3.5
2
-4
VOUT = VC - 4 V 1
-4.5
VOUT = VC - 15 V
-5 0
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
o o
Ambient Temperature ( C) Ambient Temperature ( C)
Figure 7. Figure 8.
140 -0.3
130 -0.5
120 -0.7
110 -0.9
100 -1.1
TA = -40oC
90 TA = 25oC -1.3 IOUT = -650 mA
TA = 125oC IOUT = -100 mA
80 -1.5
0 5 10 15 20 25 30 -40 -20 0 20 40 60 80 100 120 140
o
Output Voltage (V) Ambient Temperature ( C)
Figure 9. Figure 10.
HIGH OUTPUT VOLTAGE vs. OUTPUT DRIVE CURRENT LOW OUTPUT VOLTAGE vs. TEMPERATURE
30 0.35
TA = -40oC
IOUT = 100 mA
29.5 TA = 25oC
VOH - High Output Voltage (V)
TA = 125oC
VOL - Low Output Voltage (V)
29 0.3
28.5
28 0.25
27.5
27 0.2
26.5
26 0.15
25.5
25 0.1
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.5 -40 -20 0 20 40 60 80 100 120 140
o
Output Drive Current (A) Ambient Temperature ( C)
Figure 11. Figure 12.
-0.21
4
Current (mA)
-0.23
3 -0.25
-0.27
2
-0.29
TA = -40oC -0.31
1
TA = 25oC -0.33
TA = 125oC
0 -0.35
0 0.5 1 1.5 2 2.5 -40 -20 0 20 40 60 80 100 120 140
o
Output Sink Current (A) Ambient Temperature ( C)
Figure 13. Figure 14.
230
Propagation Delay (ns)
7.5
220
7.3
210
7.1
200
6.9 tPLH at VCC1 = 3.3 V
tPHL at VCC1 = 3.3 V
6.7 190 tPLH at VCC1 = 5 V
tPHL at VCC1 = 5 V
6.5 180
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
o o
Ambient Temperature ( C) Ambient Temperature ( C)
Figure 15. Figure 16.
PROPAGATION DELAY vs. VCC1 SUPPLY VOLTAGE PROPAGATION DELAY vs. VCC2 SUPPLY VOLTAGE
225 230
RG = 10 W, RG = 10 W,
CL = 10 nF 225 CL = 10 nF
220
220
Propagation Delay (ns)
215
215
210
210
205
1000
350
800
300
600
250
400 tPLH at VCC1 = 3.3 V
tPHL at VCC1 = 3.3 V
200
200 tPLH at VCC1 = 5 V VCC2 = 15 V
tPHL at VCC1 = 5 V VCC2 = 30 V
0 150
0 10 20 30 40 50 60 70 80 90 100 -40 -20 0 20 40 60 80 100 120 140
o
Load Capacitance (nF) Ambient Temperature ( C)
Figure 19. Figure 20.
RG = 10 W,
1400 CL = 10 nF
2
1200
1000 1.5
800
600 1
400
0.5
200 VCC2 = 15 V VCC2 = 15 V
VCC2 = 30 V VCC2 = 30 V
0 0
0 10 20 30 40 50 60 70 80 90 100 -40 -20 0 20 40 60 80 100 120 140
o
Load Capacitance (nF) Ambient Temperature ( C)
Figure 21. Figure 22.
15
400
14
12 350
10
300
8
6 250
4
VCC2 = 15 V
200 VCC2 = 15 V
2
VCC2 = 30 V VCC2 = 30 V
0 150
0 10 20 30 40 50 60 70 80 90 100 -40 -20 0 20 40 60 80 100 120 140
o
Load Capacitance (nF) Ambient Temperature ( C)
Figure 23. Figure 24.
8.5
8
7.5
7 VCC1 = 3 V
5 V / div
VCC1 = 3.3 V
6.5
VCC1 = 3.6 V
6 VCC1 = 4.5 V
5.5 VCC1 = 5 V
VCC1 = 5.5 V
5
-40 -20 0 20 40 60 80 100 120 140 Time 125 ns / div
o
Ambient Temperature ( C)
Figure 25. Figure 26.
2.5
1.5
0
-40 -20 0 20 40 60 80 100 120 140
o
Ambient Temperature ( C)
Figure 27.
TEST CIRCUITS
SPACER
1 1
VIN+ VE 16 VIN+ VE 16
ICC1
ICC1
0.1 2 0.1 2
5.5 V µF VIN- VEE-L 15 5.5 V µF VIN- VEE-L 15
3 3
VCC1 DESAT 14 VCC1 DESAT 14
4 4
GND1 VCC2 13 GND1 VCC2 13
5 5
RESET VC 12 RESET VC 12
6 6
FAULT VOUT 11 FAULT VOUT 11
7 7
NC VEE-L 10 NC VEE-L 10
8 8
GND1 VEE-P 9 GND1 VEE-P 9
Figure 28. ICC1H Test Circuit Figure 29. ICC1L Test Circuit
SPACER
SPACER
1 16 16
VIN+ VE 1 VIN+ VE
0.1 2 15 15
5V µF VIN- VEE-L 2 VIN- VEE-L
3 14 14
VCC1 DESAT 3 VCC1 DESAT
ICC2 ICC2
4 13 13
GND1 VCC2 4 GND1 VCC2
IC IC
5 12 12
RESET VC 5 RESET VC
30 V
6 11 0.1 11 30 V 0.1
FAULT VOUT µF 6 FAULT VOUT µF
7 VEE-L 10 10
NC IOUT 7 NC VEE-L
8 9 9
GND1 VEE-P 8 GND1 VEE-P
Figure 30. ICC2H, ICH Test Circuit Figure 31. ICC2L, ICL Test Circuit
SPACER
SPACER
1 16 1 16
VIN+ VE VIN+ VE
0.1 2 15 0.1 0.1 2 15
5V µF VIN- VEE-L 5.5 V µF VIN- VEE-L
µF
3 14 V1 3 14
VCC1 DESAT Sweep VCC1 DESAT
4 13 0.1 4 13
GND1 VCC2 µF GND1 VCC2
5 12 5 12
RESET VC V2
RESET VC
0.1
6 11 VOUT µF 5.5 V 6 11 30 V 0.1
FAULT VOUT FAULT VOUT µF
IFAULT
7 10 7 10
NC VEE-L NC VEE-L
8 9 8 9
GND1 VEE-P GND1 VEE-P
Figure 32. VIT(UVLO) Test Circuit Figure 33. IFH Test Circuit
SPACER
1 16 1 16
VIN+ VE VIN+ VE
0.1 2 15 0.1 2 15
3V µF VIN- VEE-L 5V µF VIN- VEE-L
3 14 3 14
VCC1 DESAT VCC1 DESAT
4 13 4 13 VPULSE
GND1 VCC2 GND1 VCC2
5 12 5 12
RESET VC RESET VC 0.1 4.7
30 V µF µF
0.4 V 6 11 30 V 0.1 6 11
FAULT VOUT µF FAULT VOUT
IFAULT IOUT
7 10 7 10
NC VEE-L NC VEE-L
8 9 8 9
GND1 VEE-P GND1 VEE-P
Figure 34. IFL Test Circuit Figure 35. IOH Test Circuit
SPACER
SPACER
16 1 16
1 VIN+ VE VIN+ VE
15 0.1 2 15
2 VIN- VEE-L 5V µF VIN- VEE-L
14 3 14
3 VCC1 DESAT VCC1 DESAT
13 4 13
4 GND1 VCC2 GND1 VCC2
12 5 12 0.1
5 RESET VC 0.1 4.7 RESET VC µF
30 V 30 V
VPULSE µF µF IOUT
11 6 11
6 FAULT VOUT FAULT VOUT
IOUT
14 V
7 NC VEE-L 10 7
NC VEE-L
10
9 8 9
8 GND1 VEE-P GND1 VEE-P
Figure 36. IOL Test Circuit Figure 37. IOF Test Circuit
SPACER
SPACER
1 16 1 16
VIN+ VE VIN+ VE
0.1 2 15 0.1 2 15
5V µF VIN- VEE-L 5V µF VIN- VEE-L
3 14 3 14
VCC1 DESAT VCC1 DESAT
4 13 4 13
GND1 VCC2 GND1 VCC2
5 12 VOUT 0.1 5 12 100 0.1
RESET VC µF RESET VC mA µF
30 V 30 V
6 11 6 11
FAULT VOUT FAULT VOUT
VOUT
7 10 7 10
NC VEE-L IOUT NC VEE-L
8 9 8 9
GND1 VEE-P GND1 VEE-P
Figure 38. VOH Test Circuit Figure 39. VOL Test Circuit
SPACER
SPACER
Figure 40. IEH Test Circuit Figure 41. IEL Test Circuit
SPACER
SPACER
1 16 1 16
VIN+ VE VIN+ VE
0.1 SWEEP 0.1
5V 2 15 0.1 5V 2 15
µF VIN- VEE-L µF VIN- VEE-L
µF
3 14 3 14
VCC1 DESAT V1
VCC1 DESAT
IDESAT
4 13 0.1 4 13
GND1 VCC2 µF GND1 VCC2
5 12 5 12
RESET VC 3k RESET VC
V2
0.1 0.1 4.7 30 V
6 11 µF 6 11 µF µF
FAULT VOUT SCOPE FAULT VOUT
7 10 7 10
NC VEE-L 100 pF NC VEE-L 10 W
8 9 8 9
GND1 VEE-P GND1 VEE-P 10
nF
VCM
Figure 42. ICHG, IDSCHG, VDSTH Test Circuit Figure 43. CMTI VFH Test Circuit
SPACER
SPACER
1 16 1 16
VIN+ VE VIN+ VE
0.1 2 15 0.1 2 15
5V µF VIN- VEE-L 5V µF VIN- VEE-L
3 14 3 14
VCC1 DESAT VCC1 DESAT
4 13 4 13
GND1 VCC2 GND1 VCC2
5 12 5 12
3k RESET VC 3k RESET VC SCOPE
0.1 4.7 30 V 0.1 4.7 30 V
6 11 µF µF 6 11 µF µF
SCOPE FAULT VOUT FAULT VOUT
7 10 100 pF 7 10
100 pF NC VEE-L 10 W NC VEE-L 10 W
8 9 8 9
GND1 VEE-P 10 GND1 VEE-P 10
nF nF
VCM VCM
Figure 44. CMTI VFL Test Circuit Figure 45. CMTI VOH Test Circuit
SPACER
1 16 1 16
VIN+ VE VIN VIN+ VE
0.1 2 15
5V µF 2 15
VIN- VEE-L GND1 VIN- VEE-L
3 14 3 14
VCC1 DESAT VCC1 DESAT
4 13 4 13
GND1 VCC2 GND1 VCC2
0.1 VOUT
5 12 5V µF 5 12
3k RESET VC SCOPE RESET VC 0.1 4.7
V1 µF µF
0.1 4.7 30 V 3k
6 11 µF µF 6 11
FAULT VOUT FAULT VOUT
10 W
100 pF 7 10 7 10
NC VEE-L 10 W NC VEE-L 10
nF
8 9 8 9
GND1 VEE-P 10 GND1 VEE-P
nF
VCM
Figure 46. CMTI VOL Test Circuit Figure 47. tPLH, tPHL, tr, tf Test Circuit
SPACER
1 16
VIN+ VE 100
VIN
2 15 pF
0.1
VIN- VEE-L µF
3 14
VCC1 DESAT V1 0.1
DESAT µF
4 13
GND1 VCC2
5 12 VOUT
RESET VC 0.1 4.7
V2
µF µF
6 11
5V
FAULT VOUT
3k 10 W
7 10
NC VEE-L 10
0.1
µF nF
8 9
GND1 VEE-P
VIN- 0V VIN-
50 % 50 %
tr tf tr tf
90% 90%
50% 50%
Figure 49. VOUT Propagation Delay, Non-inverting Figure 50. VOUT Propagation Delay, Inverting
Configuration Configuration
tDESAT (FAULT )
tDESAT (10%)
VDESAT 50%
tDESAT (90%)
90%
VOUT
10%
FAULT 50 % 50 %
tRESET (FAULT )
RESET 50%
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed circuit board do not reduce this distance.space
Creepage and clearance on a printed circuit board become equal according to the measurement techniques shown in the isolation
glossary. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase their specification.
(2) All pins on each side of the barrier tied together creating a two-terminal device
REGULATORY INFORMATION
VDE CSA UL
Certified according to DIN EN 60747-5-2 and Approved under CSA Component Recognized under 1577 Component
EN 61010-1 Acceptance Notice 5A Recognition Program
Basic Insulation
Basic and Reinforced Insulation per CSA (1)
Maximum Transient Overvoltage, 6000 VPK Single Protection, 4243 VRMS
60950-1-07 and IEC 60950-1 (2nd Ed)
Maximum Working Voltage, 1200 VPK
File Number: pending File Number: pending File Number: E181974
(1) Production tested ≥ 5092 VRMS for 1 second in accordance with UL 1577.
The safety-limiting constraint is the absolute-maximum junction temperature specified in the Absolute Maximum
Ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the
application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the
Thermal Information table is that of a device installed in the High-K Test Board for Leaded Surface-Mount
Packages. The power is the recommended maximum input voltage times the current. The junction temperature is
then the ambient temperature plus the power times the junction-to-air thermal resistance.
Safety Limiting Current - mA
600
500
VCC1 = 3.6V
400
300
VCC1 = 5.5V
200
VCC2 - VEE-P = 30 V
100
0
0 50 100 150 200
o
Case Temperature - C
Figure 52. DW-16 θJC Thermal Derating Curve per IEC 60747-5.2
THERMAL INFORMATION
ISO5500
THERMAL METRIC (1) UNITS
DW (16) PIN
θJA Junction-to-ambient thermal resistance 76
θJCtop Junction-to-case (top) thermal resistance 34
θJB Junction-to-board thermal resistance 36
°C/W
ψJT Junction-to-top characterization parameter 8
ψJB Junction-to-board characterization parameter 35
θJCbot Junction-to-case (bottom) thermal resistance n/a
TSHDN+ 185 °C
Thermal Shutdown
TSHDN- 173 °C
TSHDN-HYS Thermal Shutdown Hysteresis 12 °C
PD Power Dissipation See Equation 2 through Equation 6 592 mW
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
BEHAVIORAL MODEL
Figure 53 and Figure 54 show the detailed behavioral model of the ISO5500 for a non-inverting input
configuration and its corresponding timing diagram for normal operation, fault condition, and Reset.
+HV
ISO5500 DESAT 14
+
1 VIN+
PWM
DIS ISO - CBLK
7.2V
270 μA
2 VIN-
VCC2 13
-
UVLO
μC
ISO - Barrie r
DELAY +
VREG
12.3V
3 VCC1 VC 12
3.3V
15V
to Q1b Q1a
5V
VOUT 11
6 FAULT
I/P
FAULT
Q S
R VE 16
5 RESET Q3
O/P
Q2b Q2a
15V
LOAD
4,8 GND1
VREG VCC2 VEE-P 9
VEE-L 10,15
-HV
VIN+ 5
ISO
4
7.2V
VDESAT
VOUT
FAULT
3
De
2
lay
1
DIS
FAULT
RESET
6
DEVICE INFORMATION
POWER SUPPLIES
VCC1 and GND1 are the power supply input and output for the input side of the ISO5500. The supply voltage at
VCC1 can range from 3 V up to 5.5 V with respect to GND1, thus supporting the direct interface to state-of-the-art
3.3 V low-power controllers as well as legacy 5 V controllers.
VCC2, VEE-P and VEE-L are the power supply input and supply returns for the output side of the ISO5500. VEE-P is
the supply return for the output driver and VEE-L is the return for the logic circuitry. With VEE-P as the main
reference potential, VEE-L should always be directly connected to VEE-P. The supply voltage at VCC2 can range
from 15 V up to 30 V with respect to VEE-P.
A third voltage input, VE, serves as reference voltage input for the internal UVLO and DESAT comparators. VE
also represents the common return path for the gate voltage of the external power device. The ISO5500 is
designed for driving MOSFETs and IGBTs. Because MOSFETs do not require a negative gate-voltage, the
voltage potential at VE with respect to VEE-P can range from 0 V for MOSFETs and up to 15 V for IGBTs.
ISO5500 ISO5500
VCC2 VCC2
ISOLATION
Power Device Power Device
VE VE
Common Common
GND1 0 V-15 V GND1
0 V-15 V
0-(-15 V) -15 V
VEE-P VEE-P
VEE-L VEE-L
The output supply configuration on the left uses symmetrical ±15 V supplies for VCC2 and VEE-P with respect to
VE. This configuration is mostly applied when deriving the output supply from the input supply via an isolated DC-
DC converter with symmetrical voltage outputs. The configuration on the right, having both supplies referenced to
VEE-P, is found in applications where the device output supply is derived from the high-voltage IGBT supplies.
ISOLATION
GND1 GND1
VOUT VOUT
OUTPUT STAGE
The output stage provides the actual IGBT gate drive by switching the output voltage pin, VOUT, between the
most positive potential, typically VCC2, and the most negative potential, VEE-P.
VCC2
ISO5500 VC
VIN+
15V
Q1b Q1a
30V
On
VOUT Q3
VOUT Q1 Q2 Q1
Gate
Drive 0V Q2
VGE
Off
Q3 VE
Slow +15V
Q2b Q2a
Off 15V
VE VE
VEE-P VGE
-15V
VEE-L
This stage consists of an upper transistor pair (Q1a and Q1b) turning the IGBT on, and a lower transistor pair
(Q2a and Q2b) turning the IGBT off. Each transistor pair possesses a bipolar transistor for high current drive and
a MOSFET for close-to-rail switching capability.
An additional, weak MOSFET (Q3) is used to softly turn-off the IGBT in the event of a short circuit fault to
prevent large di/dt voltage transients which potentially could damage the output circuitry.
The output control signals, On, Off, and Slow-Off are provided by the gate-drive and fault-logic circuit which also
includes a break-before-make function to prevent both transistor pairs from conducting at the same time.
By introducing the reference potential for the IGBT emitter, VE, the final IGBT gate voltage, VGE, assumes
positive and negative values with respect to VE.
A positive VGE of typically 15 V is required to switch the IGBT well into saturation while assuring the survival of
short circuit currents of up to 5–10 times the rated collector current over a time span of up to 10 μs.
Negative values of VE, ranging from a required minimum of –5 V up to a recommended –15 V, are necessary to
keep the IGBT turned off and to prevent it from unintentional conducting due to noise transients, particularly
during short circuit faults. As previously mentioned, MOSFETs do not require a negative gate-voltage and thus
allow the VE-pin to be directly connected to VEE-P.
The timing diagram in Figure 57 shows that during normal operation VOUT follows the switching sequence of VIN+
(here shown for the non-inverting input configuration), and only the Q1 and Q2 transistor pairs applying VCC2 and
VEE-P potential to the VOUT-pin respectively.
In the event of a short circuit fault, however, while the IGBT is actively driven, the Q1 pair is turned off and Q3
turns on to slowly reduce VOUT in a controlled manner down to a level of approximately 2 V above VEE-P. At this
voltage level, the strong Q2 pair then conducts holding VOUT at VEE-P potential.
VCC2 12.3V
VCC2
- 11.1V
UVLO VC 2V
+
On 15V
VIN+
Drive VOUT
VGE
Failsafe
VE VOUT Low Q1 Q2 Q1 Q2 Q1
0V
Off
R PD Q2
Q2b Q2a 15V VE
+15V
ISO5500 VEE-P VE
VGE
VEE-L -15V
Because VCC2 with respect to VE represents the gate-on voltage, VGE-ON = VCC2 – VE, the UVLO comparator
compares VCC2 to a 12.3 V reference voltage that is also referenced to VE via the connection of the ISO5500 VE-
pin to the emitter potential of the power device.
The comparator hysteresis is 1.2 V typical and the typical values for the positive and negative going input
threshold voltages are VTH+ = 12.3 V and VTH– = 11.1 V.
The timing diagram shows that at VCC2 levels below 2 V VOUT is 0 V. Because none of the internal circuitry
operates at such low supply levels, an internal 100 kΩ pull-down resistor is used to pull VOUT down to VEE-P
potential. This initial weak clamping, known as failsafe-low output, strengthens with rising VCC2. Above 2 V the
Q2-pair starts conducting gradually until VCC2 reaches 12.3 V at which point the logic states of the control inputs
VIN+ and VIN– begin to determine the state of VOUT.
Another UVLO event takes place should VCC2 drop slightly below 11 V while the IGBT is actively driven. At that
moment the UVLO comparator output causes the gate-drive logic to turn off Q1 and turn on Q2. Now VOUT is
clamped hard to VEE-P. This condition remains until VCC2 returns to above 12.3 V and normal operation
commences.
NOTE
An Under Voltage Lockout does not indicate a Fault condition.
VCC2
VC
ISO5500 15V
DESAT VIN+
+
DESAT
-
CBLK 7.2V
On VDESAT Q4
VE VOUT
Fault Off
Slow Q3
Off
Q2b Q2a 15V
Fault
VEE-P
VEE-L
The DESAT fault detection involves a comparator that monitors the IGBT’s VCE and compares it to an internal 7.2
V reference. If VCE exceeds this reference voltage, the comparator causes the gate-drive and fault-logic to initiate
a fault shutdown sequence. This sequence starts with the immediate generation of a fault signal, which is
transmitted across the isolation barrier towards the Fault indicator circuit at the input side of the ISO5500.
At the same time the fault logic turns off the power-pair Q1 and turns on the small discharge MOSFETs, Q3 and
Q4. Q3 slowly discharges the IGBT gate voltage which causes the high short-circuit current through the IGBT to
gradually decrease, thereby preventing large di/dt induced voltage transients. Q4 discharges the blanking
capacitor. Once VOUT is sufficiently close to VEE-P potential (at approximately 2 V), the large Q2-pair turns on in
addition to Q3 to clamp the IGBT gate to VEE-P.
NOTE
The DESAT detection circuit is only active when the IGBT is turned on. When the IGBT is
turned off, and its VCE is at maximum, the fault detection is simply disabled to prevent
false triggering of fault signals.
The timing diagram in Figure 59 shows the DESAT function for both, normal operation and a short-circuit fault
condition. The use of VIN+ as control input implies non-inverting input configuration.
During normal operation VDESAT will display a small sawtooth waveform every time VIN+ goes high. The ramp of
the sawtooth is caused by the internal current source charging the blanking capacitor. Once the IGBT collector
has sufficiently dropped below the capacitor voltage, the DESAT diode conducts and discharges CBLK through
the IGBT.
In the event of a short circuit fault; however, high IGBT collector voltage prevents the diode from conducting and
the voltage at the blanking capacitor continues to rise until it reaches the DESAT threshold. When the output of
the DESAT comparator goes high, the gate-drive and fault-logic circuit initiates the soft shutdown sequence and
also produces a Fault signal that is fed back to the input side of the ISO5500.
FAULT ALARM
The Fault alarm unit consists of three circuit elements, a RS flip-flop to store the fault signal received from the
gate-drive and fault-logic, an open-drain MOSFET output signaling the fault condition to the micro controller, and
a delay circuit blocking the control inputs after the soft shutdown sequence of the IGBT has been completed.
Figure 60 shows the ISO5500 in a non-inverting input configuration. Because the FAULT-pin is an open-drain
output, it requires a pull-up resistor, RPU, in the order of 3.3 kΩ to 10 kΩ. The internal signals DIS, ISO, and
FAULT represent the input-disable signal, the isolator output signal, and the fault feedback signal respectively.
VCC1 “IGBT
ISO5500 On”
3.3V VIN+ 5
VIN+
PWM ISO
DIS ISO Sh
oc ort 4
VIN- cu
rs
ISO - Barrier
µC RPU FAULT 3
DELAY
De
2
lay
FAULT 1
I/P DIS
FAULT
Q S
R
FAULT
RESET
O/P
RESET 6
GND1
The timing diagram shows that the micro controller initiates an IGBT-on command by taking VIN+ high. After
propagating across the isolation barrier ISO goes high, activating the output stage.
1. Upon a short circuit condition the gate-drive and fault-logic feeds back a fault signal (FAULT = high) which
sets the RS-FF driving the FAULT output active-low.
2. After a delay of approximately 3 μs, the time required to shutdown the IGBT, DIS becomes high and blocks
the control inputs
3. This in turn drives ISO low
4. which, after propagating through the output fault-logic, drives FAULT low.
At this time both flip-flop inputs are low and the fault signal is stored.
5. Once the failure cause has been removed the micro controller must set the control inputs into an "Output-
low" state before applying the Reset pulse.
6. Taking the RESET-input low resets the flip-flop, which removes the fault signal from the controller by pulling
FAULT high and releases the control inputs by driving DIS low
APPLICATION INFORMATION
TYPICAL APPLICATION
Figure 61 shows the typical application of a three-phase inverter using six ISO5500 isolated gate drivers. Three-
phase inverters are used for variable-frequency drives to control the operating speed of AC motors and for high
power applications such as High-Voltage DC (HVDC) power transmission.
The basic three-phase inverter consists of three single-phase inverter switches each comprising two ISO5500
devices that are connected to one of the three load terminals. The operation of the three switches is coordinated
so that one switch operates at each 60 degree point of the fundamental output waveform, thus creating a six-
step line-to-line output waveform. In this type of applications carrier-based PWM techniques are applied to retain
waveform envelope and cancel harmonics.
ISOLATION BARRIER
ISO 5500
ISO 5500
1
2
3
PWM 4 ISO 5500
5
6
3-PHASE
INPUT µC
M
ISO 5500
FAULT
ISO 5500
ISO 5500
1 ISO5500 16
V IN+ VE 100 0.1 0.1
2 15 pF μF μF DS (opt.)
V IN- VEE -L
D DESAT
3 14 100 Ω
V CC1 DESAT -
3.3V 0.1 +
μC μF VF
3.3 4 13
GND1 V CC2 Q1
kΩ 4.7 +
5 12 μF
RESET VC 15V VCE
Rg
6 11 -
FAULT VOUT 0.1 3-PHASE
7 10 μF OUTPUT
330 pF NC VEE -L Q2
15V +
8 9
GND1 V EE-P VCE
-
1 ISO5500
VIN+
2
VIN-
3
0.1
VCC1
µC 5V
µF 4
3.3 GND1
kW
5
RESET
6
FAULT
7
330 pF NC
8
GND1
1 ISO5500 1 ISO5500
VIN+ VIN+
2 2
VIN- VIN-
3 3
VCC1 VCC1
µC µC
4 4
RF GND1 RF GND1
5 5
RESET RESET
6 6
FAULT FAULT
7 7
NC NC
8 8
GND1 GND1
Figure 64. Local Shutdown and Reset for Non-inverting (left) and Inverting Input Configuration (right)
1 ISO5500
VIN+
2
VIN-
3
VCC1
µC
4
GND1
5
RESET
6
FAULT
7
NC
8
to other to other GND1
RESETs FAULTs
AUTO-RESET
Connecting RESET to the active control input (VIN+ for non-inverting, or VIN– for inverting operation) configures
the ISO5500 for automatic reset capability. In this case, the gate control signal at VIN is also applied to the
RESET input to reset the fault latch every switching cycle. During normal IGBT operation, asserting RESET low
has no effect on the output. For a fault condition, however, the gate driver remains in the latched fault state until
the gate control signal changes to the 'gate low' state and resets the fault latch.
If the gate control signal is a continuous PWM signal, the fault latch will always be reset before VIN+ goes high
again. This configuration protects the IGBT on a cycle by cycle basis and automatically resets before the next
'on' cycle. When the ISO5500 is configured for Auto Reset, the specified minimum FAULT signal pulse width is
3 μs.
1 ISO5500 1 ISO5500
VIN+ VIN+
2 2
VIN- VIN-
3 3
VCC1 VCC1
µC µC
4 4
GND1 GND1
5 5
RESET RESET
6 6
FAULT FAULT
7 7
NC NC
8 8
GND1 GND1
Figure 66. Auto Reset for Non-inverting and Inverting Input Configuration
1 ISO5500 1 ISO5500
VIN+ VIN+
2 2
VIN- VIN-
3 3
VCC1 VCC1
µC µC
4 4
GND1 GND1
5 5
RESET RESET
6 6
FAULT FAULT
7 7
NC NC
8 8
GND1 GND1
Figure 67. Auto Reset with Prior Gate-low Assertion for Non-inverting and Inverting Input Configuration
ISO5500 16
VE 100 +
15 pF DS (opt.)
VEE-L VFW
RS DDESAT
14 -
DESAT
13
VCC2 -
12
VC 15V VFW-inst
Rg
11 +
VOUT
VEE-L 10
15V
9
VEE-P
Figure 68. DESAT Pin Protection with Series Resistor and Optional Schottky Diode
ISO5500
VCC2
VC
15 V
ron-max
VOUT RG
QG
roff-max
15 V
VEE-P
ISO5500 ISO5500
VCC2 VCC2
VC VC
15 V 15 V
RG CG RG CG
VE VE
15 V 15 V
VEE-P VEE-P
Off-to-On Transition
In the off-state, the upper plate of the gate capacitance, CG, assumes a steady-state potential of –VEE-P with
respect to VE. When turning on the power device, VCC2 is applied to VOUT and the voltage drop across RG results
in a peak charge current of ION-PK = (VCC2 – VEE-P)/RG. Solving for RG then provides the necessary resistor value
for a desired on-current via:
V - VEE-P
RG = CC2
ION-PK (7)
On-to-Off Transition
When turning the power device off, the current and voltage relations are reversed but the equation for calculating
RG remains the same.
Once RG has been calculated, it is necessary to check whether the resulting, worst-case power consumption,
POD-WC, (derived in Equation 6) is below the calculated maximum, POL = 125 mW (calculated in Equation 5).
Example
The example below considers an IGBT drive with the following parameters:
ION-PK = 2 A, QG = 650 nC, fINP = 20 kHz, VCC2 = 15V, VEE-P = –5 V
Applying Equation 7, the value of the gate resistor is calculated with
15V - ( - 5V)
RG = = 10 Ω
2A (8)
Then, calculating the worst-case output power consumption as a function of RG, using Equation 6 yields
æ 4Ω 2.5 Ω ö
POL-WC = 0.5 ´ 20 kHz ´ 650 nC ´ (15 V - ( - 5V))´ ç + ÷ = 63 mW
è 4 Ω + 10Ω 2.5 Ω + 10 Ω ø (9)
Because POL-WC = 63 mW is well below the calculated maximum of POL = 125 mW, the resistor value of RG =
10Ω is fully suitable for this application.
ISO5500 ISO5500
VCC2 VCC2
VC RC VC VC
C2 - 15 V
VE
15 V E- P
VCC2 - VEE-P
Ion-pk Ioff-pk
VOUT VOUT
RG CG RG CG
VE VE
15 V 15 V
VEE-P VEE-P
Figure 71 (right) shows that during the on-transition, the (VCC2 – VEE-P) voltage drop occurs across the series
resistance of RC + RG, thus reducing the peak charge current to: ION-PK = (VCC2 – VEE-P) /(RC + RG). Solving for RC
provides:
V - VEE-P
RC = CC2 - RG
ION-PK (10)
To stay below the maximum output power consumption, RG must be calculated first via:
VCC2 - VEE-P
RG =
IOFF-PK
(11)
and the necessary comparison of POL-WC versus POL must be completed.
Once RG is determined, calculate RC for a desired on-current using Equation 10.
Another method is to insert Equation 11 into Equation 10 and arriving at:
æI ö
RC = R G ´ ç OFF-PK - 1÷
è ION-PK ø (12)
Example
Reducing the peak charge current from the previous example to ION-PK = 1.5 A, requires a RC value of:
æ 2A ö
RC = 10 Ω ´ ç - 1÷ = 3.33 Ω
è 1.5 A ø (13)
ISO5500 16
VE
15
VEE-L 100 pF
14
DESAT
13 MJD44H11
VCC2 or
12 D44VH10
VC 15 V
10 W 4.5 W
11
VOUT
2.5 W
10
VEE-L
MJD45H11
9 or
VEE-P D45VH10
15 V
Spacer
REVISION HISTORY
www.ti.com 24-Jan-2013
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Qty Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Top-Side Markings Samples
(1) Drawing (2) (3) (4)
ISO5500DW ACTIVE SOIC DW 16 40 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ISO5500DW
& no Sb/Br)
ISO5500DWR ACTIVE SOIC DW 16 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ISO5500DW
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Only one of markings shown within the brackets will appear on the physical device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Jan-2013
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Jan-2013
Pack Materials-Page 2
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