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STP57N65M5
N-channel 650 V, 0.056 Ω typ., 42 A MDmesh™ V Power MOSFET
in I²PAK, TO-220, TO-220FP and D²PAK packages
Datasheet — production data
Features
TAB
VDSS @ RDS(on)
Order codes ID
TJmax max 3
1
3
STB57N65M5 2
D²PAK 1
STF57N65M5
710 V < 0.063 Ω 42 A TO-220FP
STI57N65M5
TAB TAB
STP57N65M5
I²PAK TO-220
■ Excellent switching performance
■ Easy to drive, 100% avalanche tested
Figure 1. Internal schematic diagram
Applications
$ 4!"
■ Switching applications
Description
These devices are N-channel MDmesh™ V
'
Power MOSFETs based on an innovative
proprietary vertical process technology, which is
combined with STMicroelectronics’ well-known
PowerMESH™ horizontal layout structure. The 3
resulting product has extremely low on-
resistance, which is unmatched among silicon-
based Power MOSFETs, making it especially !-V
Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) .......................... 6
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1 Electrical ratings
2 Electrical characteristics
Drain-source
V(BR)DSS ID = 1 mA, VGS = 0 650 V
breakdown voltage
Zero gate voltage VDS = 650 V 1 µA
IDSS
drain current (VGS = 0) VDS = 650 V, TC=125 °C 100 µA
Gate-body leakage
IGSS VGS = ± 25 V ±100 nA
current (VDS = 0)
VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 3 4 5 V
Static drain-source on-
RDS(on VGS = 10 V, ID = 21 A 0.056 0.063 Ω
resistance
Table 5. Dynamic
Symbol Parameter Test conditions Min. Typ. Max. Unit
Input capacitance
Ciss 4200 pF
Output capacitance VDS = 100 V, f = 1 MHz,
Coss - 115 - pF
Reverse transfer VGS = 0
Crss 9 pF
capacitance
Equivalent output
VGS = 0, VDS = 0 to 80%
Co(er)(1) capacitance energy - 93 - pF
V(BR)DSS
related
Equivalent output
VGS = 0, VDS = 0 to 80%
Co(tr)(2) capacitance time - 303 - pF
V(BR)DSS
related
Intrinsic gate
RG f = 1 MHz open drain - 1.3 - Ω
resistance
Qg Total gate charge VDD = 520 V, ID = 21 A, 98 nC
Qgs Gate-source charge VGS = 10 V - 23 - nC
Qgd Gate-drain charge (see Figure 18) 40 nC
1. Co(er) is a constant capacitance value that gives the same stored energy as Coss while VDS is rising from 0
to 80% VDSS
2. Co(tr) is a constant capacitance value that gives the same charging time as Coss while VDS is rising from 0
to 80% VDSS
100 is
ea )
ar S(on
is
th RD
in ax
n
it o y m
10 ra b 10µs
pe ed
O mit 100µs
L i
1ms
Tj=150°C
10ms
1 Tc=25°C
Single
pulse
0.1
0.1 1 10 100 VDS(V)
Figure 4. Safe operating area for TO-220FP Figure 5. Thermal impedance for TO-220FP
AM14704v1
ID
(A)
100
is
ea )
ar (on
i s DS
th x R
in
10 n ma
a tio by 10µs
r d
pe te
O imi
L 100µs
1 1ms
Tj=150°C 10ms
Tc=25°C
0.1
Single
pulse
0.01
0.1 1 10 100 VDS(V)
100 VDS= 25 V
VGS= 8 V 100
80 80
VGS= 7 V
60 60
40 40
20 VGS= 6 V 20
0 0
0 4 8 12 16 VDS(V) 3 4 5 6 7 8 9 VGS(V)
2 100 0.052
0 0 0.05
0 20 40 60 80 100 Qg(nC) 0 10 20 30 ID(A)
Figure 10. Capacitance variations Figure 11. Output capacitance stored energy
AM14710v1 AM14711v1
C Eoss
(pF) (µJ)
18
10000 16
Ciss 14
1000 12
10
100 Coss 8
6
10 Crss 4
2
1 0
0.1 1 10 100 VDS(V) 0 100 200 300 400 500 600 VDS(V)
Figure 12. Normalized gate threshold voltage Figure 13. Normalized on-resistance vs
vs temperature temperature
VGS(th) AM05459v1 AM05460v1
RDS(on)
(norm) (norm)
1.10 2.1
ID = 250 µA VGS= 10V
1.9 ID= 21 A
1.00 1.7
1.5
0.90 1.3
1.1
0.80 0.9
0.7
0.70 0.5
-50 -25 0 25 50 75 100 TJ(°C) -50 -25 0 25 50 75 100 TJ(°C)
Figure 14. Source-drain diode forward Figure 15. Normalized BVDSS vs temperature
characteristics
AM05461v1 AM10399v1
VSD VDS
(norm)
(V) TJ=-50°C
1.08
1.2 ID = 1mA
1.06
1.0
1.04
0.8 1.02
TJ=25°C
1.00
0.6
TJ=150°C 0.98
0.4
0.96
0.2
0.94
0 0.92
0 10 20 30 40 50 ISD(A) -50 -25 0 25 50 75 100 TJ(°C)
AM14712v1
E (μJ)
VDD=400V Eon
VGS=10V
800 ID=28A
600
Eoff
400
200
0
0 10 20 30 40 RG(Ω)
1. Eon including reverse recovery of a SiC diode
3 Test circuits
Figure 17. Switching times test circuit for Figure 18. Gate charge test circuit
resistive load
VDD
12V 47kΩ
1kΩ
100nF
RL 2200 3.3
μF μF
VDD IG=CONST
VD Vi=20V=VGMAX 100Ω D.U.T.
VGS 2200
RG D.U.T. μF 2.7kΩ VG
PW
47kΩ
PW 1kΩ
AM01468v1 AM01469v1
Figure 19. Test circuit for inductive load Figure 20. Unclamped inductive load test
switching and diode recovery times circuit
L
A A A
D
FAST L=100μH VD
G D.U.T. DIODE 2200 3.3
μF μF VDD
S B 3.3 1000
B B μF μF
25 Ω VDD ID
D
RG S
Vi D.U.T.
Pw
AM01470v1 AM01471v1
Figure 21. Unclamped inductive waveform Figure 22. Switching time waveform
V(BR)DSS Id
Concept waveform for Inductive Load Turn-off
VD 90%Vds 90%Id
Tdelay-off
-off
IDM
Vgs
90%Vgs on
ID
Vgs(I(t))
))
Vds
Trise Tfall
Tcross --over
AM01472v1 AM05540v2
A 4.40 4.60
A1 0.03 0.23
b 0.70 0.93
b2 1.14 1.70
c 0.45 0.60
c2 1.23 1.36
D 8.95 9.35
D1 7.50
E 10 10.40
E1 8.50
e 2.54
e1 4.88 5.28
H 15 15.85
J1 2.49 2.69
L 2.29 2.79
L1 1.27 1.40
L2 1.30 1.75
R 0.4
V2 0° 8°
0079457_T
12.20 5.08
1.60
3.50
9.75
Footprint
A 4.4 4.6
B 2.5 2.7
D 2.5 2.75
E 0.45 0.7
F 0.75 1
F1 1.15 1.70
F2 1.15 1.70
G 4.95 5.2
G1 2.4 2.7
H 10 10.4
L2 16
L3 28.6 30.6
L4 9.8 10.6
L5 2.9 3.6
L6 15.9 16.4
L7 9 9.3
Dia 3 3.2
7012510_Rev_K_B
A 4.40 4.60
A1 2.40 2.72
b 0.61 0.88
b1 1.14 1.70
c 0.49 0.70
c2 1.23 1.32
D 8.95 9.35
e 2.40 2.70
e1 4.95 5.15
E 10 10.40
L 13 14
L1 3.50 3.93
L2 1.27 1.40
0004982_Rev_H
A 4.40 4.60
b 0.61 0.88
b1 1.14 1.70
c 0.48 0.70
D 15.25 15.75
D1 1.27
E 10 10.40
e 2.40 2.70
e1 4.95 5.15
F 1.23 1.32
H1 6.20 6.60
J1 2.40 2.72
L 13 14
L1 3.50 3.93
L20 16.40
L30 28.90
∅P 3.75 3.85
Q 2.65 2.95
0015988_typeA_Rev_S
mm mm
Dim. Dim.
Min. Max. Min. Max.
10 pitches cumulative
tolerance on tape +/- 0.2 mm
Top cover P0 D P2
T tape
E
F
K0 W
B0
A0 P1 D1
Bending radius
User direction of feed
AM08852v2
40mm min.
Access hole
At sl ot location
A N
AM08851v2
6 Revision history
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