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Hardware Modeling Using Verilog

Assignment- Week 3
TYPE OF QUESTION: MCQ/MSQ/SA
Number of questions: 10 Total mark: 10 X 1 = 10
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QUESTION 1:
Which of the following statements is/are true?

a. The “assign” statement implements continuous assignment between the

expression specified on the right-hand side and a “net” type variable specified on
the left-hand side.
b. The “assign” statement implements continuous assignment between the
expression specified on the right-hand side and a “reg” type variable specified on
the left-hand side.
c. The “assign” statement can be used to model a latch, which is a sequential
circuit.
d. None of these.

Correct Answer: a, c

Detailed Solution:

For an “assign” statement, the left hand side can only be a “net” type variable, and cannot be a
“reg” type variable. It models continuous assignment, and a pair of assign statements can be
used to model two cross-coupled NAND/NOR gates implementing a latch. Thus, the correct
answers are (a) and (c).

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QUESTION 2:
Which of the following are true for the following code segment?
input [15:0] a;
input [5:2] b;
input sel;
output f;
assign f = sel ? a[b] : 1’b0;
a. One 32-to-1 and one 2-to-1 multiplexers will be generated.
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b. Only one 16-to-1 multiplexer will be generated.

c. One 16-to-1 and one 2-to-1 multiplexers will be generated.
d. None of these.

Correct Answer: c

Detailed Solution:

The conditional statement “? :” will be generating a 2-to-1 multiplexer, with “sel” as the select
input. The first input of the multiplexer will be connected to 0, while the second input will be
connected to a[b], which is the output of a 16-to-1 multiplexer. This multiplexer will have the
bits of “a” as inputs, and “b” as the select lines.

The correct answer is (c).

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QUESTION 3:
Which of the following constructs will be generating a multiplexer, where “a”, “b” and “c” are
variables?

a. assign a = b[c];
b. assign b[c] = a;
c. assign a = (b) ? c : ~c;
d. assign a = b & c

Correct Answer: a, c

Detailed Solution:

A multiplexer will be generated if the RHS of an assignment is an array reference with a variable
as index (as in option (a)), or is a conditional statement (as in option (c)). Thus, correct options
are (a) and (c).

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QUESTION 4:
What does the following code segment implement?
assign d = ~(c | b);
assign c = ~(a | d);
a. A 1-bit latch.
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b. A 2-bit shift-register.
c. Two NOR gates connected in cascade.
d. A 2-bit comparator.

Correct Answer: a

Detailed Solution:

The first NOR will have “b” and “c” as inputs and give “d” as output. The second NOR will have
“a” and “d” as inputs and give “c” as output. This corresponds to a pair of cross-coupled NOR
gates, which is used to build a one-bit latch. Thus the correct answer is (a).

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QUESTION 5:
What is the purpose of the “initial” procedural block in Verilog test benches?

a. It is used to specify a procedural block that is executed only once.

b. It can be used to specify a procedural block for synthesis.
c. Every time an “always” block is executed, variables are initialized as specified in
the “initial” block.
d. If there are multiple “initial” blocks in a module, they are executed one by one in
sequence.

Correct Answer: a

Detailed Solution:

The “initial” block is used only in test benches, and cannot be used to write a module that can
be synthesized. It is executed only once during simulation, and is typically used to apply input
stimulus to the module under test. All “initial” blocks in a test bench are executed
simultaneously. Also, it has no connections with initializing variables in “always” block.
Hence, the correct option is (a).

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QUESTION 6:
The following code segment generates a periodic clock signal “clk” with time period:
initial clk = 1’b1;
always #10 clk = ~clk;

a. 10
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b. 20
c. 30
d. None of these

Correct Answer: b

Detailed Solution:

The “initial” block initializes the “clk” signal to 1 at time 0. The “always” block toggles “clk” with
a delay of 10 time units. Clearly, the period of the clock is 20 time units.
Hence, the correct option is (b).

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QUESTION 7:
If “clk” and “clear” are two inputs of a counter module, which of the following event
expressions must be used if we want to implement asynchronous clear (assuming “clear” is
active low, active high edge of “clk” signal is used for counting, and single “always” block is used
for the implementation)?

a. always @(posedge clk)

b. always @(negedge clear)
c. always @(posedge clk or negedge clear)
d. None of these.

Correct Answer: c

Detailed Solution:

For asynchronous clear, the “always” block must be activated whenever “clear” goes low
irrespective of the “clk” edge whereas at each low-to-high “clk” edge the counter performs
counting. Thus option (c) is correct.

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QUESTION 8:
Which of the following is true for the following module?
module mydesign (a, b);
input [1:0] b;
output reg a;
always @(b)
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begin
if (b == 2’b00) a = 1’b0;
else if (b == 2’b11) a = 1’b0;
else a = 1’b1;
end
endmodule

a. A combinational circuit implementing a XOR function will be generated.

b. A combinational circuit implementing an AND function will be generated.
c. A latch will be generated for the output “a”.
d. The synthesis tool will give an error.

Correct Answer: a

Detailed Solution:

Assignment to variable “a” is specified for all values of the input “b”, and hence a combinational
circuit will be generated. “a” is assigned 1 if “b” is neither 00 nor 11. Hence, it implements the
XOR function, and option (a) is correct.

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QUESTION 9:
Which of the following is true for the “repeat” loop?

a. It can be used to iterate a block until a specified condition is true.

b. It can be used to iterate a block indefinitely.
c. It can be used to repeat execution of the block exactly two times.
d. None of these.

Correct Answer: d

Detailed Solution:

The syntax of the “repeat” statement is “repeat (n) begin … end”, where “n” is some constant.
The block of statements in “begin … end” are executed “n” times. In other words, it can be used
to iterate the execution of a block a fixed number of times. None of (a), (b) or (c) is true; hence
(d) is the correct option.

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QUESTION 10:
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What does the construct “#5” indicate in simulation?

a. It specifies that the unit of delay is 5 nanoseconds.

b. It specifies a delay of 5 time units before executing the next statement.
c. It schedules the execution of the next statement at time 5.
d. It pauses execution of the statements that follow after time 5.

Correct Answer: b

Detailed Solution:

Whenever the construct #5 is encountered, simulation is delayed for 5 time units before going
to the next statement. Hence, option (b) is correct.
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