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Indian Institute of Technology Kharagpur

Hardware Modeling Using Verilog

Assignment- Week 1
TYPE OF QUESTION: MCQ/MSQ/SA
Number of questions: 10 Total mark: 10 x 1 = 10
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QUESTION 1:
Which of the following VLSI design styles only allows layouts of functional blocks with fixed
height?
a. Standard cell.
b. Full custom.
c. FPGA.
d. None of these.

Correct Answer: a

Detailed Solution:

In standard cell, the technology library contains optimized layouts of functional modules,
each with fixed height.

Thus option (a) is the correct answer.

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QUESTION 2:
Which of the following statement(s) is/are false?
a. FPGA based design is slower than standard cell based design.
b. Standard cell based design is faster than full custom design.
c. FPGA based design is faster than full custom design.
d. None of these.
Correct Answer: b, c

Detailed Solution:

In decreasing order of speed, we can order the design styles as full custom, semi custom (or
standard cell), gate array, FPGA.
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Indian Institute of Technology Kharagpur

Hence, the statements (b) and (c) are false.

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QUESTION 3:
Which of the following design descriptions represent a netlist?

a. A set of gates and their interconnections.

b. Interconnection of register transfer level components.
c. The truth table representation of a function.
d. All of these.

Correct Answer: a, b

Detailed Solution:

A netlist refers to a set of building blocks and their interconnection. Both (a) and (b) satisfy
these criterial

Thus options (a) and (b) are correct.

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QUESTION 4:
Which of the following is carried out before the others in a typical VLSI design flow?

a. Logic design.
b. Data path design.
c. Physical design.
d. Layout design.

Correct Answer: b

Detailed Solution:

Among the steps mentioned, data path design is carried out first, followed by logic design,
and then physical design, and then layout design.

Thus correct option is (b).

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Indian Institute of Technology Kharagpur

QUESTION 5:
What are the basic building blocks in a switch level description of s VLSI design?

a. Gates
b. RTL level modules
c. Transistors
d. Relay switches

HINT: (If options a, b and c are all correct, select option d as the answer.)

Correct Answer: c

Detailed Solution:

Switch level description is a netlist of transistors and the way they are interconnected.

Thus correct option is (c).

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QUESTION 6:
Which of the following is used to specify a design in Verilog?

a. A Verilog module.
b. A Verilog test bench.
c. A Verilog design bench.
d. None of these.

Correct Answer: a

Detailed Solution:

A Verilog module is used to describe the specification of a design, whereas a test bench is
used to specify the input stimulus and output behavior during simulation. There is nothing
called “design bench”.

Thus options (a) is true.

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Indian Institute of Technology Kharagpur

QUESTION 7:
The process of converting a function specification to a netlist of gates/modules is called:

a. Evolution
b. Simulation
c. Synthesis
d. Emulation

Correct Answer: c

Detailed Solution:

Converting a design specification into the corresponding implementation is called synthesis.

The correct option is (c).

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QUESTION 8:
For FPGA design style, what is the full form of CLB?

a. Combinational logic block.

b. Constant logic bit.
c. Cumulative logic bias.
d. Combinational latch block.

Correct Answer: a

Detailed Solution:

The full form of CLB is combinational logic block.

Thus option (c) is correct.

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QUESTION 9:
The truth table description of a function represents a behavioral description.

a. True
b. False
Correct Answer: a
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Detailed Solution:

The truth table specifies the input-output behavior of a function, without specifying its
implementation. It represents a behavioral description.

The correct option is (a).

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QUESTION 10:
How many distinct functions of 3 variables are possible?

a. 8
b. 256
c. 9
d. None of these

Correct Answer: b

Detailed Solution:

The number of distinct functions of n variables is given by 2^(2^n).

Thus option (b) is correct.

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