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Indian Institute of Technology Kharagpur

Course Name: VLSI PHYSICAL DESIGN

Assignment- Week 7
TYPE OF QUESTION: MCQ/MSQ/SA
Number of questions: 10 Total mark: 10 x 1 = 10
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QUESTION 1:
Which of the following statement(s) is/are true about interconnecting graph, T, in timing-
driven routing?
a. The radius (T) is the maximum path length between any two nodes.
b. The cost (T) is the maximum edge weight between any two nodes.
c. The radius (T) is the maximum path length between source and a sink node.
d. The cost (T) is the sum of edge weights between all nodes.

Correct Answer: c, d

Detailed Solution: The interconnecting graph for timing-driven routing is represented as a

Spanning Tree T, and the two metrics radius(T) and cost(T) are defined by option (c) and
(d) .
The correct options are (c) and (d).
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QUESTION 2:
Which of the following statement(s) is/are true about computing radius and cost of an
interconnecting graph, T?
a. Dijkstra’s algorithm is used to compute radius(T).
b. Dijkstra’s algorithm is used to compute cost(T).
c. Prim’s algorithm is used to compute radius(T).
d. Prim’s algorithm is used to compute cost(T).
Correct Answer: a, d

Detailed Solution: Dijkstra’s algorithm gives single source shortest path. Thus radius(T)
can be obtained from the resulting shortest path tree. Since Prim’s algorithm provides
minimum spanning tree, the cost(T) metric is computed as the sum of edge weights.
The correct options are (a) and (d).
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QUESTION 3:
Which of the following statement(s) is/are false?
a. Setting ε=0, the BRBC algorithm yields a minimum radius tree.
b. Setting ε=0, the BRBC algorithm yields a minimum cost tree.
c. Setting γ=0, the Prim-Dijkstra algorithm yields a minimum radius tree.
d. Setting γ =0, the Prim-Dijkstra algorithm yields a minimum cost tree.
Correct Answer: b, c

Detailed Solution: In BRBC (Bounded Radius and Bounded Cost) algorithm, the radius is
defined as radius(T’) <= (1+ε)radius(T). Thus setting ε = 0, it produces minimum radius
tree.
Whereas in Prim-Dijkstra, the tradeoff is defined as γ . cost(s0, si) + cost(si, sj) which
provides a minimum weight tree by setting γ=0. Thus the options (a) and (d) are true.
Hence, the correct options are (b) and (c).
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QUESTION 4:
Which of the following feature size of a transistor have the lowest source-to-drain
resistance?

a. 1:1
b. 2:1
c. 1:2
d. All of the above.

Correct Answer: c

Detailed Solution: The aspect ratio of a transistor is defined as L:W, where L is the channel
length and W is the channel width. Reducing L or increasing W will reduce the source-to-
drain resistance.
Hence, the correct option is (c).
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QUESTION 5:
A speed of a CMOS gate can be made faster by:
a. Increasing the capacitive load of gate output.
b. Increasing the channel area of the transistors.
c. Decreasing the capacitive load of gate output.
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d. None of these.

Correct Answer: c

Detailed Solution: The switching speed of a gate depends on the capacitive load of output.
Increasing the channel area does not make it faster as the gate capacitance increases.
The correct option is (c).
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QUESTION 6:
Which of the following statement(s) is/are false about gate delay?
a. For large capacitive load, gate with smaller feature size have larger delay.
b. For large capacitive load, gate with larger feature size have larger delay.
c. For small capacitive load, gate with larger feature size have larger delay.
d. For small capacitive load, gate with smaller feature size have larger delay.
e. None of these.

Correct Answer: b, d

Detailed Solution: When capacitive load is high, load dependent delay will dominate and
smaller size gate encounter large delay. But when capacitive load is small, the intrinsic
delay will dominate and large gate in such case have more operation delay. Hence options
(a) and (c) are true.
Hence, the correct options are (b) and (d).
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QUESTION 7:
Consider a wire of length L connecting a source and destination is divided into three equal
size segments by inserting buffer in between them. What will be the delay of the wire
between the source and destination?
a. The delay of the wire will increase by a factor of 3.
b. The delay of the wire will decrease by a factor of 3.
c. The delay of the wire will increase by a factor of 32.
d. The delay of the wire will decrease by a factor of 32.
e. None of these.

Correct Answer: b
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Detailed Solution: Here delay α L2, i.e. delay = KL2, where L is the wire length and K is a
constant. Dividing the wire in 3 equal size segments by inserting buffer, the delay of each
segment will be K(L/3)2. Thus total delay will be 3K(L/3)2 = KL2(1/3).
The correct option is (b).
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QUESTION 8:
Which of the following approaches can reduce the output load capacitance due to large
number of fanout?
a. Duplicating the gate with each gate driving a subset of fanout.
b. Inserting buffers at the gate output, each driving a subset of fanout.
c. Redesign of the fanin tree.
d. None of these.
Correct Answer: a, b

Detailed Solution: Cloning and buffering both can be used to distribute the output load
capacitance of a gate. The capacitive load of output does not change redesigning the fanin
tree.
The correct options are (a) and (b).
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QUESTION 9:
Which of the following statement(s) is/are true about cloning and buffering?
a. Cloning increases the fanout of upstream gates.
b. Buffering increases the fanout of upstream gates.
c. Cloning is more suitable for downstream logic restricted in a region.
d. Buffering is more suitable for downstream logic restricted in a region.
e. None of these.
Correct Answer: a, d

Detailed Solution: Duplicating gates requires the input fanout for driving each duplicate
gate, thus cloning increases the capacitive load of upstream gates. Buffering on the other
hand keeps the upstream logic unchanged, and is more useful in situations where gate
fanout are restricted in a smaller area.
The correct options are (a) and (d).
____________________________________________________________________________
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QUESTION 10:
Which of the following circuit elements have logically equivalent input pins?
a. 4-to-2 priority encoder.
b. 2-to-1 multiplexer.
c. 1-bit full adder.
d. None of these.

Correct Answer: c

Detailed Solution: Changing the position of input pins will change the functionality of
encoder as well as multiplexer, but output of 1-bit full adder will remain unchanged as it
implements a symmetric function.
Hence, the correct option is (c).
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