Sự giống và khác nhau giữa vi xử lý 8086 và CPU của vi xử lý ARM Cortex M

Similarities:
 Both of them use registers to transfer data
 Registers:
- ARM: R13 (Stack Pointer –> SP in 8086)
- ARM: R15, Program Counter (PC) -> points to the next instruction to
be fetched from memory (like the IP (Instruction Pointer) register of
8086)
- ARM and 8086 have registers to show status (Flag registers in 8086
and Status registers in ARM)
 Use stack structure and little endian

Differences:

8086 microprocessors ARM Cortex-M CPUs

- Memory Segmentation: - No memory segmentation structure
 4 segments, each segment has 64
KB memory
 Using 20 bit address (= 1MB
address)
 2 units: Bus Interface Unit and
Execution Unit

- Registers: (16 bit) - Registers: (32 bit)

 4 general-purpose registers: AX,
BX, CX, DX (all pertain to the EU
block)
 CS (Code Segment), DS (Data
Segment), SS (Stack Segment), ES
(Extra Segment) (pertain to the
BIU)
 SI (Source Index), DI (Destination
Index), BS (Base Pointer)
 R0 -> R12: General-purpose
registers (13 registers)
 R13: Stack Pointer (SP) divided
into Main Stack Pointer (MSP – for
OS software) and Process Stack
Pointer (PSP – for user software).
Only 1 register active at a time
(The software considering is in a
high-reliability OS)
 R14: Link Register (LR) -> Store
return location for functions
 R15: Program Counter (PC) ->
points to the next
- Physical Address: (20 bit)
 Physical address = Segment
address (16 bit) * 10h + Offset
address (16 bit)
- Data:
 A word = 16 bit data
- Instructions:
 Depend on each instruction
- Flag Registers:
 6 status flags: CF (Carry Flag), PF
(Parity Flag), AF (Auxiliary Flag),
ZF (Zero Flag), SF (Sign Flag), OF
(Overflow Flag)
 3 control flags: TF (Trap Flag), IF
(Interrupt Flag), DF (Direction
Flag)
- Stack:
 Only 1 stack
- Aliased-address using bit-banding
formula:
 To access bit b of the byte in RAM:
0x2200.0000 + 32*n + 4*b
n means address 0x2000.0000 + n
 To access bit b of the byte in I/O
space: 0x4200.0000 + 32*n + 4*b
n means address 0x4000.0000 + n
- Data:
 A halfword = 16 bit data
 A word = 32 bit data
- Instructions:
 All are halfword aligned (16 bit)
- Status Registers:
 3 status registers: APSR
(Application Program Status
Register), IPSR (Interrupts
Program Status Register), EPSR
(Execution Program Status
Register)
 Special bits: N (Negative?), Z (the
result is zero?), C (carry is set on
an unsigned overflow), V (signed
overflow), Q (saturation flag), T
(always be 1)
- Stack:
 Divided into 2 stacks: The Main
Stack and The Process Stack