ARM architecture

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For the Australian architectural firm, see ARM Architecture (Ashton Raggatt McDougall).
For processor core designs, see List of ARM microarchitectures.
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ARM architectures

The ARM logo

Designer Arm Holdings
Bits 32-bit, 64-bit
Introduced 1985; 35 years ago
Design RISC
Type Register-Register
Branching Condition code, compare and branch
Open Proprietary
64/32-bit architectures
Introduced 2011; 9 years ago
ARMv8-A, ARMv8.1-A, ARMv8.2-A,
Version ARMv8.3-A, ARMv8.4-A, ARMv8.5-
A, ARMv8.6-A
AArch64/A64 and AArch32/A32 use
32-bit instructions, T32 (Thumb-2) uses
Encoding
mixed 16- and 32-bit instructions;
ARMv7 user-space compatibility.[1]
Endianness Bi (little as default)
SVE;SVE2;TME; All mandatory:
Extensions Thumb-2, NEON, VFPv4-D16, VFPv4
Obsolete: Jazelle
Registers
General
31 × 64-bit integer registers[1]
purpose
32 × 128-bit registers[1] for scalar 32-
Floating
and 64-bit FP or SIMD FP or integer; or
point
cryptography
32-bit architectures (Cortex)
ARMv8-R, ARMv8-M, Armv8.1-M,
Version ARMv7-A, ARMv7-R, ARMv7E-M,
ARMv7-M, ARMv6-M
 32-bit, except Thumb-2 extensions use
Encoding
mixed 16- and 32-bit instructions.
Bi (little as default); Cortex-M is fixed
Endianness
and can't change on the fly.
Thumb-2, Neon, Jazelle, DSP,
Extensions
Saturated, FPv4-SP, FPv5, Helium
Registers
General 15 × 32-bit integer registers, including
purpose R14 (link register), but not R15 (PC)
Floating Up to 32 × 64-bit registers,[2]
point SIMD/floating-point (optional)
32-bit architectures (legacy)
ARMv6, ARMv5, ARMv4T, ARMv3,
Version
ARMv2
32-bit, except Thumb extension uses
Encoding
mixed 16- and 32-bit instructions.
Bi (little as default) in ARMv3 and
Endianness
above
Extensions Thumb, Jazelle
Registers
15 × 32-bit integer registers, including
General
R14 (link register), but not R15 (PC,
purpose
26-bit addressing in older)

ARM, previously Advanced RISC Machine, originally Acorn RISC Machine, is a family
of reduced instruction set computing (RISC) architectures for computer processors,
configured for various environments. Arm Holdings develops the architecture and licenses it
to other companies, who design their own products that implement one of those architectures‍
—‌including systems-on-chips (SoC) and systems-on-modules (SoM) that incorporate
memory, interfaces, radios, etc. It also designs cores that implement this instruction set and
licenses these designs to a number of companies that incorporate those core designs into their
own products.

Processors that have a RISC architecture typically require fewer transistors than those with a
complex instruction set computing (CISC) architecture (such as the x86 processors found in
most personal computers), which improves cost, power consumption, and heat dissipation.
These characteristics are desirable for light, portable, battery-powered devices‍—‌including
smartphones, laptops and tablet computers, and other embedded systems[3][4][5]‍—‌but are also
useful for servers and desktops to some degree. For supercomputers, which consume large
amounts of electricity, ARM is also a power-efficient solution.[6]

Arm Holdings periodically releases updates to the architecture. Architecture versions ARMv3
to ARMv7 support 32-bit address space (pre-ARMv3 chips, made before Arm Holdings was
formed, as used in the Acorn Archimedes, had 26-bit address space) and 32-bit arithmetic;
most architectures have 32-bit fixed-length instructions. The Thumb version supports a
variable-length instruction set that provides both 32- and 16-bit instructions for improved
code density. Some older cores can also provide hardware execution of Java bytecodes; and
newer ones have one instruction for JavaScript. Released in 2011, the ARMv8-A architecture
added support for a 64-bit address space and 64-bit arithmetic with its new 32-bit fixed-
length instruction set.[7] Some recent Arm CPUs have simultaneous multithreading (SMT)
with e.g. Arm Neoverse E1 being able to execute two threads concurrently for improved
aggregate throughput performance. ARM Cortex-A65AE for automotive applications is also
a multithreaded processor, and has Dual Core Lock-Step for fault-tolerant designs
(supporting Automotive Safety Integrity Level D, the highest level). The Neoverse N1 is
designed for "as few as 8 cores" or "designs that scale from 64 to 128 N1 cores within a
single coherent system".[8]

With over 130 billion ARM processors produced,[9][10][11][12] as of 2019, ARM is the most
widely used instruction set architecture (ISA) and the ISA produced in the largest quantity.[13]
[4][14][15][16]
Currently, the widely used Cortex cores, older "classic" cores, and specialized
SecurCore cores variants are available for each of these to include or exclude optional
capabilities.