Memory Design PDF

Memory Design
• Memory Types
• Memoryy Organization
g
• ROM design
• g
RAM design
• PLA design
Adapted from J. M. Rabaey, A. Chandrakasan and B. Nikolic, Digital

Integrated Circuits, 2nd ed. Copyright 2003 Prentice Hall/Pearson.
ECE 261 James Morizio 1

Semiconductor Memory
Classification
Non-Volatile
Read-Write Memory Read-Write Read-Only Memory
Memory
Random Non-Random EPROM Mask-Programmed

Access Access 2
E PROM P
Programmable
bl (PROM)
SRAM FIFO FLASH
DRAM LIFO
Shift Register
CAM

M
Memory Timing:
Ti i Definitions
D fi i i
Read cycle
y
READ
Write cycle
Read access Read access
WRITE
Write access
Data valid
DATA
Data written

Memory
y Architecture:
DecodersM bits M bits
S0 S0
Word 0 Word 0
S1
Word 1 A0 Word 1
S2 Storage Storage
Word 2 A1 Word 2
cell cell
words A K2 1
N SN 2 2
Word N 2 2 Decoder Word N 2 2
SN 2 1
Word N 2 1 Word N 2 1
K 5 log2N
Input-Output Input-Output
(M bits) (M bits)
Intuitive architecture for N x M memory Decoder reduces the number of select signals
Too many select signals: K = log2N
N words
d == N select
l t signals
i l

Array-Structured Memory Architecture
Problem: ASPECT RATIO or HEIGHT >> WIDTH
2L 2 K Bit line
Storage cell
AK
Row Decoder
A K1 1 Word line
AL2 1
M.2K
Amplify swing to
Sense amplifiers / Drivers rail-to-rail amplitude
A0
Column decoder Selects appropriate
A K2 1 word
p p
Input-Output
(M bits)

Hierarchical Memory Architecture
Block 0 Block i Block P 2 1
Row
address
dd
Column
address
Block
address
Global data bus

Control Block selector Global
circuitry amplifier/driver
I/O
Advantages:
1. Shorter wires within blocks
2. Block address activates only 1 block => power savings
R d O l Memory
Read-Only M Cells
C ll
BL BL BL
VDD
WL
WL WL
1
BL BL BL
WL WL
WL
0
GND
Diode ROM MOS ROM 1 MOS ROM 2

MOS OR ROM
BL[0] BL[1] BL[2] BL[3]
WL[0]
V DD
WL[1]
WL[2]
V DD
WL[3]
V bias
Pull-down loads

ROM Example
• 4-word x 6-bit ROM Word 0: 010101
– Represented with dot diagram Word 1: 011001
– Dots indicate 1’s in ROM Word 2: 100101
weak
pseudo-nMOS Word 3: 101010
A1 A0
pullups
2:4
DEC
ROM Arrayy
Y5 Y4 Y3 Y2 Y1 Y0
Looks like 6 4
4-input
input pseudo
pseudo-nMOS
nMOS NORs

MOS NOR ROM
V DD
Pull up devices
Pull-up
WL[0]
GND
WL [1]
WL [2]
GND
WL [3]
BL [0] BL [1] BL [2] BL [3]

MOS NOR ROM Layout
Cell (9.5λ x 7λ)
Programmming using the

Active Layer
y Only
y
Polysilicon
Metal1
Diffusion
Metal1 on Diffusion

MOS NOR ROM Layout
Cell (11λ x 7λ)
Programmming using
the Contact Layer Only
Polysilicon
Metal1
Diffusion
Metal1 on Diffusion

MOS NAND ROM
V DD
Pull-up devices
BL [0] BL[1] BL[2] BL[3]
WL [0]
WL [1]
WL [2]
WL [3]
All word lines high by default with exception of selected row

MOS NAND ROM Layout
Cell (8λ x 7λ)
Programmming
P i using
i
the Metal-1 Layer Only
No contact to VDD or GND necessary;

drastically reduced cell size
Loss in performance compared to NOR ROM
Polysilicon
Diffusion
Metal1 on Diffusion

NAND ROM Layout
Cell (5λ x 6λ)
Programmming
P i using
i
Implants Only
Polysilicon
Threshold-altering
implant
Metal1 on Diffusion

Decreasing
g Word Line Delayy
Driver
WL Polysilicon word line
Metal word line
(a) Driving the word line from both sides
Metal bypass
WL K cells Polysilicon word line
(b) Using a metal bypass

Precharged
g MOS NOR ROM
f V DD
pre
Precharge devices
WL [0]
GND
WL [1]
WL [2]
GND
WL [3]
BL [0] BL [1] BL [2] BL [3]
PMOS precharge device can be made as large as necessary,

but clock driver becomes harder to design.
design
Read-Write Memories (RAM)
STATIC (SRAM)
Data
D t stored
t d as llong as supply
l iis applied
li d
Large (6 transistors/cell)
Fast
Differential
DYNAMIC (DRAM)
Periodic refresh required
Small (1-3 transistors/cell)
Slower
Single Ended
6 transistor CMOS SRAM Cell
6-transistor
WL
V DD
M2 M4
Q
M5 Q M6
M1 M3
BL BL

6T-SRAM — Layout
M2 M4
VDD
Q Q
M1 M3
GND
M5 M6 WL
BL BL

Statue of Goethe and Schiller: the German National Theater, Weimar

3-Transistor DRAM Cell
BL 1 BL 2
WWL
RWL WWL
M3 RWL
M1 X X
M2
CS BL 1
BL 2
No constraints on device ratios

Reads are non-destructive
Value stored at node X when writing a “1” = V WWL-VTn
3T-DRAM — Layout
BL2 BL1 GND
RWL
M3
M2
WWL
M1

1-Transistor DRAM Cell
BL
WL Write 1 Read 1
WL
M1
X GND V DD 2 V T
CS
V DD
BL
V DD /2 V /2
sensing DD
CBL
Write: C S is charged or discharged by asserting WL and BL.

Read: Charge redistribution takes places between bit line and storage capacitance
CS
ΔV = VBL – V PRE = V BIT – V PRE ------------
C S + CBL
Voltage swing is small; typically around 250 mV.

DRAM Cell Observations
1T DRAM requires a sense amplifier for each bit line, due to
charge redistribution read-out.
DRAM memory cells ll are single-ended
i l d d in
i contrast to SRAM
cells.
The read-out of the 1T DRAM cell is destructive; read and
refresh
f h operations
ti are necessary for
f correctt operation.
ti
Unlike 3T cell, 1T cell requires presence of an extra
capacitance that must be explicitly included in the design.
When writing a “1” into a DRAM cell, a threshold voltage is
lost. This charge loss can be circumvented by bootstrapping
the word lines to a higher value than VDD

1-T DRAM Cell
Capacitor
Metal word line M 1 word

SiO2 line
Poly
n+ n+ Field Oxide
Inversion layer Diffused

Poly bit line
induced by
plate bias
Polysilicon
Polysilicon
gate plate
Cross-section
Cross section Layout
Uses Polysilicon-Diffusion Capacitance
Expensive in Area (trend now is to use trench capacitors

Periphery
p y
Decoders
Sense Amplifiers
p
Input/Output Buffers
Control / Timing Circuitry

R D
Row Decoders
d
Collection of 2M complex logic gates
Organized in regular and dense fashion
(N)AND Decoder
NOR Decoder

Hierarchical Decoders
Multi-stage implementation improves performance
•••
WL 1
WL 0
A 0A 1 A 0A 1 A 0A 1 A 0A 1 A 2A 3 A 2A 3 A 2A 3 A 2A 3
•••
NAND decoder using
2-input pre
pre--decoders
A1 A0 A0 A1 A3 A2 A2 A3

D namic Decoders
Dynamic
Precharge devices GND GND VDD
WL3
VDD
WL 3
WL 2
WL 2 VDD
WL 1
WL 1
V DD
WL 0
WL 0
VDD φ A0 A0 A1 A1
A0 A0 A1 A1 φ
2-input NOR decoder 2-input NAND decoder

4-to-1 tree based column decoder
BL 0 BL 1 BL 2 BL 3
A0
A0
A1
A1
D
Number of devices drastically reduced
Delay increases quadratically with # of sections; prohibitive for large decoders
Solutions: buffers
progressive sizing
combination
bi ti off tree
t andd pass transistor
t i t approachesh

PLA versus ROM
Programmable Logic Array
structured approach to random logic
“two level logic implementation”
NOR-NOR (product of sums)
NAND-NAND (sum of products)
SIMILAR TO ROM
Main difference
ROM: fully populated
PLA: one element per minterm
Note: Importance
p of PLA’s has drastically
y reduced
1. slow
2. better software techniques (mutli-level logic
synthesis)
B t…
But
Programmable Logic Array
P
Pseudo-NMOS
d NMOS PLA
V DD
GND GND GND GND
GND
GND
GND
V DD X0 X0 X1 X1 X2 X2 f0 f1
AND-plane OR-plane
Dynamic PLA
f AND
GND V DD
f OR
f OR
f AND
V DD X0 X0 X1 X1 X2 X2 f0 f 1 GND
AND-plane
AND plane OR-plane
OR plane

PLA Layout
And-Plane Or-Plane
VDD φ GND
x0 x0 x1 x1 x2 x2 f0 f1
Pull-up devices Pull-up devices
CAMs
• Extension
E t i off ordinary
di memory ((e.g. SRAM)
– Read and write memory as usual
– Also match to see which words contain a key
adr data/key
read
CAM match
write

10T CAM Cell
• Add four match transistors to 6T SRAM
– 56 x 43 λ unit cell
bit bit b
bit_b
word
cell
cell_b
match

CAM Cell Operation
• Read and write like ordinary SRAM
CAM cell
• For matching: clk weak

miss
– Leave wordline low
row decoder
address match0
– Precharge matchlines match1
– Place key on bitlines match2
– Matchlines evaluate read/write column circuitry

match3
• Miss line data
– Pseudo-nMOS NOR of match lines

– Goes high if no words match

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Memory Design

Adapted from J. M. Rabaey, A. Chandrakasan and B. Nikolic, Digital

ECE 261 James Morizio 1

Random Non-Random EPROM Mask-Programmed

SRAM FIFO FLASH

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Global data bus

Diode ROM MOS ROM 1 MOS ROM 2

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BL [0] BL [1] BL [2] BL [3]

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Programmming using the

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BL [0] BL[1] BL[2] BL[3]

All word lines high by default with exception of selected row

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No contact to VDD or GND necessary;

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Metal word line

(a) Driving the word line from both sides

WL K cells Polysilicon word line

(b) Using a metal bypass

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BL [0] BL [1] BL [2] BL [3]

PMOS precharge device can be made as large as necessary,

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No constraints on device ratios

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Write: C S is charged or discharged by asserting WL and BL.

Voltage swing is small; typically around 250 mV.

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Metal word line M 1 word

Inversion layer Diffused

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2-input NOR decoder 2-input NAND decoder

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• For matching: clk weak

– Precharge matchlines match1

– Place key on bitlines match2

– Matchlines evaluate read/write column circuitry

• Miss line data

– Pseudo-nMOS NOR of match lines

ECE 261 James Morizio 38

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