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ECE 271 Lab 3 Sequential Circuits - An Application
ECE 271 Lab 3 Sequential Circuits - An Application
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Questions and Musings…
Is a baby bear running through the forest with out the bottom part called a bare minimum?
Is it true that in Portugal they call Portuguese babies Portugoslings?
Is it easier to get ketchup out of a bottle if you are south of the equator where gravity makes
things fall down?
In the autumn, do they call geese feathers Fall down?
If we are in Da Nang on a really really tall building and can see all the way to Australia, we
see that the birds are all flying upside down.
If a bird is flying south for the winter, when do they decide to turn over and fly upside
down?
Impedance Matching:
Many instruments are designed with 50 ohm output impedance.
Offset Adjustment:
Most good signal generators have what is called an offset adjustment. This
adjustment is there because they are designed such that the normal output is centered
at ground and goes positive and negative from there. See the left hand graphic in
figure 0.
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Offset 0 Offset +5 V
+5 V +10 V
-5 V
Figure 0
Signal Generator Outputs
We use the offset adjustment to move the output waveform with respect to ground.
If you adjust the offset in the signal above, you can create a 0-10 volt waveform as in
the right hand figure.
You must determine where ground is first.
You must do this to generate the proper waveform into your circuit.
Notice that you now have a 10V signal. You must adjust its amplitude to +5 volts.
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System Requirements Specification
Overview
The project is to design and build a portion of a new process control system to be
installed at the Arberlour Distillary for manufacturing a’bunadh Scotch whisky. The
prototype system will demonstrate one such system that is to be used to time the
fermentation process and to manage the transfer the whisky from one tank to the next.
Specification
The required system operation is as follows.
Mode 1: Automatic
When the timer reaches the 80% mark, the system contacts the main processing
station to request permission to execute the transfer.
When the fermentation is 90% complete, the system generates a signal that can be
used by other tanks to prepare for a transfer younger whisky to the tank that is
being emptied.
When the fermentation step is 100% complete and the execute transfer command
has been received, the system will transfer the aged batch to the new tank, load
the new, younger batch, and begin the fermentation anew.
When the fermentation step is 100% complete and permission has not been given
to execute the transfer, the tank is flushed and the whisky lost.
The transfer takes half as long as the fermentation.
The flush takes as long as the fermentation plus the transfer.
The state of the system should be displayed for easy user viewing.
Mode 2: Manual
The required system operations are the same with automatic mode but the input
commands are entered via set of switches. And the user can switch between
automatic mode and manual mode intermediately during the system operating (do
not need to reset the system).
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When the fermentation is 100% complete and the control system has received a
Transfer command, the system shall will transfer the batch to the new tank, load
the new batch, and begin the fermentation anew.
When the fermentation step is 100% complete and permission has not been given
to execute the transfer, the system will enter the Flush state, tank is flushed and
the whisky lost.
If the system enters the Flush state, it shall remain there until the tank is empty.
All output signals are active low.
All input signals are active high.
Deliverables
This following are your deliverables and schedule:
Phase 1
1. Determine the necessary inputs and outputs to the complete system.
2. Draw a high-level timing diagram of the system.
3. Draw a high-level functional block diagram of the system.
4. Determine the state diagrams for the timer and the control system.
5. Develop the state table for your timer.
6. Detailed design and implementation, in Verilog, of a model of the timer. Execute
your simulation and verify proper operation. This must be a structural model.
Phase 2
7. In the Quartus environment, create a new project and implement your timer design as
a logic / schematic diagram. Use the design based upon the Verilog model that you
have tested.
8. Debug your design to ensure that the timer is operating properly
9. All deliverables should be ready for a design review.
Phase 3
1. Develop the state table for your control system.
2. Detailed design and implementation, in Verilog, of a model for the control system.
This must be a structural model. Execute your simulation and verify proper
operation.
3. Develop any necessary Verilog test vectors that can be used to demonstrate to you
and your customer that your circuit works correctly under normal and error
conditions.
Phase 4
4. In the Quartus environment, create a new project for your control system and
implement your control system design as a Verilog model.
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5. Debug your control system to ensure that it is working properly. Temporarily model
the timer signals and behaviour with switches.
6. Using the Quartus tools, convert your timer logic/schematic diagram into a Verilog
file.
File→Create/Update→Create HDL Design for Current File
Follow the remaining steps in section B.5.2 of Appendix B in the text.
7. Integrate your timer and control system into the final deliverable product. See the
class text, Appendix B section B.5.2 Using Verilog at the Top Level.
8. Debug the integrated system.
9. Develop a set of test cases to prove that your design operates according to your
specification.
10. Update your documentation.
11. Demo your design.
12. Write up a formal report for the design of your system.
Please include in your lab report an estimate of the number of hours each partner spent
working on each of the following:
Design
Test / Debug
Documentation
Extra Credit
For extra credit, propose and implement additional features or capabilities for the
fermentation system. You can add outputs and/or inputs up to the limit of what the Altera
Cyclone II FPGA supports. Extra credit points will be based upon originality, creativity,
and imagination.
To receive extra credit, all of the basic features must be working properly.
To be considered for extra credit, each added feature must be fully functional.
Lab Report
Please include in your lab report an estimate of the number of hours each partner spent
working on each of the following:
Design
Test / Debug
Documentation
If you were not able to get your design to work, include a contingency section describing
the problem you are having, an explanation of possible causes, a discussion of what you
did to try to solve the problem, and why such attempts failed.
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Each person in your group must contribute equally to the design, development, and demo
of the system.
NOTE: If any of the above requirements is not clear, or you have any concerns or
questions about you are required to do, please do not hesitate to ask us.
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