EE 271 Lab 3

Sequential Circuits - An Application

Using Verilog, the Quartus IDE, and the Altera Cyclone FPGA
The University of Da Nang - Department of Electrical Engineering
James K. Peckol and Tuan V. Pham

Lab Objectives and Overview:

The purpose of this lab is to study sequential circuits, to continue to enhance our modeling
skills using the Verilog language, and to learn more about the design and development of
digital systems using sequential arrayed logics.
For this project, our goals will be to design, develop, and implement a portion of a Scotch
whisky fermentation control system. Our system will be based upon two simple sequential
machines, the first will be a counter/timer and the second the control logic.
Prerequisites:
Familiarity with Verilog design language, the Quartus IDE, the DE1 board, and just about
everything else. Someone’s permission to be in this class. Nothing to do until the end of the
quarter.
Reference Material
Reference material for this lab includes:
 Referenced sections from Appendices B and C in the Brown and Vranesic text, 2nd ed.,
 The DE 1 Board tutorials on the class web page under documentation.
 The Verilog design examples,
 The Verilog Tutorials.
Cautions and Warnings…not Musings
The Cyclone II FPGA is a semiconductor integrated circuit. All such circuits are very
sensitive….so is your TA … treat them both nicely. They also don’t like static discharge, so
doing so is not a good plan.
Never leave the function generator leads disconnected with the generator turned on. The
signal will slowly leak out and the generator will run out of that kind of signal.
Never try to pick up stray 0’s or 1’s that may have leaked out of the function generator. Try
to borrow a bit bucket and scoop to clean them up.
Never tangle the oscilloscope leads because the electrons will get confused and not know
where to go.
Never tangle with a lion….if you can’t figure out why…well, never go out in the jungle by
your self….even if you think he’s telling the truth.
When walking in the forest never dismiss a roll of TP hanging on a tree branch…there may be
bears nearby….yes, they do, in the woods.

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Questions and Musings…
Is a baby bear running through the forest with out the bottom part called a bare minimum?
Is it true that in Portugal they call Portuguese babies Portugoslings?
Is it easier to get ketchup out of a bottle if you are south of the equator where gravity makes
things fall down?
In the autumn, do they call geese feathers Fall down?
If we are in Da Nang on a really really tall building and can see all the way to Australia, we see
that the birds are all flying upside down.
If a bird is flying south for the winter, when do they decide to turn over and fly upside down?

Signal Generator Smarts

If you're using a signal generator, please make sure it is configured properly before
connecting it up to any circuit.

 Have you provided the proper termination - 50

Ohms.
 Have you properly adjusted the offset.
 Have you set the proper voltage level.

The Proper Use of Signal and Waveform Generators

To use measuring and stimulus instruments, such as our signal generators, correctly we
always need to learn what the instrument can and can't do. We also need to learn how
to set things up properly so that we are getting the results we expect and so that we
don't damage the thing we're trying to measure.

Impedance Matching:
Many instruments are designed with 50 ohm output impedance.

Offset Adjustment:
Most good signal generators have what is called an offset adjustment. This adjustment
is there because they are designed such that the normal output is centered at ground
and goes positive and negative from there. See the left hand graphic in figure 0.

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 Offset 0 Offset +5 V

+5 V +10 V

-5 V

Figure 0
Signal Generator Outputs

We use the offset adjustment to move the output waveform with respect to ground.
If you adjust the offset in the signal above, you can create a 0-10 volt waveform as in
the right hand figure.
You must determine where ground is first.
You must do this to generate the proper waveform into your circuit.
Notice that you now have a 10V signal. You must adjust its amplitude to +5 volts.

The Design Problem

The Problem
Your company has just won a contract from one of the premiere (yet
little known) distilleries in all of Scotland. Arberlour, on the edge of the
beautiful and rugged Grampian Mountains in the highlands of Scotland,
needs a control system for a portion of their new distillation system.
The prototype system will demonstrate the control of one production
line that will process one of their finest whiskeys called a’bunadh.
The control system is intended to run with minimal attention and is to be
integrated into a much larger management and control system. As part
of the process, the system must periodically transfer the aged (but still young) raw whisky
from one fermenter to the next for additional processing and aging. At the same time, the
younger whisky must be transferred in and mixed with a small portion of the older.
To demonstrate the efficacy of our design, we will implement a simple version that will control
only one unit; we must design and build that version.
Each vat has a timer for tracking the length of time the fermentation process has been on
going. When the timer reaches 80% of the required fermentation time, the system contacts the
main processing station to request permission to begin the transfer to the next station. When
the timer reaches is 100%, and permission has been granted, the transfer commences. If
permission has not been granted to transfer, the control system flushes the tank, thus, loosing
all the whisky. The first prototype will be based on a 1 tank control system.
System Requirements Specification
Overview
The project is to design and build a portion of a new process control system to be installed
at the Arberlour Distillary for manufacturing a’bunadh Scotch whisky. The prototype
system will demonstrate one such system that is to be used to time the fermentation
process and to manage the transfer the whisky from one tank to the next.

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 Specification
The required system operation is as follows.
Mode 1: Automatic
 When the timer reaches the 80% mark, the system contacts the main processing
station to request permission to execute the transfer.
 When the fermentation is 90% complete, the system generates a signal that can be
used by other tanks to prepare for a transfer younger whisky to the tank that is
being emptied.
 When the fermentation step is 100% complete and the execute transfer command
has been received, the system will transfer the aged batch to the new tank, load the
new, younger batch, and begin the fermentation anew.
 When the fermentation step is 100% complete and permission has not been given
to execute the transfer, the tank is flushed and the whisky lost.
 The transfer takes half as long as the fermentation.
 The flush takes as long as the fermentation plus the transfer.
 The state of the system should be displayed for easy user viewing.
Mode 2: Manual
 The required system operations are the same with automatic mode but the input
commands are entered via set of switches. And the user can switch between
automatic mode and manual mode intermediately during the system operating (do
not need to reset the system).

System Design Specification

Operation
Internally, the system comprises a timer system and a control system. The timer system
may be modeled using a decade/hex counter.
Commands, typically sent from the controller, can be entered via a set of switches.
The required system operation is as follows.
 While the batch is fermenting, it shall issue a Fermenting status indicator.
 When the fermentation is 80% complete, the system issues a ReadyToTransfer
signal to the master control station to request permission to transfer.
 When the fermentation is 90% complete, the system generates PrepareToTransfer
signal for other tank(s).
 When the fermentation is 100% complete and the control system has received a
Transfer command, the system shall will transfer the batch to the new tank, load
the new batch, and begin the fermentation anew.
 When the fermentation step is 100% complete and permission has not been given
to execute the transfer, the system will enter the Flush state, tank is flushed and the
whisky lost.
 If the system enters the Flush state, it shall remain there until the tank is empty.

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  All output signals are active low.
 All input signals are active high.

Deliverables
This following are your deliverables and schedule:
Phase 1
1. Determine the necessary inputs and outputs to the complete system.
2. Draw a high-level timing diagram of the system.
3. Draw a high-level functional block diagram of the system.
4. Determine the state diagrams for the timer and the control system.
5. Develop the state table for your timer.
6. Detailed design and implementation, in Verilog, of a model of the timer. Execute your
simulation and verify proper operation. This must be a structural model.
Phase 2
7. In the Quartus environment, create a new project and implement your timer design as
a logic / schematic diagram. Use the design based upon the Verilog model that you
have tested.
8. Debug your design to ensure that the timer is operating properly
9. All deliverables should be ready for a design review.
Phase 3
1. Develop the state table for your control system.
2. Detailed design and implementation, in Verilog, of a model for the control system. This
must be a structural model. Execute your simulation and verify proper operation.
3. Develop any necessary Verilog test vectors that can be used to demonstrate to you and
your customer that your circuit works correctly under normal and error conditions.
Phase 4
4. In the Quartus environment, create a new project for your control system and
implement your control system design as a Verilog model.
5. Debug your control system to ensure that it is working properly. Temporarily model
the timer signals and behaviour with switches.
6. Using the Quartus tools, convert your timer logic/schematic diagram into a Verilog
file.
File→Create/Update→Create HDL Design for Current File
Follow the remaining steps in section B.5.2 of Appendix B in the text.
7. Integrate your timer and control system into the final deliverable product. See the
class text, Appendix B section B.5.2 Using Verilog at the Top Level.
8. Debug the integrated system.
9. Develop a set of test cases to prove that your design operates according to your
specification.

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 10. Update your documentation.
11. Demo your design.
12. Write up a formal report for the design of your system.

Please include in your lab report an estimate of the number of hours each partner spent
working on each of the following:
Design
Test / Debug
Documentation

Extra Credit
For extra credit, propose and implement additional features or capabilities for the
fermentation system. You can add outputs and/or inputs up to the limit of what the Altera
Cyclone II FPGA supports. Extra credit points will be based upon originality, creativity,
and imagination.
To receive extra credit, all of the basic features must be working properly.
To be considered for extra credit, each added feature must be fully functional.

Lab Report
Please include in your lab report an estimate of the number of hours each partner spent
working on each of the following:
Design
Test / Debug
Documentation
If you were not able to get your design to work, include a contingency section describing
the problem you are having, an explanation of possible causes, a discussion of what you
did to try to solve the problem, and why such attempts failed.
Each person in your group must contribute equally to the design, development, and demo
of the system.
NOTE: If any of the above requirements is not clear, or you have any concerns or
questions about you are required to do, please do not hesitate to ask us.

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