SEMESTER IV L T P C

VLSI DESIGN 3 0 0 3
Aim
To provide the knowledge on VLSI fabrication and circuit design procedures
Objective
 To understand the MOS transistor theory, CMOS technologies and the Layout
 To understand the circuit concepts and scaling of MOS Circuits.
 To understand the concepts of designing combinational and sequential circuit using CMOS logic
configuration
 To understand the subsystem design of IC’s
 To understand the concepts of CMOS testing

Unit – I: Introduction to MOS Technology 9

A brief History-MOS transistor, Ideal I-V characteristics, C-V characteristics, Non ideal I-V effects, DC transfer
characteristics - CMOS technologies, Layout design Rules, CMOS process enhancements, Technology related
CAD issues, Manufacturing issues.

Unit – II: Concepts and Scaling of MOS Circuits 9

Sheet resistance – Area capacitances of layers – Delay: Inverter Delays – Driving Large Capacitance loads –
Propagation Delay – Wiring Capacitances – Choice of Layers – Scaling of MOS Circuits: Scaling models and
factors – Scaling factors of device parameters – Limitation of Scaling.

Unit – III: Combinational and Sequential Circuit design 9

Circuit families –Low power logic design – comparison of circuit families – Sequencing static circuits, circuit design
of latches and flip flops, Static sequencing element methodology- sequencing dynamic circuits – synchronizers

Unit – IV: Datapath and Array Subsystems 9

Addition/ Subtraction – one/Zero Detectors – Comparators – Boolean Logical Operations – Coding – Shifters –
Multiplication – Division – Parallel Prefix Computations – SRAM – DRAM – ROM – Serial Access Memory –
Programmable Logic Arrays – Array yield, Reliability and Self-test.

Unit – V: Testing 9
Need for testing- Testers, Text fixtures and test programs- Logic verification- Silicon debug principles-
Manufacturing test – Design for testability – Boundary scan
Total Hours: 45
Text Books:
1. Weste and Harris: CMOS VLSI DESIGN (Third edition) Pearson Education, Third edition, 2006.
2. D.A Pucknell & K. Eshraghian Basic VLSI Design, Third edition, PHI, 2003
Reference Books:
1. Wayne Wolf, Modern VLSI design, Pearson Education, 3 rd edition 2003
2. M. J. S. Smith: Application specific integrated circuits, Pearson Education, 1997
3. J. Bhasker: Verilog HDL primer, BS publication, 2001.

HOD\ECE

BE_ECE_PT_CBCS
 Dr.T.MUTHUMANICKAM
VINAYAKA MISSIONS RESEARCH FOUNDATION
(DEEMED TO BE UNIVERSITY)
VMKV ENGINEERING COLLEGE, SALEM
&
AARUPADAI VEEDU INSTITUTE OF TECHNOLOGY, CHENNAI
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
QUESTION BANK

DEGREE / BRANCH : B.E – ECE (PART TIME)

SUBJECT NAME : VLSI Design
SUBJECT CODE : 334716403
YEAR & SEMESTER : II / IV
REGULATION : CBCS R 2016

UNIT-I INTRODUCTION TO MOS TECHNOLOGY

PART-A
1. What are four generations of Integrated Circuits?
2. What is Enhancement mode transistor?
3. What is Depletion mode Device?
4. List out the different types of CMOS process.
5. What are the advantages of Silicon-on-Insulator process?
6. When the channel is said to be pinched –off?
7. What are the advantages of CMOS process?
8. Define Threshold voltage in CMOS.
9. Define Body effect.
10. What is Channel-length modulation?
11. What are the different design rules?
12. Define Impact Ionization.
13. List the basic process for IC fabrication
14. What are the 3 modes of an n-MOS enhancement transistor?
15. Define FEOL, BEOL.
16. What are the secondary effects of MOS transistor?
17. What is LOCOS?
18. What is SWAMI?
19. Sketch the DC transfer characteristics of a CMOS transistor.
20. Define Antenna effect.
PART-B
1. Elaborate the operation of N-MOS enhancement transistor with neat diagram.
2. Explain the n-well process of CMOS fabrication.
3. Describe with neat diagrams the Twin tub process in CMOS fabrication.
4. Derive the equation for ideal I-V characteristics.
5. Explain in detail the DC transfer characteristics of CMOS.
6. Give a detailed note on non ideal I-V effects of MOS transistor.
7. Explain in detail the C-V characteristics of MOS transistor
8. Narrate the lay out design rules of MOS transistor.
9. Elucidate about the CMOS Process enhancements.
10. Give a detailed note on Design for Manufacturability related to manufacturing issues.

PREPARED BY VERIFIED BY HOD\ECE

Dr.T.SHEELA Mr. C.ARUN KUMAR Dr.T.MUTHUMANICKAM
MAHDUVAPPAN

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 UNIT – II: CONCEPTS AND SCALING OF MOS CIRCUITS

PART-A

1. What are the components in wire capacitance?

2. What are the sources of variation available in Design margin?
3. Define RC Delay model.
4. Define propagation delay.
5. Define sheet resistance.
6. What is total load capacitance?
7. Define slope rate.
8. Sketch the parasitic capacitance of a MOS transistor.
9. What are the components of delay?
10. What are the limitations in scaling?
11. Mention the choice of layers.
12. What is meant by wiring capacitance?
13. What is fan in?
14. What is fan out?
15. Draw OR gate with pass transistors.
16. Draw the circuit for inverter type super buffer.
17. What are the types of scaling of MOS?
18. What is transistor scaling?
19. What is Lateral Scaling?
20. Mention scaling factors of device parameters.

PART-B

1. Explain the sheet resistance concept applied to MOS transistors and inverters with relevant
diagram.
2. Describe three sources of wiring capacitances. Also explain the effect of wiring capacitance on
the performance of a VLSI circuit.
3. Explain in detail about Propagation delay.
4. What is the problem encountered by VLSI circuits in driving large capacitive Loads?
5. Explain
a. Implement the function F = ab +c (a+b) using CMOS logic.
b. Define constant voltage scaling. Give necessary equations.
6. Draw the logic circuit for Inverter with a transmission gate to provide tri-state output, and
explain the same.
7. Explain clearly about different parasitic capacitances of an nMOS transistor.
8. Describe in detail the scaling factors of MOS device parameters.
9. Explain about
a. Pass Transistor Logic, with examples.
b. Derive the expressions for Rise-Time and fall time for CMOS inverter.
10. Express the Area capacitance in terms of standard capacitance units.

PREPARED BY VERIFIED BY
Dr.T.SHEELA Mr. C.ARUN KUMAR MAHDUVAPPAN

BE_ECE_PT_CBCS
 UNIT – III: COMBINATIONAL AND SEQUENTIAL CIRCUIT DESIGN

PART-A

1. What are the static properties of complementary CMOS Gates?

2. Draw the equivalent RC model for a two-input NAND gate.
3. What are the major limitations associated with complementary CMOS gate?
4. Define ratioed logic.
5. What is true single phase clocked register?
6. Define evaluation phase.
7. Sketch the CMOS transmission gate.
8. What is CLB?
9. Which MOS can pass logic 1 and logic 0 strongly?
10. What is precharge phase?
11. Define contamination delay.
12. What do you mean by bubble pushing?
13. List the drawbacks of ratioed circuits..
14. Write the features of CMOS Domino Logic?
15. Define clock skew.
16. How to reduce static power?
17. Mention the methods of reducing dynamic power.
18. What is CVSL?
19. What are the various forms of inverter based CMOS logic?
20. Define synchronizers.
PART –B
1. Explain in detail the static CMOS circuits.
2. Discuss in detail about the ratioed circuit and dynamic circuit CMOS logic configurations.
3. Explain clocked CMOS logic, domino logic and n-p CMOS logic.
4. Describe briefly about Signal Integrity Issues in Dynamic Design.
5. Elaborate on Dynamic CMOS Design.
6. Explain the working principle of LATCHES and REGISTERS.
7. Give a detailed note on CLOCK SKEW in CMOS design.
8. Explain briefly about KLASS SEMIDYNAMIC FLIP-FLOP (SDFF).
9. Write a detailed description on Radiation-Hardened Flip-Flops.
10. Explain briefly about i) Synchronizers ii) Arbiters.

UNIT – IV: DATA PATH AND ARRAY SUBSYSTEMS

PART-A

1. What is a data path subsystem?

2. What is a shifter?
3. What is the difference between shifter and barrel shifter?
4. Write the truth table for full adder.
5. Draw the circuit of one detector with AND gates.
6. Draw the circuit of zero detector with AND gates.

PREPARED BY VERIFIED BY
Dr.T.SHEELA Mr. C.ARUN KUMAR MAHDUVAPPAN

BE_ECE_PT_CBCS
7. What is comparator?
8. Draw the circuit of comparator.
9. What is parity generator?
10. What is the difference between synchronous and asynchronous counter.
11. Write the categories of memory arrays.
12. Define RAM.
13. Define EEPROM.
14. What is serial access memory?
15. What is content Addressable memory?
16. Draw the 6-Transistor SRAM cell
17. Draw the 1-Transistor DRAM cell
18. What are the different types of serial access memories?
19. What is flash memory?
20. Define PLA and mention its application.

PART-B
1. Design and explain the working of the following circuits using CMOS transistors
a. 2 bit counter
b. zero cross detector
2. With neat circuit diagram, explain the operation of
a. Carry look ahead adder
b. Barrel shifter.
3. Explain the following
a. Implementation of Full Adder using transmission gate logic.
b. Parity generator
4. Implement ALU functions with Adder.
5. Explain the following
a. 4 transistor SRAM.
b. One cell dynamic RAM circuit.
6. Give a detailed note on Error Correcting Codes.
7. Explain about pseudo nMOS PLA.
8. Explain the serial access memories.
9. Describe the function of Content addressable memory.
10. Explain the basic memory chip architecture.

UNIT – V: TESTING

PART-A

1. What are the different types of CMOS testing?

2. What is the aim of adhoc test techniques?
3. Define BIST.
4. List any two faults that occur during manufacturing
5. What is the need for testing?
6. What do you mean by functionality test?
7. Define manufacturing test.
8. Mention the defects that occur in a chip?
9. What is meant by fault models?
10. Give some examples of fault models.
11. What is meant by observability?
12. What is meant by controllability?
13. Mention the ideas to increase the speed of fault simulation.
14. What are the approaches in design for testability?
15. What are the scan-based test techniques?
16. What are the self-test techniques?

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17. What is known as BILBO?
18. Define IDDQ testing.
19. What is boundary scan?
20. Mention the levels at which testing of a chip can be done.

PART –B

1. Explain about different fault models in VLSI testing with examples.

2. Explain fault models.
a). Stuck-At Faults
b). Explain ATPG.
3. Briefly explain
a) Fault grading & fault simulation
b) Delay fault testing
c) Statistical fault analysis
4. Explain scan-based test techniques.
5. Explain in detail Ad-Hoc testing and chip level test techniques.
6. Elucidate about self-test techniques and IDDQ testing.
7. Explain system-level test techniques.
8. Write short notes on i.) Testers ii). Test Fixtures iii). Handlers.
9. Explain a) BILBO b) TAP controller c) Observability d) Controllability.
10. Give a detailed note on i). BIST ii). Boundary scan Testing.

PREPARED BY VERIFIED BY HOD\ECE

Dr.T.SHEELA Mr. C.ARUN KUMAR Dr.T.MUTHUMANICKAM
MAHDUVAPPAN

BE_ECE_PT_CBCS