23-02-2019

1. What are the imputs to PD .v .sdc .lib(logical) .lef physical

1. Shape of die comes from def file
2. ASIC input PPA&Cost Area – cost performance – power
3. Flow: spec-Architecture-design – verification-synthesis(behaviral to structural / elabaration
mapping optimization )
4. AND2X -AND4X difference
5. Howmany logic levels are to be there.
6. Virtual clock (sta nanometer book 34567 chapters)
7. How to constraint a design? set_drive_strength set_load
8.create_clock & generated_clock difference set_clock_uncertainity set_clock_latency clock
constraints
9. universal gate with 2x1 mux
10. 12 track 9 track routing resourse standard cell rails?
11.28nm height of standard cell? 1.7ns> lef file contains SITE of cell
12. M1(H) M2(V) M3(H) M4(V) M5(H) M6(V) M7(H) M8(V) M9(H) CT between H & V is little
13.M1 cant be used for routing resourse because it may short
M2 we can use 80% 4 routing 20% is required for vias.
M2 12 tracks? Railsz7tracks??
14. How 2 chose soft&hard placement blockage? Based on height & io pins of macros
Drive strength of macro pin
LEC RTL/synthe+DFT NL issues because of scan insertion
each cell has 3 physical views LEF GDS SPICE netlist used4lvs phyisical netlistVs GDS is LVS
extraction &STA& Signoff
Post route->Dcap&filler additions-->sign off below are done
LEC(logical netlist vs synth netlist, synthNL vs placeopt/routed & RTL &synth netlist) LVS(synth
netlist Vs GDS) PDV RAIL EXTRACTION &STA
Extraction:RC spef (cell+wire) dspf. STA inputs spef sdc,lib,def(4physical aware timing analysis)
STA chesk DRV(max tran/max cap/max fanout) logical drc setup&hold analysis inclusive cross talk
impact, Noise analysis(glitches) & min pulse width checks for clock
SI Cross talk
As wires are placed closer and CT is more for thicker wires as coupling capaciatnce.
CT impact on delay & functionality in the same layer. Agressor & victim nets. Each victim net can
have multiple agressor nets. When both agressor & victim are switching same dir transition
improves /opposite direction transition worsens it impacts delay. It depends on Coupling
cap/Agressor switching directions & strength. If the victim net is an input of a cell lead to
setup/hold versening scenarios. If the timing window overlap present between agressor & victim
nets causes CT. Agressor is switching and victim is static then it causes glitches(over shoot/under
shoot) results noise/functional issue.
AOCV
OCV is pessimistic: As derate is applied to all cells. In reality not all cells will have same worst
derate. There will be an average OCV impact on cells. If more cells in a Data path average impact is
more & derate value will be less (stage based ocv) and distance based ocv
OCV derate given by foundrt
AOCV: lookup table based on depth library vendor .avcv file
Rail Analysis:(CAD toos?)
1. Power dissipation (Psw+Pint+Pleakage)
2. Electro migration: power em/signal em
3.IR drop: Voltage drop
1.Avg/static IR drop snalysis: Based on average activity factor power
2.Dynamic IR drop analysis: Based on actual switching dynamic cells peak current analysis
Violations
signal em: is reduce load/add buffer
power em: Add another parallel power strap add missing vias. Spread cells which have more
switching activity. Add DECAP cells for dynamic IR drop. Decaps are placed near clock
buffers/high drive cells as a methodology as pre placed cells. What if analysis helps in placing
small/bigger decap based on dynamic power drop
Power Gating&Multi vdd
FINFET
To mitigate/overcome short channel impact (DIBL) Higher leakage MOSFET doesb’t shutoff even
after gate voltage is reduced then Vt.. Planar to finfet device (3 sided gate/gate cap is more) 16nm
onwords

Synth,latch based timing,lockup latch

ECO
DPT Dual patterning
Manufacturing: Photo lithiography
Light is passed through mask(mask is prepared on gds layers) – reduction lense -> wafer loaded
Raw wafers, Raw masks, Stepper are inputs
Critical Dimension = KYWL(lambda)/Refractive index RI XNA numerical apparture) 120nm
CD is redused by reducing wave length which requires new stepper. Or change RI by filling with
anaother gas. 76Nm is achieved.
If 38nm M2 pitch is wanted with same stepper use M1layer Mask1, M1 layer with Mask2
Patterning can be made beyond 5nm.
Signoff Coloring GDS layers/tracks PD
Bottom (M1 m2 m3 DPT 16/14nm more pitch)