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32-bit Adder
The object of this project to implement 32-bit adder in FPGA and simulate
1- Implementation
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ECE 462 MIPS Project SPRING 2020
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ECE 462 MIPS Project SPRING 2020
library IEEE;
use IEEE.std_logic_1164.all;
Ctrl+ C
use IEEE.std_logic_arith.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity adder_32 is
port (
x,y: in std_logic_vector(31 downto 0);
z: out std_logic_vector(31 downto 0)
);
end entity;
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ECE 462 MIPS Project SPRING 2020
CTRL+V
1.6 SYNTHESIS
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ECE 462 MIPS Project SPRING 2020
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ECE 462 MIPS Project SPRING 2020
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ECE 462 MIPS Project SPRING 2020
1.10 POWER
2. Simulation
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ECE 462 MIPS Project SPRING 2020
`
ECE 462 MIPS Project SPRING 2020
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.Numeric_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity adder_32_tb is
end;
architecture bench of adder_32_tb is
component adder_32 is
port (x,y: in std_logic_vector(31 downto 0);
z: out std_logic_vector(31 downto 0)
);
end component;
signal x : STD_LOGIC_vector(31 downto 0);
signal y : STD_LOGIC_vector(31 downto 0);
signal z : STD_LOGIC_vector(31 downto 0);
begin
uut: adder_32 port map( x => x, y => y, z => z);
stimulus : process
begin
x <= "00000000000000000000000000000000";
y <= "00000000000000000000000000000000";
wait for 10 ns;
x <= "00000000000000000000000011111111";
y <= "00000000000000000000000000000000";
wait for 10 ns;
x <= "00000000000000000000000011101001";
y <= "00000000000000000000000010111011";
wait for 10 ns;
x <= "00000000000000000000000011111110";
y <= "00000000000000000000000011011101";
wait;
end process;
end;
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ECE 462 MIPS Project SPRING 2020
`
ECE 462 MIPS Project SPRING 2020