Using Icarus Verilog, VVP and Gtkwave

Icarus Verilog (iverilog) and VVP were DOS based programs. Assuming the readers are familiar in using
iverilog, here are the steps to compile and simulate a Verilog code.
1. Create a Verilog file of the circuit you want to design and simulate. Example given here is a full adder
circuit. The file name is fa.v and this file is saved in the folder C:\iverilog\bin\

`timescale 1ns/100ps //file fa.v

module fa (
input a,b,c,
output sum,carry );
wire d,e,f;
xor(sum,a,b,c);
and(d,a,b);
and(e,b,c);
and(f,a,c);
or(carry,d,e,f);
endmodule

2. Compile the file fa.v by typing at the DOS prompt C:\iverilog\bin\iverilog fa.v
3. If there is syntax error/s, correct it and compile again. No message displayed when there is no error/s.

4. Create a testbench file to simulate the full adder circuit. Example given (at the bottom) is the testbench
file fatb.v and this file is saved in the folder C:\iverilog\bin\
5. Compile the testbench file fatb.v by typing at the DOS prompt C:\iverilog\bin\iverilog fatb.v
6. If there is syntax error/s, correct it and compile again. No message displayed when there is no error/s.
At this point, an output file called a.out is created in the C:\iverilog\bin\

7. To display the table of the input and output signals, type at the DOS prompt C:\iverilog\bin\vvp a.out

Mohd Uzir Kamaluddin / October 2017

8. To display the output waveforms, navigate to C:\iverilog\gtkwave\bin.
9. Type C:\iverilog\gtkwave\bin\gtkwave. This will launch the gtkwave.
10. When the gtkwave window open, select File>Open New Tab
11. Open the file C:\iverilog\bin\test.vcd

12. Double click the SST window folder fulladdt_b and you will see the uut subfolder.
13. Click the uut subfolder, and all the signals is displayed in the Signals window below.
14. Select and drag one by one of the input and output signals of the full adder circuit, the wire a, wire b,
wire c, wire carry and wire sum signals, and place it in the Waves window.
15. Click the unzoom button until the signals is displayed properly.

Mohd Uzir Kamaluddin / October 2017

 `timescale 1ns/100ps //file fatb.v
`include "fa.v"
module fulladdt_b;
reg a;
reg b;
reg c;
wire sum;
wire carry;
fa uut ( .a(a), .b(b),.c(c), .sum(sum), .carry(carry) );
initial
begin
$dumpfile("test.vcd");
$dumpvars(0, fulladdt_b); //for gtkwave display
a=0; b=0; c=0; //input signals for full adder
#50 a=0; b=0; c=1;
#50 a=0; b=1; c=0;
#50 a=0; b=1; c=1;
#50 a=1; b=0; c=0;
#50 a=1; b=0; c=1;
#50 a=1; b=1; c=0;
#50 a=1; b=1; c=1;
#50 a=0; b=0; c=0;
end
initial
begin //for display in DOS window
$monitor("a=%d, b=%d, c=%d, carry=%d, sum=%d \n", a, b, c, carry, sum);
end
endmodule

Mohd Uzir Kamaluddin / October 2017

The following is a JK flip flop verilog code. The JK flip flop has asynchronous inputs: set (S), reset (R)
and chip enable (CE).
//JK flip flop module
module FJKRSE(
input J,K,Clk,R,S,CE,
output Qout );

//Internal variable
reg Qout;

always@ (posedge(Clk)) //Everything is synchronous to positive edge of clock

begin
if(R == 1) //reset has highest priority.
Qout = 0;
else
if(S == 1) //set has next priority
Qout = 1;
else
if(CE == 1) //J,K values are considered only when CE is ON.
if(J == 0 && K == 0)
Qout = Qout; //no change J=K=0
else if(J == 0 && K == 1)
Qout = 0; //reset J=0,K=1
else if(J == 1 && K == 0)
Qout = 1; //set J=1, K=0
else
Qout = ~Qout; //toggle J=K=1
else
Qout = Qout; //no change
end

endmodule

//JK flip flop testbench module

`timescale 1ns/1ps
`include "jkff.v"
module tb_jkff;
// Inputs
reg J; reg K; reg Clk; reg R; reg S; reg CE;
// Outputs
wire Qout;

// Instantiate the Unit Under Test (UUT)

FJKRSE uut (.J(J), .K(K), .Clk(Clk), .R(R), .S(S), .CE(CE), .Qout(Qout));

Mohd Uzir Kamaluddin / October 2017

 //Create 50 Mhz clock(20 ns clock period).
initial Clk = 0;
always #10 Clk = ~Clk;

initial begin
$dumpfile("test1.vcd");
$dumpvars(0, tb_jkff); //for the gtkwave waveform viewer

// Initialize Inputs
J = 0; K = 0; R = 0; S = 0; CE = 0;

//Apply inputs
#30; R = 1;
#50; R = 0; S = 1;
#50; S = 0; J = 1; K = 1;
#50; CE = 1;
#50; J = 0; K = 0;
#50; J = 0; K = 1;
#50; J = 1; K = 0;
#50; J = 1; K = 1;
#50; CE = 0;
#30; $finish;
end

initial begin //for the DOS tabular display

$monitor("t=%3d, J=%d,K=%d, R=%d,S=%d, CE=%d, Qout=%d",$time,J,K,R,S,CE,Qout);
end

endmodule

Mohd Uzir Kamaluddin / October 2017