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  • Session 3 - LFSR

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    Jukio
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    This document provides instructions for a preliminary study on linear feedback shift registers (LFSRs) including: 1) Filling out a chronogram showing the LFSR operation over multiple cycles. 2) Creating an LFSR circuit scheme and simulating it with an initial reset, key loading of the binary coded decimal value 3, and at least five shift cycles. 3) Calculating the clock oscillation frequency of 108 Hz using the clock period of 10ns. 4) Listing the CPLD pin numbers for the enable, load, reset, key, and clock signals.

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    Session 3_ LFSR

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    This document provides instructions for a preliminary study on linear feedback shift registers (LFSRs) including: 1) Filling out a chronogram showing the LFSR operation over multiple cycles. 2) Creating an LFSR circuit scheme and simulating it with an initial reset, key loading of the binary coded decimal value 3, and at least five shift cycles. 3) Calculating the clock oscillation frequency of 108 Hz using the clock period of 10ns. 4) Listing the CPLD pin numbers for the enable, load, reset, key, and clock signals.

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    © All Rights Reserved
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    5 views2 pages

    Session 3 - LFSR

    Uploaded by

    Jukio
    This document provides instructions for a preliminary study on linear feedback shift registers (LFSRs) including: 1) Filling out a chronogram showing the LFSR operation over multiple cycles. 2) Creating an LFSR circuit scheme and simulating it with an initial reset, key loading of the binary coded decimal value 3, and at least five shift cycles. 3) Calculating the clock oscillation frequency of 108 Hz using the clock period of 10ns. 4) Listing the CPLD pin numbers for the enable, load, reset, key, and clock signals.

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    Fernando Burrieza Galán

    Lucía Carrera Saenz

    Session 3: LFSR

    Preliminary study:

    1) Fill out the next chronogram:

    2) Make the LFSR circuit scheme and simulate it. The simulation must show an initial
    reset, a key loading ((k1-k4)=BCD(LSB DNI)) and, at least, five shift cycles after the
    loading.

    We use the number 3 in BCD code.

    3) Obtain the CLK oscillation frequency.


    The frequency of the CLK is the inverse of the period of each rise edge:

    f = 1/T

    The period of the CLK is 10ns. So the f = 108 Hz


    Fernando Burrieza Galán
    Lucía Carrera Saenz

    4) Write down the CPLD pin numbers for the next inputs: ENABLE, LOAD, RST, key and
    CLK.

    Enable: 22
    Load: 12
    RST: 39
    Key: 18, 19, 14, 15 (From k1 to k4)
    CLK: 37

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