Cont. No.

: +91 7020281523/7875256765
FEROZ AHMED Mail Id: ferozer3@gmail.com
Address: Bangalore-India
CHOUDHARY
LinkedIn: http://www.linkedin.com/in/ferozchoudhary

Objective
Seeking a respectable position in a prominent organization that offers professional growth with mental
satisfaction to utilize my skills and abilities while being resourceful, innovative and flexible.

Education
College/University Degree/Certificate Percentage/CGP Year or passing
A
REVA University, Bengaluru. MTech In VLSI & Embedded systems. 9.1/10 2019
Goa Engineering College BE in electronics and tele- 65% 2017
(Goa University), Ponda-Goa. communication engineering
Agnel Polytechnic, Verna. Diploma in Electronics and 75% 2014
communication Engineering

Experience
SOCDV Technologies pvt ltd – Physical Design Engineer Intern June 2018 to May 2019 (Bengaluru)
PROJECT DETAILS Project: Block level -1
Technology/Layers 14nm / 12
Macros 80
Std. Cells 1.34 M
No. Of Clocks 4
Frequency 1.2 GHz
Used Tools IC Compiler, Calibre

 This block consists of 1.34M Instance count that Contains 4 clocks have 12 metal layers.
 I have done data setup, floorplan, pin placement, macro placement, boundary cap insertion, power switches,
tap insertion, stripgen and Post_PG_Insertion and then verify DRC and clear base DRC.
Challenges:
 Facing for placing macros in order to reduce congestion issues.
 Placed partial blockages to overcome congestion some extent in placement stage.
 Facing and resolve DRC, DP, PM. (responsible for PV also)
 Fixed cell density and pin density (Congestion)

Siemens – Jan 2016 (Verna, Goa-India)

Industrial Trainee Engineer

Tools and Languages

 EDA Tools & software: Synopsys IC Compiler, Prime Time, StarRC, Design Compiler.
 Other Tools & Programming Languages: Cadence Virtuoso, OrCad, KiCad, Xilinx ISE, PSpice, Magic VLSI,
Code Blocks, SimaticStep7, TCL, Perl, Python, Verilog, C, Assembly Language, JavaScript, HTML & CSS
scripting.
  Boards & Operating Systems: FPGA (Spartan 3E & Spartan 6), ARM Cortex-M3, Arduino (UNO, Mega,
Leonardo & Nano), Raspberry Pi 2, Windows, Unix, Linux.
Certification Courses
Certification Authority Courses
Duke University Course offered by  Nanotechnology: A Makers Course
Coursera.
Udemy  KiCad PCB Design
 PCB Designing with OrCad Capture/ Allegro
 SOC Verification for Beginners
 Practical IOT using Arduino UNO
Protein Knowledge Solution  PLC Basics

Professional VLSI Training

1.VLSI Physical design with Synopsys IC Compiler, Primetime & StarRC.
2.TCL Scripting
 Institute: VLSIGuru Training Institute.
Projects
1. Worked on ORCATOP single core 32bit RISC processor for single voltage and multi voltage domain as follows.
Project details Project 1: Single voltage domain Project 2: Multi voltage domain
Technology 28nm 28nm
Layer 9 Routing Layers 9 Routing Layers
Macro’s 40 40
No. of Clocks 6 Clocks 6 Clocks
Total Cells 0.52M 0.68M
Target Clock Frequency 416 MHz 416 MHz with 6 Clocks in Design
Tools Used Synopsys ICC, StarRC, Primetime Synopsys ICC, StarRC, Primetime.
RESPONSIBILITIES
 Imported Verilog netlist, Read SDC, TLU+ files and linked physical library.
 Performed Sanity check.
 Floorplan: Used source file for IO Port locations and Boundary. Provided core to IO boundary, Placed
Macros and fixed Macros and IO ports. Derived PG connection, created power straps for nets VDD, VSS
and preroute standard cell rails, performed cut rows near Macros, Added End-Cap Cells Tap cells and
set attribute fixed true, Created placement blockages.
 Placement: Inserted buffers for all IO ports, create placement and legalized placement and Verified GRC,
Cell density, Pin density, Module placement. Placement utilization, Congestion report, Timing reports
are done, Pre-CTS optimization.
 CTS: Defined the routing rules width and spacing (layers and width), applied routing rule to clock nets,
performed timing optimization, CTO buffers used for optimization.
 Routing: Defined Routing layers, Global route, Track assignment, Detailed route, Route optimization.
 verified congestion, Timing and Qor.
 Performed DRC Fixes (shorts and opens)
2. Verification of AMBA Based AHB2APB Bridge Protocol. (MTech Final Year Project)
Wrote the Bridge Code in Verilog and verified the code by writing different test cases to make the APB
and AHB signal compatible with each other.
3. Design of CMOS Inverter (MTech Mini project)
Designed CMOS Inverter using Cadence Virtuoso and Obtained the Desired DC, AC, and transient curve.
 4. Gesture Based Interaction with A Wrist Worn Sensor. (BE Final year project)
Device is used to control mouse pointer and use as a joystick to play games on pc via wrist gestures.
5. Object Counter Using 8051 Microcontroller(AT89S51). (BE Mini project)
The circuit count the number of objects passing through a door. Based on the concept of LDR and LED.
6. RFID Based Attendance System (Diploma Final year project)
It uses RFID Tags to record attendance. Each student is assigned a unique RFID tag, which he/she is
required to swipe over the reader to give his/her attendance.
7. Website Design of Indian Cuisines (Diploma Mini project)
Used Html and CSS Scripting for designing the website with few java scripts to perform automatic
image switching.

Publications
 Feroz Ahmed Choudhary1, Amay Naik2, Deepa MK3, Bharthiya SH4 “Low Cost Wrist Worn Sensor Based
On Gesture Interaction” published at IEEE- 4th International Conference on Recent Trends on
Electronics, Information, Communication & Technology (IRTEICT-2019).
 Feroz Ahmed Choudhary1, Rajashekhar C Biradar2 “Physical Design Implementation of DTMF Single
Core 32Bit RISC Processor on 28nm Technology” published at International Research Journal of
Engineering and Technology (IRJET).
 Feroz Ahmed Choudhary1, Rajashekhar C Biradar2 “VLSI Design and Verification of AMBA Based
AHB2APB Bridge” published at International Journal of Science and Innovative Engineering &
Technology (IJSIET).

Achievements
 Part of the ECE Assets council as a Graphics Designer at Goa College of Engineering.
 Campus Manager at Channel V star India Pvt Ltd for V Fest which was held at Baga, Goa.
 Participated in march-past and awarded certificate by district collector, south Goa.
 Participated in many Cultural and Sports events during Academics and awarded with prizes.

Soft Skills
 Positive Attitude
 Punctual and disciplined
 Active learner and Go getter
 Interactive and co-operative nature
 Comprehensive problem solving ability, willingness to learn and good as a team player.

Personal Profile
 Date of Birth : 2nd November 1994
 Marital status : single
 Nationality : Indian
 Languages : English, Hindi, Konkani, Urdu, Bhojpuri
 Hobbies : traveling, reading, chess, riding Bikes, Playing outdoor games.
 Permanent Address : #276J/II, Panchbhatt, Maina-Curtorim, Salcete-Goa.
 Passport Number : T5737932
Declaration
I hereby declare that all the information stated above is true to best of my knowledge and belief. I take the
responsibility of any mistakes in data if occur in future.

Place: Bengaluru-India (Feroz Ahmed Chaudhary)