CHEPTER 5

RADIATION HARDENED BY DESIGN TECHNIQUES (RHBD)

5.1 General

The field of Radiation Hardening By Design (RHBD) can be subdivided into Device-
level and circuit-level hardening. Separate from Radiation Hardening By Process, in
which the actual semiconductor manufacturing processes are modified to reduce
Radiation sensitivity, device-level RHBD uses only minor modifications to an existing
device without typically violating any major design rules. The modifications are ideally
transparent to the fab, and should not incur any additional costs for fabrication.  In this
section we redesign the PLLs component using Radiation Hardening By Design
techniques.
The proposed phase locked loop (PLL) component is similar to a generic PLL. The
basic PLL building blocks are (a) Ring voltage controlled oscillator (VCO), (b) Phase/
Frequency Detector (PFD) (c) Charge Pump (CP), and (d) Loop filter (LF) [1, 2, 3].
The circuit level implementation of individual building blocks of phase locked loop is
presented. The analysis, design, and radiation hardened considerations of, phase
frequency detector, charge pump, and loop filter, ring voltage controlled oscillator are
explained in the following sections. The PLL circuit consists of both analog and digital
circuit. As shown in Figure 5.1, the charge pump, loop filter, and the VCO are mainly
analog circuits. They are sensitive to the threshold voltage variation. The PFD is a
digital circuit. It is sensitive to the Single Event Effect (SEE). [4, 5, 6].

Figure 5.1 Typical Phase-Locked Loop Architecture

145 
 
All the components of PLLs are implemented using Radiation Harden using Radiation
Harden BY Design Technique (RHBD) [1, 7, 8, 9, 10, 11].

5.2 Phase/Frequency Detector

“The circuit shown in Figure 5.2 is the modified inverter circuit which is capable of
withstands radiation, the variation in basic inverter characteristic during radiation is the
most important are the switch point, the decreased output rail voltage, and the increased
leakage current. If radiation becomes strong enough then proper inverter operation may
fail. As shown in Figure 5.2, When VIN is low and NMOS cuts off, it may turn back on
during irradiation. The inverter connects between VIN and the NMOS source terminal.
When VIN is low, the NMOS source terminal becomes high and Vgs becomes negative.
The main idea is to maintain the output voltage by making Vgs negative when the
NMOS cuts off. Figure 5.2 shows the radiation hardened inverter circuit. It is shown
that the switch point improves” [1, 12, 13, 14, 9].

Figure 5.2 Rad Hard Inverter

“The basic phase frequency detector circuit is shown in Figure 5.3 .In order to redesign
the circuit under radiation environment. The above radiation hardened inverter circuit is
implemented in each gate of PFD. An additional inverter is also added for each NMOS

146 
 
to radiation harden the NAND gate and AND-NOR gate. The rad-hard NAND gate and
AND-NOR gate are shown in Fig. 5.4 that an additional PMOS and NMOS pair is
added for each NMOS to make circuit radiation resistant” [15, 16, 17, 9].

Figure 5.3 Phase/Frequency Detector Circuit.

Figure 5.4 Radiations Hard NOR Gate.

147 
 
All the circuit component of PFD is implemented in AMD VLSI tool and simulation
has done and the main purpose to make all circuit component radiation harden using
RDBD techniques. The simulated results and circuit design are reported below from
figure 5.4 to 5.9.

Figure 5.5 Rad Hard AND-NOR Circuit

Figure 5.6 Schematic of Phase/Frequency Detector Circuit

148 
 
5.2.1 Simulation Results

Figure 5.7 Reference Clock Lead Feedback Clock

Figure 5.8 Reference Clock Lag Feedback Clock

149 
 
 Figure 5.9 Reference Clock Equals Feedback Clock

5.3 Charge Pump

“Charge Pumps are used to convert the pulse signals from the PFD to a current signal.
That current is used to generate voltage signal for controlling the VCO through the loop
filter. Figure 5.10 shows the detailed circuit schematic of charge pump designed using
AMD VLSI software. In this circuit, M5 – M8, D1, D2 and R1 are used to provide a
stable current source. The thermal voltage referenced self-biasing techniques are used in
this circuit” [1]. The output current is

I ------- 5.1

Where n is a constant value, in the range from 1.0 – 2.0 depending on process, VT is the
thermal voltage and equal to 25.6 mV, and D2 has an emitter area K times larger than
D1 [17, 18].

Since the value of current source is not dependent on the threshold voltage, it is
relatively stable in a radiation environment when all the MOSFET drift in the same
way.

“M1-M3 is used to initiate the current source to operate when the power is turned on
and the charge pump is enabled. The charge pump circuit can function under both large

150 
 
and small current. It is realized by switching transistors M13 and M14. When these two
transistors are turned on, the current flow through M23 or M24 is about 160uA when
the UP or Down signal is enabled. When M13 and M14 are turned off than the output
current is only 40 uA. The large and small current is controlled by the input control
signal. The large current is normally used when the PLL begins operation. It can
significantly reduce the lock in time. The small current is used when the output becomes
stable. Thus the phase difference will only make fine adjustments in the control voltage
and further reduce jitter in the output.

The output stage includes transistors M17 – M25. It mirrors the current from the current
source. The UP and Down inputs are employed to control the output to source or to sink
current through the current source.

The whole charge pump circuit can be disabled through input labeled. This function can
be operated in the power save mode when the high frequency output is not needed”.

Here the circuit is design and simulated using AMD simulator and results are produced
from figure 5.10, 5.12 & 5.13.

Figure 5.10 Radiation Hard Charge Pump

151 
 
5.3.1 Loop Filter
F

“Thhe loop filteer used in th

his circuit is a typical lo
oop filter circuit for PLL
L as shown in
Figgure 5.11, which
w here are smaall variations in the input
acts ass a low passs filter. If th
currrent, the currrent IPD lineearly chargees C1 and C22. This resullts in an aveeraging effecct.
Forr fast variatioons, since C1 C the currennt IPd appearrs as though it
C is much laarger than C2,
sim
mply drives the
t resistor R, remove the averaginng effect. Thus
T allowinng the PLL to
f the large phase diffeerences. The values of thhe capacitorrs and resistor
tracck quickly for
deteermine the overall
o dynaamic responnse PLL [1].. The lock range
r (∆ωL),, the range of
freq
quency over which PLL will track thhe input freqquency signaal and remainns locked”.

--- 5.2

here ξ is the damping facctor and ωn is the naturall frequency.

Wh

---- 5.3

----- 5.44

Wh
here KPFD is the gain of the
t PFD, KVCO
V is the gaiin of VCO. N is the freqquency dividder
ratiio in the feed
dback loop.

Figure 5.111 Loop Filter Circuit

Table 5.1 Dim

mensions andd values of co
omponents in Loop Filter

Cs 100
0pF
Rs 800
0 ohm
Cp 10p
pF

152
5.3.2 Simulation Results

Figure 5.12 UP Signal Lead DOWN Signal

Figure 5.13 UP Signal Lag DOWN Signal

153 
 
5.4 Radiation Hard Voltage Controlled Oscillator

“One of the most important design specifications for a VCO is its frequency versus
control voltage characteristic. If this characteristic varies due to radiation, it will affect
the central frequency of the VCO as well as its tuning range that resulting in an unstable
PLL. Therefore, it is desirable to have a VCO of which the frequency remains
unchanged at a given a control voltage in the presence of radiation. With such purpose
in mind we switched over to Radiation Hardened PPL” [1, 14, 19].

“The VCO circuit is shown in Figure 5.14, it includes two current controlled ring
oscillators (M12-M23, M24-M35) for noise rejection purpose. Each ring oscillator
includes three inverters, and each inverter consists of four transistors for rad-hard
purposes. The total current of oscillators is supplied by M3 and M5-M8. Transistor M3
converts the control voltage to current while M5-M8 provides minimum current for ring
oscillators when M3 is off. The sum of the current is mirrored through M10, M11 and
then controls the ring oscillators. The cross coupled transistors M28, M29 synchronize
the two oscillators so that the outputs are 180° degrees out of phase. The simple diff-
amp (M38-M42) converts the outputs of two ring oscillators to a single ended value and
restores the VCO output voltage swing to full rail-to-rail output”.

Figure 5.14 Radiation Hard VCO Circuit

154 
 
The range of output frequency is more than the required range. The maximum output
frequency is far beyond the requirement to provide enough margins for large current is
generally used when the PLL begins operation. It can significantly reduce the lock in
time.

“The small current is used when the output becomes stable. Thus the phase difference
will only make fine adjustments in the control voltage and further reduce jitter in the
output. The output stage includes transistors M17 – M25. It mirrors the current from the
current source. The UP and Down inputs are used to control the output to source or to
sink current through the current source. The whole charge pump circuit can be disabled
through input labeled Enabled. This function can be used in the power save mode when
the high frequency output is not required” [20, 21].

5.4.1 Simulation Results

Figure 5.15 Result of VCO Output Verses Input

5.5 Circuit Level Radiation Harden By Design

“After analyzing the total dose response in this chapter and measuring the device-level
transient response, the next step is naturally to apply that knowledge to an entire circuit.
The study of device-hardening, while very complex and challenging in its own right,
eventually must lead to hardened circuits, either by switching to a Radiation Hardened

155 
 
By Process solution or by adapting existing circuit topologies to be more robust to the
ion strikes they inevitably encounter. While the former may be a simple change (but an
expensive one), the latter is more complicated. Taking an off-the-shelf technology and
building it to be Radiation Hardened By Design potentially offers a cheap and reliable
alternative to expensive process changes.

The design level solution is very attractive because it allows the use of a standard
CMOS process [8]. However, this solution is specific for each kind of circuit. For
example, a micro-controller or an ASIC can include different design techniques to avoid
SEU. The design engineer is responsible to project the hardened circuit according to it
architecture and application” [1, 2, 22, 23, 24, 25].

5.5.1 Design Based Techniques

“The design-based techniques, also called architectural techniques, are highly accepted
because they can be applied to many different levels of the design without any
modification in the fabrication process technology. They can be planned to just detect
the presence of an upset in the system or they can be more complex in order to detect
and correct the system error in the presence of an upset. All design-based techniques are
composed of some kind of redundancy, which can be provided by extra components
(hardware redundancy) or by an extra execution time or by different instants of data
sampling (time redundancy). Very often, techniques implement a combination of [2, 5,
27].

Hardware redundancy is basically supported on logic redundancy which is characterized

as extra components or extra paths that allow the design to continue operation even
when some of parts fail. Error detection and correction codes (EDAC) can also been
seen as a hardware redundancy because it generates redundant bits to be able to detect
and correct upsets.

Each technique has some advantages and drawbacks, and there is always a compromise
between area, performance, power dissipation and fault tolerance efficiency” [27, 28].

Design-based mitigation techniques:

• Triple Modular Redundancy (TMR)
• Code Word State Preserving Technique (CWSP)
156 
 
5.5.2 Triple Modular Redundancy (TMR)

“This technique consists of triplicating elements in such a way that the logic value
resulting from at least two elements are propagated. This technique can be used to
prevent an error as result of a single fault occurring inside the elements .On the other
hand when a single event transient occurs before the inputs, the transient pulse may be
captured by the flip flops.TMR technique can be operated in such way that the fault is
propagated to only one flip flop by inserting temporal redundancy. There are two
implementation of the TMR technique. In the first implementation the clock signal of
each flip flop is delayed in such a way that the input signal is captured at three different
moments. Thus a transient fault at the input is captured only by one of the flip flops. In
the other implementation the input signal is delayed by the delay block” [29, 30].

“A triplicate voting system compares the outputs of three identical devices bit by bit,
relying on the fact that while each bit is equally vulnerable to upset, the probability of
the same bit upsetting in two independent devices is very low. Even a worst case SEFI
can only corrupt all the bits on a single chip and so it is correctable by triplicate voting
and the probability of two SEFIs are negligibly small. The downside of triplicate voting
is that it involves over 200% overheads and for large data words, voting each bit can
lead to very complicated voting circuitry.

The most common example of TMR is a D-type flip-flop that has been triplicate and to
which a voter has been added on its output. By replacing all flip-flops in design with the
circuit shown in figure 5.16, one would protect the design against SEUs in the flip-
flops. However, this would not protect against SEUs in the combinatorial logic
connecting the flip-flops in the design” [31].

Figure 5.16 Triple Modular Redundancy with voting

157 
 
Static Triple Modulo Redundancy is an approach where three identical circuits are
employed for each logic operation. “The outputs of the three identical logic circuits are
fed into a voting system which produces an output based on the majority of values. This
technique assumes that a radiation particle will only strike the diffusion region of one of
the circuits creating an SEU. Since the other two circuits in this approach are
unaffected, the voting system will disregard the inconsistent result of the effected circuit
and produce the correct output” [29].

Figure 5.17 Example Circuit with Radiation Tolerance using Static

Triple Modulo Redundancy (TMR)

“The drawback of this approach is the increased area and power consumption associated
with having three redundant circuits and the additional voting hardware. While the
increase in area is not necessarily a problem due to the high density of modern
processes but the power consumption of extra circuitry is a unfavorable issues to
satellite and mission spacecraft running on portable power cells” [32].

5.5.2.1 Simulation Results

In order to implement various design techniques we used the HDL simulation in result
shown below. All basic logic gates coding done in HDL for above triple modular

158 
 
redundancy technique and triple modular redundancy technique with voting are shown
in Figure 5.17 to 5.19. 

Figure 5.18 Triple modular Redundancy (TMR)

Figure 5.19 Triple modular Redundancy (TMR) with Input Change

159 
 
 Figure 5.20 Triple Modular Redundancy with voting

5.5.3 Code Word State Preserving Technique

“A radiation strike makes charge to be dumped on a diffusion node which results in

voltage glitches on these nodes. We are mainly concerned with those glitches that cause
nodes to change their logical value (i.e. those that cross the switch point of the gate in
question) and can be captured in a latch or flip-flop [33], thereby leading to incorrect
circuit operation [27].

Our approach make use of CWSP elements to achieve 100% SET tolerance. In case of a
SET event, the correct value is always computed by the CWSP element (which is
connected in a secondary path, off the functional circuit critical paths). This correct
value is used to repeat the computation in case of a SET event, by introducing a bubble
in the computation For a k input gate, the CWSP element has 2k inputs”. One set of k
inputs are connected to the inputs of the gate that the CWSP element replaces. The other
set of k inputs are connected to the delayed version (by a delay value d) of the first set
of k inputs The CWSP element tolerates glitches of width up to d. In Figure 2, the
inputs a and b are the un-delayed inputs, while the inputs a* and b* are delayed versions
of a and b respectively (delayed by d time units). Consider the CWSP element of either
the INVERTER or the NAND2 gate. When the input a = a*, and b = b*, each CWSP
element behaves normally, and the outputs are resistively driven to not (a) and not (ab)

160 
 
for the INVERTER and the NAND2 gate respectively. However, whenever there is an
SET event which results in a glitch on any input, the gate stops driving the output
resistively, since both the pull up and pull down paths are disabled. At this point the
output is held to its last correct value [11, 34].

Figure 5.21 Radiation Hardened Inverter (a) and NAND gate (b)

5.5.3.1 SIMULATION RESULTS

In order to implement various design techniques we used the T-SPICE and a simulation
has been done. All basic logic gates were designed in code word state preserving
technique.
1) INVERTER

Figure 5.22(a) Transient Analysis of Radiation Hardened Inverter

161 
 
 Figure 5.22(b) Transient Analysis of Radiation Hardened Inverter with State Preserving

2) NAND GATE

Figure 5.23 (a) Transient Analysis of Radiation Hardened NAND Gate by CWSP

162 
 
 Figure 5.23 (b) Transient Analysis of Radiations Hardened NAND Gate by CWSP

3) D-FLIPFLOP

Figure 5.24 Transient Analysis of Radiation Hardened D-FLIPFLOP by CWSP

163 
 
4) R-S FLIPFLOP

Figure 5.25 Transient Analysis of Radiation Hardened R-S FLIP-FLOP by CWSP

5.6 Summary

In this chapter, Basic building block of the PLLs- PFD, Charge pump and VCO
designed using modified inverter circuit which has been simulated in Ch-3 and results
are reported.
Finally, RBC technique proposed and results concludes that digital blocks incorporate
redundancy to prevent single event upsets. Combinational blocks are not seriously
affected by SEE. Memory elements in digital systems employ feedback and these
elements get corrupted easily during clock transitions. A majority voting relies on the
fact that the probability of two adjacent transistors being hit at the same moment is low.
It takes at least three elements to make an unambiguous decision when one of the
elements is wrong. Results show the operation of a majority decision circuit. When such
a scheme is not implemented a single latch would suffer as a result of SEU. With
redundancy and majority voting, the error in one of the latches is corrected by the other
two. This block would replace any latch which is susceptible to SEU.
 

164 
 
 REFERENCES

1. Dong Pan, H.W. Li, B.M. Wilamowski, “A Radiation-hard Phase-Locked Loop”,

IEEE International Symposium on Industrial Electronics, ISIE’03, Volume: 2,
page no. 901-906, June 2003.
2. Thomas Daniel Loveless, Brian D. Olson, Bharat L. Bhuva, W. Timothy Holman,
Craig C. Hafer, and Lloyd W. Massengill, “Analysis of Single-Event Transients in
Integer-N Frequency Dividers and Hardness Assurance Implications for Phase-
Locked Loops”, IEEE Transactions on Nuclear Science, Vol. 56, No. 6,
December 2009.
3. Rajat Sengupta, Bert Vermeire, Lawrence T. Clark, and Bertan Bakkaloglu, “A
133 MHz Radiation-Hardened Delay-Locked Loop”, IEEE Transactions on
Nuclear Science, Vol. 57, No. 6, December 2010.
4. Alvin L. S. Loke, Robert K. Barnes, Tin Tin Wee, Michael M. Oshima, Charles E.
Moore, Ronald R. Kennedy, and Michael J. Gilsdorf, “A Versatile 90-nm CMOS
Charge-Pump PLL for SerDes Transmitter Clocking” IEEE Journal of Solid-State
Circuits, Vol. 41, No. 8, August 2006.
5. Dominik Przyborowski and Marek Idzik, “A 10-bit Low-Power Small-Area High-
Swing CMOS DAC, “IEEE Transactions on Nuclear Science, Vol. 57, No. 1,
February 2010.
6. Allan H. Johnston, and B. G. Rax, “Failure Modes and Hardness Assurance for
Linear Integrated Circuits in Space Applications”, IEEE Transactions on Nuclear
Science, Vol. 57, No. 4, August 2010.
7. Xiaoyin Yao, Lawrence T. Clark, Srivatsan Chellappa, Keith E. Holbert, and
Nathan D. Hindman, “Design and Experimental Validation of Radiation Hardened
by Design SRAM Cells”, IEEE Transactions on Nuclear Science, Vol. 57, No. 1,
February 2010.
8. Pierre Maillard, W. Timothy Holman, T. Daniel Loveless, Bharat L. Bhuva, and
Lloyd W. Massengill, “An RHBD Technique to Mitigate Missing Pulses in Delay
Locked Loops”, IEEE Transactions on Nuclear Science, Vol. 57, No. 6,
December 2010.
9. Zhiyuan Hu, Zhangli Liu, Hua Shao, Zhengxuan Zhang, Bingxu Ning, Ming
Chen, Dawei Bi, and Shichang Zou, “Radiation Hardening by Applying Substrate
Bias”, IEEE Transactions on Nuclear Science, Vol. 58, No. 3, June 2011.

165 
 
10. Stephen J. Horst, Stanley D. Phillips, John D. Cressler, Kirby Kruckmeyer, Robert
Eddy, Arlo Aude, Patrick O’Farrell, Benyong Zhang, Edward Wilcox, and Ken
LaBel, “A Study of Total Dose Mitigation Approaches for Charge Pumps in
Phase-Locked Loop Applications”, IEEE Transactions on Nuclear Science, Vol.
58, No. 6, December 2011.
11. Kenneth P. Rodbell, David F. Heidel, Jonathan A. Pellish, Paul W. Marshall,
Henry H. K. Tang, Conal E. Murray, Kenneth A. LaBel, Michael S. Gordon,
Kevin G. Stawiasz, James R. Schwank, Melanie D. Berg, Hak S. Kim, Mark. R.
Friendlich, Anthony M. Phan, and Christina M. Seidleck, “32 and 45 nm
Radiation-Hardened-by-Design (RHBD) SOI Latches”, IEEE Transactions on
Nuclear Science, Vol. 58, No. 6, December 2011.
12. Xiaoyin Yao, Lawrence T. Clark, Srivatsan Chellappa, Keith E. Holbert, and
Nathan D. Hindman, “Design and Experimental Validation of Radiation Hardened
by Design SRAM Cells”, IEEE Transactions On Nuclear Science, Vol. 57, No. 1,
February 2010.
13. Y. Gonzalez Velo, Jérôme Boch, Nicolas Jean-Henri Roche, Stephanie Pérez,
Jean-Roch Vaillé, Laurent Dusseau, Frédéric Saigné, Eric Lorfèvre, Ronald. D.
Schrimpf, Christian Chatry, and Anna Canals, “Bias Effects on Total Dose-
Induced Degradation of Bipolar Linear Microcircuits for Switched Dose-Rate
Irradiation”, IEEE Transactions on Nuclear Science, Vol. 57, No. 4, August 2010.
14. P. E. Dodd, M. R. Shaneyfelt, J. R. Schwank, and J. A. Felix, “Current and Future
Challenges in Radiation Effects on CMOS Electronics”, IEEE Transactions on
Nuclear Science, Vol. 57, No. 4, August 2010.
15. David L. Hansen, Eric J. Miller, Aj Kleinosowski, Kirk Kohnen, Anthony Le,
Dick Wong, Karina Amador, Mark Baze, David DeSalvo, Maryanne Dooley,
Kenneth Gerst, Barrie Hughlock, Bradford Jeppson, R. D. Jobe, David Nardi,
Isabel Ojalvo, Brad Rasmussen, David Sunderland, John Truong, Michael Yoo,
and E. Zayas, “Clock, Flip-Flop, and Combinatorial Logic Contributions to the
SEU Cross Section in 90 nm ASIC Technology”, IEEE Transactions on Nuclear
Science, Vol. 56, No. 6, December 2009.
16. Ethan H. Cannon and Manuel Cabanas-Holmen, “Heavy Ion and High Energy
Proton-Induced Single Event Transients in 90 nm Inverter, NAND and NOR
Gates”, IEEE Transactions on Nuclear Science, Vol. 56, No. 6, December 2009.

166 
 
17. Marta Bagatin, Simone Gerardin, Alessandro Paccagnella, Angelo Visconti, Silvia
Beltrami, Massimo Bertuccio, and Laura T. Czeppel, “Effects of Total Ionizing
Dose on the Retention of 41-nm NAND Flash Cells”, IEEE Transactions on
Nuclear Science, Vol. 58, No. 6, December 2011.
18. Edward P. Wilcox, Stanley D. Phillips, John D. Cressler, Paul W. Marshall,
Martin A. Carts, Jonathan A. Pellish, Larry Richmond, William Mathes, Barbara
Randall, Devon Post, Barry Gilbert, and Erik Daniel, “Non-TMR SEU-Hardening
Techniques for SiGe HBT Shift Registers and Clock Buffers”, IEEE Transactions
on Nuclear Science, Vol. 57, No. 4, August 2010.
19. Srikanth Jagannathan, Daniel R. Herbison, William Timothy Holman, and Lloyd.
W. Massengill, “Behavioral Modeling Technique for TID Degradation of
Complex Analog Circuits”, IEEE Transactions on Nuclear Science, Vol. 57, No.
6, December 2010.
20. Ahmed A. Abou-Auf, Hamzah A. Abdel-Aziz, and Mostafa M. Abdel-Aziz,
“Fault Modeling and Worst-Case Test Vectors for Logic Failure Induced by
Total-Dose in Combinational Circuits of Cell-Based ASICs”, IEEE Transactions
on Nuclear Science, Vol. 57, No. 4, August 2010.
21. S. Jagannathan, T. D. Loveless, B. L. Bhuva, S.-J. Wen, R. Wong, M. Sachdev, D.
Rennie, and L. W. Massengill, “Single-Event Tolerant Flip-Flop Design in 40-nm
Bulk CMOS Technology”, IEEE Transactions on Nuclear Science, Vol. 58, No. 6,
December 2011.
22. Tonmoy S. Mukherjee, Akil K. Sutton, Kevin T. Kornegay, Ramkumar
Krithivasan, John D. Cressler, Guofu Niu, and Paul W. Marshall, “A Novel
Circuit-Level SEU Hardening Technique for High-Speed SiGe HBT Logic
Circuits”, IEEE Transactions on Nuclear Science, Vol. 54, No. 6, December 2007.
23. Nadim F. Haddad, Ernesto Chan, Scott Doyle, Andrew T. Kelly, Reed K.
Lawrence, David Lawson, Dinu Patel, and Jason Ross, “The Path and Challenges
to 90-nm Radiation-Hardened Technology”, IEEE Transactions on Nuclear
Science, Vol. 56, No. 4, August 2009.
24. Daisuke Kobayashi, Kazuyuki Hirose, Véronique Ferlet-Cavrois, Dale
McMorrow, Takahiro Makino, Hirokazu Ikeda, Yasuo Arai and Morifumi Ohno,
“Device-Physics-Based Analytical Model for Single-Event Transients in SOI
CMOS Logic”, IEEE Transactions on Nuclear Science, Vol. 56, No. 6, December
2009.

167 
 
25. Xiaoyin Yao, Lawrence T. Clark, Dan W. Patterson, and Keith E. Holbert, “A 90
nm Bulk CMOS Radiation Hardened by Design Cache Memory”, IEEE
Transactions on Nuclear Science, Vol. 57, No. 4, August 2010.
26. E. H. Cannon, M. Cabanas-Holmen, J. Wert, T. Amort, R. Brees, J. Koehn, B.
Meaker, and E. Normand, “ Heavy Ion, High-Energy, and Low-Energy Proton
SEE Sensitivity of 90-nm RHBD SRAMs”, IEEE Transactions on Nuclear
Science, Vol. 57, No. 6, December 2010.
27. Xiaoxuan She, N. Li, and D. Waileen Jensen, “SEU Tolerant Memory Using
Error Correction Code”, IEEE Transactions on Nuclear Science, Vol. 59, No. 1,
February 2012.
28. Xiaoxuan She, N. Li, and D. Oliswy Erstad”, SET Tolerant Dynamic Logic,
“IEEE Transactions on Nuclear Science, Vol. 59, No. 2, April 2012.
29. Nathan D. Hindman, Lawrence T. Clark, Dan W. Patterson, and Keith E. Holbert,
“Fully Automated, Testable Design of Fine-Grained Triple Mode Redundant
Logic”, IEEE Transactions on Nuclear Science, Vol. 58, No. 6, December 2011.
30. Xiaoxuan She and K. S. McElvain, “Time Multiplexed Triple Modular
Redundancy for Single Event Upset Mitigation”, IEEE Transactions on Nuclear
Science, Vol. 56, No. 4, August 2009.
31. Slawosz Uznanski, Gilles Gasiot, Philippe Roche, Jean-Luc Autran, and
Veronique Ferlet-Cavrois, “Monte-Carlo Based Charge Sharing Investigations on
a Bulk 65 nm RHBD Flip-Flop”, IEEE Transactions on Nuclear Science, Vol. 57,
No. 6, December 2010.
32. Slawosz Uznanski, Gilles Gasiot, Philippe Roche, Clement Tavernier, and Jean-
Luc Autran, “Single Event Upset and Multiple Cell Upset Modeling in
Commercial Bulk 65-nm CMOS SRAMs and Flip-Flops”, IEEE Transactions on
Nuclear Science, Vol. 57, No. 4, August 2010.
33. Paul E. Dodd, Marty R. Shaneyfelt, Richard S. Flores, James R. Schwank,
Thomas A. Hill, Dale McMorrow, Gyorgy Vizkelethy, Scot E. Swanson, and
Scott M. Dalton, “Single-Event Upsets and Distributions in Radiation-Hardened
CMOS Flip-Flop Logic Chains”, IEEE Transactions on Nuclear Science, Vol. 58,
No. 6, December 2011.
34. Bradley I. Matush, Thomas John Mozdzen, Lawrence T. Clark, and Jonathan E.
Knudsen, “Area-Efficient Temporally Hardened by Design Flip-Flop Circuits”,
IEEE Transactions on Nuclear Science, Vol. 57, No. 6, December 2010.

168 
 
35. Jiahui Yuan, Kurt A. Moen, John D. Cressler, Holger Rücker, Bernd
Heinemann, and Wolfgang Winkler, “ SiGe HBT CML Ring Oscillator With
2.3-ps Gate Delay at Cryogenic Temperatures”, IEEE Transactions on Electron
Devices, Vol. 57, No. 5, May 2010.

169