Following a Sequence…

1 2
State Machines
In VHDL 6 3

5 4
example…

Using a single process… Replacing "Count" with State…

If reset = '1' then
Count <= 1;
elsif rising_edge (clock) then A B
if ClockEnable = '1' then
Clock count <= count + 1;
Enable Case Count is Output
when 1 => output <= value1;
when 2 => output <= value2; F C
Clock when 3 => output <= value3;
•
•
•
when N => output <= valueN;
end case;
end if; E D
Reset example…

1
 Declaring a State Signal State machines in VHDL
…with an enumerated type Two VHDL processes....

clock & reset

Architecture….
•
•
• next current
outputs
state state
Type state_t is (A, B, C, D, E, F); inputs Combinational State Combinational
Logic Storage Logic
Signal state : state_t;
•
•
•
Begin next state & clock output
process process

State machines in VHDL Finite State Machine Notation

If reset = '1' then
State <= A;
Process (State)
•
Moore Mealy
elsif rising_edge (clock) then •
•
Input = '0'
Inputs if ClockEnable = '1' then Case State is
Case State is
Input = '0' Output =
when A => State
when A => Drive Outputs…
Clock Test Inputs… State
Enable State Outputs
Define Next State… when B => Output
when B => •
• •
Clock •
•
• when F => Input = '1' Input = '1'
when F => end case;
end case; • Transition Transition Output =
•
Reset end if; •
end if; end Process;

Described by Two VHDL Processes - Moore Machine

2
Example FSM - Robot Line Follower Robot FSM - State Diagram
State
Motors
010 "PL DL PR DR"

Inputs from
Sensors
Outputs
Forwards to motors
1010
110 011
010 010
100 001
010 000

On Line Drift Right Big Drift Right

Go_Left Turn Go_Right
0010 1011 1000
Line Follow
Robot

Case Statement
Robot FSM - Output Process

3
 Alternative: Nested Case Statement

VLD © UoP 2010 14

Two Process Architecture.... Two Process Architecture....

Moore Mealy
Clock Reset Input Output Clock Reset Input Output

Output Output
Clock and State Process Process Clock and State Process Process
(Moore) (Mealy)

State State